A SJ-LIGBT device structure combined with HK collector gate

Abstract

The present invention provides a SJ-LIGBT device structure combined with a HK collector gate, and relates to the field of semiconductor technology. It includes: a P-type substrate region, an emitter structure, a gate structure, a drift region structure and a collector structure, and the collector structure includes a first collector, a first N-bufferlayer region, a second N-bufferlayer region, a third N-bufferlayer region and a HK dielectric region. A multi-layer N-buffer structure, namely a first N-bufferlayer region, a second N-bufferlayer region and a third N-bufferlayer region, is provided to assist the depletion of the P-type substrate region, and the HK collector gate optimizes the longitudinal electric field and improves the breakdown voltage of the SJ-LIGBT device; the multi-layer N-buffer structure is combined with the HK dielectric region to accelerate the turn-off speed and reduce the turn-off loss when the SJ-LIGBT device is turned off.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SJ-LIGBT device structure combined with a HK collector gate. Background Art

[0002] The Insulated Gate Bipolar Transistor (IGBT) can be roughly regarded as a combination of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Bipolar Junction Transistor (BJT). Therefore, it has the gate voltage control characteristics of MOSFET and the dual-carrier conduction characteristics of BJT. Among them, the Lateral Insulated Gate Bipolar Transistor (LIGBT) is a bipolar power semiconductor device with the characteristics of large breakdown voltage, small on-state voltage drop, and high operating frequency. It is widely used in various electronic fields such as transportation and communication. Super-Junction (SJ) is an emerging structure that can be applied to devices such as MOS and IGBT. SJ changes the N-type drift region in MOS and IGBT into a structure where N-pillar and P-pillar alternate with each other, and introduces a lateral electric field inside the device without affecting the longitudinal electric field of the device, thereby increasing the breakdown voltage of the device without affecting the on-state voltage drop. When the device is turned off, the N-pillar and P-pillar deplete each other, and the drift region of the device can be approximately regarded as an intrinsic semiconductor, thereby increasing the breakdown voltage of the device and optimizing the ratio of breakdown voltage to on-state voltage drop from 2.52 to 1.3, successfully breaking through the traditional "silicon limit".

[0003] In order to completely deplete the N-type drift region and achieve the maximum breakdown voltage, the N-pillar and the P-pillar often need to have the same doping concentration. However, in LIGBT, since the substrate is a low-doped P-type substrate, there is a parasitic PN junction between the N-pillar and the substrate. The P-type substrate makes the N-pillar completely depleted before the P-pillar, so that the P-pillar cannot be completely depleted, resulting in a decrease in the device breakdown voltage. In addition, IGBT is a gate voltage controlled power device, so the IGBT breakdown voltage is large and the operating frequency is high. Because the IGBT is a bi-carrier conductive device, the IGBT conduction voltage drop is small. However, bipolar conduction also has defects. When the device is turned off, the residual carriers in the drift region will cause a certain tail current, increasing the turn-off loss of the device. This is because there is a P region in the collector of the device, which will act as a barrier to hinder the extraction of electrons when the device is turned off. Therefore, the excess carriers in the N-type drift region of the device need to disappear through recombination, which makes the turn-off time longer and generates a tail current, resulting in a significant increase in the turn-off loss of the device. Summary of the invention

[0004] The purpose of the embodiment of the present invention is to provide a SJ-LIGBT device structure combined with a HK collector gate to solve the problem that the P-pillar cannot be completely depleted, resulting in a decrease in the device breakdown voltage and a significant increase in the device turn-off loss.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] The present invention provides a SJ-LIGBT device structure combined with a HK collector gate, comprising a P-type substrate region, an emitter structure, a gate structure, a drift region structure and a collector structure;

[0007] An emitter structure formed on one side of the upper surface of the P-type substrate region;

[0008] A gate structure is formed on the other side of the upper surface of the emitter structure, and a portion of the gate structure is wrapped by the emitter structure;

[0009] A drift region structure is formed in a middle region of the upper surface of the P-type substrate region, and the drift region structure is adjacent to the emitter structure;

[0010] A collector structure is formed on the other side of the upper surface of the P-type substrate region and extends from the upper surface of the P-type substrate region into the P-type substrate region, and the collector structure wraps a portion of the drift region structure; the collector structure includes a first collector, a first N-bufferlayer region, a second N-bufferlayer region, a third N-bufferlayer region and a HK dielectric region; the first N-bufferlayer region is formed on the other side of the P-type substrate region and is adjacent to the drift region structure, and the upper surface of the first N-bufferlayer region and the upper surface of the P-type substrate region are located in the same plane, the second N-bufferlayer region is formed on the lower surface of the first N-bufferlayer region, the third N-bufferlayer region is formed on the lower surface of the second N-bufferlayer region, the first collector is formed on the upper surface of the first N-bufferlayer region and is adjacent to the drift region structure, the HK dielectric region extends from the upper surface of the first collector and passes through the first collector, the first N-bufferlayer region, the second N-bufferlayer region and the third N-bufferlayer region, and the bottom of the HK dielectric region is located in the P-type substrate region.

[0011] In some embodiments, the first collector includes a collector N-buffer region, a collector P region, and a collector metal electrode;

[0012] A collector N-buffer region is formed on the upper surface of the first N-bufferlayer region, the collector N-buffer region is adjacent to the drift region structure, and the collector N-buffer region wraps the collector P region;

[0013] A collector metal electrode formed on the upper surface of the collector P region;

[0014] The HK dielectric region extends from the upper surface of the collector P region through the collector P region, the collector N-buffer region, the first N-bufferlayer region, the second N-bufferlayer region and the third N-bufferlayer region, and the bottom of the HK dielectric region is located in the P-type substrate region.

[0015] In some embodiments, the emitter structure includes an emitter P+ region, an emitter N+ region, an emitter P-well region, and an emitter metal electrode;

[0016] An emitter P-well region is formed on one side of the upper surface of the P-type substrate region, the emitter P-well region wraps the emitter P+ region and the emitter N+ region, and the emitter P+ region and the emitter N+ region are adjacent;

[0017] The emitter metal electrode is formed on the upper surface of the emitter P+ region and the emitter N+ region, and the emitter metal electrode is adjacent to the gate structure.

[0018] In some embodiments, the thickness of the emitter P+ region, the emitter N+ region, and the collector P region are the same.

[0019] In some embodiments, the gate structure includes a gate oxide layer and a gate metal electrode;

[0020] A gate oxide layer is formed on the other side of the upper surface of the emitter P-well region and is adjacent to the emitter metal electrode;

[0021] The gate metal electrode is formed on the upper surface of the gate oxide layer.

[0022] In some embodiments, the drift region structure includes an N-pillar drift region and a P-pillar drift region;

[0023] An N-pillar drift region is formed in a middle region between the P-type substrate region and the upper surface of the first N-bufferlayer region, and the N-pillar drift region is adjacent to the emitter P-well region and the collector N-buffer region;

[0024] A P-pillar drift region is formed in the middle region of the upper surface of the P-type substrate region and the first N-bufferlayer region; the P-pillar drift region is adjacent to the emitter P-well region and the collector N-buffer region;

[0025] The N-pillar drift region and the P-pillar drift region are arranged adjacent to each other in the lateral direction.

[0026] In some embodiments, the thickness of the N-pillar drift region is the same as the thickness of the P-pillar drift region, and the thickness of the collector N-buffer region is the same as the thickness of the emitter P-well region.

[0027] In some embodiments, the thickness of the first N-bufferlayer region, the thickness of the second N-bufferlayer region, and the thickness of the third N-bufferlayer region are all the same, and the length of the first N-bufferlayer region is greater than the length of the second N-bufferlayer region, and the length of the second N-bufferlayer region is greater than the length of the third N-bufferlayer region.

[0028] In some embodiments, the first N-bufferlayer region, the second N-bufferlayer region, and the third N-bufferlayer region constitute an auxiliary depletion region.

[0029] In some embodiments, the collector N-buffer region, the collector P region, the first N-bufferlayer region, the second N-bufferlayer region, the third N-bufferlayer region, the collector metal electrode, and the HK dielectric region constitute an electron extraction structure, and the doping concentrations of the collector N-buffer region, the collector P region, the first N-bufferlayer region, the second N-bufferlayer region, and the third N-bufferlayer region simultaneously meet the charge balance of the SJ-LIGBT device, the optimization of the surface and longitudinal electric field distribution, and the carrier extraction requirements.

[0030] Compared with the prior art, the present invention provides a SJ-LIGBT device structure combined with a HK collector gate, comprising a P-type substrate region, an emitter structure, a gate structure, a drift region structure and a collector structure; the emitter structure is formed on one side of the upper surface of the P-type substrate region; the gate structure is formed on the other side of the upper surface of the emitter structure, and part of the gate structure is wrapped by the emitter structure; the drift region structure is formed in the middle area of ​​the upper surface of the P-type substrate region, and the drift region structure is adjacent to the emitter structure; the collector structure is formed on the other side of the upper surface of the P-type substrate region, and extends from the upper surface of the P-type substrate region into the P-type substrate region, and the collector structure wraps part of the drift region structure; the collector structure comprises a first collector, a first N-bufferlayer region, a second N-bufferlayer region, a third N-bufferlayer region and HK a dielectric region; a first N-bufferlayer region is formed on the other side of the P-type substrate region, adjacent to the drift region structure, and an upper surface of the first N-bufferlayer region is located in the same plane as an upper surface of the P-type substrate region; a second N-bufferlayer region is formed on a lower surface of the first N-bufferlayer region; a third N-bufferlayer region is formed on a lower surface of the second N-bufferlayer region; a first collector is formed on an upper surface of the first N-bufferlayer region, and adjacent to the drift region structure; a HK dielectric region extends from an upper surface of the first collector, through the first collector, the first N-bufferlayer region, the second N-bufferlayer region and the third N-bufferlayer region, and a bottom of the HK dielectric region is located in the P-type substrate region. In this way, the multi-layer N-buffer structure, namely the first N-bufferlayer region, the second N-bufferlayer region and the third N-bufferlayer region, can assist the P-type substrate region in depletion, and the HK collector gate can optimize the longitudinal electric field of the SJ-LIGBT device structure, thereby improving the breakdown voltage of the SJ-LIGBT device structure; in addition, the multi-layer N-buffer structure combined with the HK dielectric region can assist in extracting electrons when the SJ-LIGBT device structure is turned off to speed up the turn-off speed of the SJ-LIGBT device structure and reduce the turn-off loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0032] Figure 1The schematic diagram of the structure of the SJ-LIGBT device structure combined with the HK collector gate is schematically shown;

[0033] Figure 2 The cross-sectional view of the SJ-LIGBT device structure combined with HK collector gate is schematically shown.

[0034] Description of reference numerals:

[0035] 1. P-type substrate region; 2. Emitter structure; 21. Emitter P+ region; 22. Emitter N+ region; 23. Emitter P-well region; 24. Emitter metal electrode; 3. Gate structure; 31. Gate oxide layer; 32. Gate metal electrode; 4. Drift region structure; 41. N-pillar drift region; 42. P-pillar drift region; 5. Collector structure; 51. First collector; 511. Collector N-buffer region; 512. Collector P region; 513. Collector metal electrode; 52. First N-bufferlayer region; 53. Second N-bufferlayer region; 54. Third N-bufferlayer region; 55. HK dielectric region. DETAILED DESCRIPTION

[0036] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0037] The following is a detailed description of a SJ-LIGBT device structure combined with an HK collector gate in an embodiment of the present invention.

[0038] See also Figure 1 and Figure 2 As shown, Figure 1 The schematic diagram of the structure of the SJ-LIGBT device structure combined with the HK collector gate is shown schematically, Figure 2 A cross-sectional view of a SJ-LIGBT device structure combined with a HK collector gate is schematically shown. An embodiment of the present invention provides a SJ-LIGBT device structure combined with a HK collector gate, comprising a P-type substrate region 1, an emitter structure 2, a gate structure 3, a drift region structure 4 and a collector structure 5;

[0039] An emitter structure 2 is formed on one side of the upper surface of the P-type substrate region 1;

[0040] A gate structure 3 is formed on the other side of the upper surface of the emitter structure 2, and a portion of the gate structure 3 is wrapped by the emitter structure 2;

[0041] A drift region structure 4 is formed in a middle region of the upper surface of the P-type substrate region 1, and the drift region structure 4 is adjacent to the emitter structure 2;

[0042] The collector structure 5 is formed on the other side of the upper surface of the P-type substrate region 1 and extends from the upper surface of the P-type substrate region 1 to the inside of the P-type substrate region 1, and the collector structure 5 wraps a portion of the drift region structure 4; the collector structure 5 includes a first collector 51, a first N-bufferlayer region 52, a second N-bufferlayer region 53, a third N-bufferlayer region 54 and a HK dielectric region 55; the first N-bufferlayer region 52 is formed on the other side of the P-type substrate region 1, adjacent to the drift region structure 4, and the upper surface of the first N-bufferlayer region 52 is located in the same plane as the upper surface of the P-type substrate region 1, and the second N-bufferlayer region 53 is located in the same plane as the drift region structure 4. The drift layer region 53 is formed on the lower surface of the first N-bufferlayer region 52, the third N-bufferlayer region 54 is formed on the lower surface of the second N-bufferlayer region 53, the first collector 51 is formed on the upper surface of the first N-bufferlayer region 52 and is adjacent to the drift region structure 4, the HK dielectric region 55 extends from the upper surface of the first collector 51 through the first collector 51, the first N-bufferlayer region 52, the second N-bufferlayer region 53 and the third N-bufferlayer region 54, and the bottom of the HK dielectric region 55 is located in the P-type substrate region 1.

[0043] The directions in the embodiment of the present invention are: "up", "down", "thickness" and "height" are from top to bottom along the direction from the emitter P+ region 21 to the P-type substrate region 1; "length", "left" and "right" are from left to right along the direction from the emitter P+ region 21 to the collector P region 512; and "width", "front" and "back" are from front to back along the direction from the N-pillar drift region 41 to the P-pillar drift region 42.

[0044] Specifically, the first N-bufferlayer region 52, the second N-bufferlayer region 53 and the third N-bufferlayer region 54 are referred to as a multi-layer N-buffer structure. The P-type substrate region 1 is located at the bottom of the SJ-LIGBT device structure. The emitter structure 2 is located on the left side and below part of the gate structure 3, and surrounds the gate structure 3 in an L shape. The first collector 51 is disposed on the upper surface of the first N-bufferlayer region 52, and is in an inverted L shape.

[0045] In this embodiment, the first collector 51 includes a collector N-buffer region 511 , a collector P region 512 , and a collector metal electrode 513 ;

[0046] A collector N-buffer region 511 is formed on the upper surface of the first N-bufferlayer region 52 , the collector N-buffer region 511 is adjacent to the drift region structure 4 , and the collector N-buffer region 511 wraps around the collector P region 512 ;

[0047] A collector metal electrode 513 formed on the upper surface of the collector P region 512;

[0048] The HK dielectric region 55 extends from the upper surface of the collector P region 512 through the collector P region 512 , the collector N-buffer region 511 , the first N-bufferlayer region 52 , the second N-bufferlayer region 53 and the third N-bufferlayer region 54 , and the bottom of the HK dielectric region 55 is located in the P-type substrate region 1 .

[0049] Specifically, in the collector structure 5, the HK dielectric region 55 is located at the edge of the other side of the SJ-LIGBT device structure. The collector N-buffer region 511 wraps the collector P region 512, that is, the collector N-buffer region 511 is located on the left and below the collector P region 512, and surrounds the collector P region 512 in an L shape. The collector metal electrode 513 is located above the collector P region 512 and covers the collector P region 512. The thickness of the HK dielectric region 55 exceeds the sum of the collector N-buffer region 511, the first N-bufferlayer region 52, the second N-bufferlayer region 53 and the third N-bufferlayer region 54.

[0050] The collector metal electrode 513 is located above the collector P region 512 , and together they form a carrier extraction structure.

[0051] In this embodiment, the emitter structure 2 includes an emitter P+ region 21, an emitter N+ region 22, an emitter P-well region 23, and an emitter metal electrode 24;

[0052] An emitter P-well region 23 is formed on one side of the upper surface of the P-type substrate region 1. The emitter P-well region 23 wraps the emitter P+ region 21 and the emitter N+ region 22. The emitter P+ region 21 and the emitter N+ region 22 are adjacent to each other.

[0053] The emitter metal electrode 24 is formed on the upper surfaces of the emitter P+ region 21 and the emitter N+ region 22 , and the emitter metal electrode 24 is adjacent to the gate structure 3 .

[0054] Specifically, the emitter P+ region 21 and the emitter N+ region 22 are sequentially arranged at the edge of the upper surface of the emitter P-well region 23. The emitter P-well region 23 wraps the emitter P+ region 21 and the emitter N+ region 22, that is, the emitter P-well region 23 is arranged below and to the side of the emitter P+ region 21 and the emitter N+ region 22, and surrounds the emitter P+ region 21 and the emitter N+ region 22 in an inverted L shape. The emitter metal electrode 24 is plate-shaped and covers the emitter P+ region 21 and the emitter N+ region 22.

[0055] In this embodiment, the thickness of the emitter P+ region 21 , the thickness of the emitter N+ region 22 , and the thickness of the collector P region 512 are the same.

[0056] In this embodiment, the gate structure 3 includes a gate oxide layer 31 and a gate metal electrode 32;

[0057] A gate oxide layer 31 is formed on the other side of the upper surface of the emitter P-well region 23 and is adjacent to the emitter metal electrode 24;

[0058] The gate metal electrode 32 is formed on the upper surface of the gate oxide layer 31 .

[0059] In this embodiment, the drift region structure 4 includes an N-pillar drift region 41 and a P-pillar drift region 42;

[0060] The N-pillar drift region 41 is formed in the middle region between the P-type substrate region 1 and the upper surface of the first N-bufferlayer region 52 , and the N-pillar drift region 41 is adjacent to the emitter P-well region 23 and the collector N-buffer region 511 ;

[0061] The P-pillar drift region 42 is formed in the middle region between the P-type substrate region 1 and the upper surface of the first N-bufferlayer region 52; the P-pillar drift region 42 is adjacent to the emitter P-well region 23 and the collector N-buffer region 511;

[0062] The N-pillar drift region 41 and the P-pillar drift region 42 are arranged adjacent to each other in the lateral direction.

[0063] Specifically, the N-pillar drift region 41 and the P-pillar drift region 42 have the same shape and size.

[0064] In this embodiment, the thickness of the N-pillar drift region 41 is the same as the thickness of the P-pillar drift region 42 , and the thickness of the collector N-buffer region 511 is the same as the thickness of the emitter P-well region 23 .

[0065] Specifically, the thickness of the N-pillar drift region 41 , the thickness of the P-pillar drift region 42 , the thickness of the collector N-buffer region 511 and the thickness of the emitter P-well region 23 are the same. The collector P region 512 and the emitter P+ region 21 have the same thickness.

[0066] In this embodiment, the thickness of the first N-bufferlayer region 52 , the thickness of the second N-bufferlayer region 53 and the thickness of the third N-bufferlayer region 54 are all the same, and the length of the first N-bufferlayer region 52 is greater than the length of the second N-bufferlayer region 53 , and the length of the second N-bufferlayer region 53 is greater than the length of the third N-bufferlayer region 54 .

[0067] In this embodiment, the first N-bufferlayer region 52 , the second N-bufferlayer region 53 and the third N-bufferlayer region 54 constitute an auxiliary depletion region.

[0068] In this embodiment, the collector N-buffer region 511, the collector P region 512, the first N-bufferlayer region 52, the second N-bufferlayer region 53, the third N-bufferlayer region 54, the collector metal electrode 513, and the HK dielectric region 55 constitute an electron extraction structure; the doping concentrations of the collector N-buffer region 511, the collector P region 512, the first N-bufferlayer region 52, the second N-bufferlayer region 53, and the third N-bufferlayer region 54 simultaneously meet the charge balance of the SJ-LIGBT device, the optimization of the surface and longitudinal electric field distribution, and the carrier extraction requirements.

[0069] The doping concentrations of the collector N-buffer region 511, the collector P region 512, the first N-bufferlayer region 52, the second N-bufferlayer region 53 and the third N-bufferlayer region 54 simultaneously meet the three conditions of charge balance of the SJ-LIGBT device, optimization of surface and longitudinal electric field distribution, and carrier extraction requirements, i.e., optimization of the carrier extraction channel. Therefore, the total dose is related to the super junction doping concentration, and the length and thickness are optimized depending on the device withstand voltage value. The doping concentration distribution of different layers needs to be combined with the carrier extraction time, and the carrier extraction process needs to be completed before the N-buffer layer, i.e., the multi-layer N-buffer structure, is exhausted.

[0070] As an optional embodiment of the present invention, the length of the emitter P+ region 21 is 2μm, the length of the emitter N+ region 22 is 2μm, the length of the emitter P-well region 23 is 6μm, the length of the P-type substrate region 1 is 74μm, the length of the emitter metal electrode 24 is 4μm, the length of the gate oxide layer 31 and the gate metal electrode 32 is 2μm, the length of the N-pillar drift region 41 and the P-pillar drift region 42 are both 60μm, the length of the collector N-buffer region 511 is 5μm, the length of the collector P region 512 is 4.5μm, the length of the first N-bufferlayer region 52 is 8μm, the length of the second N-bufferlayer region 53 is 6μm, the length of the third N-bufferlayer region 54 is 4μm, the length of the collector metal electrode 513 is 4.5μm, and the length of the HK dielectric region 55 is 1μm.

[0071] As an optional embodiment of the present invention, without considering the metal electrodes (i.e., the emitter metal electrode 24, the gate metal electrode 32, and the collector metal electrode 513), the thickness of the SJ-LIGBT device structure as a whole is 100 μm, the thickness of the emitter P+ region 21 is 0.2 μm, the thickness of the emitter N+ region 22 is 0.2 μm, the thickness of the emitter P-well region 23 is 0.6 μm, the thickness of the P-type substrate region 1 is 99.4 μm, the emitter metal electrode 24, the collector metal electrode 513, the gate The thickness of the oxide layer 31 and the gate metal electrode 32 are both 0.1μm, the thickness of the N-pillar drift region 41 and the P-pillar drift region 42 are both 0.2μm, the thickness of the collector N-buffer region 511 is 0.6μm, the thickness of the collector P region 512 is 0.3μm, the thickness of the first N-bufferlayer region 52, the second N-bufferlayer region 53 and the third N-bufferlayer region 54 are all 0.5μm, and the thickness of the HK dielectric region 55 is 6μm.

[0072] As an optional embodiment of the present invention, except for the N-pillar drift region 41 and the P-pillar drift region 42 , the width of other regions of the SJ-LIGBT device structure is 2 μm, and the width of the N-pillar drift region 41 and the P-pillar drift region 42 is 1 μm.

[0073] As an optional embodiment of the present invention, the emitter P+ region 21 in the SJ-LIGBT device structure is P-type doped with a doping concentration of 1e19 cm -3 , the emitter N+ region 22 is N-type doped, with a doping concentration of 1e19cm -3 , the emitter P-well region 23 is P-type doped with a doping concentration of 1e16cm -3, the P-type substrate region 14 is P-type doped, and the doping concentration is 1e14cm -3 The N-pillar drift region 41 and the P-pillar drift region 42 are N-type doped and P-type doped, respectively, and the doping concentration is 1e16cm -3 The collector N-buffer region 511 is N-type doped with a doping concentration of 5e16cm -3 The collector P region 512 is P-type doped with a doping concentration of 1e17 cm -3 The first N-bufferlayer region 52, the second N-bufferlayer region 53 and the third N-bufferlayer region 54 are all N-type doped, and the doping concentration is 1e16cm -3 .

[0074] The working principle of the device of the present invention is as follows:

[0075] When the SJ-LIGBT device structure is forward-conducted, the gate metal electrode 32 is connected to a positive voltage, the emitter metal electrode 24 is connected to a negative voltage, the collector metal electrode 513 is connected to a positive voltage, and the HK dielectric region 55 is connected to a positive voltage. There is an electron extraction structure on the right side of the collector P region 512, namely the HK dielectric region 55 and the collector metal electrode 513. Since a positive voltage is applied to the HK dielectric region 55, the holes in the part of the collector P region 512 that contacts the HK dielectric region 55 are repelled, forming a depletion region, thereby generating a conductive channel. Electrons flow through the conductive channel generated in the collector P region 512 and flow into the collector metal electrode 513 without passing through the PN junction barrier generated by the collector N-buffer region 511 and the collector P region 512, thereby reducing the conduction voltage drop.

[0076] When the SJ-LIGBT device structure withstands voltage, the gate metal electrode 32 is connected to a negative voltage, the emitter metal electrode 24 is connected to a negative voltage, the collector metal electrode 513 is connected to a positive voltage, and the HK dielectric region 55 is connected to a positive voltage. Since there are multiple layers of N-buffer structures in the P-type substrate region 1, the multiple layers of N-buffer structures and the P-type substrate region 14 are mutually depleted, which expands the depletion region in the substrate. In addition, since the HK dielectric region 55 is connected to a positive voltage and the multiple layers of N-buffer structures are in direct contact with the HK dielectric region 55, the depletion region is further expanded under the action of voltage, which can effectively prevent the device from undergoing longitudinal breakdown, improve the longitudinal withstand voltage capability of the device, and achieve full utilization of the substrate. In addition, the mutual depletion of the multiple layers of N-buffer structures and the P-type substrate region 1 can also prevent the P-type substrate region 1 from affecting the mutual depletion between the N-pillar drift region 41 and the P-pillar drift region 42, thereby improving the lateral withstand voltage capability of the SJ-LIGBT device structure.

[0077] At the moment when the SJ-LIGBT device structure is turned off, the gate metal electrode 32 changes from positive voltage to negative voltage, the emitter metal electrode 24 is connected to negative voltage, the collector metal electrode 513 is connected to positive voltage, and the HK dielectric region 55 is connected to positive voltage. On the right side of the collector P region 512, there is an electron extraction structure, namely the HK dielectric region 55 and the collector metal electrode 513. Since a positive voltage is applied to the HK dielectric region 55, the holes in the part of the collector P region 512 that contacts the HK dielectric region 55 are repelled, thereby generating a conductive channel. When the SJ-LIGBT device structure is turned off, the remaining electrons remaining in the drift region can flow through the collector N-buffer region 511 and the conductive channel and flow into the collector metal electrode 513 without passing through the PN junction barrier generated by the collector N-buffer region 511 and the collector P region 512. Compared with the traditional SJ-LIGBT device, the SJ-LIGBT device structure of the present invention provides a conductive channel for electron extraction when turned off, which reduces the turn-off time and reduces the turn-off loss when the SJ-LIGBT device is turned off.

[0078] On the basis of the traditional LIGBT device, the present invention introduces the N-pillar drift region 41 and the P-pillar drift region 42 to form a super junction structure, thereby improving the breakdown voltage of the SJ-LIGBT device structure and reducing the on-state voltage drop; introduces the collector N-buffer region 511, the collector P region 512, the collector metal electrode 513, and the HK dielectric region 55 to form an electron extraction structure. When the SJ-LIGBT device structure is turned off, a forward voltage is applied to the HK dielectric region 55 so that a conductive channel appears in the collector P region 512. Electrons can flow through the conductive channel and directly flow into the collector metal electrode 513 without passing through the collector P region 512 like the traditional LIGBT, and there is no need to pass through the P region barrier, thereby accelerating the extraction of electrons and effectively reducing the turn-off time and turn-off loss of the device. The first N-bufferlayer1 region, the second N-bufferlayer region 53, the third N-bufferlayer region 54 and the HK dielectric region 55 are introduced to form an auxiliary depletion structure to optimize the longitudinal electric field of the device, thereby increasing the breakdown voltage of the SJ-LIGBT device structure and providing a path for the extraction of electrons when the SJ-LIGBT device structure is turned off.

[0079] Based on the above Figure 1It can be seen from the implementation method that an SJ-LIGBT device structure combined with a HK collector gate in an embodiment of the present application includes a P-type substrate region 1, an emitter structure 2, a gate structure 3, a drift region structure 4 and a collector structure 5; the emitter structure 2 is formed on one side of the upper surface of the P-type substrate region 1; the gate structure 3 is formed on the other side of the upper surface of the emitter structure 2, and part of the gate structure 3 is wrapped by the emitter structure 2; the drift region structure 4 is formed in the middle area of ​​the upper surface of the P-type substrate region 1, and the drift region structure 4 is adjacent to the emitter structure 2; the collector structure 5 is formed on the other side of the upper surface of the P-type substrate region 1, and extends from the upper surface of the P-type substrate region 1 to the P-type substrate region 1, and the collector structure 5 wraps part of the drift region structure 4; the collector structure 5 includes a first collector 51, a first N-bufferlayer region 52, a second N-bufferlayer region 53, a third N-bufferlayer region 54 and a HK dielectric region 55; a first N-bufferlayer region 52 is formed on the other side of the P-type substrate region 1, adjacent to the drift region structure 4, and an upper surface of the first N-bufferlayer region 52 is located in the same plane as an upper surface of the P-type substrate region 1, a second N-bufferlayer region 53 is formed on a lower surface of the first N-bufferlayer region 52, a third N-bufferlayer region 54 is formed on a lower surface of the second N-bufferlayer region 53, a first collector 51 is formed on an upper surface of the first N-bufferlayer region 52, and adjacent to the drift region structure 4, a HK dielectric region 55 extends from an upper surface of the first collector 51 through the first collector 51, the first N-bufferlayer region 52, the second N-bufferlayer region 53 and the third N-bufferlayer region 54, and a bottom of the HK dielectric region 55 is located in the P-type substrate region 1. In this way, the multi-layer N-buffer structure, namely the first N-bufferlayer region 52, the second N-bufferlayer region 53 and the third N-bufferlayer region 54, can assist the P-type substrate region 1 in depletion, and the HK collector gate can optimize the longitudinal electric field of the SJ-LIGBT device structure, thereby improving the breakdown voltage of the SJ-LIGBT device structure; in addition, the multi-layer N-buffer structure combined with the HK dielectric region 55 can assist in extracting electrons when the SJ-LIGBT device structure is turned off to speed up the turn-off speed of the SJ-LIGBT device structure and reduce the turn-off loss.

[0080] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict.

[0081] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A SJ-LIGBT device structure combined with HK collector gate, characterized in that: The SJ-LIGBT device structure combined with HK collector gate includes a P-type substrate region, an emitter structure, a gate structure, a drift region structure and a collector structure; The emitter structure is formed on one side of the upper surface of the P-type substrate region; The gate structure is formed on the other side of the upper surface of the emitter structure, and a portion of the gate structure is wrapped by the emitter structure; The drift region structure is formed in a middle area of ​​the upper surface of the P-type substrate region, and the drift region structure is adjacent to the emitter structure; The collector structure is formed on the other side of the upper surface of the P-type substrate region and extends from the upper surface of the P-type substrate region into the P-type substrate region, and the collector structure wraps a portion of the drift region structure; the collector structure includes a first collector, a first N-buffer layer region, a second N-buffer layer region, a third N-buffer layer region and a high dielectric constant dielectric region; the first N-buffer layer region is formed on the other side of the P-type substrate region, adjacent to the drift region structure, and the upper surface of the first N-buffer layer region is located on the same plane, the second N-buffer layer region is formed on the lower surface of the first N-buffer layer region, the third N-buffer layer region is formed on the lower surface of the second N-buffer layer region, the first collector is formed on the upper surface of the first N-buffer layer region and is adjacent to the drift region structure, the high dielectric constant dielectric region extends from the upper surface of the first collector through the first collector, the first N-buffer layer region, the second N-buffer layer region and the third N-buffer layer region, and the bottom of the high dielectric constant dielectric region is located in the P-type substrate region.

2. The SJ-LIGBT device structure combined with HK collector gate according to claim 1, characterized in that: The first collector includes a collector N-buffer region, a collector P region and a collector metal electrode; The collector N-buffer region is formed on the upper surface of the first N-buffer layer region, the collector N-buffer region is adjacent to the drift region structure, and the collector N-buffer region wraps the collector P region; The collector metal electrode is formed on the upper surface of the collector P region; The high dielectric constant dielectric region extends from the upper surface of the collector P region through the collector P region, the collector N-buffer region, the first N-buffer layer region, the second N-buffer layer region and the third N-buffer layer region, and the bottom of the high dielectric constant dielectric region is located in the P-type substrate region.

3. The SJ-LIGBT device structure combined with HK collector gate according to claim 2, characterized in that: The emitter structure includes an emitter P+ region, an emitter N+ region, an emitter P-well region, and an emitter metal electrode; The emitter P-well region is formed on one side of the upper surface of the P-type substrate region, the emitter P-well region wraps the emitter P+ region and the emitter N+ region, and the emitter P+ region and the emitter N+ region are adjacent; The emitter metal electrode is formed on the upper surfaces of the emitter P+ region and the emitter N+ region, and the emitter metal electrode is adjacent to the gate structure.

4. The SJ-LIGBT device structure combined with HK collector gate according to claim 3, characterized in that: The thickness of the emitter P+ region, the emitter N+ region and the collector P region are the same.

5. The SJ-LIGBT device structure combined with HK collector gate according to claim 3, characterized in that: The gate structure includes a gate oxide layer and a gate metal electrode; The gate oxide layer is formed on the other side of the upper surface of the emitter P-well region and is adjacent to the emitter metal electrode; The gate metal electrode is formed on the upper surface of the gate oxide layer.

6. The SJ-LIGBT device structure combined with HK collector gate according to claim 5, characterized in that: The drift region structure includes an N-column drift region and a P-column drift region; The N-column drift region is formed in the middle area of ​​the upper surface of the P-type substrate region and the first N-buffer layer region, and the N-column drift region is adjacent to the emitter P-well region and the collector N-buffer region; The P-column drift region is formed in the middle area of ​​the upper surface of the P-type substrate region and the first N-buffer layer region; the P-column drift region is adjacent to the emitter P-well region and the collector N-buffer region; The N-column drift region and the P-column drift region are arranged adjacent to each other in a lateral direction.

7. The SJ-LIGBT device structure combined with HK collector gate according to claim 6, characterized in that: The thickness of the N-column drift region is the same as the thickness of the P-column drift region, and the thickness of the collector N-buffer region is the same as the thickness of the emitter P-well region.

8. The SJ-LIGBT device structure combined with HK collector gate according to claim 1, characterized in that: The thickness of the first N-buffer layer region, the thickness of the second N-buffer layer region and the thickness of the third N-buffer layer region are all the same, and the length of the first N-buffer layer region is greater than the length of the second N-buffer layer region, and the length of the second N-buffer layer region is greater than the length of the third N-buffer layer region.

9. The SJ-LIGBT device structure combined with HK collector gate according to claim 1, characterized in that: The first N-buffer layer region, the second N-buffer layer region, and the third N-buffer layer region constitute an auxiliary depletion region.

10. The SJ-LIGBT device structure combined with HK collector gate according to claim 2, characterized in that: The collector N-buffer region, the collector P region, the first N-buffer layer region, the second N-buffer layer region, the third N-buffer layer region, the collector metal electrode, and the high dielectric constant dielectric region constitute an electron extraction structure, and the doping concentrations of the collector N-buffer region, the collector P region, the first N-buffer layer region, the second N-buffer layer region, and the third N-buffer layer region simultaneously meet the charge balance, surface and longitudinal electric field distribution optimization, and carrier extraction requirements of the super junction-LIGBT device.

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