Semiconductor structure

Abstract

This application provides a semiconductor structure, relating to the field of semiconductor technology, to address the problem of difficulty in improving the performance of semiconductor structures. The semiconductor structure includes: a substrate, including an isolation structure and an active region defined by the isolation structure; a gate trench disposed within the substrate; a gate electrode located within the gate trench, the gate electrode including a gate semiconductor layer; and a gap located within the gate trench, at least one gap being connected to the gate semiconductor layer. By placing the gap in the gate trench and ensuring that at least one gap is connected to the gate semiconductor layer, this application achieves improved semiconductor structure performance while maintaining a small size.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor structure. Background Technology

[0002] With the development of semiconductor technology, semiconductor integrated circuits are becoming more inclined towards small-size design and high-density arrangement. However, for increasingly smaller semiconductor structures, it is becoming more and more difficult to further reduce the size while ensuring the performance of the semiconductor structure.

[0003] In related technologies, since the traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing process is difficult to continuously miniaturize, how to improve the traditional planar MOS transistor, thereby reducing the geometric size of the MOS transistor and / or improving the performance of the transistor device, has become an urgent technical problem to be solved. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a semiconductor structure that can reduce the geometric size of the semiconductor structure while improving its performance.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] This application provides a semiconductor structure, including: a substrate, including an isolation structure and an active region defined by the isolation structure; a gate trench disposed in the substrate; a gate electrode located in the gate trench, the gate electrode including a gate semiconductor layer; and a gap located in the gate trench, at least one of the gaps being connected to the gate semiconductor layer.

[0007] In some embodiments, the semiconductor structure further includes a gate dielectric layer; the gate electrode further includes: a gate conductive layer disposed on the gate dielectric layer; and a barrier layer disposed between the gate dielectric layer and the gate conductive layer; wherein the gate semiconductor layer is located on the barrier layer and the gate conductive layer, and is in direct contact with the barrier layer and the gate conductive layer.

[0008] In some embodiments, the midpoints of two adjacent sides of the gate semiconductor layer and the intersection of the two adjacent sides together form a preset region.

[0009] In some embodiments, the gate semiconductor layer includes a first side and a second side, which are respectively enclosed by the endpoints of the first side, the midpoint of the first side, and the midpoint of the second side to form a triangular region, and the triangular region forms the preset region.

[0010] In some embodiments, the triangular region at least partially overlaps with the gate semiconductor layer, and at least one of the gaps is located in the overlapping region.

[0011] In some embodiments, at least one of the gaps is in direct contact with the gate dielectric layer.

[0012] In some embodiments, a portion of the void is located in the gate dielectric layer such that the spacing between the void and the active region is smaller than the spacing between the gate semiconductor layer and the active region.

[0013] In some embodiments, the gap is formed between the barrier layer, the gate dielectric layer, and the gate semiconductor layer.

[0014] In some embodiments, the gate electrode further includes a gate insulating layer, and the gap is formed between the gate insulating layer, the gate semiconductor layer and the gate dielectric layer.

[0015] In some embodiments, the gate semiconductor layer has an arc-shaped corner between at least two adjacent sides.

[0016] In some embodiments, the work function of the gate conductive layer is greater than the work function of the gate semiconductor layer.

[0017] In some embodiments, at least a portion of the gap is located on the barrier layer and is in direct contact with the barrier layer.

[0018] In some embodiments, the gap also directly contacts the gate dielectric layer and the gate semiconductor layer.

[0019] In the semiconductor structure provided in this application embodiment, by setting gaps in the gate trench and connecting at least one gap to the gate semiconductor layer, the performance of the semiconductor structure can be improved while ensuring a small size.

[0020] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions as described above, other technical problems that the semiconductor structure provided by the embodiments of this application can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0023] Figure 2 For along Figure 1 A partial schematic diagram of the first type of semiconductor structure with line A-A';

[0024] Figure 3 For along Figure 1 A partial schematic diagram of the second structure of the semiconductor structure with line A-A';

[0025] Figure 4 For along Figure 1 A partial schematic diagram of the third type of semiconductor structure with line A-A';

[0026] Figure 5 For along Figure 1 A partial schematic diagram of the fourth type of semiconductor structure with line A-A';

[0027] Figure 6 For along Figure 1 A partial schematic diagram of the semiconductor structure of line B-B' from another angle;

[0028] Figures 7-12 This is a top view schematic diagram illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0029] because Figures 1 to 12 The illustrations are intended for illustrative purposes, so the elements in the figures do not necessarily need to be drawn to scale. For example, some elements may be enlarged or exaggerated for clarity.

[0030] Explanation of reference numerals in the attached figures:

[0031] 110-substrate;

[0032] 120 - Active region;

[0033] 121 - Isolation structure;

[0034] 130 - Gate electrode;

[0035] 131 - Gate conductive layer;

[0036] 132 - Gate semiconductor layer;

[0037] 133 - Gate insulating layer;

[0038] 134 - Barrier layer;

[0039] 135 - Gate trench;

[0040] 140 - Gate dielectric layer;

[0041] 150-gap;

[0042] 160 - Preset area.

[0043] 175 - Contact layer;

[0044] 1100 - Spacer structure; 1110 - First spacer; 1120 - Second spacer;

[0045] 210 - bit line; 214 - first conductive line; 211, 212 - second conductive lines; 213 - bit line cover film; 215 - bit line dielectric layer. Detailed Implementation

[0046] With the development of technology, semiconductor integrated circuits are increasingly trending towards smaller size designs and higher density arrangements. However, for increasingly smaller semiconductor structures, further reduction in size while maintaining performance becomes increasingly challenging. In related technologies, during the fabrication of MOS transistors, the adhesion between different materials results in unavoidable gaps within the semiconductor structure. The location of these gaps is crucial; in some locations, they may affect the performance of the semiconductor device, while in others they may have little impact.

[0047] Based on the above problems, this application provides a semiconductor structure that improves the performance of the semiconductor structure while ensuring its small size by setting gaps in the gate trench and connecting at least one gap to the gate semiconductor layer.

[0048] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0049] For clarity and to aid in understanding the semiconductor structure provided in this application, please refer to [link / reference]. Figure 1 and Figure 2The figure shows spatial reference directions D1, D2, D3, and D4. Directions D1, D2, and D3 are approximately parallel to the surface of substrate 110, while direction D4 is approximately perpendicular to the surface of substrate 110. In this paper, direction D4 can also be referred to as the vertical direction, and directions D1, D2, and D3 can also be referred to as the horizontal direction.

[0050] The overall structure of the semiconductor structure 100 is described below with reference to the accompanying drawings.

[0051] like Figure 1 and Figure 2 As shown, the semiconductor structure includes a substrate 110, which includes an isolation structure 121 and an active region 120 defined by the isolation structure 121. Multiple gate electrodes 130 are disposed within the substrate 110, spanning the active region 120 and the isolation structure 121. Multiple bit lines 210 are located above the gate electrodes 130. Each gate electrode 130 may extend along a second direction D2, and the multiple gate electrodes 130 may be spaced apart along a first direction D1, with equal spacing between them. The second direction D2 may intersect the first direction D1; for example, within the same plane, the second direction D2 may be perpendicular to the first direction D1. The width of the gate electrode 130 or the gap between adjacent gate electrodes 130 can be determined according to actual requirements. Correspondingly, each bit line 210 can extend in the first direction D1, and multiple bit lines 210 can be arranged at intervals in the second direction D2. For example, multiple bit lines 210 are arranged at equal intervals in the second direction D2. The width of the bit line 210 or the gap between the bit lines 210 can be determined according to actual needs.

[0052] like Figure 1 and Figure 2 As shown, the active region 120 is defined by the isolation structure 121 on the substrate 110, and the active region 120 can extend along a third direction D3. The third direction D3 can be a direction different from the first direction D1 and the second direction D2, located in the same plane, wherein the third direction D3 has an inclined angle with the first direction D1 and the second direction D2 respectively. Each active region 120 can be configured as a strip extending along a straight line, the extension directions of each active region 120 are parallel to each other, and the end position of each active region 120 can be configured to be relative to the center position of the adjacent active region 120.

[0053] The substrate 110 can be any substrate suitable for manufacturing semiconductor devices, such as a silicon (Si) substrate 110, an epitaxial silicon (epi-Si) substrate 110, a silicon germanium (SiGe) substrate 110, a silicon carbide (SiC) substrate 110, or a silicon-on-insulator (SOI) substrate 110, but is not limited thereto. The substrate 110 includes an isolation structure 121 made of an insulating material. The isolation structure 121 can be in the form of an isolation film, and can be manufactured using any one of silicon oxide, silicon nitride, silicon oxide nitride, and combinations thereof.

[0054] In some embodiments, such as Figure 7 As shown, a gate trench 135 is also provided in the substrate 110, and a gate electrode 130 is located in the gate trench 135. The gate electrode 130 includes a gate semiconductor layer 132. In addition, a gap 150 is formed in the gate trench, wherein at least one gap 150 is connected to the gate semiconductor layer 132.

[0055] In this embodiment, by setting gaps in the gate trench and ensuring that at least one gap connects to the gate semiconductor layer, the performance of the semiconductor structure can be improved while maintaining a small size. Figure 1 , 2 and Figure 7 As shown, a plurality of gate trenches 135 are formed within the substrate 110. The gate trenches 135 are recessed structures formed within the substrate 110. Gate electrodes 130 are disposed within the gate trenches 135, and the outer wall of the gate electrode 130 is in contact with the gate trenches 135. The areas on the substrate 110 without gate trenches 135 are defined as active regions 120. The sidewalls of the gate trenches 135 can extend along a second direction D2, but the overall extension direction of the gate trenches 135 forms an angle with a third direction D3. The number of gate trenches 135 can be multiple, and the depth of the gate trenches 135 on the substrate 110 can vary.

[0056] In some embodiments, the gate electrode 130 includes a gate semiconductor layer 132, a gate dielectric layer 140, and a gate insulating layer 133. The gate dielectric layer 140 can be a thin film structure covering the surface of the gate trench 135. The gate semiconductor layer 132 is located on the gate dielectric layer 140, and the gate insulating layer 133 is disposed on the gate semiconductor layer 132 and in direct contact with the gate semiconductor layer 132. The gate semiconductor layer 132 can be doped or undoped polysilicon. A gap 150 is formed inside the gate trench 135, and the gap 150 can be connected to the gate semiconductor layer 132. Exemplarily, the gap 150 can be entirely located in the gate semiconductor layer 132 or partially located in the gate semiconductor layer 132. Furthermore, there can be one or more gaps 150, with at least a portion of at least one of the gaps 150 located in the gate semiconductor layer 132.

[0057] For example, the gap 150 may be disposed on one side of the gate semiconductor layer 132 near the gate insulating layer 133; or, as Figure 3 and Figure 4 As shown, the gap 150 can be disposed on both sides of the gate semiconductor layer 132 near the gate dielectric layer 140.

[0058] In this embodiment of the application, by controlling the location of the gap 150 during the fabrication process, the performance of the semiconductor device is improved, thereby increasing the yield of the semiconductor structure.

[0059] Additionally, please refer to Figure 1 and Figure 2 As shown, bit line 210 may include a first conductive line 214, a second conductive line (211 / 212), and a bit line capping film 213 stacked sequentially. The first conductive line 214 and the second conductive line (211 / 212) may be made of at least one of polycrystalline silicon, titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicon nitride (WSiN), and combinations thereof. The bit line capping film 213 may be disposed on the second conductive line (211 / 212), and the bit line capping film 213 may be made of a silicon nitride, such as silicon nitride.

[0060] In some embodiments, refer to Figure 6 As shown, bit line 210 also includes bit line dielectric layer 215, which is located between the first conductive line 214 and the gate insulating layer 133.

[0061] In addition, such as Figure 2As shown, the semiconductor structure may further include a capacitor structure (not shown), which may include a lower electrode, a dielectric film, and an upper electrode. The capacitor structure can store charge within the dielectric film by utilizing the potential difference generated between the lower and upper electrodes. The capacitor structure also includes a landing solder layer and a contact layer 175 arranged and in contact with each other along the fourth direction D4. The lower electrode is in contact with the landing solder layer, and the contact layer 175 is in contact with the active region 120. Thus, the capacitor structure can be electrically connected to the active region 120 through the landing solder layer and the contact layer 175. The capacitor structure is controlled by a first conductive line 214, a second conductive line (211 / 212), and a gate electrode 130, and can store data. In some embodiments, the semiconductor structure 100 further includes an interlayer insulating layer, which may be disposed in the landing solder layer on a side opposite to the contact layer 175, while the interlayer insulating layer is in contact with a fence layer. The interlayer insulating layer can define the landing solder layer to form a plurality of spaced regions. The interlayer insulation layer can expose one end of the landing solder layer away from the contact layer 175, so that the lower electrode is in contact with the landing solder layer.

[0062] In some embodiments, refer to Figure 2 As shown, the semiconductor structure also includes a spacer structure 1100, which can cover both sides of the bit line 210. The spacer structure 1100 can include a first spacer 1110 and a second spacer 1120. The first spacer 1110 can be along the sidewall of the bit line 210 and is attached to the bit line 210, while the second spacer 1120 is attached to the side of the first spacer 1110 opposite to the bit line 210. The first spacer 1110 and the second spacer 1120 can be made of one of silicon oxide, silicon nitride, silicon oxide nitride (SiON), silicon oxide carbon nitride (SiOCN), air, and combinations thereof.

[0063] In some embodiments, such as Figure 3 As shown, the semiconductor structure 100 also includes a gate conductive layer 131, which is disposed on the gate dielectric layer 140; the material of the gate conductive layer 131 includes, but is not limited to, conductive materials such as tungsten, copper, and silver.

[0064] In some embodiments, the semiconductor structure further includes a barrier layer 134, which is located between the gate dielectric layer 140 and the gate conductive layer 131, i.e., the barrier layer 134 is disposed outside the gate conductive layer 131; wherein, the gate semiconductor layer 132 is located on the barrier layer 134 and the gate conductive layer 131, and is in direct contact with the barrier layer 134 and the gate conductive layer 131. In this embodiment, by providing the barrier layer 134 and disposing of it outside the gate conductive layer 131, metal migration in the gate conductive layer 131 can be prevented by the barrier layer 134. In addition, the barrier layer 134 can increase the adhesion between the gate conductive layer 131 and the gate dielectric layer 140, thereby improving the overall performance of the semiconductor structure.

[0065] In some embodiments, the material of the gate dielectric layer 140 includes, but is not limited to, silicon oxide, silicon nitride, silicon nitride, and / or a high dielectric constant material having a higher dielectric constant than silicon oxide. The gate conductive layer 131 may be manufactured using at least one of a metallic material, a conductive metal nitride, and combinations thereof, such as at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), and combinations thereof.

[0066] Furthermore, the material of the barrier layer 134 includes, but is not limited to, titanium nitride (TiN), or a composite layer formed of titanium (Ti) and titanium nitride (TiN), such as titanium / titanium nitride (Ti / TiN). The barrier layer 134 is located between the gate dielectric layer 140 and the gate conductive layer 131, such that a portion or all of the outer wall of the gate conductive layer 131 is in contact with the gate dielectric layer 140 through the barrier layer 134. This increases the adhesion reliability between the gate dielectric layer 140 and the gate conductive layer 131.

[0067] In some embodiments, please refer to Figure 4 As shown, the gap 150 is located near the edge of the gate semiconductor layer 132, that is, the gap 150 is located at the junction of the barrier layer 134 and the gate semiconductor layer 132. In this way, the overall performance of the semiconductor device can be guaranteed to be unaffected by the gap 150.

[0068] In some embodiments, please continue to refer to Figure 4 As shown, the gate semiconductor layer 132 with gap 150 is in direct contact with both the barrier layer 134 and the gate conductive layer 131. Specifically, the bottom of the gate semiconductor layer 132 is in direct contact with the top of the barrier layer 134 and the gate conductive layer 131. In this way, the overall performance of the semiconductor device can be guaranteed to be unaffected by the gap 150.

[0069] In order to ensure that the overall performance of the semiconductor device is not affected by the gap 150, in this embodiment of the application, the gap 150 is set in a preset area to improve the overall performance of the semiconductor device.

[0070] In some embodiments, such as Figure 2 and Figure 3 As shown, a preset region 160 is formed by the midpoints (e.g., A, C) of two adjacent sides of the gate semiconductor layer 132 and the intersection point (e.g., B) of the two adjacent sides. A gap 150 is disposed within the preset region 160. In this way, by setting the gap 150 within the set region, the influence of the gap 150 on the performance of the semiconductor device can be avoided.

[0071] For example, the cross-section of the gate semiconductor layer 132 has multiple sides, and the boundary line of the preset region 160 passes through the midpoint of two adjacent sides and the intersection of two adjacent sides. The outer contour of the preset region 160 can be a circle, a rectangle, a rounded rectangle, etc., and the preset region 160 is mainly used to determine the location of the gap 150.

[0072] In some embodiments, such as Figure 2 and Figure 3 As shown, the gate semiconductor layer 132 includes a first side and a second side, which are respectively enclosed by the endpoint (B) of the first side, the midpoint (A) of the first side and the midpoint (C) of the second side to form a triangular region, and the triangular region forms a preset region 160.

[0073] In this embodiment of the application, the endpoint of the first side can be the endpoint of the first side that connects to the second side, or it can be the endpoint of the first side that is far from the second side. For example... Figure 2 and Figure 3 As shown in the figure, point A is the midpoint of the first side, point B is the endpoint of the first side, and point C is the midpoint of the second side.

[0074] In some embodiments, such as Figure 2 and Figure 3 As shown, the triangular region at least partially overlaps with the gate semiconductor layer 132. For example, part or all of the triangular region overlaps with the gate semiconductor layer 132. The overlapping part is called the overlapping region, and at least one of the plurality of gaps 150 is located in the overlapping region to avoid or improve the impact of the gaps 150 on the overall performance of the semiconductor device.

[0075] In addition, the outline shape of the gap 150 can be a ring structure formed by any curve.

[0076] In some embodiments, please refer to Figure 4 and Figure 5At least one gap 150 is in direct contact with the gate dielectric layer 140. In this way, the gap 150 is closer to the edge of the gate semiconductor layer 132, thereby avoiding or improving the impact of the gap 150 on the overall performance of the semiconductor device.

[0077] In this embodiment, at least one of the gaps 150 is attached to the sidewall of the gate dielectric layer 140. That is, the gap 150 is actually formed by the gate semiconductor layer 132 and the gate dielectric layer 140 together, and the gap 150 is formed by removing a portion of the outer wall of the complete gate semiconductor layer 132. Furthermore, the gap 150 does not penetrate the gate dielectric layer 140, meaning it does not contact the active region 120, thus avoiding any impact of the gap 150 on the overall performance of the semiconductor device. In some embodiments, such as... Figure 4 and Figure 5 As shown, a portion of the gap 150 is located in the gate dielectric layer 140, such that the distance between the gap 150 and the active region 120 is smaller than the distance between the gate semiconductor layer 132 and the active region 120. In this way, the gap 150 is closer to the edge of the gate semiconductor layer 132, which can avoid the gap 150 from affecting the overall performance of the semiconductor device, and the gap 150 will not contact the active region 120 to avoid leakage.

[0078] In some embodiments, such as Figures 2-5 As shown, a gap 150 is formed between the barrier layer 134, the gate dielectric layer 140 and the gate semiconductor layer 132. That is, the gap 150 is formed at the junction of the barrier layer 134, the gate dielectric layer 140 and the gate semiconductor layer 132. In this way, the gap 150 can be avoided from affecting the overall performance of the semiconductor device.

[0079] For example, the gap 150 is formed by the barrier layer 134, the gate dielectric layer 140, and the gate semiconductor layer 132. In this case, the gap 150 can be located at the junction of the barrier layer 134 and the gate semiconductor layer 132, and the gap 150 is located on the outer wall of the gate semiconductor layer 132 to achieve contact with the gate dielectric layer 140. Alternatively, the end of the gap 150 can also penetrate into the barrier layer 134 and / or the gate dielectric layer 140. Alternatively, the gap 150 can also be located in the gate semiconductor layer 132 near the junction of the gate semiconductor layer 132 itself with the barrier layer 134 and the gate dielectric layer 140, but the gap 150 does not contact the barrier layer 134 and the gate dielectric layer 140.

[0080] In some embodiments, such as Figure 4 and Figure 5As shown, the gate electrode 130 also includes a gate insulating layer 133. A gap 150 is formed between the gate insulating layer 133, the gate semiconductor layer 132 and the gate dielectric layer 140. By setting the gap 150 at this location, the impact of the gap 150 on the overall performance of the semiconductor device can be avoided.

[0081] In this embodiment, the gap 150 may be located at the junction of the gate insulating layer 133 and the gate semiconductor layer 132, and the gap 150 may be located on the outer wall of the gate semiconductor layer 132 to achieve contact with the barrier layer 134 and the gate dielectric layer 140. Alternatively, the end of the gap 150 may also penetrate into the barrier layer 134 and / or the gate insulating layer 133. Alternatively, the gap 150 may also be located in the gate semiconductor layer 132 near the junction of the gate semiconductor layer 132 itself with the gate insulating layer 133 and the gate dielectric layer 140, but the gap 150 does not contact the gate insulating layer 133 and the gate dielectric layer 140.

[0082] In some embodiments, such as Figure 5 As shown, the gate semiconductor layer 132 has an arc-shaped corner between at least two adjacent sides. For example, the cross-section of the gate semiconductor layer 132 has multiple sides. For each pair of adjacent sides, at least one pair of adjacent sides has an arc-shaped corner at the junction. This arc-shaped corner makes the edge of the gate semiconductor layer 132 an arc-shaped edge, thus reducing adhesion between the gate semiconductor layer 132 and adjacent materials to form gaps 150, thereby avoiding the impact of gaps 150 on the overall performance of the semiconductor device.

[0083] In some embodiments, the work function of the gate conductive layer 131 is greater than the work function of the gate semiconductor layer 132. For example, the work function of the gate conductive layer 131 can be set to 4.5 eV to 4.6 eV, and the work function of the gate semiconductor layer 132 can be set to less than 4.5 eV. More specifically, the material of the gate conductive layer 131 may include tungsten (W) with a work function of 4.5 eV; the material of the gate semiconductor layer 132 may include tungsten nitride (WN) with a work function equal to 4.3 eV.

[0084] In some embodiments, such as Figure 2 As shown, at least a portion of the gap 150 is located on and in direct contact with the barrier layer 134. For example, the end of the gap 150 penetrates into the barrier layer 134, that is, a portion of the barrier layer 134 is removed, and the barrier layer 134 and the gate semiconductor layer 132 together enclose the gap 150. In this way, the gap 150 can be made closer to the edge of the gate semiconductor layer 132 to avoid the gap 150 affecting the overall performance of the semiconductor device.

[0085] In some embodiments, such as Figure 2 As shown, the gap 150 also directly contacts the gate dielectric layer 140 and the gate semiconductor layer 132. Exemplarily, the end of the gap 150 simultaneously penetrates the barrier layer 134, the gate dielectric layer 140, and the gate semiconductor layer 132. The gap 150 is formed by the barrier layer 134, the gate dielectric layer 140, and the gate semiconductor layer 132 together. This allows the gap 150 to be closer to the edge of the gate semiconductor layer 132, thus avoiding any impact of the gap 150 on the overall performance of the semiconductor device. For specific manufacturing of the semiconductor structure 100 provided in this embodiment, please refer to [reference needed]. Figure 6 An active region 120 defined by an isolation structure 121 is provided in the substrate 110. A gate trench is provided in the substrate, and a gate dielectric layer 140, a barrier layer 134, a gate semiconductor layer 132, and a gate insulating layer 133 are deposited sequentially into the gate trench. As can be seen from the figure, the gaps 150 are mainly distributed on both sides of the gate semiconductor layer 132, that is, mainly distributed at the junction of the gate semiconductor layer 132 and the barrier layer 134, and at the junction of the gate semiconductor layer 132 and the gate insulating layer 133. In other words, the gaps 150 in this application are mainly distributed at the edge of the gate semiconductor layer 132, which can avoid affecting the performance of the semiconductor device.

[0086] The fabrication method of the semiconductor structure will be described below with reference to the accompanying drawings. Please refer to... Figure 7 Multiple isolation trenches are etched in the substrate 110 to form an array, and isolation material is filled in the isolation trenches to form an isolation structure 121, which defines the active region 120. Then, gate trenches 135 are formed on the substrate 110, passing through the active region 120 and the isolation structure 121 and extending along the second direction (D2). The multiple gate trenches 135 are arranged at equal intervals along the first direction D1. After that, a gate dielectric layer (not shown in the figure) is deposited on the trench walls of the gate trenches 135.

[0087] Please refer to Figure 8 , Figure 9 After forming a gate dielectric layer on the trench wall of the gate trench 135, a barrier layer 134 and a gate conductive layer 131 are sequentially deposited on the gate dielectric layer. An etch-back process is then performed on the barrier layer 134 and the gate conductive layer 131. The remaining barrier layer 134 and the gate conductive layer 131 are then... Figure 10 As shown, it has an uneven surface, further reference Figure 11A gate semiconductor layer 132 is deposited on top of the remaining barrier layer 134 and gate conductive layer 131. The process can be adjusted to minimize gaps at the interface between the gate semiconductor layer 132 and the gate conductive layer 131, ensuring that gaps 150 are mostly present at the interface between the gate semiconductor layer 132 and the barrier layer 134. Then, an etch-back process is performed on the gate semiconductor layer 132, resulting in grooves on its surface. Finally, refer to... Figure 12 After the gate insulating layer 133 is deposited in the gate semiconductor layer 132, a gap 150 will eventually be formed because the groove is not filled by the gate insulating layer 133.

[0088] As can be seen, in the semiconductor structure provided in this application embodiment, by adjusting the process, unavoidable gaps are set in a preset area. For example, the gaps are set at the edge of the gate semiconductor layer of the gate electrode, and the gaps do not directly contact the active region. In this way, while ensuring the small size of the semiconductor structure, the impact of gaps on the performance of the semiconductor device can be avoided, thereby improving the yield of the semiconductor structure.

[0089] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0090] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes an isolation structure and an active region defined by the isolation structure; A gate trench is disposed within the substrate; A gate electrode is located within the gate trench, and the gate electrode includes a gate semiconductor layer; Multiple gaps are located within the gate trench, and at least a portion of at least one of the gaps is located in the gate semiconductor layer; The gate semiconductor layer includes an adjacent first side and a second side, which are respectively enclosed by the endpoint of the first side, the midpoint of the first side and the midpoint of the second side to form a triangular region. The endpoint of the first side is the endpoint where the first side and the second side meet. The at least one of the gaps is located in the triangular region.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes a gate dielectric layer; The gate electrode further includes: A gate conductive layer is disposed on the gate dielectric layer; A barrier layer is located between the gate dielectric layer and the gate conductive layer; The gate semiconductor layer is located on the barrier layer and the gate conductive layer, and is in direct contact with the barrier layer and the gate conductive layer.

3. The semiconductor structure according to claim 2, characterized in that, The triangular region at least partially overlaps with the gate semiconductor layer, and at least one of the gaps is located in the overlapping region.

4. The semiconductor structure according to claim 2, characterized in that, At least one of the gaps is in direct contact with the gate dielectric layer.

5. The semiconductor structure according to claim 4, characterized in that, A portion of the void is located in the gate dielectric layer such that the spacing between the void and the active region is smaller than the spacing between the gate semiconductor layer and the active region.

6. The semiconductor structure according to claim 2, characterized in that, The gap is formed between the barrier layer, the gate dielectric layer and the gate semiconductor layer.

7. The semiconductor structure according to claim 2, characterized in that, The gate electrode further includes a gate insulating layer, and the gap is formed between the gate insulating layer, the gate semiconductor layer and the gate dielectric layer.

8. The semiconductor structure according to any one of claims 1-6, characterized in that, The gate semiconductor layer has an arc-shaped corner between at least two adjacent sides.

9. The semiconductor structure according to claim 2, characterized in that, The work function of the gate conductive layer is greater than the work function of the gate semiconductor layer.

10. The semiconductor structure according to claim 2, characterized in that, At least a portion of the gap is located on the barrier layer and is in direct contact with the barrier layer.

11. The semiconductor structure according to claim 10, characterized in that, The gap also directly contacts the gate dielectric layer and the gate semiconductor layer.

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