An oxide thin film transistor device and its preparation method and related equipment

Abstract

The present application provides an oxide thin film transistor device and a method for preparing the same, as well as related equipment, relating to the field of semiconductor technology. The present application sequentially prepares a first electrode layer, an insulating layer, and a second electrode layer on a substrate, such that an oxide layer is provided between the second electrode layer and / or the first electrode layer and the insulating layer, and ensures that the sides of the second electrode layer, the insulating layer, and the oxide layer are aligned. A semiconductor layer, a gate dielectric layer, and a gate electrode layer are then sequentially prepared, such that an ohmic contact or quasi-ohmic contact is formed between the semiconductor layer and the first electrode layer and the second electrode layer, respectively, and a depletion region is formed in a local area directly in contact with the oxide layer, so that the short channel effect of the transistor device is suppressed by the formed depletion region, the range of electrode material selection is expanded, and the thickness requirement for the semiconductor layer is reduced, thereby facilitating the preparation of high-performance semiconductor devices with ultra-short channels.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an oxide thin film transistor device, a preparation method thereof, and related equipment. Background Art

[0002] With the continuous advancement of technology, the related technical requirements of many high-tech technologies such as high-resolution active-matrix display technology, dynamic random access memory (DRAM) technology, and flexible integrated circuit technology are driving the development of thin-film transistors towards short channels, high mobility, and high stability. Among them, oxide thin-film transistors (TFTs), represented by indium gallium zinc oxide (IGZO), have become one of the key research targets in the current semiconductor field due to their high carrier mobility, extremely low leakage current, and excellent electrical uniformity over large areas.

[0003] However, as the channel size decreases, oxide thin-film transistors tend to lose their switching characteristics due to the short channel effect. The main reasons for the short channel effect in oxide thin-film transistors are: (1) the use of metal materials with low work function (e.g., aluminum) to prepare electrodes causes the metal electrode to transfer carriers to the semiconductor layer, thereby causing the free carrier concentration of the semiconductor layer to be too high; (2) oxidation occurs at the contact interface between the metal electrode and the semiconductor layer, resulting in a significant increase in the oxygen vacancy concentration of the semiconductor layer at the contact interface, thereby causing the free carrier concentration of the semiconductor layer to be too high; (3) the electrode material of the metal electrode diffuses into the semiconductor layer, causing donor doping, thereby causing the free carrier concentration of the semiconductor layer to be too high.

[0004] At present, in order to solve the problem that short-channel semiconductor devices are prone to failure due to the short-channel effect, the mainstream industry usually uses metal materials with relatively stable chemical properties and high work functions to prepare source / drain electrodes, and the semiconductor layer needs to be prepared to a relatively thin state. However, it is worth noting that the use of metal materials with high work functions to prepare source / drain electrodes, although it can to a certain extent prevent the transfer of carriers from the metal electrode to the semiconductor layer, will also form a certain Schottky barrier between the source / drain electrode and the semiconductor layer, resulting in an increase in contact resistance, which will cause a current crowding effect and cause the corresponding semiconductor device to deviate from the ideal electrical characteristics; at the same time, the use of thinner semiconductor layers will also cause the carrier concentration of the semiconductor layer to be more sensitive to changes in the materials and preparation processes of other film layers (for example, the gate dielectric layer or the passivation layer, etc.), and put forward more stringent requirements on the preparation conditions of semiconductor devices. Summary of the Invention

[0005] In view of this, the purpose of the present application is to provide an oxide thin film transistor device and a preparation method thereof, a dynamic random access memory and a display panel, which can form a depletion region in the semiconductor layer at the contact area with the oxide layer by introducing an oxide layer. Even if the electrode material used increases the free carrier concentration of the semiconductor layer due to factors such as low work function, oxidation of the contact interface or material diffusion doping, the depletion region formed can effectively reduce the free carrier concentration in the channel region of the semiconductor layer, ensuring that the entire transistor device can easily achieve channel pinch-off, thereby effectively suppressing the short channel effect, and effectively expanding the selection range of electrode materials, reducing the layer thickness requirements for the semiconductor layer, which is beneficial to the preparation of high-performance semiconductor devices with ultra-short channels.

[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, the present application provides an oxide thin film transistor device, the transistor device comprising:

[0008] substrate;

[0009] a first electrode layer disposed on the substrate;

[0010] an insulating layer and a second electrode layer stacked in sequence on a side of the first electrode layer away from the substrate, wherein an oxide layer is provided between the second electrode layer and / or the first electrode layer and the insulating layer, and the second electrode layer, the insulating layer, and the oxide layer are aligned laterally;

[0011] a semiconductor layer grown along sidewalls of the insulating layer and the oxide layer, wherein the semiconductor layer covers the outer surface of the second electrode layer away from the substrate and covers a target surface area of ​​the outer surface of the first electrode layer away from the substrate, the target surface area not being covered by the insulating layer or the oxide layer; wherein the first electrode layer and the second electrode layer respectively form an ohmic contact or a quasi-ohmic contact with the semiconductor layer, and a local area of ​​the semiconductor layer that is in direct contact with the oxide layer forms a depletion region;

[0012] A gate dielectric layer covering the semiconductor layer, and a gate electrode layer covering the gate dielectric layer.

[0013] In an optional embodiment, when the number of the oxide layer is one, the electrode layer close to the oxide layer in the first electrode layer and the second electrode layer is used as a source electrode layer, and the remaining electrode layer is used as a drain electrode layer;

[0014] When the number of the oxide layers is two, any one of the first electrode layer and the second electrode layer is used as a source electrode layer, and the remaining electrode layer is used as a drain electrode layer.

[0015] In an optional embodiment, the first electrode layer, the second electrode layer and the gate electrode layer each have a thickness ranging from 5 to 1000 nm;

[0016] The thickness of the insulating layer is in the range of 5-1000 nm;

[0017] The thickness of the oxide layer is in the range of 5-500 nm;

[0018] The thickness of the semiconductor layer is in the range of 1-200 nm;

[0019] The thickness of the gate dielectric layer is in the range of 5-500 nm.

[0020] In an optional embodiment, the gate electrode layer, the first electrode layer, and the second electrode layer are each made of any one of aluminum, molybdenum, tantalum, titanium, chromium, copper, tungsten, nickel, platinum, palladium, gold, cobalt, indium tin oxide, fluorine-doped tin oxide, and aluminum-doped zinc oxide.

[0021] The insulating layer and the gate dielectric layer are each made of at least one of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide;

[0022] The material of the oxide layer is a P-type oxide material, and the material of the semiconductor layer is an N-type semiconductor material, wherein the P-type oxide material includes at least one of copper oxide, nickel oxide, tin oxide, chromium oxide, cobalt oxide, molybdenum oxide, tellurium oxide, tungsten oxide, and germanium oxide, and the N-type semiconductor material is any one of indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth-doped indium zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide, and tin oxide;

[0023] Alternatively, the material of the oxide layer is an N-type oxide material, and the material of the semiconductor layer is a P-type semiconductor material, wherein the N-type oxide material includes at least one of zinc oxide, gallium oxide, indium oxide, tin oxide and titanium oxide, and the P-type semiconductor material is any one of tellurium oxide, tellurium selenide oxide, copper oxide, copper chromium oxide, nickel oxide, nickel lithium oxide, tin oxide, tin copper oxide, and tin copper nickel oxide.

[0024] In a second aspect, the present application provides a method for preparing an oxide thin film transistor device, the method comprising:

[0025] Providing a substrate, and depositing a first electrode layer on one surface of the substrate;

[0026] forming an insulating layer, a second electrode layer, and an oxide layer on a surface of the first electrode layer away from the substrate to obtain an intermediate-stage device, wherein the insulating layer is between the first electrode layer and the second electrode layer, an oxide layer is spaced apart from the insulating layer by the first electrode layer and / or the second electrode layer, and the second electrode layer, the insulating layer, and the oxide layer are laterally aligned;

[0027] A semiconductor layer, a gate dielectric layer and a gate electrode layer are sequentially prepared on the outer surface of the intermediate stage device away from the substrate, wherein the semiconductor layer simultaneously covers the outer surface of the second electrode layer away from the substrate, and a target surface area of ​​the outer surface of the first electrode layer away from the substrate, wherein the target surface area is not covered by the insulating layer or the oxide layer; the first electrode layer and the second electrode layer respectively form an ohmic contact or a quasi-ohmic contact with the semiconductor layer, a local area of ​​the semiconductor layer directly in contact with the oxide layer forms a depletion region, the gate dielectric layer covers the semiconductor layer, and the gate electrode layer covers the gate dielectric layer.

[0028] In an optional embodiment, when the number of the oxide layer is one and the insulating layer and the first electrode layer are separated by the oxide layer, the first electrode layer is used as a source electrode layer, and the second electrode layer is used as a drain electrode layer; in this case, the step of forming the insulating layer, the second electrode layer, and the oxide layer on the surface of the first electrode layer away from the substrate to obtain the intermediate-stage device includes:

[0029] forming an oxide layer on a surface of the first electrode layer away from the substrate by atomic layer deposition or magnetron sputtering;

[0030] forming an insulating layer by growing the insulating layer on a surface of the oxide layer away from the substrate based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method;

[0031] forming a second electrode layer on a surface of the insulating layer away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation;

[0032] The prepared second electrode layer, the insulating layer and the oxide layer are sequentially subjected to photolithographic patterning to obtain the intermediate stage device, wherein the second electrode layer, the insulating layer and the oxide layer are aligned in side surface after patterning.

[0033] In an optional embodiment, when the number of the oxide layer is one and the insulating layer and the second electrode layer are separated by the oxide layer, the second electrode layer is used as a source electrode layer, and the first electrode layer is used as a drain electrode layer; in this case, the step of forming the insulating layer, the second electrode layer, and the oxide layer on the surface of the first electrode layer away from the substrate to obtain the intermediate-stage device includes:

[0034] forming an insulating layer on a surface of the first electrode layer on a side away from the substrate by growing the insulating layer based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method;

[0035] forming an oxide layer on a surface of the insulating layer away from the substrate by atomic layer deposition or magnetron sputtering;

[0036] forming a second electrode layer on a surface of the oxide layer away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation;

[0037] The prepared second electrode layer, the oxide layer and the insulating layer are sequentially subjected to photolithographic patterning to obtain the intermediate stage device, wherein the second electrode layer, the oxide layer and the insulating layer are aligned in side surface after patterning.

[0038] In an optional embodiment, when the number of the oxide layers is two, and the second electrode layer and the first electrode layer are both separated from the insulating layer by an oxide layer, any one of the first electrode layer and the second electrode layer is used as a source electrode layer, and the remaining electrode layer is used as a drain electrode layer; in this case, the step of forming the insulating layer, the second electrode layer, and the oxide layer on the surface of the first electrode layer away from the substrate to obtain the intermediate stage device includes:

[0039] forming a first oxide layer on a surface of the first electrode layer away from the substrate by atomic layer deposition or magnetron sputtering;

[0040] forming an insulating layer by growing the insulating layer on a surface of the first oxide layer away from the substrate based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method;

[0041] forming a second oxide layer on a surface of the insulating layer away from the substrate by atomic layer deposition or magnetron sputtering;

[0042] forming a second electrode layer on a surface of the second oxide layer away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation;

[0043] The prepared second electrode layer, the second oxide layer, the insulating layer and the first oxide layer are sequentially photolithographically patterned to obtain the intermediate stage device, wherein the patterned second electrode layer, the second oxide layer, the insulating layer and the first oxide layer are laterally aligned.

[0044] In a third aspect, the present application provides a dynamic random access memory, which includes a plurality of oxide thin film transistor devices as described in any one of the aforementioned embodiments, and the plurality of oxide thin film transistor devices cooperate with each other to realize a dynamic data storage function.

[0045] In a fourth aspect, the present application provides a display panel, which includes a pixel unit array and a plurality of oxide thin film transistor devices as described in any one of the aforementioned embodiments, wherein the plurality of oxide thin film transistor devices cooperate with each other to form a driving circuit for the pixel unit array.

[0046] In this case, the beneficial effects of the embodiments of the present application are:

[0047] The present application sequentially prepares a first electrode layer, an insulating layer, and a second electrode layer on a substrate, so that an oxide layer is provided between the second electrode layer and / or the first electrode layer and the insulating layer, and ensures that the sides of the second electrode layer, the insulating layer, and the oxide layer are aligned. Then, a semiconductor layer is prepared that covers the first electrode layer and the second electrode layer at the same time, so that the semiconductor layer can form an ohmic contact or a quasi-ohmic contact with the first electrode layer and the second electrode layer, respectively, and directly contact the side walls of the insulating layer and the oxide layer, so as to facilitate the formation of a depletion region in the local area of ​​the semiconductor layer that is in direct contact with the oxide layer. Then, a gate dielectric layer and a gate electrode layer are sequentially prepared on the semiconductor layer, so that by introducing the oxide layer, a depletion region is formed in the contact area of ​​the semiconductor layer with the oxide layer, thereby overcoming the short channel effect of the short channel device. Therefore, when adopting the technical solution of the present application, even if the electrode material used will increase the free carrier concentration of the semiconductor layer due to factors such as low work function, contact interface oxidation or material diffusion doping, the depletion region in the present application can also effectively reduce the free carrier concentration in the channel region of the semiconductor layer, ensuring that the entire transistor device can easily achieve channel pinch-off, so as to effectively suppress the short channel effect, expand the selection range of electrode materials, reduce the layer thickness requirements for the semiconductor layer, and benefit the preparation of ultra-short channel high-performance semiconductor devices.

[0048] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 A schematic diagram of the composition of a first oxide thin film transistor device provided in an embodiment of the present application;

[0051] Figure 2 A schematic diagram of the composition of a second oxide thin film transistor device provided in an embodiment of the present application;

[0052] Figure 3 This is a schematic diagram of the composition of the third oxide thin film transistor device provided in an embodiment of the present application;

[0053] Figure 4 The second schematic diagram of the composition of the third oxide thin film transistor device provided in the embodiment of the present application;

[0054] Figure 5 A schematic flow chart of a method for preparing an oxide thin film transistor device according to an embodiment of the present application;

[0055] Figure 6 for Figure 5 One of the flowcharts of the sub-steps included in step S220;

[0056] Figure 7 This is one of the schematic diagrams for manufacturing an intermediate stage device provided in an embodiment of the present application;

[0057] Figure 8 for Figure 5 2 is a flow chart of the sub-steps included in step S220;

[0058] Figure 9 The second schematic diagram of the fabrication of the intermediate stage device provided in the embodiment of the present application;

[0059] Figure 10 for Figure 5 Flowchart 3 of the sub-steps included in step S220;

[0060] Figure 11 This is the third schematic diagram of the fabrication of the intermediate stage device provided in the embodiment of the present application.

[0061] Icon: 10-oxide thin film transistor device; 11-substrate; 12-first electrode layer; 13-insulating layer; 14-second electrode layer; 15-oxide layer; 16-semiconductor layer; 17-gate dielectric layer; 18-gate electrode layer; 19-depletion region. DETAILED DESCRIPTION

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0063] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0064] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0065] In the description of this application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the application is usually placed when in use, or are the orientation or position relationship commonly understood by those skilled in the art. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0066] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0067] In addition, in the description of the present application, it is understood that relational terms such as the terms "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0068] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0069] Please refer to Figure 1 , Figure 1 Schematic diagram of the composition of the first oxide thin film transistor device 10 provided in an embodiment of the present application. In the embodiment of the present application, the oxide thin film transistor device 10 provided in the present application can form a depletion region in the contact area of ​​the semiconductor layer with the oxide layer by introducing an oxide layer. Even if the electrode material used increases the free carrier concentration of the semiconductor layer due to factors such as low work function, oxidation of the contact interface, or diffusion doping of the material, the depletion region in the present application can effectively reduce the free carrier concentration in the channel region of the semiconductor layer, ensuring that the entire transistor device can easily achieve channel pinch-off, thereby effectively suppressing the short channel effect, and expanding the range of electrode material selection (i.e., the corresponding electrode material does not need to be limited to high work function materials), reducing the layer thickness requirement of the semiconductor layer (i.e., the corresponding semiconductor layer does not need to be prepared to a relatively thin state), which is beneficial to the preparation of high-performance semiconductor devices with ultra-short channels.

[0070] In the embodiments of this application, Figure 1 The oxide thin film transistor device 10 shown may include a substrate 11 , a first electrode layer 12 , an insulating layer 13 , a second electrode layer 14 , a semiconductor layer 16 , a gate dielectric layer 17 , a gate electrode layer 18 and an oxide layer 15 .

[0071] In an embodiment of the present application, the first electrode layer 12 is arranged on the substrate 11; the insulating layer 13 and the second electrode layer 14 are stacked on each other on the side surface of the first electrode layer 12 away from the substrate 11, the insulating layer 13 is between the first electrode layer 12 and the second electrode layer 14, and an oxide layer 15 is separated from the insulating layer 13 and the first electrode layer 12; the second electrode layer 14, the insulating layer 13 and the oxide layer 15 are aligned laterally, that is, the projection areas of the second electrode layer 14, the insulating layer 13 and the oxide layer 15 on the substrate 11 overlap with each other; the projection area of ​​the second electrode layer 14 on the substrate 11 is within the projection area of ​​the first electrode layer 12 on the substrate 11.

[0072] In this embodiment, the semiconductor layer 16 grows along the aligned sidewalls of the insulating layer 13 and the oxide layer 15, and covers the outer surface of the second electrode layer 14 away from the substrate 11. It also covers the target surface area of ​​the outer surface of the first electrode layer 12 away from the substrate 11 that is not covered by the oxide layer 15. At this time, the first electrode layer 12 forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer 16, and the second electrode layer 14 also forms an ohmic contact or a quasi-ohmic contact with the semiconductor layer 16.

[0073] In this embodiment, the gate dielectric layer 17 is arranged on the outer surface of the semiconductor layer 16 away from the substrate 11 and covers the semiconductor layer 16; the gate electrode layer 18 is arranged on the outer surface of the gate dielectric layer 17 away from the substrate 11 and covers the gate dielectric layer 17.

[0074] In this embodiment, Figure 1 The oxide layer 15 is arranged closer to the first electrode layer 12 than the second electrode layer 14. In this case, the first electrode layer 12 is used as a source electrode layer, and the second electrode layer 14 is used as a drain electrode layer. Figure 1 The oxide layer 15 and the semiconductor layer 16 are made of different materials. For example, the material used in the oxide layer 15 needs to have a large work function difference with the material used in the semiconductor layer 16, the oxide layer 15 uses a P-type oxide material and the semiconductor layer 16 uses an N-type semiconductor material, or the oxide layer 15 uses an N-type oxide material and the semiconductor layer 16 uses a P-type semiconductor material, so that Figure 1When the oxide thin film transistor device 10 shown is operating in a saturated state, the oxide thin film transistor device 10 may form a depletion region 19 in a local area of ​​the semiconductor layer 16 that is in direct contact with the oxide layer 15. The depletion region 19 extends from the side where the first electrode layer 12 (i.e., the source electrode layer) achieves ohmic (quasi-ohmic) contact to the side where the second electrode layer 14 (i.e., the drain electrode layer) is located, and reaches the interface between the semiconductor layer 16 and the gate dielectric layer 17 on the side of the second electrode layer 14 (see Figure 1 The expansion distribution of the depletion region 19 in the embodiment of the present invention is used to achieve the pinch-off effect of the channel.

[0075] Therefore, the application provides Figure 1 The oxide thin film transistor device 10 shown can form a depletion region 19 at the contact area between the semiconductor layer 16 and the oxide layer 15. Even if the electrode material used in the oxide thin film transistor device 10 provided in this application increases the free carrier concentration of the semiconductor layer 16 due to factors such as low work function, contact interface oxidation, or material diffusion doping, the depletion region 19 in this application will effectively reduce its own free carrier concentration in the channel region of the semiconductor layer 16, ensuring that the entire transistor device is still easy to achieve channel pinch-off, thereby effectively suppressing the short channel effect, expanding the range of electrode material selection, and reducing the thickness requirement for the semiconductor layer 16. Therefore, the oxide thin film transistor device 10 provided in this application is substantially beneficial for the preparation of high-performance semiconductor devices with ultra-short channels, and can improve the reliability of corresponding products in application scenarios such as high-resolution active matrix display technology, dynamic random access memory technology, and flexible integrated circuit technology.

[0076] In the embodiment of the present application, the substrate 11 can be a rigid substrate such as glass or silicon dioxide, or a flexible organic polymer substrate such as polyimide or polyethylene naphthalate. It is understood that the actual type of the substrate 11 includes but is not limited to the aforementioned examples, and any substrate material that can be used to prepare a conventional oxide thin film transistor device falls within the scope of protection of this application.

[0077] In the embodiment of the present application, the thickness of each of the first electrode layer 12, the second electrode layer 14, and the gate electrode layer 18 is in the range of 5-1000 nm. The electrode materials used for the gate electrode layer 18, the first electrode layer 12, and the second electrode layer 14 can be metals, alloys, or transparent conductive oxide materials. In one implementation of this embodiment, the electrode materials used for each of the gate electrode layer 18, the first electrode layer 12, and the second electrode layer 14 are any one of aluminum, molybdenum, tantalum, titanium, chromium, copper, tungsten, nickel, platinum, palladium, gold, cobalt, indium tin oxide, fluorine-doped tin oxide, and aluminum-doped zinc oxide.

[0078] In the embodiment of the present application, the thickness of the insulating layer 13 is in the range of 5-1000 nm, and the thickness of the gate dielectric layer 17 is in the range of 5-500 nm; the material of each of the insulating layer 13 and the gate dielectric layer 17 is at least one of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide.

[0079] In the embodiment of the present application, the thickness of the semiconductor layer 16 is in the range of 1-200 nm, and the thickness of the oxide layer 15 is in the range of 5-500 nm; when the material of the oxide layer 15 is a P-type oxide material, the material of the semiconductor layer 16 is an N-type semiconductor material, wherein the P-type oxide material includes any one of copper oxide, nickel oxide, tin oxide, chromium oxide, cobalt oxide, molybdenum oxide, tellurium oxide, tungsten oxide, and germanium oxide, or a multi-component compound of the foregoing materials, and the N-type semiconductor material is indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth oxide, or a plurality of other materials. Any one of earth-doped indium zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide and tin oxide; when the material of the oxide layer 15 is an N-type oxide material, the material of the semiconductor layer 16 is a P-type semiconductor material, wherein the N-type oxide material includes any one of zinc oxide, gallium oxide, indium oxide, tin oxide and titanium oxide or a multinary compound of the foregoing materials, and the P-type semiconductor material is any one of tellurium oxide, tellurium selenide oxide, copper oxide, copper chromium oxide, nickel oxide, nickel lithium oxide, tin oxide, tin copper oxide, and tin copper nickel oxide.

[0080] Alternatively, see Figure 2 , Figure 2 Schematic diagram of the composition of the second oxide thin film transistor device 10 provided in the embodiment of the present application. Figure 1 Compared to the oxide thin film transistor device 10 shown, Figure 2 The oxide thin film transistor device 10 shown is Figure 1 The oxide thin film transistor device 10 shown has the same transistor device composition, but Figure 2 The oxide thin film transistor device 10 shown is Figure 1 The differences between the oxide thin film transistor devices 10 shown are mainly as follows: Figure 2 The oxide layer 15 in the oxide thin film transistor device 10 shown is arranged between the second electrode layer 14 and the insulating layer 13, and the first electrode layer 12 is in direct contact with the insulating layer 13. At this time, the target surface area covered by the semiconductor layer 16 is the surface area on the outer surface of the first electrode layer 12 away from the substrate 11 that is not covered by the insulating layer 13.

[0081] In this embodiment, Figure 2The oxide layer 15 is arranged closer to the second electrode layer 14 than the first electrode layer 12. In this case, the second electrode layer 14 is used as the source electrode layer, and the first electrode layer 12 is used as the drain electrode layer. Figure 2 When the oxide thin film transistor device 10 shown is operating in a saturated state, the oxide thin film transistor device 10 may form a depletion region 19 in a local area of ​​the semiconductor layer 16 that is in direct contact with the oxide layer 15. The depletion region 19 extends from the side where the second electrode layer 14 (i.e., the source electrode layer) achieves ohmic (quasi-ohmic) contact to the side where the first electrode layer 12 (i.e., the drain electrode layer) is located, and reaches the interface between the semiconductor layer 16 and the gate dielectric layer 17 on the side of the first electrode layer 12 (see Figure 2 The expansion distribution of the depletion region 19 in the embodiment of the present invention is used to achieve the pinch-off effect of the channel.

[0082] Therefore, the application provides Figure 2 The oxide thin-film transistor device 10 shown can also form a depletion region 19 at the contact area between the semiconductor layer 16 and the oxide layer 15. Even if the electrode material used in the oxide thin-film transistor device 10 provided in this application increases the free carrier concentration of the semiconductor layer 16 due to factors such as low work function, contact interface oxidation, or material diffusion doping, the depletion region 19 in this application will effectively reduce the free carrier concentration in the channel region of the semiconductor layer 16, ensuring that the entire transistor device can still easily achieve channel pinch-off, thereby effectively suppressing the short channel effect, expanding the range of electrode material selection, and reducing the thickness requirement for the semiconductor layer 16. Therefore, the oxide thin-film transistor device 10 provided in this application is substantially beneficial for the preparation of ultra-short channel high-performance semiconductor devices.

[0083] Optionally, please refer to Figure 3 and Figure 4 ,in Figure 3 This is one of the schematic diagrams of the composition of the third oxide thin film transistor device 10 provided in the embodiment of the present application. Figure 4 This is the second schematic diagram of the composition of the third oxide thin film transistor device 10 provided in the embodiment of the present application. Figure 1 or Figure 2 Compared to the oxide thin film transistor device 10 shown, Figure 3 or Figure 4 The practical differences of the oxide thin film transistor device 10 shown are mainly: Figure 3 or Figure 4The oxide thin film transistor device 10 shown includes two oxide layers 15, the first oxide layer 15 of the two oxide layers 15 is arranged between the first electrode layer 12 and the insulating layer 13, and the second oxide layer 15 of the two oxide layers 15 is arranged between the second electrode layer 14 and the insulating layer 13. Two depletion regions 19 are correspondingly formed in the semiconductor layer 16, the first depletion region 19 of the two depletion regions 19 is formed in a local area of ​​the semiconductor layer 16 that is in direct contact with the first oxide layer 15, and the second depletion region 19 of the two depletion regions 19 is formed in a local area of ​​the semiconductor layer 16 that is in direct contact with the second oxide layer 15.

[0084] In this embodiment, since the first electrode layer 12 and the second electrode layer 14 are respectively in direct contact with one oxide layer 15 , any one of the first electrode layer 12 and the second electrode layer 14 can serve as a source electrode layer, and the remaining electrode layer can serve as a drain electrode layer.

[0085] In the case where the first electrode layer 12 is used as a source electrode layer and the second electrode layer 14 is used as a drain electrode layer, if Figure 3 The oxide thin film transistor device 10 shown is operated in a saturated state. At this time, the first depletion region 19 in the oxide thin film transistor device 10 extends from the side where the first electrode layer 12 (i.e., the source electrode layer) realizes ohmic (quasi-ohmic) contact to the side where the second electrode layer 14 (i.e., the drain electrode layer) is located, and reaches the interface between the semiconductor layer 16 and the gate dielectric layer 17 on the side of the second electrode layer 14 (see Figure 3 At the same time, the second depletion region 19 in the oxide thin film transistor device 10 will expand from the insulating layer 13 to the side where the second electrode layer 14 (i.e., the drain electrode layer) realizes ohmic (quasi-ohmic) contact, and does not touch the interlayer interface between the semiconductor layer 16 and the gate dielectric layer 17 on the side close to the second electrode layer 14 (see Figure 3 The expansion distribution of the depletion region 19 on the upper side of the channel is achieved by pinching off the channel. Figure 3 The saturated output current of the oxide thin film transistor device 10 shown is mainly controlled by the extent of the expansion of the first depletion region 19 .

[0086] In the case where the first electrode layer 12 is used as a drain electrode layer and the second electrode layer 14 is used as a source electrode layer, if Figure 5The oxide thin film transistor device 10 shown is operated in a saturated state. At this time, the first depletion region 19 in the oxide thin film transistor device 10 extends from the insulating layer 13 to the side where the first electrode layer 12 (i.e., the drain electrode layer) realizes ohmic (quasi-ohmic) contact, and does not touch the interface between the semiconductor layer 16 and the gate dielectric layer 17 on the side close to the first electrode layer 12 (see Figure 4 At the same time, the second depletion region 19 in the oxide thin film transistor device 10 will expand from the side where the second electrode layer 14 (i.e., the source electrode layer) realizes ohmic (quasi-ohmic) contact to the side where the first electrode layer 12 (i.e., the drain electrode layer) is located, and until it touches the interlayer interface between the semiconductor layer 16 and the gate dielectric layer 17 on the side of the first electrode layer 12 (see Figure 4 The expansion distribution of the depletion region 19 on the upper side of the channel is achieved by pinching off the channel. Figure 4 The saturated output current of the oxide thin film transistor device 10 shown is mainly controlled by the extent of the expansion of the second depletion region 19 .

[0087] Therefore, the application provides Figure 3 or Figure 4 The oxide thin-film transistor device 10 shown can also form a depletion region 19 at the contact area between the semiconductor layer 16 and the oxide layer 15. Even if the electrode material used in the oxide thin-film transistor device 10 provided in this application increases the free carrier concentration of the semiconductor layer 16 due to factors such as low work function, contact interface oxidation, or material diffusion doping, the depletion region 19 in this application will effectively reduce the free carrier concentration in the channel region of the semiconductor layer 16, ensuring that the entire transistor device can still easily achieve channel pinch-off, thereby effectively suppressing the short channel effect, expanding the range of electrode material selection, and reducing the thickness requirement for the semiconductor layer 16. Therefore, the oxide thin-film transistor device 10 provided in this application is substantially beneficial for the preparation of ultra-short channel high-performance semiconductor devices.

[0088] In this application, to ensure Figure 1 、 Figure 2 、 Figure 3 or Figure 4 The oxide thin film transistor device 10 shown can be prepared and formed quickly and orderly so as to effectively suppress the short channel effect by forming a depletion region 19 in a local area of ​​the semiconductor layer 16 that is in direct contact with the oxide layer 15, reduce the thickness requirement of the semiconductor layer 16, and expand the range of choices for electrode materials. The embodiment of the present application achieves the above functions by providing a method for preparing an oxide thin film transistor device.

[0089] Please refer to Figure 5 , Figure 5: is a flow chart of a method for preparing an oxide thin film transistor device provided in an embodiment of the present application. In the embodiment of the present application, Figure 5 The preparation method shown may include steps S210 to S240 to prepare Figure 1 、 Figure 2 、 Figure 3 or Figure 4 The oxide thin film transistor device 10 is shown.

[0090] In step S210 , a substrate is provided, and a first electrode layer is deposited on a surface of one side of the substrate.

[0091] In this embodiment, the first electrode layer 12 can be deposited on one side surface of the substrate 11 using magnetron sputtering, thermal evaporation, or electron beam evaporation, and then the first electrode layer 12 can be photolithographically patterned so that the patterned first electrode layer 12 is aligned with the side surface of the substrate 11. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited first electrode layer 12 away from the substrate 11, and the photoresist layer can be patterned. Then, under the shielding effect of the patterned photoresist layer, the local area of ​​the first electrode layer 12 not covered by the photoresist layer can be etched to achieve the patterning effect of the first electrode layer 12, wherein acetone can be used to remove the patterned photoresist layer.

[0092] In step S220, an insulating layer, a second electrode layer and an oxide layer are formed on the surface of the first electrode layer away from the substrate to obtain an intermediate stage device, wherein the insulating layer is between the first electrode layer and the second electrode layer, the first electrode layer and / or the second electrode layer is separated from the insulating layer by an oxide layer, and the second electrode layer, the insulating layer and the oxide layer are aligned laterally.

[0093] In this embodiment, when the intermediate stage device includes only one oxide layer 15, and the insulating layer 13 and the first electrode layer 12 are separated by the oxide layer 15, the intermediate stage device is suitable for preparing Figure 1 The oxide thin film transistor device 10 shown in FIG. 1; when the intermediate stage device comprises only one oxide layer 15, and the insulating layer 13 and the second electrode layer 14 are separated by the oxide layer 15, the intermediate stage device is suitable for preparing Figure 2 The oxide thin film transistor device 10 shown; when the intermediate stage device includes two oxide layers 15, and the second electrode layer 14 and the first electrode layer 12 are separated from the insulating layer 13 by an oxide layer 15, the intermediate stage device is suitable for preparing Figure 3 or Figure 4 The oxide thin film transistor device 10 is shown.

[0094] Optionally, please refer to Figure 6 and Figure 7 ,in Figure 6 yes Figure 5 One of the flow charts of the sub-steps included in step S220, Figure 7 This is one of the schematic diagrams for manufacturing an intermediate stage device provided in the embodiment of the present application. In the embodiment of the present application, the step S220 may include sub-steps S221 to S224 to ensure that the prepared intermediate stage device is suitable for manufacturing Figure 1 The oxide thin film transistor device 10 is shown.

[0095] In sub-step S221 , an oxide layer is grown on the surface of the first electrode layer away from the substrate by atomic layer deposition or magnetron sputtering.

[0096] In this embodiment, Figure 7 (a) is a schematic diagram of a device in which an oxide layer 15 in the form of a complete film is prepared on the first electrode layer 12, wherein the oxide layer 15 may not require photolithography patterning during preparation, or may undergo preliminary photolithography patterning.

[0097] Sub-step S222 , growing an insulating layer on the surface of the oxide layer away from the substrate based on plasma enhanced chemical vapor deposition or atomic layer deposition.

[0098] In this embodiment, Figure 7 (b) is a schematic diagram of a device in which an insulating layer 13 in the form of a complete film layer is prepared on the oxide layer 15 .

[0099] Sub-step S223 , forming a second electrode layer on the surface of the insulating layer away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation.

[0100] In this embodiment, Figure 7 (c) is a schematic diagram of a device in which a second electrode layer 14 in the form of a complete film layer is prepared on the insulating layer 13 .

[0101] In sub-step S224 , the prepared second electrode layer, insulating layer, and oxide layer are sequentially photolithographically patterned to obtain an intermediate stage device, wherein the patterned second electrode layer, insulating layer, and oxide layer are laterally aligned.

[0102] In this embodiment, Figure 7 (d) is a schematic diagram of a device in which a patterned oxide layer 15, an insulating layer 13 and a second electrode layer 14 are sequentially prepared on the first electrode layer 12. Figure 7 The device structure shown in (d) is the same as Figure 1In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited second electrode layer 14 away from the substrate 11, and the photoresist layer can be patterned. Then, under the shielding effect of the patterned photoresist layer, the local areas of the second electrode layer 14, the insulating layer 13, and the oxide layer 15 that are not covered by the photoresist layer are sequentially etched to achieve a patterning effect on the second electrode layer 14, the insulating layer 13, and the oxide layer 15. Acetone can be used to remove the patterned photoresist layer.

[0103] Therefore, the present application can ensure that the intermediate stage device prepared is suitable for preparing the device by executing the above sub-steps S221 to S224. Figure 1 The oxide thin film transistor device 10 is shown.

[0104] Optionally, please refer to Figure 8 and Figure 9 ,in Figure 8 yes Figure 5 The second flowchart of the sub-steps included in step S220 is as follows: Figure 9 This is the second schematic diagram of the manufacturing of the intermediate stage device provided in the embodiment of the present application. In the embodiment of the present application, the step S220 may include sub-steps S225 to S228 to ensure that the prepared intermediate stage device is suitable for the preparation of Figure 2 The oxide thin film transistor device 10 is shown.

[0105] In sub-step S225 , an insulating layer is grown on the surface of the first electrode layer away from the substrate by plasma enhanced chemical vapor deposition or atomic layer deposition.

[0106] In this embodiment, Figure 9 (a) is a schematic diagram of a device in which an insulating layer 13 in the form of a complete film layer is prepared on the first electrode layer 12.

[0107] Sub-step S226 , forming an oxide layer on the surface of the insulating layer away from the substrate by atomic layer deposition or magnetron sputtering.

[0108] In this embodiment, Figure 9 (b) is a schematic diagram of a device in which a complete oxide layer 15 is formed on the insulating layer 13. The oxide layer 15 may be formed without photolithography patterning, or may be subjected to preliminary photolithography patterning.

[0109] Sub-step S227 , forming a second electrode layer on the surface of the oxide layer away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation.

[0110] In this embodiment, Figure 9 (c) is a schematic diagram of a device in which a second electrode layer 14 in the form of a complete film layer is prepared on the oxide layer 15 .

[0111] Sub-step S227 , sequentially performing photolithographic patterning on the prepared second electrode layer, oxide layer, and insulating layer to obtain an intermediate stage device, wherein the patterned second electrode layer, oxide layer, and insulating layer are laterally aligned.

[0112] In this embodiment, Figure 9 (d) is a schematic diagram of a device in which a patterned insulating layer 13, an oxide layer 15 and a second electrode layer 14 are sequentially prepared on the first electrode layer 12. Figure 9 The device structure shown in (d) is the same as Figure 2 In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited second electrode layer 14 away from the substrate 11, and the photoresist layer can be patterned. Then, under the shielding effect of the patterned photoresist layer, the local areas of the second electrode layer 14, the oxide layer 15, and the insulating layer 13 that are not covered by the photoresist layer are sequentially etched to achieve a patterning effect on the second electrode layer 14, the oxide layer 15, and the insulating layer 13. Acetone can be used to remove the patterned photoresist layer.

[0113] Therefore, the present application can ensure that the intermediate stage device prepared is suitable for preparing the device by executing the above sub-steps S225 to S228. Figure 2 The oxide thin film transistor device 10 is shown.

[0114] Optionally, please refer to Figure 10 and Figure 11 ,in Figure 10 yes Figure 5 The third flowchart of the sub-steps included in step S220 is as follows: Figure 11 This is the third schematic diagram of the manufacturing of the intermediate stage device provided in the embodiment of the present application. In the embodiment of the present application, the step S220 may include sub-steps S229 to S2213 to ensure that the prepared intermediate stage device is suitable for the preparation of Figure 3 or Figure 4 The oxide thin film transistor device 10 is shown.

[0115] In sub-step S229 , a first oxide layer is grown on the surface of the first electrode layer away from the substrate by atomic layer deposition or magnetron sputtering.

[0116] In this embodiment, Figure 11(a) is a schematic diagram of a device in which a first oxide layer 15 in the form of a complete film is formed on the first electrode layer 12. The first oxide layer 15 may be formed without photolithography patterning, or may be subjected to preliminary photolithography patterning.

[0117] In sub-step S2210 , an insulating layer is grown on a surface of the first oxide layer away from the substrate by plasma enhanced chemical vapor deposition or atomic layer deposition.

[0118] In this embodiment, Figure 11 (b) is a schematic diagram of a device in which an insulating layer 13 in the form of a complete film layer is prepared on the first oxide layer 15 .

[0119] Sub-step S2211 , forming a second oxide layer on a surface of the insulating layer away from the substrate by atomic layer deposition or magnetron sputtering.

[0120] In this embodiment, Figure 11 (c) is a schematic diagram of a device in which a second oxide layer 15 in the form of a complete film is prepared on the insulating layer 13. The oxide layer 15 may not require photolithography patterning during its preparation, or may undergo preliminary photolithography patterning.

[0121] In sub-step S2212 , a second electrode layer is formed on a surface of the second oxide layer on a side away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation.

[0122] In this embodiment, Figure 11 (d) is a schematic diagram of a device in which the second electrode layer 14 in the form of a complete film layer is prepared on the second oxide layer 15 .

[0123] In sub-step S2213, the prepared second electrode layer, second oxide layer, insulating layer and first oxide layer are sequentially photolithographically patterned to obtain an intermediate stage device, wherein the patterned second electrode layer, second oxide layer, insulating layer and first oxide layer are laterally aligned.

[0124] In this embodiment, Figure 11 (e) is a schematic diagram of a device in which a patterned first oxide layer 15, an insulating layer 13, a second oxide layer 15 and a second electrode layer 14 are sequentially prepared on the first electrode layer 12. Figure 11 The device structure shown in (e) is the same as Figure 3 or Figure 4Adapted intermediate stage device. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited second electrode layer 14 away from the substrate 11, and the photoresist layer can be patterned. Then, under the shielding effect of the patterned photoresist layer, the local areas of the second electrode layer 14, the second oxide layer 15, the insulating layer 13, and the first oxide layer 15 that are not covered by the photoresist layer are sequentially etched to achieve a patterning effect on the second electrode layer 14, the second oxide layer 15, the insulating layer 13, and the first oxide layer 15. Acetone can be used to remove the patterned photoresist layer.

[0125] Therefore, the present application can ensure that the intermediate stage device prepared is suitable for preparing the device by executing the above sub-steps S229 to S2213. Figure 3 or Figure 4 The oxide thin film transistor device 10 is shown.

[0126] Step S230 , sequentially forming a semiconductor layer, a gate dielectric layer, and a gate electrode layer on the outer surface of the intermediate stage device away from the substrate.

[0127] In this embodiment, when the Figure 7 (d) Figure 9 (d) or Figure 11 After the intermediate stage device shown in (e) is formed, a semiconductor layer 16, a gate dielectric layer 17 and a gate electrode layer 18 can be sequentially prepared on the outer surface of the intermediate stage device away from the substrate 11, and the semiconductor layer 16 covers the outer surface of the second electrode layer 14 away from the substrate 11, and covers the target surface area of ​​the outer surface of the first electrode layer 12 away from the substrate 11 that is not covered by the insulating layer 13 or the oxide layer 15. At this time, the first electrode layer 12 and the second electrode layer 14 respectively form an ohmic contact or a quasi-ohmic contact with the semiconductor layer 16, and the local area of ​​the semiconductor layer 16 that is in direct contact with the oxide layer 15 will form a depletion region 19 in the saturated state of the device; the gate dielectric layer 17 will cover the outer surface of the semiconductor layer 16 away from the substrate 11, and the gate electrode layer 18 will cover the outer surface of the gate dielectric layer 17 away from the substrate 11, thereby obtaining Figure 1 、 Figure 2 、 Figure 3 or Figure 4 The oxide thin film transistor device 10 is shown.

[0128] Among them, the semiconductor layer 16 can be prepared by magnetron sputtering or atomic layer deposition, and patterned by photolithography; the gate dielectric layer 17 can be prepared by atomic layer deposition; the gate electrode layer 18 can be prepared by magnetron sputtering, thermal evaporation or electron beam evaporation, and patterned by photolithography.

[0129] Therefore, this application can ensure that the above steps S210 to S230 are executed. Figure 1 、 Figure 2 、 Figure 3 or Figure 4 The oxide thin film transistor device 10 shown can be prepared and formed quickly and orderly so as to effectively suppress the short channel effect by forming a depletion region 19 in a local area of ​​the semiconductor layer 16 that is in direct contact with the oxide layer 15, reduce the thickness requirement of the semiconductor layer 16, and expand the range of choices for electrode materials.

[0130] In the present application, embodiments of the present application may further provide a display panel, comprising a pixel unit array and a plurality of any of the aforementioned oxide thin film transistor devices 10, wherein the plurality of oxide thin film transistor devices 10 cooperate with each other to form a drive circuit for the pixel unit array. The display panel may be, but is not limited to, an AMLCD (active matrix liquid crystal display) display panel, an AMOLED (active matrix organic light emitting diode display) display panel, a Mini-LED (mini light emitting diode) display panel, a Micro-LED (micro light emitting diode) display panel, and the like.

[0131] In the present application, an embodiment of the present application further provides a dynamic random access memory, comprising a plurality of any of the aforementioned oxide thin film transistor devices 10, wherein the plurality of oxide thin film transistor devices 10 cooperate with each other to implement a dynamic data storage function. In one implementation of this embodiment, a 2TOC three-dimensional dynamic random access memory can be constructed using the plurality of oxide thin film transistor devices 10.

[0132] The above are merely various embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An oxide thin film transistor device, characterized in that: The transistor device comprises: substrate; a first electrode layer disposed on the substrate; an insulating layer and a second electrode layer stacked in sequence on a side of the first electrode layer away from the substrate, wherein an oxide layer is provided between the second electrode layer and / or the first electrode layer and the insulating layer, and the second electrode layer, the insulating layer, and the oxide layer are aligned laterally; a semiconductor layer grown along the sidewalls of the insulating layer and the oxide layer, wherein the semiconductor layer covers the outer surface of the second electrode layer away from the substrate and covers a target surface area of ​​the outer surface of the first electrode layer away from the substrate, the target surface area not covered by the insulating layer or the oxide layer; wherein the first electrode layer and the second electrode layer respectively form an ohmic contact or a quasi-ohmic contact with the semiconductor layer, and a local area of ​​the semiconductor layer directly in contact with the oxide layer forms a depletion region; wherein the material of the oxide layer is a P-type oxide material, and the material of the semiconductor layer is an N-type semiconductor material; or wherein the material of the oxide layer is an N-type oxide material, and the material of the semiconductor layer is a P-type semiconductor material; A gate dielectric layer covering the semiconductor layer, and a gate electrode layer covering the gate dielectric layer.

2. The transistor device according to claim 1, wherein: When the number of the oxide layer is one, the electrode layer close to the oxide layer in the first electrode layer and the second electrode layer is used as a source electrode layer, and the remaining electrode layer is used as a drain electrode layer; When the number of the oxide layers is two, any one of the first electrode layer and the second electrode layer is used as a source electrode layer, and the remaining electrode layer is used as a drain electrode layer.

3. The transistor device according to claim 1, wherein: The thickness of each of the first electrode layer, the second electrode layer and the gate electrode layer is in the range of 5-1000 nm; The thickness of the insulating layer is in the range of 5-1000 nm; The thickness of the oxide layer is in the range of 5-500 nm; The thickness of the semiconductor layer is in the range of 1-200 nm; The thickness of the gate dielectric layer is in the range of 5-500 nm.

4. The transistor device according to any one of claims 1 to 3, wherein: The material of each of the gate electrode layer, the first electrode layer and the second electrode layer is any one of aluminum, molybdenum, tantalum, titanium, chromium, copper, tungsten, nickel, platinum, palladium, gold, cobalt, indium tin oxide material, fluorine-doped tin oxide material, and aluminum-doped zinc oxide material; The insulating layer and the gate dielectric layer are each made of at least one of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide; The P-type oxide material includes at least one of copper oxide, nickel oxide, tin oxide, chromium oxide, cobalt oxide, molybdenum oxide, tellurium oxide, tungsten oxide, and germanium oxide; the N-type semiconductor material is any one of indium gallium zinc oxide, indium zinc oxide, indium zinc tin oxide, rare earth-doped indium zinc oxide, indium gallium oxide, zinc oxide, gallium oxide, indium oxide, and tin oxide; The N-type oxide material includes at least one of zinc oxide, gallium oxide, indium oxide, tin oxide and titanium oxide, and the P-type semiconductor material is any one of tellurium oxide, tellurium selenide oxide, copper oxide, copper chromium oxide, nickel oxide, nickel lithium oxide, tin oxide, tin copper oxide, and tin copper nickel oxide.

5. A method for preparing an oxide thin film transistor device, characterized in that: The preparation method comprises: Providing a substrate, and depositing a first electrode layer on one surface of the substrate; forming an insulating layer, a second electrode layer, and an oxide layer on a surface of the first electrode layer away from the substrate to obtain an intermediate-stage device, wherein the insulating layer is between the first electrode layer and the second electrode layer, an oxide layer is spaced apart from the insulating layer by the first electrode layer and / or the second electrode layer, and the second electrode layer, the insulating layer, and the oxide layer are laterally aligned; A semiconductor layer, a gate dielectric layer and a gate electrode layer are sequentially prepared on the outer surface of the intermediate stage device away from the substrate, wherein the semiconductor layer simultaneously covers the outer surface of the second electrode layer away from the substrate, and a target surface area of ​​the outer surface of the first electrode layer away from the substrate, wherein the target surface area is not covered by the insulating layer or the oxide layer; the first electrode layer and the second electrode layer respectively form an ohmic contact or a quasi-ohmic contact with the semiconductor layer, a local area of ​​the semiconductor layer directly in contact with the oxide layer forms a depletion region, the gate dielectric layer covers the semiconductor layer, and the gate electrode layer covers the gate dielectric layer; wherein the material of the oxide layer is a P-type oxide material, and the material of the semiconductor layer is an N-type semiconductor material; or the material of the oxide layer is an N-type oxide material, and the material of the semiconductor layer is a P-type semiconductor material.

6. The preparation method according to claim 5, characterized in that When the number of the oxide layer is one, and the insulating layer and the first electrode layer are separated by the oxide layer, the first electrode layer is used as a source electrode layer, and the second electrode layer is used as a drain electrode layer; At this time, the step of forming an insulating layer, a second electrode layer, and an oxide layer on the surface of the first electrode layer away from the substrate to obtain an intermediate stage device includes: forming an oxide layer on a surface of the first electrode layer away from the substrate by atomic layer deposition or magnetron sputtering; forming an insulating layer by growing the insulating layer on a surface of the oxide layer away from the substrate based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method; forming a second electrode layer on a surface of the insulating layer away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation; The prepared second electrode layer, the insulating layer and the oxide layer are sequentially subjected to photolithographic patterning to obtain the intermediate stage device, wherein the second electrode layer, the insulating layer and the oxide layer are aligned in side surface after patterning.

7. The preparation method according to claim 5, characterized in that When the number of the oxide layer is one, and the oxide layer is separated from the insulating layer and the second electrode layer, the second electrode layer is used as a source electrode layer, and the first electrode layer is used as a drain electrode layer; At this time, the step of forming an insulating layer, a second electrode layer, and an oxide layer on the surface of the first electrode layer away from the substrate to obtain an intermediate stage device includes: forming an insulating layer on a surface of the first electrode layer away from the substrate by growing the insulating layer based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method; forming an oxide layer on a surface of the insulating layer away from the substrate by atomic layer deposition or magnetron sputtering; forming a second electrode layer on a surface of the oxide layer away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation; The prepared second electrode layer, the oxide layer and the insulating layer are sequentially subjected to photolithographic patterning to obtain the intermediate stage device, wherein the second electrode layer, the oxide layer and the insulating layer are aligned in side surface after patterning.

8. The preparation method according to claim 5, characterized in that When the number of the oxide layers is two, and the second electrode layer and the first electrode layer are both separated from the insulating layer by an oxide layer, any one of the first electrode layer and the second electrode layer is used as a source electrode layer, and the remaining electrode layer is used as a drain electrode layer; in this case, the step of forming the insulating layer, the second electrode layer, and the oxide layer on the surface of the first electrode layer away from the substrate to obtain the intermediate stage device includes: forming a first oxide layer on a surface of the first electrode layer away from the substrate by atomic layer deposition or magnetron sputtering; forming an insulating layer by growing the insulating layer on a surface of the first oxide layer away from the substrate based on a plasma enhanced chemical vapor deposition method or an atomic layer deposition method; forming a second oxide layer on a surface of the insulating layer away from the substrate by atomic layer deposition or magnetron sputtering; forming a second electrode layer on a surface of the second oxide layer away from the substrate by magnetron sputtering, thermal evaporation or electron beam evaporation; The prepared second electrode layer, the second oxide layer, the insulating layer and the first oxide layer are sequentially photolithographically patterned to obtain the intermediate stage device, wherein the patterned second electrode layer, the second oxide layer, the insulating layer and the first oxide layer are laterally aligned.

9. A dynamic random access memory, characterized in that: The memory comprises a plurality of oxide thin film transistor devices according to any one of claims 1 to 4, and the plurality of oxide thin film transistor devices cooperate with each other to realize a dynamic data storage function.

10. A display panel, characterized in that: The display panel includes a pixel unit array and a plurality of oxide thin film transistor devices according to any one of claims 1 to 4, wherein the plurality of oxide thin film transistor devices cooperate with each other to form a driving circuit for the pixel unit array.

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