CDMA-based multi-transceiver PAM-5 channel multiplexing system and communication method

Abstract

The present invention discloses a CDMA-based multi-transceiver PAM-5 channel multiplexing system and communication method. The system includes four transceivers and a differential transmission line channel multiplexed by the four transceivers. The transceivers are connected to an external microprocessor, with each transceiver connected to a different microprocessor. The microprocessor outputs a serial input signal and a clock signal to the transceiver. The transmitter circuit of the transceiver performs CDMA encoding and outputs the encoding result to the channel. The four encoding results form a PAM-5 signal on the channel. The receiver circuit of the transceiver converts the PAM-5 signal into a four-bit binary digital signal, integrates the four-bit binary digital signal to obtain a decoded output signal, and outputs the decoded output signal to the microprocessor connected to the transceiver, thereby enabling communication between the four microprocessors. This enables four transceiver circuits to transmit and communicate with each other simultaneously on the same transmission line, reducing communication costs.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a PAM-5 channel multiplexing system and a communication method of multiple transceivers based on CDMA. Background Art

[0002] Data transmission methods can be categorized as parallel or serial. Historically, parallel transmission technology was more widely used because, at the same frequency, the data bit width is larger, resulting in a greater data transmission bandwidth. Consequently, most communication systems used parallel interfaces. However, parallel transmission has several serious drawbacks. First, parallel transmission interfaces require numerous signal lines, complicating board wiring and requiring a significant amount of transmission media. Furthermore, parallel interfaces transmit single-ended signals, leading to significant interference between multiple signal lines as transmission rates increase. Furthermore, parallel transmission often synchronizes data and clock signals, both of which generate jitter during transmission. As frequencies increase and transmission distances increase, serious timing issues arise, leading to data sampling errors and significantly impacting data transmission reliability. For these reasons, serial transmission, with its higher transmission frequencies, improved stability, and lower costs, has gradually gained traction. As a key interface technology within serial transmission, SerDes (SerDes) has garnered widespread attention.

[0003] SerDes is the abbreviation of serializer and deserializer, which also explains that the main function of SerDes is to convert low-speed parallel signals into high-speed low-voltage differential signals (LVDS) and send them through a serial link. At the same time, it can receive serial input LVDS signals and correctly convert them into low-speed parallel signals. Simply put, it completes the conversion between parallel and serial. Converting low-speed parallel signals into high-speed serial signal transmission can effectively reduce the difficulty of wiring and the impact of crosstalk between signal lines. The transmission medium is only two differential signal lines. However, the signal lines also limit the cost of simultaneous communication between multiple devices.

[0004] In the context of high-performance computing and big data applications, the pursuit of performance requires modular, scalable, energy-efficient, and low-cost many-core systems. Dividing the system into multiple chiplets and 3D stacking these chiplets onto a large interposer can achieve a large-scale modular architecture and reduce the cost of advanced technologies. However, the limited number of RDL (Redistribution Layer) layers in advanced packaging cannot meet the wiring requirements of high-density inter-chip signal interconnection for a large number of homogeneous and heterogeneous chiplets. To address these issues, this paper proposes a PAM-5 channel multiplexing transceiver and communication method based on CDMA (Code Division Multiple Access), enabling the standardized design of silicon interposers. Summary of the Invention

[0005] The present invention proposes a CDMA-based multi-transceiver PAM-5 channel multiplexing system communication method. The purpose is to enable four transceiver circuits to transmit and communicate with each other simultaneously on the same transmission line through circuit design and communication methods, thereby reducing communication costs.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention discloses a CDMA-based multi-transceiver PAM-5 channel multiplexing system, comprising four transceivers and a differential transmission line channel multiplexed by the four transceivers;

[0008] The transceiver includes a transmitter circuit and a receiver circuit, each transceiver is connected to an external microprocessor and obtains a serial input signal and a clock signal from its corresponding microprocessor;

[0009] The transmitter circuit includes an encoding circuit and a driving circuit. The encoding circuit performs CDMA encoding on a serial input signal and a clock signal to obtain a CDMA signal, and outputs the CDMA signal to the driving circuit. The driving circuit outputs the CDMA signal to a differential transmission line channel. The four CDMA signals output by the four driving circuits form a PAM-5 signal on the differential transmission line channel, and the PAM-5 signal is output to each receiver circuit.

[0010] The receiver circuit includes a comparator circuit and a decoding circuit. The comparator circuit converts the PAM-5 signal into a four-bit binary digital signal and outputs it to the decoding circuit. The decoding circuit integrates the four-bit binary digital signal to obtain a decoded output signal, and outputs the decoded output signal to a microprocessor connected to the transceiver, thereby realizing communication between the four microprocessors.

[0011] Furthermore, the encoding circuit is connected to the driving circuit via two inverters connected in series.

[0012] Furthermore, the comparator circuit includes a voltage-controlled clock delayer and a clock-controlled dynamic comparator. The microprocessor further outputs a delay control signal to the voltage-controlled clock delayer. The voltage-controlled clock delayer receives the delay control signal and the clock signal and outputs a first clock signal, which is a delayed clock signal. The voltage-controlled clock delayer outputs the first clock signal to the clock-controlled dynamic comparator and the decoding circuit.

[0013] The clocked dynamic comparator receives a first clock signal and a PAM-5 signal, processes the PAM-5 signal based on the first clock signal, obtains a four-bit binary digital signal, and outputs the signal to a decoding circuit.

[0014] Furthermore, the clocked dynamic comparator is a dynamic comparator based on the Strong Arm architecture.

[0015] In a second aspect, the present invention discloses a multi-transceiver communication method using the system, comprising the following steps:

[0016] 1) The transceiver receives a serial input signal and a clock signal output by an external microprocessor, the encoding circuit performs CDMA encoding on the serial input signal and the clock signal to obtain a CDMA signal, and outputs the CDMA signal to the driving circuit, which outputs the CDMA signal to a differential transmission line channel;

[0017] 2) The four CDMA signals output by the four driver circuits form PAM-5 signals on the differential transmission line channels, and the PAM-5 signals are output to each receiver circuit;

[0018] 3) The comparator circuit of the receiver circuit converts the PAM-5 signal into a four-bit binary digital signal and outputs it to the decoding circuit. The decoding circuit integrates the four-bit binary digital signal to obtain a decoded output signal and outputs the decoded output signal to the microprocessor connected to its transceiver, thus realizing communication between the four microprocessors.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] (1) The present invention adopts CDMA encoding to encode four serial signals into PAM5 signals on the same channel, thus overcoming the problem that the limited number of RDL layers in advanced packaging cannot meet the wiring requirements of high-density inter-chip signal interconnection of a large number of homogeneous / heterogeneous chiplets, thereby improving the level of channel multiplexing.

[0021] (2) The present invention enables mutual communication between four transceiver interfaces using only one channel. Therefore, chiplets or digital chips using this interface design can be arranged in a regular row, column, or other regular shape during layout without excessive consideration of wiring resources, thereby speeding up the design process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a system block diagram of a CDMA-based multi-transceiver PAM-5 channel multiplexing system provided in an embodiment of the present application;

[0023] Figure 2 1 is a circuit diagram of a transmitter circuit of a CDMA-based multi-transceiver PAM-5 channel multiplexing system provided by an embodiment of the present application;

[0024] Figure 3 is a circuit diagram of a receiver circuit of a CDMA-based multi-transceiver PAM-5 channel multiplexing system provided by an embodiment of the present application;

[0025] Figure 4 Schematic diagram of a communication method for a CDMA-based multi-transceiver PAM-5 channel multiplexing system provided in an embodiment of the present application;

[0026] Figure 5 This is a PAM-5 signal simulation eye diagram of a transmitter circuit of a CDMA-based multi-transceiver PAM-5 channel multiplexing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The present invention will be further described and illustrated below in conjunction with specific embodiments. The embodiments are merely illustrative of the present disclosure and do not limit its scope. The technical features of the various embodiments of the present invention may be combined accordingly, provided that there is no conflict between them.

[0028] The word “exemplary” is used in this application to mean “serving as an example, instance, or illustration.” Any embodiment or design described in this application as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0030] SERDES interface technology converts low-speed parallel signals into high-speed serial signals for transmission, effectively reducing wiring complexity and the impact of crosstalk between signal lines. The transmission medium is transmission lines or other channels. However, signal lines also limit the cost of simultaneous communication between multiple devices. For example, if four devices need to communicate with each other, a traditional SERDES interface would require 12 transmission lines.

[0031] Based on this, an embodiment of the present invention proposes a CDMA-based multi-transceiver PAM-5 channel multiplexing system and communication method, which can enable four transceiver circuits to transmit and communicate with each other simultaneously on the same transmission line, thereby reducing communication costs.

[0032] The present invention will be further described below with reference to the accompanying drawings and specific examples.

[0033] like Figure 1 As shown, the system of the present invention includes four transceivers and a differential transmission line channel multiplexed by the four transceivers;

[0034] The transceiver includes a transmitter circuit and a receiver circuit (i.e., the transmitter circuit and the receiver circuit together constitute a transceiver IP). One transceiver is connected to an external microprocessor and each transceiver is connected to a different microprocessor. The microprocessor outputs a serial input signal and a clock signal to the transceiver.

[0035] The transmitter circuit includes an encoding circuit and a driving circuit. The encoding circuit performs CDMA encoding on a serial input signal and a clock signal to obtain a CDMA signal, and outputs the CDMA signal to the driving circuit. The driving circuit outputs the CDMA signal to a differential transmission line channel. The four CDMA signals output by the four driving circuits form a PAM-5 signal on the differential transmission line channel, and the PAM-5 signal is output to each receiver circuit.

[0036] The receiver circuit includes a comparator circuit and a decoding circuit. The comparator circuit converts the PAM-5 signal into a four-bit binary digital signal and outputs it to the decoding circuit. The decoding circuit integrates the four-bit binary digital signal to obtain a decoded output signal, and outputs the decoded output signal to the microprocessor connected to its transceiver, thereby realizing communication between the four microprocessors.

[0037] Each receiver circuit and transmitter circuit is connected to the multiplexed differential transmission line channel; when communicating, the four CDMA signals output by the four driver circuits form a PAM5 signal on the differential transmission line channel.

[0038] Reference Figure 1 and Figure 2The transmitter circuit of the present invention includes an encoding circuit 1, a first inverter 2, a second inverter 3 and a driving circuit. The output of the encoding circuit is connected to the input of the driving circuit through an inverter chain (i.e., the connected first inverter 2 and second inverter 3); that is, the encoding circuit is connected to the driving circuit through two inverters connected in series.

[0039] The drive circuit includes multiple parallel-connected NMOS transistors 4, multiple parallel-connected PMOS transistors 5, a first resistor 6, and a second resistor 7. The first inverter 2 and the second inverter 3 provide drive current for the NMOS transistors 4 and PMOS transistors 5. The source of the PMOS transistor 5 is connected to a high level, and the drain is connected to the second resistor 7. The source of the NMOS transistor 4 is connected to a low level, and the drain is connected to the first resistor 6. The first and second resistors 6 and 7 are connected to the output of the drive circuit. The first and second resistors 6 and 7 balance the entire drive circuit, allowing it to match the impedance of the differential transmission line channel in all states.

[0040] In a specific embodiment of the present invention, the encoding circuit is implemented by a digital circuit and analyzes the input serial signal; each encoding circuit is set with its own four-bit identification code, the four four-bit identification codes corresponding to the four encoding circuits are mutually orthogonal, and each encoding circuit stores the four four-bit identification codes; each encoding circuit performs a bitwise exclusive OR operation on the input serial input signal and the clock signal based on its own four-bit identification code to obtain its own CDMA signal.

[0041] Reference Figure 1 and Figure 3 The receiver circuit of the present invention includes a voltage-controlled clock delayer 8, a clock-controlled dynamic comparator 9, and a decoding circuit 10. An external clock signal is also input to the voltage-controlled clock delayer. At the same time, the microprocessor also outputs a delay control signal to the voltage-controlled clock delayer. The voltage-controlled clock delayer outputs a first clock signal, which is a delayed clock signal. The delayed clock signal and the PAM-5 signal on the differential transmission line channel are input to the clock-controlled dynamic comparator 9 together. The clock-controlled dynamic comparator 9 is connected to the decoding circuit 10, which decodes and outputs a signal, that is, outputs the four recovered serial input signals.

[0042] The transmitter circuit and receiver circuit of a transceiver share a clock signal. The clock signal at the receiving end is delayed by the voltage-controlled clock delay 8 and then connected to the clock-controlled dynamic comparator 9 circuit to align the PAM-5 eye diagram.

[0043] The clocked dynamic comparator 9 outputs a four-bit binary digital signal to a decoding circuit 10. The clocked dynamic comparator 9 is a high-speed comparator that performs a precharge-comparison process under clock control within a comparison cycle. In the embodiment of the present invention, a Strong-Arm dynamic comparator with a good DC input bias is used.

[0044] As a preferred embodiment of the present invention, the voltage-controlled clock delay circuit 8 is a delay circuit that controls the delay time or phase with voltage, but does not change the signal frequency or duty cycle. In one embodiment of the present invention, a voltage-controlled clock delay circuit is used, consisting of an inverter chain driven by a voltage-controlled current source and an output buffer.

[0045] As a preferred embodiment of the present invention, the clocked dynamic comparator 9 is a high-speed comparator that performs a precharge-comparison process through clock control within a comparison cycle; the polarity and magnitude of the differential level output by the clocked dynamic comparator 9 are positively correlated with the polarity and magnitude of the amplitude difference of the input differential signal in the comparison state.

[0046] like Figure 5 As shown, the present invention provides a communication method for a CDMA-based multi-transceiver PAM-5 channel multiplexing system, and the specific steps are as follows:

[0047] Step 1): the encoding circuit receives a serial input signal and an external clock, performs CDMA encoding on the input signal, and obtains a CDMA signal. The driving circuit drives and transmits the CDMA signal, and the driving circuit outputs the CDMA signal to a differential transmission line channel.

[0048] Step 2): The CDMA signals output by the four transmitter circuits together form a PAM-5 signal on the differential transmission line channel, and the PAM-5 signal is output to each receiver circuit;

[0049] Step 3): The comparator circuit of the receiver circuit converts the PAM-5 signal into a four-bit binary digital signal and outputs it to the decoding circuit. The decoding circuit integrates the four-bit binary digital signal to obtain a decoded output signal, and outputs the decoded output signal to the microprocessor connected to its transceiver, thereby realizing communication between the four microprocessors.

[0050] The comparator circuit can compare the PAM-5 signal and distinguish different levels through the feedback resistor. The decoding circuit receives the PAM-5 signal processed by the comparator circuit and decodes it. The process of the receiver circuit receiving the PAM-5 signal includes the following:

[0051] 3.1) The PAM5 signal consists of five levels ranging from VDD / 2 to VDD. The clock signal passes through voltage-controlled clock delay 8 and is input into clocked dynamic comparator 9. The rising edge of the delayed clock signal is aligned with the center of the eye diagram and compared. The five levels are converted into a four-bit binary digital signal.

[0052] 2.2): The decoding circuit can restore the four-bit binary digital signal to the information transmitted by the four transmitter circuits through integration operation.

[0053] The decoding circuit performs an integration operation on a four-bit binary digital signal to obtain a decoded output signal, including:

[0054] Within one clock cycle, the clocked dynamic comparator outputs a four-bit binary digital signal to a decoding circuit, which stores four four-bit identification codes. Within four clock cycles, the decoding circuit performs four positive edge sampling on the four four-bit binary digital signals output by the clocked dynamic comparator to obtain four binary codes. The four binary codes are XORed with the identification code of each transceiver, and all XOR results of the four binary codes and the identification code of one transceiver are summed. The summed result is compared with a preset reference. If the summed result is greater than the preset reference, a high-level signal is output and the high-level signal is 1; if the summed result is less than the preset reference, a low-level signal is output and the high-level signal is 0. The output signal is a single-bit signal of the serial input signal of the transceiver corresponding to the identification code. After the decoding circuit integrates all four-bit binary digital signals obtained by the clocked dynamic comparator, the decoded output signal is the four serial input signals of the four transceivers.

[0055] Reference Figure 1 The CDMA-based multi-transceiver PAM-5 channel multiplexing system proposed in the embodiment of the present application can enable four transceivers to communicate with each other on the same channel at the same time, greatly reducing the system communication cost.

[0056] Reference Figure 5 In this embodiment, the PAM-5 signal has good linearity, a clear opening, a large eye circle, and the system noise is within an acceptable range. The PAM-5 signal can be normally recognized and processed by the clocked dynamic comparator, and finally, the four microprocessors can communicate with each other through the decoding circuit.

[0057] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they are not to be construed as limiting the scope of the present invention. Persons skilled in the art will readily appreciate that variations and modifications may be made without departing from the spirit of the present invention, and all such variations and modifications fall within the scope of protection of the present invention.

Claims

1. A CDMA-based multi-transceiver PAM-5 channel multiplexing system, characterized in that: including four transceivers and a differential transmission line channel multiplexed by the four transceivers; The transceiver includes a transmitter circuit and a receiver circuit, each transceiver is connected to an external microprocessor and obtains a serial input signal and a clock signal from its corresponding microprocessor; The transmitter circuit includes an encoding circuit and a driving circuit. The encoding circuit performs CDMA encoding on a serial input signal and a clock signal to obtain a CDMA signal, and outputs the CDMA signal to the driving circuit. The driving circuit outputs the CDMA signal to a differential transmission line channel. The four CDMA signals output by the four driving circuits form a PAM-5 signal on the differential transmission line channel, and the PAM-5 signal is output to each receiver circuit. The receiver circuit includes a comparator circuit and a decoding circuit. The comparator circuit converts the PAM-5 signal into a four-bit binary digital signal and outputs it to the decoding circuit. The decoding circuit integrates the four-bit binary digital signal to obtain a decoded output signal, and outputs the decoded output signal to a microprocessor connected to the transceiver, thereby realizing communication between the four microprocessors.

2. The system according to claim 1, wherein: Each of the encoding circuits is provided with its own four-bit identification code, the four four-bit identification codes corresponding to the four encoding circuits are mutually orthogonal, and each encoding circuit stores the four four-bit identification codes; each encoding circuit performs a bitwise exclusive OR operation on the input serial input signal and the clock signal based on its own four-bit identification code to obtain its own CDMA signal.

3. The system according to claim 1, wherein: The encoding circuit is connected to the driving circuit via two inverters connected in series.

4. The system according to claim 1, wherein: The comparator circuit includes a voltage-controlled clock delayer and a clock-controlled dynamic comparator. The microprocessor further outputs a delay control signal to the voltage-controlled clock delayer. The voltage-controlled clock delayer receives the delay control signal and the clock signal and outputs a first clock signal, which is a delayed clock signal. The voltage-controlled clock delayer outputs the first clock signal to the clock-controlled dynamic comparator and the decoding circuit. The clocked dynamic comparator receives a first clock signal and a PAM-5 signal, processes the PAM-5 signal based on the first clock signal, obtains a four-bit binary digital signal, and outputs the signal to a decoding circuit.

5. The system according to claim 4, characterized in that The clocked dynamic comparator is a dynamic comparator based on the Strong Arm architecture.

6. The system according to claim 2, wherein: The decoding circuit performs an integration operation on a four-bit binary digital signal to obtain a decoded output signal, including: Within one clock cycle, the clocked dynamic comparator outputs a four-bit binary digital signal to a decoding circuit, which stores four four-bit identification codes. Within four clock cycles, the decoding circuit performs four positive edge sampling on the four four-bit binary digital signals output by the clocked dynamic comparator to obtain four binary codes. The four binary codes are XORed with the identification code of each transceiver, and all XOR results of the four binary codes and the identification code of one transceiver are summed. The summed result is compared with a preset reference. If the summed result is greater than the preset reference, a high-level signal is output and the high-level signal is 1; if the summed result is less than the preset reference, a low-level signal is output and the high-level signal is 0. The output signal is a single-bit signal of the serial input signal of the transceiver corresponding to the identification code. After the decoding circuit integrates all four-bit binary digital signals obtained by the clocked dynamic comparator, the decoded output signal is the four serial input signals of the four transceivers.

7. A multi-transceiver communication method using the system of claim 1, characterized in that: The following steps are included: 1) The transceiver receives a serial input signal and a clock signal output by an external microprocessor, the encoding circuit performs CDMA encoding on the serial input signal and the clock signal to obtain a CDMA signal, and outputs the CDMA signal to the driving circuit, which outputs the CDMA signal to a differential transmission line channel; 2) The four CDMA signals output by the four driver circuits form PAM-5 signals on the differential transmission line channels, and the PAM-5 signals are output to each receiver circuit; 3) The comparator circuit of the receiver circuit converts the PAM-5 signal into a four-bit binary digital signal and outputs it to the decoding circuit. The decoding circuit integrates the four-bit binary digital signal to obtain a decoded output signal and outputs the decoded output signal to the microprocessor connected to its transceiver, thus realizing communication between the four microprocessors.

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