A task runtime scheduling method and device for a data stream many-core processor

Abstract

The application provides a task runtime scheduling method and device for a data stream many-core processor. The method comprises the following steps: in a runtime environment, marking a resource-adapted task from a task emission queue to construct a task group according to residual resources of a PE array, residual resources of on-chip storage space and attribute information of each task; pre-processing the tasks in the task group to obtain a pre-processed task group, and mapping the pre-processed task group to the PE array for execution. The pre-processing comprises the following steps: identifying an associated pair formed by two tasks with data dependency in the task group, and modifying microinstruction codes corresponding to a predecessor task and a successor task in the associated pair, so that a PE core processing the predecessor task directly transmits result data to a PE core processing the successor task.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer architecture, in particular to the field of dataflow many-core processor, and more particularly to a task runtime scheduling method and device for dataflow many-core processor. BACKGROUND

[0002] A dataflow many-core processor is a high-performance computing system with many computing cores (Process Element, PE for short). Each PE core supports concurrent processing of tasks to fully exploit the parallelism between tasks, and is suitable for big data processing, artificial intelligence, 5G communication, etc.

[0003] A conventional dataflow many-core processor mainly includes a PE array composed of multiple processing units, on-chip storage, direct memory access (DMA), on-chip network, and off-chip storage. The PE array is a computing component for executing tasks; the on-chip storage is responsible for storing source data required for task execution and result data after execution; the DMA is responsible for moving data from off-chip storage to on-chip storage; the on-chip network is responsible for data exchange between different PE cores on the PE array and between the PE core and the on-chip storage; and the off-chip storage stores the application program to be executed.

[0004] In a dataflow many-core processor, an application program is compiled by a compiler into a task flow graph that embodies the dependency relationship between tasks, and each task in the task flow graph is described as a directed acyclic dataflow graph and mapped to the PE array for execution. For example, Figure 1 An example is given to show the relationship between the application program, the task flow graph, and the dataflow graph; assume that there are three application programs, namely application programs 1-3, wherein the task flow graph corresponding to the application program 1 contains six tasks: tasks 1-6, and the dataflow graph corresponding to the task 4 contains eight nodes: nodes 1-8; wherein the dependency relationship between tasks in the task flow graph and the dependency relationship between nodes in the dataflow graph are represented by edges (arrows). Taking the dataflow graph as an example, each node represents a microinstruction code, that is, a specific calculation or processing required for the data, and the edge in the dataflow graph represents the flow direction of the data and the dependency relationship between the nodes. The data flows along the edge from the root node according to the dataflow graph until the task execution reaches the leaf node. The dataflow many-core processor, which is centered on data, not only can exploit the parallelism in tasks, but also can reduce the access of the PE core to the storage and the waiting time of the PE core, thereby improving the efficiency of task execution.

[0005] Generally, the order of task execution in the task flow graph is determined according to the dependency relationship between tasks, and then the PE array executes the tasks in the task flow graph in a fixed order. Under different data scales, the number of PE cores occupied by a task is not fixed. When the data scale is small, a task may only need to occupy 2 or even 1 PE core. During the execution of the task, other tasks cannot be mapped to the PE array for execution, which is obviously not conducive to the utilization of the PE array. At the same time, the data interaction between tasks can only be realized through on-chip storage, and the transmission delay is large, which reduces the overall processing efficiency of the task.

[0006] It can be seen that the prior art has the problems of low utilization of the PE array and low overall processing efficiency of the task.

[0007] It should be noted that the background art is only used to introduce the related information of the present application, so as to help understand the technical solutions of the present application, but does not mean that the related information must be prior art. The related information is submitted and disclosed together with the present application scheme, and in the absence of evidence that the related information has been publicly disclosed before the filing date of the present application, the related information should not be regarded as prior art. SUMMARY

[0008] Therefore, the purpose of the present application is to overcome the defects of the prior art, and to provide a task runtime scheduling method and device for a data flow many-core processor.

[0009] The purpose of the present application is achieved by the following technical solutions:

[0010] According to a first aspect of the present application, a task runtime scheduling method for a data flow many-core processor is provided, comprising the following operations in a runtime environment: obtaining an application program, generating a task flow graph describing the dependency relationship between tasks in the application program, a node in the task flow graph representing a task, an edge between nodes representing a data dependency relationship, the starting point of the edge representing a predecessor task, and the end point of the edge representing a successor task, each node recording attribute information of the task; when there is a free space in the task launch queue, selecting a task from the task flow graph according to the data dependency relationship, and transmitting the attribute information of the selected task into the task launch queue; according to the remaining resources of the PE array, the remaining resources of the on-chip storage space, and the attribute information of each task, marking the resource-adapted tasks in the task launch queue to construct a task group; preprocessing the tasks in the task group to obtain a preprocessed task group, and mapping the preprocessed task group to the PE array for execution, wherein the preprocessing comprises: identifying an associated pair consisting of two tasks with data dependency in the task group, modifying the microinstruction code corresponding to the predecessor task and the successor task in the associated pair, so that the PE core processing the predecessor task directly transmits the result data to the PE core processing the successor task.

[0011] Optionally, the modifying the microinstruction code corresponding to the predecessor task and the successor task in the associated pair comprises: replacing a store instruction in the microinstruction code corresponding to the predecessor task with a data transfer instruction, wherein the store instruction is used to instruct to store result data of the predecessor task to on-chip storage, and the data transfer instruction is used to instruct the PE core processing the predecessor task to directly transmit the result data to the PE core processing the successor task through the on-chip network; and removing a load instruction in the microinstruction code corresponding to the successor task, wherein the load instruction is used to instruct to load result data of the predecessor task in the associated pair from the on-chip storage.

[0012] Optionally, the attribute information of the task comprises a task sequence number, a successor task sequence number and a task state, wherein the task state comprises a to-be-activated state and a wake-up state, and the initial task state of all tasks is the to-be-activated state; and the manner of selecting the task according to the data dependency relationship comprises: when all non-root nodes do not have a predecessor task that has been transmitted into the task launch queue, selecting a root node of a task flow graph from a set of current task flow graphs, and transmitting the attribute of the task corresponding to the root node into the task launch queue; otherwise, transmitting the attributes of the to-be-activated successor tasks into the task launch queue one by one according to the data dependency relationship, wherein the task state in the attribute initially transmitted into the task launch queue is modified to the wake-up state. Through the manner, the tasks of one task flow graph can be completely transmitted into the task launch queue before the tasks of another task flow graph are selected to be transmitted into the task launch queue, so that the waiting process of some application programs is avoided from being too long. If there are multiple candidate task flow graphs without tasks being transmitted into the task launch queue, one task flow graph is selected from the multiple task flow graphs according to a priority and / or a waiting time, and the task is selected according to the data dependency relationship in the above manner.

[0013] Optionally, the attribute information of the task further comprises a predecessor task serial number, a source data size, a result data size and a number of PE cores used, and the task state further comprises executing and ending, wherein a task group is constructed according to the predecessor task serial number and the task state according to a preset construction rule, the rule comprising: based on the predecessor task serial number and the task state, identifying an alternative task whose predecessor task state is ending, and selecting a task from the alternative task in an order from early to late according to a time when the task enters a task launch queue, wherein a task corresponding to a root node is regarded as an alternative task; after selecting a task, determining whether resources required after integrating the selected task and a marked task meet a requirement according to the source data size, the result data size and the number of PE cores used, if yes, setting the selected task as a marked task, and continuing to select a successor task of the marked task, if no, selecting another alternative task, and continuing until no alternative task meeting the requirement is found in the task launch queue, wherein the requirement is that resources required after integration do not exceed remaining resources of the PE array and remaining resources of on-chip storage space. The preset construction rule can improve the parallelism of task processing, preferentially process tasks entering the queue first, and orderly promote tasks of each application program; meanwhile, when a root node of another task enters the queue, the last opportunity can be utilized to start tasks of another application program through idle resources, and the efficiency of overall processing is improved.

[0014] Optionally, the attribute information of the task further comprises a mapping PE core serial number, wherein after the preprocessed task group is mapped to the PE array for execution, the mapping PE core serial number corresponding to a PE core processing each task is filled into the task launch queue, and the task state is modified to executing.

[0015] Optionally, the attribute information of the task further comprises a total cycle number and a cycle granularity, wherein the total cycle number refers to a total number of times of task iteration execution, and the cycle granularity refers to a number of times of task iteration execution required for obtaining result data that can be transmitted to a successor task each time; the method further comprises: for any two tasks with a dependency relationship, executing a data transmission instruction once after each iteration execution of the predecessor task for a cycle granularity number of times, and triggering iteration execution of the successor task for a cycle granularity number of times; and setting the task state to ending when the number of times of task iteration execution reaches the total cycle number.

[0016] Optionally, the attribute information of the task further comprises a source data address and a result data address, and the method further comprises: marking the source data address and the result data address of each task according to a preset address marking manner, including: for a task without a predecessor task and a successor task in the task group, marking an address of source data in on-chip storage in the source data address of the task and marking an address of result data in on-chip storage in the result data address of the task; for a task only having a successor task in the task group, marking only the address of source data in on-chip storage in the source data address of the task; for a task only having a predecessor task in the task group, marking only the address of result data in on-chip storage in the result data address of the task; for a task having both a predecessor task and a successor task in the task group, neither the source data address nor the result data address of the task needs to be marked; reading source data required by the task during task execution according to the marked source data address; and saving result data at the end of task execution in the corresponding address of on-chip storage according to the marked result data address. The address marking unit differentiates and marks the source data address and the result data address of each task as needed, which can reduce the marking time.

[0017] According to a second aspect of the present application, a task runtime scheduling device for a data flow many-core processor is provided, which is used to implement the method of the first aspect, and comprises: a micro control module configured to: acquire an application program, generate a task flow graph describing the dependency relationship between tasks in the application program, a node in the task flow graph representing a task, an edge between nodes representing a data dependency relationship, a start point of the edge representing a predecessor task, and a terminal point of the edge representing a successor task, and each node recording attribute information of the task; and in the case that a task launch queue has idle space, selecting a task from the task flow graph according to the data dependency relationship and transmitting the attribute information of the selected task into the task launch queue; and a task launch module configured to: according to the remaining resources of a PE array, the remaining resources of on-chip storage space and the attribute information of each task, marking a task group from the task launch queue, the task group being resource-adapted; and pre-processing the tasks in the task group to obtain a pre-processed task group, and mapping the pre-processed task group to the PE array for execution, wherein the pre-processing comprises: identifying an associated pair of two tasks having a data dependency relationship in the task group, and modifying the micro instruction code corresponding to the predecessor task and the successor task in the associated pair, so that the PE core of the predecessor task directly transmits result data to the PE core processing the successor task.

[0018] According to a third aspect of the present application, an electronic device is provided, comprising: one or more processors; and a memory, wherein the memory is configured to store executable instructions; and the one or more processors are configured to implement the steps of the method of the first aspect by executing the executable instructions. BRIEF DESCRIPTION OF DRAWINGS

[0019] The embodiments of the present application will be further described below with reference to the drawings, in which:

[0020] Figure 1 a schematic diagram of a task flow graph according to an embodiment of the present application;

[0021] Figure 2 a schematic diagram of a module structure of a task runtime scheduling apparatus according to an embodiment of the present application;

[0022] Figure 3 a schematic diagram of a task launch queue according to an embodiment of the present application;

[0023] Figure 4 a schematic diagram of modified microinstruction code according to an embodiment of the present application;

[0024] Figure 5 a schematic diagram of a flow example of a task runtime scheduling method according to an embodiment of the present application;

[0025] Figure 6 a schematic diagram of a flow of a task runtime scheduling method according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described below in detail with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0027] As mentioned in the background section, the prior art has the problems of low utilization of PE array and low efficiency of overall task processing. On the one hand, researches on data flow many-core processors show that when the data size of a task is small, the PE array resources occupied by the task are less, and the computation of the task cannot cover the entire PE array, resulting in low utilization of the PE array and affecting the execution efficiency of the application program. On the other hand, there are data dependencies between two or more tasks in an application program. For tasks with data dependencies, if only on-chip storage is used for data interaction, the advantages of the data flow many-core processor cannot be fully utilized. In this regard, if the hardware is improved for scheduling optimization, it will result in high cost and is not suitable for existing data flow many-core processors. Therefore, the method of the present application starts from the runtime environment and improves at the software level to generate a task flow graph for the application program and record the attribute information of the tasks in the task flow graph. When there is idle space in the task launch queue, the tasks are selected from the task flow graph according to the data dependency relationship, and the attribute information of the selected tasks is transmitted into the task launch queue to ensure that the attribute information of one task flow graph is loaded first and then the attribute information of the remaining task flow graphs is loaded. Subsequently, according to the remaining resources of the PE array, the remaining resources of the on-chip storage space and the attribute information of each task, the tasks that are resource-adapted are marked from the task launch queue to construct a task group. The attribute information can be used to fully utilize the remaining resources of the PE array and the remaining resources of the on-chip storage space to improve the utilization of the PE array. In addition, the method of the present application also identifies the associated pair consisting of two tasks with data dependencies in the task group, modifies the microinstruction code corresponding to the predecessor task and the successor task in the associated pair, so that the PE core processing the predecessor task directly transmits the result data to the PE core processing the successor task. This can avoid transmitting the result data of the predecessor task in the task group to the on-chip storage first and then reading the data from the on-chip storage by the PE core processing the successor task, reducing the time overhead and effectively improving the efficiency of overall task processing at low cost.

[0028] First, the schematic structure of the data flow many-core processor is described, which includes off-chip storage, DMA, on-chip storage and a PE array consisting of a plurality of PE cores. The off-chip storage is used to store the application program and source data to be executed. The DMA is used to transfer data from the off-chip storage to the on-chip storage. The on-chip storage is used to store the source data required for task execution and the result data after execution. The PE array is the computing component of the data flow many-core processor for executing tasks and includes a plurality of PE cores. For example Figure 2 As shown, the PE array includes 16 PE cores (which can also be 32, 64 or 128, etc., depending on the configuration of the data flow many-core processor). Any two PE cores can interact with each other through the on-chip network.

[0029] Secondly, the application provides a task runtime scheduling device for the data stream many-core processor, which comprises a micro control module and a task emission module, the task emission module comprises a task emission queue, a loop control unit and an address calibration unit.

[0030] (1) Micro control module

[0031] According to one embodiment of the present application, the micro-control module is configured to: acquire an application, generate a task flow graph describing the dependency relationship between tasks in the application, a node in the task flow graph representing a task, an edge between nodes representing a data dependency relationship, a start point of the edge representing a predecessor task, and an end point of the edge representing a successor task, and each node recording attribute information of the task; and when there is a free space in the task launch queue, select a task from the task flow graph according to the data dependency relationship, and transmit the attribute information of the selected task into the task launch queue. The way of selecting a task from the task flow graph according to the data dependency relationship includes: when all non-root nodes do not have a predecessor task that has been transmitted into the task launch queue, selecting a root node of a task flow graph from the current set of task flow graphs, and transmitting the task attribute of the task corresponding to the root node into the task launch queue; otherwise, transmitting the task attributes of the successor tasks to be activated into the task launch queue one by one according to the data dependency relationship, wherein the task state in the task attribute initially transmitted into the task launch queue is modified to be awakened. Preferably, the way of selecting a task from the task flow graph according to the data dependency relationship is: acquiring the currently selected task flow graph, modifying the task state of the task corresponding to each node to be awakened from the root node of the task flow graph, and taking the awakened task as the selected task, wherein when the attribute information of an awakened task is transmitted into the task launch queue, if the task launch queue still has a free space, the task state of the successor task of the awakened task is modified to be awakened according to the task serial number and the successor task serial number of the awakened task; if all tasks in the currently selected task flow graph are awakened, another task flow graph is selected from the other task flow graphs containing tasks to be activated, and the previous process is repeated. In this way, the tasks of one task flow graph can be completely transmitted into the task launch queue before the tasks of another task flow graph are selected to be transmitted into the task launch queue, avoiding the waiting process of some applications from being too long. If there are multiple candidate task flow graphs without tasks transmitted into the task launch queue, a task flow graph is selected from the multiple task flow graphs according to the priority and / or the waiting time, and the selected task is selected according to the data dependency relationship in the above manner.

[0032] The nodes in the task flow graph represent a certain task function divided in the application scenario, and the nodes in the data flow graph in each task represent micro-instruction codes for processing data in the task.

[0033] According to one embodiment of the present application, the attribute information of a task includes: a task serial number, a predecessor task serial number, a successor task serial number, a task state, a total cycle number, a cycle granularity, a source data size, a result data size, a source data address, a result data address, a number of PE cores used, and a mapping PE core serial number, or a combination thereof. Of course, some items in the attribute information cannot be obtained at the initial generation of the attribute information, i.e., some items can be set to default values at the initial stage, and then can be modified and improved gradually in the subsequent process.

[0034] (2) Task launch module

[0035] 2.1 Task launch queue

[0036] According to one embodiment of the present application, the task launch queue is used to record the attribute information of the task. An exemplary task launch queue is shown in FIG. 2. Figure 3

[0037] ​According to one embodiment of the present application, the task launch queue is also used to schedule a task group to execute on the PE array. For example, the task group is constructed according to the predecessor task sequence number and the task state according to a preset construction rule, which includes: based on the predecessor task sequence number and the task state, identifying the candidate tasks whose task state is end for the predecessor task, and selecting the tasks from the candidate tasks in the order from early to late according to the time of entering the task launch queue, wherein the task corresponding to the root node is regarded as a candidate task; after selecting one task, judging whether the required resources after integrating the selected task and the marked task meet the requirements according to the source data size, the result data size and the used PE core, if yes, setting the selected task as the marked task, and continuing to select the successor task of the marked task, if no, selecting other candidate tasks, and continuing until no candidate task meeting the requirements is found in the task launch queue, wherein the requirements are that the required resources after integration do not exceed the remaining resources of the PE array and the remaining resources of the on-chip storage space. For example: assuming that the task state of three predecessor tasks in the task launch queue is end, which are tasks A, B and C respectively, and a task D corresponding to a root node, the time of entering the queue is in the order of tasks A, B and C. For simplicity, it is assumed that tasks A, B and D have no successor task, and task C has a successor task c1. After selecting task A, the marked task is empty at this time, and the required resources after integrating task A and the marked task do not exceed the remaining resources of the PE array and the remaining resources of the on-chip storage space, so task A is marked; then, task B is selected, the required resources after integrating task B and the marked task A exceed the remaining resources of the PE array and the remaining resources of the on-chip storage space, so task B is not marked; then, task C is selected, the required resources after integrating task C and the marked task A do not exceed the remaining resources of the PE array and the remaining resources of the on-chip storage space, so task C is marked; then, the successor task c1 of task C is selected, the required resources after integrating task c1 and the marked tasks A and C do not exceed the remaining resources of the PE array and the remaining resources of the on-chip storage space, so task c1 is marked (note that if c1 has a successor task, the successor task of c1 will actually be selected); finally, task D is selected, the required resources after integrating task D and the marked tasks A, C and c1 do not exceed the remaining resources of the PE array and the remaining resources of the on-chip storage space, so task D is marked; and the constructed task group includes tasks A, C, c1 and D. The technical scheme of this embodiment can at least achieve the following beneficial technical effects: the parallel degree of task processing can be improved, the tasks entering the queue earlier can be processed preferentially, the tasks of each application program can be sequentially promoted, and the idle resources can be used to start the tasks of other application programs when other task root nodes enter the queue, so as to improve the overall processing efficiency.

[0038] Of course, the above preset construction rules are only preferred embodiments, and the implementer can set the preset construction rules required by the implementer to construct the human task group. For example, according to an optional embodiment of the present application, the preset construction rules for constructing the task group include:

[0039] Rule A: Based on the predecessor task sequence number and the task state, an alternative task whose predecessor task state is end is identified, and a task is selected from the alternative task in the order from early to late according to the time of entering the task launch queue, wherein the task corresponding to the root node is regarded as the alternative task;

[0040] Rule B: After selecting a task, whether the selected task meets the requirements after integration with the marked task is judged according to the source data size, the result data size and the PE core used, if yes, the selected task is set as the marked task, and the successor task of the marked task is continued to be selected, if no, other alternative task is selected until no alternative task meeting the requirements is found in the task launch queue, wherein the requirements are that the required resources after integration do not exceed the remaining resources of the PE array and the remaining resources of the on-chip storage space;

[0041] Rule C: The number of tasks belonging to the root node in the marked task needs to be less than a preset number threshold (such as 1, 3 or 10, etc., which is set according to the processing capacity of the PE array as required). By setting rule C, it can be avoided that too many root nodes of the application are loaded at one time in a task group, so as to reduce the influence on the execution efficiency of the application started earlier.

[0042] The task launch queue will maintain the task state in the attribute information of each task. The task state includes to be activated, to be woken up, to be executed and to be ended, wherein to be activated is the initial state (the state before entering the task launch queue) in the attribute information of the task, to be woken up represents the state that the attribute information of the task is activated before entering the task launch queue. To be executed represents the state that the task is launched to the PE array to perform calculation. To be ended represents the state that the task completes calculation on the PE array. For example, after the preprocessed task group is mapped to the PE array for execution, the loop control unit informs the task launch queue to fill the mapping PE core sequence number corresponding to the PE core processing each task into the task launch queue, and modifies the task state to to be executed; when the number of iterations of the task reaches the total number of cycles, the task state is set to to be ended.

[0043] 2.2, address calibration unit

[0044] According to one embodiment of the present application, after the task group to be executed is selected, each task in the task group needs to be preprocessed. The address calibration unit is configured to calibrate the addresses (positions) of the source data and the result data of each task on the chip according to a preset address calibration mode, including: rule 1: for a task without a predecessor task and a successor task in the task group, the address of the source data in the on-chip storage is calibrated in the source data address of the task, and the address of the result data in the on-chip storage is calibrated in the result data address of the task; rule 2: for a task with only a successor task in the task group, only the address of the source data in the on-chip storage is calibrated in the source data address of the task; rule 3: for a task with only a predecessor task in the task group, only the address of the result data in the on-chip storage is calibrated in the result data address of the task; and rule 4: for a task with both a predecessor task and a successor task in the task group, neither the source data address nor the result data address of the task needs to be calibrated. For rule 2, because there is no predecessor task of the task in the task group, it is difficult to coordinate the direct transmission of the result data, and therefore the corresponding source data is still obtained from the source data address; for rule 3, because there is no successor task of the task in the task group, the corresponding result data is still stored in the result data address, so as to be accessed on demand later; and for rule 4, the source data required by the task can be obtained from the upstream PE core, and the result data generated by the task can be directly transmitted to the downstream PE core, and therefore the source data address and the result data address of the task do not need to be calibrated.

[0045] According to one embodiment of the present application, the address calibration unit not only needs to calibrate the addresses of the tasks, but also needs to record the states of the tasks whose addresses are calibrated, to count the remaining resources of the on-chip storage space according to the data addresses of the tasks, and to release the on-chip storage space resources occupied by the task when the state of the task is end. The address calibration unit sends the counted remaining resources of the on-chip storage space to the task launch queue.

[0046] 2.3, loop control unit

[0047] According to one embodiment of the present application, in addition to calibrating the addresses of the tasks in the task group, the loop control unit also receives the microinstruction code of each task in the task group from the off-chip storage, and allocates the mapped PE core serial number to each task according to the remaining resources of the PE array.

[0048] For any two tasks with dependency in the task group, the microinstruction code of the tasks needs to be changed by the loop control unit, according to an embodiment of the present application, the way of modifying the microinstruction code corresponding to the predecessor task and the successor task in the associated pair includes: replacing the memory instruction in the microinstruction code corresponding to the predecessor task with a data transmission instruction, wherein the memory instruction is used to instruct to store the result data of the predecessor task to the on-chip storage, and the data transmission instruction is used to instruct the PE core processing the predecessor task to directly transmit the result data to the PE core processing the successor task through the on-chip network; removing the load instruction in the microinstruction code corresponding to the successor task, the load instruction is used to instruct to load the result data of the predecessor task in the associated pair from the on-chip storage. As shown in Figure 4 the memory instruction of the predecessor task storing the result data back to the on-chip storage and the load instruction of the successor task taking the source data to the PE core are hidden, and a data transmission instruction block is inserted at the position of the memory instruction of the predecessor task, the data transmission instruction block is generated according to the information of the memory instruction of the predecessor task and the load instruction of the successor task, including the PE core serial number corresponding to the memory instruction and the load instruction of the data operating the same address, and the register serial number of the data in the corresponding memory instruction and load instruction, so as to realize the direct transmission of a group of data from the PE core processing the predecessor task to the PE core processing the successor task.

[0049] According to an embodiment of the present application, the loop control unit is also used to promote the execution process of the loop iteration of the task. The loop control unit is configured to: for any two tasks with dependency, after the predecessor task is iteratively executed for a loop granularity number of times, execute a data transmission instruction once and trigger the successor task to iteratively execute a loop granularity number of times; when the number of iterations of the task reaches the total number of loops, notify the task launch queue to set the task state to end.

[0050] According to an embodiment of the present application, the loop control unit is also used to count the remaining resources of the PE array, i.e. the idle PE cores. The loop control unit sends the counted remaining resources of the PE array to the task launch queue.

[0051] According to one embodiment of the present application, based on the above device, a task runtime scheduling method for a data flow many-core processor can be implemented, which comprises the following operations performed in a runtime environment: obtaining an application program, generating a task flow graph describing the dependency relationship between tasks in the application program, wherein a node in the task flow graph represents a task, an edge between nodes represents a data dependency relationship, the start point of the edge represents a predecessor task, the end point of the edge represents a successor task, and each node records attribute information of the task; when there is a free space in a task launch queue, selecting a task according to the data dependency relationship from the task flow graph, and transmitting the attribute information of the selected task into the task launch queue; according to the remaining resources of the PE array, the remaining resources of the on-chip storage space, and the attribute information of each task, marking the resource-adapted tasks in the task launch queue to construct a task group; preprocessing the tasks in the task group to obtain a preprocessed task group, and mapping the preprocessed task group to the PE array for execution, wherein the preprocessing comprises: marking the source data address and the result data address of each task according to a preset address marking manner, and identifying an associated pair composed of two tasks with data dependency in the task group, and modifying the microinstruction code corresponding to the predecessor task and the successor task in the associated pair, so that the PE core processing the predecessor task directly transmits the result data to the PE core processing the successor task.

[0052] According to one example of the present application, as shown in the accompanying drawings, Figure 5 a schematic implementation flow of a task runtime scheduling method for a data flow many-core processor is provided, which comprises: A1, A2, A3, and A4.

[0053] Among them:

[0054] A1, the MCU generates a task flow graph G according to an application program P, records the node attribute information in the graph, and transmits the tasks to be executed to a task launch queue.

[0055] The schematic flow of step A1 is shown in Figure 6S1, the MCU first generates a task flow graph G describing the dependency between tasks according to the configuration information of the application P, the task flow graph G is described in a data structure, and the attribute information of the task needs to include: task serial number, predecessor task serial number, successor task serial number, task state, total cycle number, cycle granularity, source data size, address of source data in off-chip storage, result data size, address of result data in off-chip storage, and number of PE cores used. These attribute information is used as the judgment condition for task runtime scheduling, and also includes the information of task execution. Initially, the task state of all tasks in all task flow graphs G is in the idle state, at this time, according to whether there is space to accommodate the task attribute information in the task launch queue, if yes, the task state of the root node of the task flow graph G is set to the wake state. Whenever a task is changed to the wake state, the attribute information of the task needs to be sent to the task launch queue, and if the task launch queue still has space to accommodate the attribute information of the task, the task state of the successor task of the task needs to be changed to the wake state, and the cycle is repeated. If the task has no successor task, the MCU can find other tasks that are in the wake state and transmit the attribute information of the tasks to the task launch queue according to the same process, so as to improve the performance of parallel processing of the processor and the utilization rate of the PE array.

[0056] A2, the task launch module constructs a task group and pre-processes the tasks in the task group.

[0057] The schematic flow of step A2 is shown in Figure 6 S2, the attribute information of each task in the wake state is recorded in the task launch queue, as shown in Figure 3As shown, it includes task serial number, predecessor task serial number, successor task serial number, task state, predecessor task state, total cycle number, cycle granularity, source data size, result data size, source data address, result data address, number of PE cores used, and mapped PE core serial number. First, the task launch queue selects a task whose predecessor task state is over, and if there are multiple selectable tasks, the task that enters the task launch queue earlier is selected first. After selecting the task, it is determined whether the task can meet the requirements of the remaining resources of the PE array and the remaining resources of the on-chip storage space. If not, another task whose predecessor task state is over is selected. If yes, the task is marked as a task to be executed, and the successor task of the task is determined. After integrating the required resources of the predecessor task and the successor task, it is determined whether the requirements of the remaining resources of the PE array and the remaining resources of the on-chip storage space can still be met. If yes, the successor task is marked as a task to be executed. If there is no successor task, another task whose predecessor task state is over is selected, and it is determined whether the task can meet the requirements of the remaining resources of the PE array and the remaining resources of the on-chip storage space after being integrated with the marked tasks. Each selected task needs to be integrated with the marked tasks. Only when the required resources after integration can meet the requirements of the remaining resources of the PE array and the remaining resources of the on-chip storage space, the selected task can be marked as a task to be executed. In this way, a task group to be executed is selected by continuously marking tasks until no task that meets the requirements can be found in the task launch queue.

[0058] After selecting the task group to be executed, each task in the task group needs to be preprocessed. The address calibration unit calibrates the addresses of the source data and the result data of each task in the selected task group in the on-chip storage. For any two tasks with a dependency relationship, only the source data address of the predecessor task and the result data address of the successor task need to be calibrated. If a task has both a predecessor task and a successor task in the task group, the source data address and the result data address of the task do not need to be marked. The address calibration unit not only needs to calibrate the tasks, but also needs to record the states of the tasks whose addresses are calibrated, and according to the data addresses of these tasks, the remaining resources of the on-chip storage space are counted. When the task state is over, the on-chip storage space resources occupied by the task need to be released.

[0059] The pre-processing not only designates addresses for the tasks in the task group, but also receives microinstruction codes of each task in the task group from off-chip storage by the loop control unit, and allocates mapped PE core serial numbers to each task according to the remaining resources of the PE array. For any two tasks in the task group with a dependency relationship, the microinstruction codes of the tasks need to be changed, the storage instructions of the predecessor task to store the result data back to the on-chip storage and the loading instructions of the successor task to load the source data to the PE core are hidden (such as deleted or ignored), and a data transmission instruction block is generated and inserted into the position of the storage instructions of the predecessor task, and the data transmission instruction is generated according to the information of the storage instructions of the predecessor task and the loading instructions of the successor task, including the PE core serial numbers corresponding to the storage instructions and the loading instructions of the data operating on the same address, and the register serial numbers of the data in the corresponding storage instructions and loading instructions, so as to realize the direct transmission of a group of data from the PE core of the predecessor task to the PE core of the successor task. The loop control unit also needs to be responsible for counting the remaining resources of the PE array, that is, the PE cores that have not been mapped to tasks.

[0060] A3, the task group is mapped to the PE array for execution, and the task state of each task is updated after the execution of any one task ends.

[0061] The specific process of this step is shown in S3 of Figure 6 After the pre-processing of the selected task group is completed, the tasks in the task group can be mapped to the PE array according to the allocated PE core serial numbers, the microinstruction codes of the tasks are loaded by the loop control unit, and the source data is moved from off-chip storage to on-chip storage according to the designated addresses by DMA. After the instructions and source data are loaded, the loop control unit will promote the execution of the tasks, and the total number of cycles in the task attribute information is used as the number of iterations of the task, and the loop granularity refers to the number of iterations of the task required to obtain result data from a group of source data. For any two tasks with a dependency relationship, after each iteration of the predecessor task is executed for a loop granularity, a data transmission instruction block is executed, and then the iteration of the successor task is triggered for a loop granularity. In this way, when a group of source data of the predecessor task A obtains a group of result data, it can be immediately transmitted to the successor task B as a group of source data to trigger an iteration of a loop granularity, and the task B can also transmit the result data to the successor task C and trigger the execution of the task C after obtaining a group of result data. In this way, a group of data can be continuously transmitted and flowed among tasks with a dependency relationship, realizing the pipelining execution of data among tasks, and also reducing the access to on-chip storage and improving the execution efficiency of the application program.

[0062] After the task execution ends, for the task whose result data is taken over by the subsequent task, the task can be directly ended, and for the task whose result data is not taken over, the loop control unit sends a request to the DMA, and the task result data is carried from the on-chip storage to the off-chip storage according to the on-chip storage address and the off-chip storage address. After the carrying ends, the task execution ends, and the information that the task execution ends is sent to the task launch queue and the address calibration unit, the state of the corresponding task is updated to over, and the MCU is sent at the same time, and the MCU updates the task state to over.

[0063] A4, the application program P ends, and the result data is transmitted from the on-chip storage to the off-chip storage through the DMA.

[0064] When the state of all tasks in the task flow graph G of the application program P in the MCU is over, it indicates that the application program ends, and the result data is transmitted from the on-chip storage to the off-chip storage through the DMA for access by the general processor.

[0065] In general, the scheme provided by the embodiment of the application has at least one of the following beneficial effects:

[0066] (1) By sensing the remaining resources of the PE array and the on-chip storage resources required by the tasks in real time, the tasks that can be executed in the task list are dynamically scheduled and mapped to the PE array, the parallelism between the tasks is mined, the idling of the PE core is reduced, and the utilization rate of the PE array is improved.

[0067] (2) For tasks with data dependencies, the application provides a method for changing the task microinstruction code, which can execute the data blocks independent of each other in the source data of the predecessor task in a pipelined manner between tasks with dependencies, so that the tasks with data dependencies do not need to interact data through the on-chip storage, but directly transmit data between the PE cores, thereby improving the execution efficiency of the application program.

[0068] It should be noted that although the above describes the steps in a specific order, it does not mean that the steps must be performed in the above specific order, and in fact, some of the steps can be performed concurrently or even in a changed order, as long as the desired function can be achieved.

[0069] The application can be a system, a method and / or a computer program product. The computer program product can include a computer readable storage medium having computer readable program instructions loaded thereon for causing a processor to implement various aspects of the application.

[0070] A computer readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, semiconductor, or any other suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves.

[0071] Having described above several embodiments, now will be described a number of modifications and alternatives. Such description is included to provide for a more complete understanding of the various embodiments and is not intended in any way to limit the scope of possibilities. Many modifications in addition to those described above can be made by one skilled in the relevant art without departing from the scope and spirit of the described embodiments. The scope of the various embodiments disclosed herein is limited only by the claims. The terms used in this document are to be interpreted in their broadest reasonable manner, such that the principles and practical application of the various embodiments can be best explained and understood.

Claims

1. A task runtime scheduling method for a data stream multi-core processor, characterized in that: This includes performing the following actions in the runtime environment: Obtain the application and generate a task flow graph that describes the dependencies between tasks within the application. A node in the task flow graph represents a task, and edges between nodes represent data dependencies. The starting point of an edge represents a predecessor task, and the end point of an edge represents a successor task. Each node records the attribute information of a task. When there is free space in the task launch queue, a task is selected from the task flow graph according to the data dependency relationship, and the attribute information of the selected task is transferred to the task launch queue; According to the remaining resources of the PE array, the remaining resources of the on-chip storage space and the attribute information of each task, the resource-adapted tasks are marked from the task launch queue to build a task group; Preprocessing the tasks in the task group to obtain a preprocessed task group, and mapping the preprocessed task group to a PE array for execution, wherein the preprocessing includes: identifying an association pair consisting of two tasks with data dependency in the task group, and modifying microinstruction codes corresponding to a predecessor task and a successor task in the association pair so that the PE core processing the predecessor task directly transmits result data to the PE core processing the successor task.

2. The method according to claim 1, characterized in that The microinstruction codes corresponding to the predecessor task and the successor task in the modification association include: Replace the storage instruction in the microinstruction code corresponding to the predecessor task with a data transfer instruction, wherein the storage instruction is used to instruct the result data of the predecessor task to be stored in the on-chip storage, and the data transfer instruction is used to instruct the PE core processing the predecessor task to directly transfer the result data to the PE core processing the successor task via the on-chip network; The load instruction in the microinstruction code corresponding to the successor task is removed, where the load instruction is used to instruct the load instruction to load result data of the predecessor task in the associated pair from the on-chip storage.

3. The method according to claim 2, characterized in that The attribute information of the task includes the task number, the subsequent task number and the task status, wherein the task status includes pending activation and awakening, and the initial task status of all tasks is pending activation; The methods for selecting tasks from the task flow diagram based on data dependencies include: When all non-root nodes have no predecessor tasks that have been passed into the task launch queue, a root node of the task flow graph is selected from the set of the current task flow graph, and the task attributes of the task corresponding to the root node are passed into the task launch queue; Otherwise, the task attributes of the successor tasks to be activated are passed into the task emission queue one by one according to the data dependency relationship, wherein the task state in the task attributes initially passed into the task emission queue is modified to awakening.

4. The method according to claim 3, characterized in that The attribute information of the task also includes: the predecessor task number, the source data size, the result data size and the number of PE cores used. The task status also includes executing and completed. The task group is constructed according to the predecessor task number and task status according to the preset construction rules. The rules include: Based on the predecessor task sequence number and task status, identify the candidate tasks whose task status of the predecessor task is completed, and select tasks from the candidate tasks in the order of the time they entered the task launch queue from the earliest to the latest. Among them, the task corresponding to the root node is considered as the candidate task; After each task is selected, it is determined whether the resources required after integrating the selected task with the marked tasks meet the requirements based on the source data scale, result data scale and PE core used. If so, the selected task is set as the marked task, and the successor task of the marked task is continued to be selected. If not, other alternative tasks are selected until no alternative task that meets the requirements is found in the task launch queue, wherein the requirement is that the resources required after integration do not exceed the remaining resources of the PE array and the remaining resources of the on-chip storage space.

5. The method according to claim 4, characterized in that The attribute information of the task also includes: a mapped PE core sequence number, wherein after the pre-processed task group is mapped to the PE array for execution, the mapped PE core sequence number corresponding to the PE core processing each task is filled into the task emission queue, and the task status is modified to being executed.

6. The method according to claim 5, characterized in that The attribute information of the task also includes: the total number of loops and the loop granularity, wherein the total number of loops refers to the total number of iterative executions of the task, and the loop granularity refers to the number of iterative executions of the task required to obtain result data that can be passed to the subsequent task each time; The method further comprises: For any two tasks with a dependency relationship, after the predecessor task iterates for the number of loop granularity times, a data transfer instruction is executed, and the successor task is triggered to iterate for one loop granularity number; When the number of task iterations reaches the total number of loops, the task status is set to ended.

7. The method according to claim 6, characterized in that The attribute information of the task also includes: a source data address and a result data address, and the method further includes: Calibrate the source data address and result data address of each task according to the preset address calibration method, including: For a task that has no predecessor task or successor task in the task group, the address of the source data in the on-chip storage is calibrated in the source data address of the task, and the address of the result data in the on-chip storage is calibrated in the result data address of the task; For a task that has only a successor task in the task group, the address of the source data in the on-chip storage is calibrated only in the source data address of the task; For a task that has only a predecessor task in the task group, the address of the result data in the on-chip storage is calibrated only in the result data address of the task; For a task that has both a predecessor task and a successor task in the task group, the source data address and result data address of the task do not need to be calibrated; According to the calibrated source data address, the source data required by the task is read when the task is executed; According to the calibrated result data address, the result data is saved at the corresponding address of the on-chip storage at the end of the task execution.

8. A task runtime scheduling device for a data stream many-core processor, configured to implement the method according to any one of claims 1 to 7, comprising: The microcontroller module is configured to: obtain an application program, generate a task flow graph describing the dependency relationships between tasks within the application program, wherein a node in the task flow graph represents a task, an edge between nodes represents a data dependency relationship, a starting point of an edge represents a predecessor task, and an end point of an edge represents a successor task, and each node records attribute information of a task; and when there is free space in a task launch queue, select a task from the task flow graph according to the data dependency relationship, and transfer the attribute information of the selected task to the task launch queue; The task launch module is configured to: construct a task group from tasks marked with resource adaptation in the task launch queue according to the remaining resources of the PE array, the remaining resources of the on-chip storage space and the attribute information of each task; And preprocessing the tasks in the task group to obtain a preprocessed task group, mapping the preprocessed task group to the PE array for execution, wherein the preprocessing includes: identifying an association pair consisting of two tasks with a data dependency relationship in the task group, and modifying the microinstruction code corresponding to the predecessor task and the successor task in the association pair so that the PE core of the predecessor task directly transmits the result data to the PE core processing the successor task.

9. A computer-readable storage medium, characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: one or more processors; as well as a memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of one of claims 1 to 7 by executing the executable instructions.

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