Timing optimization method and pin allocation circuit for priority pin multiplexer

Abstract

The present application discloses a timing optimization method and pin allocation circuit for a priority pin multiplexer. The timing optimization method includes obtaining the signal to be timing optimized and collecting the signals corresponding to the same pin pad into a queue; obtaining the initial pin multiplexer architecture of the pin pad corresponding to each queue; obtaining the initial priority of each signal in the queue to obtain the signal to be optimized and the calibration signal; constructing an update unit, connecting the signal to be optimized and its corresponding calibration signal to the update unit, and connecting the output of the update unit to the target selector. The present application can meet the high-speed and balanced requirements of peripherals without modifying the system pin multiplexer definition and redesigning a faster unit library, consuming minimal resources; it can be applied to the timing ECO process to achieve the high-speed requirements and timing balance requirements of the target signal without affecting the existing timing of other multiplexing functions on the same pin.

Description

Technical Field

[0001] The present application belongs to the field of circuit design technology, and specifically relates to a timing optimization method for a priority pin multiplexer and a pin allocation circuit. Background Art

[0002] MCUs are integrating an increasing number of peripherals, and to cater to diverse application scenarios, chip packaging options are also diversifying. To maximize functionality within a small package, the pin multiplexing defined by input / output multiplexers (IOMUXs) is increasing. The complexity of pin multiplexing directly impacts chip timing closure, especially for peripherals with high-speed and balanced timing requirements, such as the Serial Peripheral Interface (SPI) and high-precision pulse-width modulation (HRPWM).

[0003] Specifically, for peripherals with high-speed requirements, the signals that define their functions have a low priority in the pin multiplexer, and the inherent cell library delay will lead to transmission speed limitations. Among them, the low priority is a system requirement and is not particularly easy to adjust due to compatibility and application requirements. The delay of the inherent cell library also has no particularly large adjustment space after the project process node and standard cell library are selected. For peripherals with timing balance requirements, multiple signals that require timing balance usually have different priorities in the pin multiplexer. Currently, the main method of adjusting the timing is to add dummy cells, resulting in the timing being limited by the lowest priority signal. In addition, high-speed requirements and timing balance requirements are usually established on the same peripheral at the same time. The dummy delay increases the delay on the functional path, resulting in high speed and balance not being able to be met at the same time. Summary of the Invention

[0004] The purpose of this application is to provide a timing optimization method and pin allocation circuit for a priority pin multiplexer, so as to solve the technical problem that the complexity of pin multiplexer multiplexing in the prior art directly brings difficulties to the timing convergence of the chip, especially for peripherals with high-speed timing requirements and timing balance requirements, and it is difficult to meet their high-speed and timing balance requirements.

[0005] To achieve the above objectives, the present application provides, in a first aspect, a timing optimization method for a priority pin multiplexer, comprising:

[0006] Obtain the signals to be optimized for timing, and collect the signals corresponding to the same pin pad into a queue;

[0007] Obtaining an initial pin multiplexer structure of the pin pad corresponding to each queue, wherein the initial pin multiplexer structure includes a plurality of selectors sorted according to priority, and an input terminal of each selector is connected to a signal;

[0008] Based on the initial architecture of the pin multiplexer, obtaining the initial priority of each signal in the queue, and obtaining a signal to be optimized and a calibration signal, wherein the signal to be optimized is the signal in the queue whose priority is to be increased, and the calibration signal is the timing optimization target of the signal to be optimized;

[0009] An update unit is constructed in the initial architecture of the pin multiplexer, the signal to be optimized and its corresponding calibration signal are connected to the update unit, and the output end of the update unit is connected to a target selector so that the priority of the signal to be optimized and the calibration signal are consistent. The target selector is the selector to which the calibration signal in the initial architecture of the pin multiplexer is connected.

[0010] In one or more embodiments, the queue includes multiple signals to be time-balanced, and the step of obtaining the signal to be optimized and the calibration signal is specifically:

[0011] The signal with the highest priority in the queue is used as the calibration signal, and the remaining signals are used as the signals to be optimized.

[0012] In one or more embodiments, the queue includes one or more signals with high-speed requirements, and the steps of obtaining the signal to be optimized and the calibration signal are specifically as follows:

[0013] Each signal in the queue is used as the signal to be optimized, and the signal at the target priority in the initial architecture of the pin multiplexer is used as the calibration signal, where the target priority is the priority corresponding to the high-speed requirement of the signal to be optimized.

[0014] In one or more embodiments, the update unit includes an update selector and an OR gate, wherein the update selector is used to select one of the signal to be optimized and its corresponding calibration signal and transmit it to the input end of the target selector, and the OR gate is used to transmit the control signal of the signal to be optimized and / or the control signal of the calibration signal to the control end of the target selector.

[0015] In one or more embodiments, the step of constructing the update unit in the initial architecture is specifically as follows:

[0016] Connecting the signal to be optimized and the calibration signal to the input end of the update selector respectively, and connecting the output end of the update selector to the input end of the target selector;

[0017] Connecting all or part of the control signal of the signal to be optimized and the control signal of the calibration signal to the control terminal of the update selector, so that the update selector can select any signal to output to the target selector;

[0018] The control signal of the signal to be optimized and the control signal of the calibration signal are connected to the input end of the OR gate, and the output end of the OR gate is connected to the control end of the target selector.

[0019] In one or more embodiments, the queue includes n signals to be optimized, the n signals to be optimized correspond to the same calibration signal, and the update selector includes n+1 input terminals and 1 output terminal, where n is a positive integer.

[0020] In one or more embodiments, the queue includes m signals to be optimized, at least two of the m signals to be optimized correspond to different calibration signals, where m is a positive integer greater than 1;

[0021] The steps of constructing an update unit in the pin multiplexer initial architecture are specifically: constructing an update unit for each calibration signal, connecting the update unit to the target selector corresponding to the calibration signal, and connecting the calibration signal and its corresponding signal to be optimized to the update unit.

[0022] A second aspect of the present application provides a pin allocation circuit, comprising:

[0023] Multiple selectors, sorted by priority;

[0024] An update unit has a plurality of target signals connected to its input end and a target selector connected to its output end so that the priorities of the plurality of target signals are consistent. The target selector is a selector with a target priority among the plurality of selectors.

[0025] In one or more embodiments, the updating unit includes:

[0026] an update selector, wherein the input end is connected to the plurality of target signals and the output end is connected to the input end of the target selector;

[0027] an OR gate, an input end of which is connected to the control signal of the plurality of target signals, and an output end of which is connected to the control end of the target selector;

[0028] Wherein, all or part of the control signals of the plurality of target signals are connected to the control terminal of the update selector, so that the update selector can select any one of the target signals to be output to the target selector.

[0029] In one or more embodiments, among the multiple selectors, the output end of each of the selectors is connected to the input end of a selector with a higher priority, the output end of the selector with the highest priority is connected to the corresponding pin pad, the input end of the selectors other than the target selector is connected to a signal, and the control end is connected to the control signal of the signal.

[0030] Different from the prior art, the present invention has the following advantages:

[0031] The timing optimization method and pin allocation circuit of the priority pin multiplexer of the present application can meet the high-speed and balanced requirements of the peripheral pin multiplexer multiplexing without modifying the system pin multiplexer definition and redesigning a faster unit library, and consumes very little resources; it can be applied to the timing design change ECO process, and can achieve the high-speed requirements and timing balance requirements of the target signal without affecting the existing timing of other multiplexing functions of the same pin. The ECO solution is simple and clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a flow chart of an implementation method of a timing optimization method for a priority pin multiplexer of the present application;

[0034] Figure 2 This is a structural diagram of an implementation scheme of the initial architecture of the pin multiplexer of the present application;

[0035] Figure 3 This application Figure 1 A schematic flow chart of an implementation method corresponding to S400;

[0036] Figure 4 It is a structural diagram of an embodiment of the update unit of the present application;

[0037] Figure 5 It is a structural diagram of another embodiment of the updating unit of the present application;

[0038] Figure 6 It is a structural diagram of another embodiment of the updating unit of the present application;

[0039] Figure 7 It is a structural diagram of another implementation method of the update unit of this application. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0041] The complexity of pin multiplexer multiplexing makes it difficult to close chip timing, especially for peripherals with high-speed and balanced timing requirements, such as the Serial Peripheral Interface (SPI) and high-precision pulse width modulation (HRPWM).

[0042] Currently, for peripherals with high-speed signal requirements, the timing optimization of their signals is limited by the pin multiplexer priority and the fixed cell library delay. The lower priority belongs to the system requirements and is not particularly easy to adjust due to compatibility and application requirements. The delay of the inherent cell library also has no particularly large adjustment space after the project process node and standard cell library are selected.

[0043] For peripherals that require timing balance for some signals, the timing is mainly adjusted by adding delay cells (dummy cells), resulting in the timing being limited by the lowest-priority signal. Moreover, high-speed requirements and timing balance requirements are usually established on the same peripheral at the same time. The dummy delay will increase the delay on the functional path, resulting in the inability to simultaneously meet high speed and balance.

[0044] In order to solve the above problems, the applicant has developed a new timing optimization method, which can meet the high-speed and balanced requirements of peripheral pin multiplexer multiplexing without modifying the system pin multiplexer definition and redesigning a faster unit library; especially during the timing design change (Engineering Change Order, ECO) process, the high-speed requirements and timing balance requirements of the target signal can be achieved without affecting the existing timing of other multiplexed functions on the same pin.

[0045] Specifically, see Figure 1 , Figure 1 It is a flow chart of an implementation method of a timing optimization method for a priority pin multiplexer of the present application.

[0046] like Figure 1 As shown, the method includes:

[0047] S100: Acquire signals to be timing optimized, and collect signals corresponding to the same pin pad into a queue.

[0048] In one embodiment, the signal to be timing optimized may be a signal to increase transmission speed, i.e., a signal to increase priority. This signal may be a signal defining a peripheral function with high-speed requirements. In practical applications, each pin pad may correspond to one or more signals with high-speed requirements, i.e., each queue may include one or more signals.

[0049] In another embodiment, the signal to be timing optimized may be multiple signals requiring timing balance, such as timing balance between a clock line and a data line of a communication module. It is necessary to reduce the time difference between multiple signals to achieve the purpose of timing balance.

[0050] It should be noted that multiple signals that require timing optimization may correspond to different pin pads PAD. For example, SCK (clock signal) / MISO (master input / slave output signal) / MOSI (master output / slave input signal) in the serial peripheral interface SPI need to be balanced. The functions can be defined in pin pad PAD1, pin pad PAD2, and pin pad PAD3 respectively. The multiple signals corresponding to each pin pad need to be collected separately into a queue to facilitate subsequent timing optimization.

[0051] S200: Obtain an initial pin multiplexer structure of pin pads corresponding to each queue.

[0052] The pin multiplexer initial structure of each pin pad defines its multiplexed functions and the priority of each function. The pin multiplexer initial structures corresponding to different pin pads can be the same or different. For details, please refer to Figure 2 , Figure 2 This is a structural diagram of an implementation scheme of the initial architecture of the pin multiplexer of the present application.

[0053] like Figure 2 As shown, in one embodiment, the pin multiplexer initial architecture may include a plurality of selectors sorted by priority, each selector may include at least two input terminals, an output terminal and a control terminal, one input terminal of each selector is connected to a signal AF_OUTx, the control terminal is connected to a control signal AF_SELx, and the output terminal is connected to the input terminal of a selector with a higher priority level.

[0054] Based on the above structure, the corresponding signal AF_OUTx can be enabled by controlling the signal AF_SELx to achieve selective output of multiple signals.

[0055] Of course, in other implementations, the pin multiplexer initial architecture of the present application may also adopt other pin multiplexing architectures commonly used in the art, and all of them can achieve the effects of the present implementation.

[0056] S300 , based on the initial architecture of the pin multiplexer, obtain the initial priority of each signal in the queue, and obtain the signal to be optimized and the calibration signal.

[0057] In the original architecture of the pin multiplexer, each input terminal of the selector is connected to a signal in order of priority. Therefore, the priority of the selector represents the priority of the signal connected to its input terminal.

[0058] Based on the initial architecture of the pin multiplexer, the initial priority of each signal in the queue can be obtained, thereby obtaining the signal to be optimized and the calibration signal.

[0059] The signal to be optimized is a signal in the queue whose priority is to be increased, and the calibration signal is a timing optimization target of the signal to be optimized.

[0060] In one embodiment, when a queue includes several signals with high-speed requirements, each signal in the queue is a signal to be optimized, and the timing optimization target of each signal to be optimized is a calibration signal.

[0061] For example, in Figure 2 In the initial pin multiplexer architecture shown, the signal to be optimized may be AF_OUT5. Before optimization, its priority is 7, and its target priority for high-speed requirements is 2. In this case, the signal AF_OUT0 at priority 2 is its calibration signal.

[0062] It can be understood that when the queue includes multiple signals to be optimized with high-speed requirements, the calibration signals corresponding to the multiple signals can be the same or different. For example, the target priorities of the high-speed requirements of the signals to be optimized AF_OUT5 and AF_OUT4 can be 2 and 3 respectively, then the calibration signals of the signals to be optimized AF_OUT5 and AF_OUT4 are AF_OUT0 and AF_OUT1 respectively.

[0063] In another embodiment, when a queue includes multiple signals that require timing balancing, the signal with the highest priority in the queue may be used as a calibration signal, and the remaining signals may be used as signals to be optimized.

[0064] For example, when the queue includes signals AF_OUT5 and AF_OUT0, the signal AF_OUT0 can be used as a calibration signal, and the signal AF_OUT5 can be used as a signal to be optimized.

[0065] It can be understood that when the queue includes three signals that require timing balance, illustratively, the queue includes signals AF_OUT5, AF_OUT4, and AF_OUT0. At this time, signal AF_OUT0 can be used as a calibration signal, and signals AF_OUT4 and AF_OUT5 can be used as signals to be optimized.

[0066] Of course, in some embodiments, the queue may also include multiple calibration signals to achieve timing balance of two groups of signals at the same time. For example, the queue includes signals AF_OUT5, AF_OUT4, AF_OUT1, and AF_OUT0, wherein signals AF_OUT5 and AF_OUT0 require timing balance, and signals AF_OUT4 and AF_OUT1 require timing balance. At this time, signal AF_OUT5 can be used as the signal to be optimized, and signal AF_OUT0 can be used as its calibration signal. Signal AF_OUT4 can be used as the signal to be optimized, and signal AF_OUT1 can be used as its calibration signal.

[0067] S400 , constructing an update unit in the initial architecture of the pin multiplexer, connecting the signal to be optimized and its corresponding calibration signal to the update unit, and connecting the output end of the update unit to the target selector.

[0068] The target selector is a selector for calibrating signal connections in the initial architecture of the pin multiplexer.

[0069] After obtaining the signal to be optimized and the calibration signal as described above, an update unit connected to the target selector may be constructed in the initial architecture of the pin multiplexer.

[0070] The signal to be optimized and the calibration signal are connected through the update unit, and one signal is selected to be output to the target selector to achieve the same priority of the signal to be optimized and the calibration signal, thereby achieving timing optimization.

[0071] Specifically, the update unit may include an update selector and an OR gate, the update selector is used to select one of the signal to be optimized and its corresponding calibration signal and transmit it to the input end of the target selector, and the OR gate is used to transmit the control signal of the signal to be optimized and / or the control signal of the calibration signal to the control end of the target selector.

[0072] See also Figure 3 , Figure 3 This application Figure 1 A flow chart of an implementation method corresponding to S400.

[0073] like Figure 3 As shown in Figure 1, the steps to build an update unit in the initial pin multiplexer architecture include:

[0074] S401 , connecting the signal to be optimized and the calibration signal to the input end of the update selector respectively, and connecting the output end of the update selector to the input end of the target selector.

[0075] S402 , connecting all or part of the control signal of the signal to be optimized and the control signal of the calibration signal to the control terminal of the update selector, so that the update selector can select any signal to output to the target selector.

[0076] S403 , connecting the control signal of the signal to be optimized and the control signal of the calibration signal to the input end of an OR gate, and connecting the output end of the OR gate to the control end of the target selector.

[0077] Based on the above steps, the corresponding signals are enabled by controlling the control signal of the signal to be optimized and the control signal of the calibration signal, so that the update selector selects a signal from the signal to be optimized and the calibration signal and outputs it to the target selector.

[0078] Correspondingly, each control signal reaches the control end of the target selector through the OR gate, enabling the corresponding signal, thereby controlling the corresponding signal to be output by the target selector.

[0079] Since the signal to be optimized and the calibration signal are connected to an update selector and connected to the target selector through the update selector, the priority of the signal to be optimized and the calibration signal are consistent, thereby achieving the purpose of timing optimization.

[0080] For example, see Figure 4 , Figure 4 This is a schematic diagram of the structure of an embodiment of the update unit of the present application. Figure 4 As shown, in this embodiment, the queue includes the signal to be optimized AF_OUT5 and the calibration signal AF_OUT0, and the update selector 100 is a two-to-one selector, whose two input terminals are respectively connected to AF_OUT5 and AF_OUT0, and the output terminal is connected to one input terminal of the target selector 200.

[0081] The control terminal of the update selector 100 is connected to AF_SEL0 , and AF_OUT0 or AF_OUT5 can be transmitted to the input terminal of the target selector according to whether AF_SEL0 is enabled.

[0082] In this embodiment, the OR gate 300 is a dual OR gate, whose two input terminals are connected to AF_SEL0 and AF_SEL5 respectively, and whose output terminal is connected to the control terminal of the target selector 200 , thereby transmitting AF_SEL0 and / or AF_SEL5 to the control terminal of the target selector 200 .

[0083] It can be understood that when AF_SEL0 is enabled, AF_OUT0 is first transmitted to the target selector 200 , and synchronously, the target selector 200 is controlled to transmit AF_OUT0 to the next selector, and finally output to the pin pad PAD.

[0084] Since the signal to be optimized AF_OUT5 and the calibration signal AF_OUT0 are connected to the same selector, their priorities are consistent, achieving timing balance between the two signals and the high-speed requirement of the AF_OUT5 signal.

[0085] In another embodiment, when the queue includes n signals to be optimized, and the n signals to be optimized correspond to the same calibration signal, the update selector can be an n+1 selector, which connects the n signals to be optimized and a calibration signal at the same time. Figure 5 , Figure 5 It is a structural diagram of another embodiment of the updating unit of the present application.

[0086] like Figure 5 As shown, in this embodiment, the queue includes the signals to be optimized AF_OUT5, AF_OUT4 and the calibration signal AF_OUT0, and the update selector 100 is a three-to-one selector, whose three input ends are respectively connected to AF_OUT5, AF_OUT4 and AF_OUT0, and the output end is connected to an input end of the target selector 200.

[0087] The control terminal of the update selector 100 is connected to AF_SEL0 and AF_SEL4 , and AF_OUT0 , AF_OUT4 or AF_OUT5 can be transmitted to the input terminal of the target selector 200 depending on whether AF_SEL0 and AF_SEL4 are enabled.

[0088] In this embodiment, the OR gate 300 is a triple OR gate, whose three input terminals are connected to AF_SEL0, AF_SEL4 and AF_SEL5 respectively, and the output terminal is connected to the control terminal of the target selector 200, thereby transmitting AF_SEL0, AF_SEL4 and / or AF_SEL5 to the control terminal of the target selector 200.

[0089] It can be understood that when AF_SEL0 and AF_SEL4 are both not enabled, AF_OUT5 is transmitted to the input end of the target selector 200, and the synchronous AF_SEL5 controls the target selector 200 to output AF_OUT5, and finally outputs it to the pin pad PAD; when AF_SEL0 is enabled, AF_OUT0 is transmitted to the input end of the target selector 200, and the synchronous AF_SEL0 controls the target selector 200 to output AF_OUT0, and finally outputs it to the pin pad PAD.

[0090] Since the optimized signals AF_OUT5 and AF_OUT4 and the calibration signal AF_OUT0 are connected to the same selector, the three have the same priority, which achieves the timing balance of the three signals and the high-speed requirements of AF_OUT5 and AF_OUT4.

[0091] It should be noted that the above two embodiments only show examples in which the queue includes 1 or 2 signals to be optimized and one calibration signal. In other embodiments, the queue may also include other numbers of signals to be optimized, such as 3 or 4, etc. Correspondingly, the update selector may also be a 4-to-1 or 5-to-1 selector, etc., which can achieve the effect of this embodiment.

[0092] In another embodiment, the queue may include m signals to be optimized, and at least two of the m signals to be optimized may correspond to different calibration signals. An update unit may be constructed for each calibration signal, the update unit may be connected to the target selector corresponding to the calibration signal, and the calibration signal and its corresponding signal to be optimized may be connected to the update unit. Figure 6 , Figure 6 It is a structural diagram of another implementation method of the update unit of this application.

[0093] like Figure 6 As shown, in this embodiment, the queue includes the signals to be optimized AF_OUT5 and AF_OUT4 and the calibration signals AF_OUT0 and AF_OUT1, wherein AF_OUT0 corresponds to AF_OUT5, and AF_OUT1 corresponds to AF_OUT4.

[0094] The pin multiplexer architecture may include two update selectors 100 and two OR gates 300, wherein the two input terminals of one update selector 100 are connected to AF_OUT0 and AF_OUT5, respectively, and the output terminal is connected to the input terminal of the target selector 200 with a priority of 2; and the two input terminals of one OR gate 300 are connected to AF_SEL0 and AF_SEL5, respectively, and the output terminal is connected to the control terminal of the target selector 200 with a priority of 2.

[0095] The two input terminals of another update selector 100 are connected to AF_OUT1 and AF_OUT4 respectively, and the output terminal is connected to the input terminal of the target selector 200 with a priority of 3. The two input terminals of another OR gate 300 are connected to AF_SEL1 and AF_SEL4 respectively, and the output terminal is connected to the control terminal of the target selector 200 with a priority of 3.

[0096] Based on the above architecture, the timing balance of signals AF_OUT0 and AF_OUT5, the timing balance of signals AF_OUT1 and AF_OUT4, and the high-speed requirements of signals AF_OUT5 and AF_OUT4 are achieved.

[0097] It should be noted that the above embodiment only shows an example in which the queue includes two calibration signals. In other embodiments, the queue may also include other numbers of calibration signals, and a corresponding number of update selectors and OR gates may be constructed to achieve the effect of this embodiment, which will not be repeated here.

[0098] In another embodiment, the signals defining the peripheral functions may correspond to different pin pads, that is, the signals to be time-balanced may correspond to different pin pads, and the timing optimization of the pin multiplexer initial architecture for each pin pad is required. Figure 7 , Figure 7 It is a structural diagram of another implementation method of the update unit of this application.

[0099] like Figure 7 As shown, the signals that require timing balance in this embodiment include the signal AF_OUT5 of the pin pad PAD1, the signal AF_OUT4 of the pin pad PAD2, and the signal AF_OUT0 of the pin pad PAD3. Therefore, it is necessary to construct update units in the pin multiplexer initial architecture of the pin pad PAD1 and the pin pad PAD2 respectively to balance the timing of the signals AF_OUT5, AF_OUT4, and AF_OUT0.

[0100] Specifically, the two input terminals of update selector 100 on pad PAD1 are connected to AF_OUT5 and AF_OUT0, respectively, and the output terminal is connected to an input terminal of target selector 200. The control terminal of update selector 100 is connected to AF_SEL0, and depending on whether AF_SEL0 is enabled, AF_OUT0 or AF_OUT5 can be transmitted to the input terminal of the target selector. The two input terminals of OR gate 300 are connected to AF_SEL0 and AF_SEL5, respectively, and the output terminal is connected to the control terminal of target selector 200, thereby transmitting AF_SEL0 and / or AF_SEL5 to the control terminal of target selector 200.

[0101] Update selector 100 on pad PAD2 has two inputs connected to AF_OUT4 and AF_OUT0, respectively, and an output connected to an input of target selector 200. Update selector 100 has a control terminal connected to AF_SEL0, and depending on whether AF_SEL0 is enabled, it can transmit either AF_OUT0 or AF_OUT4 to the input of the target selector. OR gate 300 has two inputs connected to AF_SEL0 and AF_SEL4, respectively, and an output connected to the control terminal of target selector 200, thereby transmitting AF_SEL0 and / or AF_SEL4 to the control terminal of target selector 200.

[0102] Based on the above implementation, the timing balance of different functional signals on different pin pads can be accelerated.

[0103] It should be noted that in the above-mentioned embodiments, among the n signals connected to the input end of each update selector, only the control signals of n-1 signals are connected to the control end of the update selector, and the selection output of another signal can be achieved based on the fact that none of the n-1 control signals are enabled; in other embodiments, the control signals of all signals connected to the input end of the update selector can also be connected to the control end of the update selector, which can also achieve the effect of this embodiment.

[0104] The timing optimization method based on the above-mentioned embodiments can meet the high-speed and balanced requirements of peripheral pin multiplexer multiplexing without modifying the system pin multiplexer definition and redesigning a faster cell library.

[0105] Especially during the ECO process of timing design changes, whether it is the pre-silicon or post-silicon ECO process, the high-speed requirements and timing balance requirements of the target signal can be achieved without affecting the existing timing of other multiplexed functions on the same pin.

[0106] This application also provides a pin allocation circuit obtained by optimizing the initial architecture of the pin multiplexer using the above timing optimization method. Figures 4 to 7 The pin allocation circuit includes a plurality of selectors 10 arranged in order of priority, wherein the output end of each selector 10 is connected to an input end of a selector 10 with a higher priority, and the output end of the selector 10 with the highest priority is connected to the corresponding pin pad.

[0107] Multiple selectors 20 include a target selector 200 with a target priority, one input end of the target selector 200 is connected to the output end of the previous selector 10, and the other input end is connected to the update unit; one input end of the remaining selectors 20 is connected to the output end of the previous selector 10, and the other input end is connected to a signal.

[0108] Specifically, the update unit includes an update selector 100 and an OR gate 200; the input end of the update selector 100 is connected to multiple target signals, and the output end is connected to the input end of the target selector 200; the input end of the OR gate 300 is connected to the control signal of multiple target signals, and the output end is connected to the control end of the target selector 200.

[0109] Among the control signals of the n target signals, n−1 control signals are connected to the control terminal of the update selector 100 , so that the update selector 100 can select any target signal to output to the target selector 200 .

[0110] It should be noted that if Figures 4 and 5 As shown, the pin allocation circuit in this embodiment can include any number of update selectors 100 and OR gates 200. The number of input terminals of the update selector 100 can be designed based on the number of target signals actually connected. The control terminal of the update selector 100 can be connected to the control signals of all target signals or the control signals of some target signals. It only needs to realize the selective output of each target signal, and the effect of this embodiment can be achieved.

[0111] Based on the above structure, the timing balance and high-speed requirements of multiple target signals can be achieved. The high-speed and balanced requirements of peripheral pin multiplexer multiplexing can be met without modifying the system pin multiplexer definition or redesigning a faster cell library. Especially during the timing design change ECO process, whether it is pre-silicon or post-silicon ECO, the high-speed and timing balance requirements of the target signal can be achieved without affecting the existing timing of other multiplexed functions on the same pin.

[0112] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0113] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A timing optimization method for a priority pin multiplexer, characterized in that: include: Obtain the signals to be optimized for timing, and collect the signals corresponding to the same pin pad into a queue; Obtaining an initial pin multiplexer structure of the pin pad corresponding to each queue, wherein the initial pin multiplexer structure includes a plurality of selectors sorted according to priority, and an input terminal of each selector is connected to a signal; Based on the initial architecture of the pin multiplexer, obtaining the initial priority of each signal in the queue, and obtaining a signal to be optimized and a calibration signal, wherein the signal to be optimized is the signal in the queue whose priority is to be increased, and the calibration signal is the timing optimization target of the signal to be optimized; An update unit is constructed in the initial architecture of the pin multiplexer, the signal to be optimized and its corresponding calibration signal are connected to the update unit, and the output end of the update unit is connected to a target selector so that the priority of the signal to be optimized and the calibration signal are consistent. The target selector is the selector to which the calibration signal in the initial architecture of the pin multiplexer is connected.

2. The timing optimization method according to claim 1, wherein: The queue includes multiple signals to be time-balanced, and the steps of obtaining the signals to be optimized and the calibration signals are specifically as follows: The signal with the highest priority in the queue is used as the calibration signal, and the remaining signals are used as the signals to be optimized.

3. The timing optimization method according to claim 1, wherein: The queue includes one or more signals with high-speed requirements, and the steps of obtaining the signal to be optimized and the calibration signal are specifically as follows: Each signal in the queue is used as the signal to be optimized, and the signal at the target priority in the initial architecture of the pin multiplexer is used as the calibration signal, where the target priority is the priority corresponding to the high-speed requirement of the signal to be optimized.

4. The timing optimization method according to claim 1, wherein: The update unit includes an update selector and an OR gate, wherein the update selector is used to select one of the signal to be optimized and its corresponding calibration signal and transmit it to the input end of the target selector, and the OR gate is used to transmit the control signal of the signal to be optimized and / or the control signal of the calibration signal to the control end of the target selector.

5. The timing optimization method according to claim 4, characterized in that: The steps of constructing the update unit in the initial architecture are specifically as follows: Connecting the signal to be optimized and the calibration signal to the input end of the update selector respectively, and connecting the output end of the update selector to the input end of the target selector; Connecting all or part of the control signal of the signal to be optimized and the control signal of the calibration signal to the control terminal of the update selector, so that the update selector can select any signal to output to the target selector; The control signal of the signal to be optimized and the control signal of the calibration signal are connected to the input end of the OR gate, and the output end of the OR gate is connected to the control end of the target selector.

6. The timing optimization method according to claim 4, wherein: The queue includes n signals to be optimized, and the n signals to be optimized correspond to the same calibration signal. The update selector includes n+1 input terminals and 1 output terminal, wherein n is a positive integer.

7. The timing optimization method according to claim 4, characterized in that: The queue includes m signals to be optimized, at least two of the m signals to be optimized correspond to different calibration signals, wherein m is a positive integer greater than 1; The steps of constructing an update unit in the pin multiplexer initial architecture are specifically: constructing an update unit for each calibration signal, connecting the update unit to the target selector corresponding to the calibration signal, and connecting the calibration signal and its corresponding signal to be optimized to the update unit.

8. A pin assignment circuit, characterized in that: include: Multiple selectors, sorted by priority; An update unit, wherein the input end is connected to a plurality of target signals, wherein the plurality of target signals include a signal to be optimized and a calibration signal, the signal to be optimized is a signal whose priority is to be increased, and the calibration signal is a timing optimization target of the signal to be optimized, and the output end of the update unit is connected to a target selector so that the priority of the signal to be optimized and the calibration signal are consistent, and the target selector is a selector among the plurality of selectors that has the priority of the calibration signal.

9. The pin allocation circuit according to claim 8, wherein: The updating unit includes: an update selector, wherein the input end is connected to the plurality of target signals and the output end is connected to the input end of the target selector; an OR gate, an input end of which is connected to the control signal of the plurality of target signals, and an output end of which is connected to the control end of the target selector; Wherein, all or part of the control signals of the plurality of target signals are connected to the control terminal of the update selector, so that the update selector can select any one of the target signals to be output to the target selector.

10. The pin allocation circuit according to claim 8, wherein: Among the multiple selectors, the output end of each selector is connected to the input end of a selector with a higher priority, the output end of the selector with the highest priority is connected to the corresponding pin pad, the input end of the selectors other than the target selector is connected to a signal, and the control end is connected to the control signal of the signal.

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