Array substrate gate driving circuit, array substrate and display panel

Abstract

This disclosure relates to an array substrate gate driving circuit, an array substrate, and a display panel. The array substrate gate driving circuit includes multiple cascaded array substrate gate driving units. Each array substrate gate driving unit includes: a pull-up module, with a first terminal for receiving a clock signal and a second terminal for outputting a scan signal for this stage; a pull-down module, with a first terminal for receiving a first low-level signal and a second terminal electrically connected to the control terminal of the pull-up module to form a node for this stage; a pull-down sustaining module, with a first terminal for receiving the first low-level signal and a second terminal electrically connected to the node for this stage, including at least one dual-gate transistor; and a callback module, with a first terminal for receiving the first low-level signal, a second terminal electrically connected to the second terminal of the pull-down sustaining module, and a third terminal electrically connected to the back gate of the dual-gate transistor, for restoring the threshold voltage in the event of a drift in the threshold voltage of the dual-gate transistor.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to an array substrate gate driving circuit, an array substrate, and a display panel. Background Technology

[0002] In electronic devices, the Gate On Array (GOA) circuit is a crucial component of the display panel, precisely controlling pixel display to enhance image quality. However, under prolonged voltage driving, the threshold voltage of the transistors in the GOA circuit can drift, causing abnormal image display and resulting in poor image quality. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides an array substrate gate driving circuit, an array substrate, and a display panel.

[0004] According to a first aspect of the present disclosure, an array substrate gate driving circuit is provided, the array substrate gate driving circuit including a plurality of cascaded array substrate gate driving units, each of the array substrate gate driving units including:

[0005] A pull-up module, wherein the first terminal of the pull-up module is used to receive a clock signal, and the second terminal of the pull-up module is used to output the current scan signal;

[0006] A pull-down module, wherein the first end of the pull-down module is used to receive a first low-level signal, and the second end of the pull-down module is electrically connected to the control end of the pull-up module to form a node at this level;

[0007] A pull-down sustaining module, wherein a first terminal of the pull-down sustaining module is used to receive the first low-level signal, and a second terminal of the pull-down sustaining module is electrically connected to the local node, and the pull-down sustaining module includes at least one dual-gate transistor;

[0008] The callback module has a first terminal for receiving the first low-level signal, a second terminal for being electrically connected to the second terminal of the pull-down sustaining module, and a third terminal for being electrically connected to the back gate of the dual-gate transistor. The callback module is used to bring back the threshold voltage when the threshold voltage of the dual-gate transistor drifts.

[0009] In some embodiments of this disclosure, the pull-down sustaining module includes:

[0010] The first transistor has a first terminal for receiving the first low-level signal, a second terminal for being electrically connected to the local node, a gate for being electrically connected to the control terminal of the callback module, and a back gate for being electrically connected to the third terminal of the callback module.

[0011] The second transistor has a first terminal for receiving a second low-level signal, a second terminal for being electrically connected to the second terminal of the pull-up module, and a gate for being electrically connected to the gate of the first transistor.

[0012] The third transistor has a first terminal for receiving the first low-level signal, a second terminal for being electrically connected to the second terminal of the pull-up module, and a gate for being electrically connected to the gates of both the first and second transistors.

[0013] In some embodiments of this disclosure, the callback module includes:

[0014] A fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to a second terminal of the first transistor, a second terminal of the fourth transistor is electrically connected to the back gate of the first transistor, and a gate of the fourth transistor is electrically connected to the gate of the first transistor.

[0015] A first capacitor, the first terminal of which is electrically connected to the second terminal of the fourth transistor, and the second terminal of the first capacitor is used to receive the first low-level signal.

[0016] In some embodiments of this disclosure, the callback module further includes:

[0017] A fifth transistor, wherein the first terminal of the fifth transistor is electrically connected to the second terminal of the second transistor, the second terminal of the fifth transistor is electrically connected to the back gate of the second transistor, and the gate of the fifth transistor is electrically connected to the gate of the second transistor;

[0018] A second capacitor, the first terminal of which is electrically connected to the second terminal of the fifth transistor, and the second terminal of which is used to receive the first low-level signal; and / or

[0019] A sixth transistor, wherein the first terminal of the sixth transistor is electrically connected to the second terminal of the third transistor, the second terminal of the sixth transistor is electrically connected to the back gate of the third transistor, and the gate of the sixth transistor is electrically connected to the gate of the third transistor;

[0020] The third capacitor has its first terminal electrically connected to the second terminal of the sixth transistor, and its second terminal is used to receive the first low-level signal.

[0021] In some embodiments of this disclosure, the pull-down sustaining module further includes:

[0022] An inverter is provided, wherein the first input terminal of the inverter is electrically connected to the current stage node, the second input terminal of the inverter is electrically connected to the previous stage node of the array substrate gate driving unit, the output terminal of the inverter is electrically connected to the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the control terminal of the callback module, and the control terminal of the inverter is used to receive the inverted signal.

[0023] In some embodiments of this disclosure, the inverter includes:

[0024] A seventh transistor, wherein both its first terminal and gate are used to receive the inverted signal;

[0025] The eighth transistor has a first terminal electrically connected to the second terminal of the seventh transistor, the second terminal of the eighth transistor is used to receive the first low-level signal, and the gate of the eighth transistor is used to be electrically connected to the front-end node.

[0026] The ninth transistor has a first terminal electrically connected to the second terminal of the seventh transistor, the second terminal of the ninth transistor is used to receive the first low-level signal, and the gate of the ninth transistor is electrically connected to the node of this stage.

[0027] The tenth transistor has its first terminal electrically connected to the first terminal of the seventh transistor, and its second terminal electrically connected to the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the control terminal of the callback module. The gate of the tenth transistor is also electrically connected to the second terminal of the seventh transistor.

[0028] The eleventh transistor has its first terminal electrically connected to the second terminal of the tenth transistor. The second terminal of the eleventh transistor is used to receive the first low-level signal, and the gate of the eleventh transistor is used to be electrically connected to the preceding node.

[0029] The twelfth transistor has its first terminal electrically connected to the second terminal of the tenth transistor, the second terminal of the twelfth transistor being used to receive the first low-level signal, and its gate being electrically connected to the node of this stage.

[0030] In some embodiments of this disclosure, each of the array substrate gate driving units further includes:

[0031] A pull-up control module, wherein the first terminal of the pull-up control module is used to receive the front-stage scanning signal output by the gate driving unit of the array substrate in the previous stage, the second terminal of the pull-up control module is electrically connected to the node of this stage, and the control terminal of the pull-up control module is used to receive the vertical synchronization signal.

[0032] A reset module, wherein the first terminal of the reset module is used to receive the first low-level signal, the second terminal of the reset module is electrically connected to the local node, and the control terminal of the reset module is used to receive a reset signal;

[0033] The cascade module has its first terminal electrically connected to the first terminal of the pull-up module, its second terminal for outputting the cascade signal of this stage, and its control terminal electrically connected to the node of this stage.

[0034] The bootstrap module has its first end electrically connected to the local node and its second end electrically connected to the second end of the pull-up module.

[0035] In some embodiments of this disclosure, the pull-up control module includes:

[0036] The thirteenth transistor has a first terminal for receiving the previous stage scan signal, a second terminal for being electrically connected to the current stage node, and a gate for receiving the vertical synchronization signal.

[0037] The reset module includes:

[0038] The fourteenth transistor has a first terminal for receiving the first low-level signal, a second terminal for being electrically connected to the current node, and a gate for receiving the reset signal.

[0039] The transmission module includes:

[0040] The fifteenth transistor has its first terminal electrically connected to the first terminal of the pull-up module, its second terminal used to output the transmission signal of this stage, and its gate electrically connected to the node of this stage.

[0041] The bootstrap module includes:

[0042] A fourth capacitor, wherein the first terminal of the fourth capacitor is electrically connected to the current node, and the second terminal of the fourth capacitor is electrically connected to the second terminal of the pull-up module; and / or,

[0043] The pull-up module includes:

[0044] The sixteenth transistor has a first terminal for receiving the clock signal and a second terminal for outputting the current-level scan signal. The gate of the sixteenth transistor is electrically connected to the current-level node.

[0045] The drop-down module includes:

[0046] The seventeenth transistor has a first terminal for receiving the first low-level signal, a second terminal for being electrically connected to the current node, and a gate for receiving the subsequent stage transmission signal output by the array substrate gate driving unit.

[0047] According to a second aspect of the present disclosure, an array substrate is provided, the array substrate including the array substrate gate driving circuit described above.

[0048] According to a third aspect of the present disclosure, a display panel is provided, the display panel including an array substrate as described above.

[0049] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0050] The array substrate gate driving circuit includes multiple cascaded array substrate gate driving units. Each array substrate gate driving unit includes a pull-up module, a pull-down module, a pull-down sustaining module, and a callback module. The control terminal of the pull-up module is electrically connected to both the pull-down module and the pull-down sustaining module, and is turned off under the control of the pull-down module and the pull-down sustaining module to stop the output clock signal. The callback module is electrically connected to the back gate of the dual-gate transistor in the pull-down sustaining module, and restores the threshold voltage when the threshold voltage of the dual-gate transistor drifts. By restoring the threshold voltage of the dual-gate transistor through the callback module, the dual-gate transistor can reliably keep the pull-up module off so that the image can be displayed normally, thereby improving the image display effect.

[0051] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0052] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0053] Figure 1 This is a schematic diagram of the structure of an array substrate gate driving unit;

[0054] Figure 2 This is a schematic diagram of the characteristic curves of a transistor;

[0055] Figure 3 This is a schematic diagram of the structure of an array substrate gate driving unit according to an exemplary embodiment;

[0056] Figure 4-1 This is a schematic diagram of the structure of an array substrate gate driving unit according to an exemplary embodiment;

[0057] Figure 4-2 This is a schematic diagram of the structure of an array substrate gate driving unit according to an exemplary embodiment;

[0058] Figure 5 This is a voltage schematic diagram of a local node according to an exemplary embodiment.

[0059] In the picture:

[0060] 10 - Pull-up module; 20 - Pull-down module; 30 - Pull-down sustain module; 40 - Callback module; 50 - Pull-up control module; 60 - Reset module; 70 - Cascade module; 80 - Bootstrap module; T1 - First transistor; T2 - Second transistor; T3 - Third transistor; T4 - Fourth transistor; T5 - Fifth transistor; T6 - Sixth transistor; T7 - ​​Seventh transistor; T8 - Eighth transistor; T9 - Ninth transistor; T10 - Tenth transistor; T11 - Eleventh transistor; T12 - Twelfth transistor; T13 - Thirteenth transistor; T14 - Fourteenth transistor; T15 - Fifteenth transistor; T16 - Sixteenth transistor; T17 - Seventeenth transistor; C1 - First capacitor; C2 - Second capacitor; C3 - Third capacitor; C4 - Fourth capacitor; C bt - Bootstrap capacitor; G(N) - Current stage scan signal; G(Nx) - Previous stage scan signal; Q(N) - Current stage node; Q(Ny) - Previous stage node; ST(N) - Current stage transmission signal; ST(N+z) - Next stage transmission signal; V SSQ - First low-level signal; V SSG - Second low-level signal; STV - Vertical synchronization signal; LC - Inverting signal; RST - Reset signal; CK - Clock signal. Detailed Implementation

[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of methods consistent with some aspects of the invention as detailed in the appended claims. It should also be understood that the term "and / or" as used in this invention refers to and includes any or all possible combinations of one or more of the associated listed items.

[0062] As a crucial component of Liquid Crystal Display (LCD) panels, the array substrate gate drive circuit integrates driving and control circuitry onto the glass substrate of the display panel. This allows for precise control of each pixel's display, enhancing image quality. However, the transistors in the array substrate gate drive circuit are made of amorphous silicon, metal oxide, or low-temperature polycrystalline silicon. Under prolonged voltage driving, their threshold voltages drift, causing abnormal image display and resulting in poor image quality.

[0063] like Figure 1 As shown, the array substrate gate driving circuit includes multiple cascaded array substrate gate driving units. Each array substrate gate driving unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a bootstrap capacitor C. bt The first transistor T1 receives the clock signal CK at its first terminal and outputs the current stage scan signal G(N) at its second terminal. Its gate serves as the current stage node Q(N). The second transistor T2 is electrically connected to the first terminal of the first transistor T1 at its first terminal and outputs the current stage transmission signal ST(N) at its second terminal. Its gate is electrically connected to the current stage node Q(N). The third transistor T3 receives the first low-level signal V at its first terminal. SSQ The second terminal is electrically connected to node Q(N) of this stage, and its gate is used to receive the subsequent stage transmission signal ST(N+z) from the gate drive unit of the subsequent array substrate. The first terminal of the fourth transistor T4 is used to receive the first low-level signal V. SSQ The second terminal is electrically connected to node Q(N) of this stage. The first terminal of the fifth transistor T5 is used to receive the second low-level signal V. SSG The second terminal is electrically connected to the second terminal of the first transistor T1. The first terminal of the sixth transistor T6 is used to receive the first low-level signal V. SSQThe second terminal is electrically connected to the second terminals of both the first transistor T1 and the second transistor T2. The first terminal and control terminal of the seventh transistor T7 are used to receive the inverting signal LC. The first terminal of the eighth transistor T8 is electrically connected to the second terminal of the seventh transistor T7, and the second terminal is used to receive the first low-level signal V. SSQ The gate is electrically connected to the front-stage node Q(Ny) of the gate driving unit on the front-stage array substrate. The first terminal of the ninth transistor T9 is electrically connected to the second terminal of the seventh transistor T7, and the second terminal is used to receive the first low-level signal V. SSQ The gate of the tenth transistor T10 is electrically connected to the first terminal of the seventh transistor T7, and its second terminal is electrically connected to the gates of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The first terminal of the eleventh transistor T11 is electrically connected to the second terminal of the tenth transistor T10, and the second terminal is used to receive the first low-level signal V. SSQ The gate of the twelfth transistor T12 is electrically connected to the gate of the eighth transistor T8. The first terminal of the twelfth transistor T12 is electrically connected to the second terminal of the tenth transistor T10, and the second terminal is used to receive the first low-level signal V. SSQ The gate of the thirteenth transistor T13 is electrically connected to node Q(N) of this stage. The first terminal of the thirteenth transistor T13 receives the pre-stage scan signal G(Nx) from the gate drive unit of the pre-stage array substrate, and the second terminal is electrically connected to node Q(N) of this stage. Its gate is used to receive the vertical synchronization signal STV. The first terminal of the fourteenth transistor T14 is electrically connected to node Q(N) of this stage, and the second terminal receives the first low-level signal V. SSQ The gate is used to receive the reset signal RST. For example... Figure 2 As shown, the threshold voltage of the fourth transistor T4 drifts under prolonged voltage driving, and the on-state current of the fourth transistor T4 decreases, causing the voltage of node Q(N) in this stage to be unable to be effectively pulled down to the first low-level signal V. SSQ The low level. Because the first transistor T1 and the second transistor T2 cannot be reliably turned off, the power consumption and leakage current of the first transistor T1 and the second transistor T2 increase, causing abnormal image display or flickering. Wherein, the horizontal axis V gs Represents the gate-source voltage, with the vertical axis I. ds The curve S1 represents the characteristic curve of the fourth transistor T4 when the threshold voltage does not drift, and the curve S2 represents the characteristic curve of the fourth transistor T4 when the threshold voltage drifts.

[0064] Based on this, the present disclosure provides an array substrate gate driving circuit, which uses a callback module in each array substrate gate driving unit to pull down the threshold voltage of the dual gate transistor in the maintenance module, thereby avoiding threshold voltage drift and abnormal image display, thus improving the image display effect.

[0065] This disclosure provides an array substrate gate driving circuit, such as... Figure 3 As shown, the array substrate gate driving circuit includes multiple cascaded array substrate gate driving units. Each array substrate gate driving unit includes a pull-up module 10, a pull-down module 20, a pull-down sustaining module 30, and a callback module 40. The first terminal of the pull-up module 10 is used to receive the clock signal CK, and the second terminal is used to output the current stage scan signal G(N). The first terminal of the pull-down module 20 is used to receive the first low-level signal V. SSQ The second terminal is electrically connected to the control terminal of the pull-up module 10 and forms the node Q(N) of this stage. The first terminal of the pull-down sustaining module 30 is used to receive the first low-level signal V. SSQ The second terminal is electrically connected to the current node Q(N), and the pull-down sustaining module 30 includes at least one dual-gate transistor. The first terminal of the callback module 40 is used to receive a first low-level signal V. SSQ The second terminal is electrically connected to the second terminal of the pull-down sustaining module 30, and the third terminal is electrically connected to the back gate of the dual-gate transistor, which is used to restore the threshold voltage in the event of a drift in the threshold voltage of the dual-gate transistor.

[0066] In this embodiment, the array substrate gate driving circuit includes multiple cascaded array substrate gate driving units. Each array substrate gate driving unit includes a pull-up module, a pull-down module, a pull-down sustaining module, and a callback module. The control terminal of the pull-up module is electrically connected to both the pull-down module and the pull-down sustaining module, and is turned off under the control of the pull-down module and the pull-down sustaining module to stop the output clock signal. The callback module is electrically connected to the back gate of the dual-gate transistor in the pull-down sustaining module, and restores the threshold voltage when the threshold voltage of the dual-gate transistor drifts. By restoring the threshold voltage of the dual-gate transistor through the callback module, the dual-gate transistor can reliably maintain the pull-up module closed so that the image can be displayed normally, thereby improving the image display effect.

[0067] In one embodiment, such as Figure 4-1 and Figure 4-2 As shown, the pull-down sustaining module 30 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first terminal of the first transistor T1 is used to receive a first low-level signal V. SSQ The second terminal is electrically connected to the current node Q(N), the gate is electrically connected to the control terminal of the callback module 40, and the back gate is electrically connected to the third terminal of the callback module 40. The first terminal of the second transistor T2 is used to receive the second low-level signal V. SSG The second terminal is electrically connected to the second terminal of the pull-up module 10, and its gate is electrically connected to the gate of the first transistor T1. The first terminal of the third transistor T3 is used to receive the first low-level signal V. SSQThe second terminal is electrically connected to the second terminal of the pull-up module 10, and the gate is electrically connected to the gate of the first transistor T1 and the gate of the second transistor T2.

[0068] In this embodiment, when the pull-down sustaining module is running, the first, second, and third transistors are turned on to reliably shut down the pull-up module. With the first transistor on, a first low-level signal is transmitted to the control terminal of the pull-up module to turn it off. With the second and third transistors on, the first and second low-level signals are transmitted to the second terminal of the pull-up module to pull down the level of the current-level scan signal. By reliably pulling down the current-level scan signal through the first, second, and third transistors, pixel erroneous emission is avoided, thereby improving the image display effect. Simultaneously, due to the voltage difference between the first and second low-level signals, the voltage difference between the control terminal and the second terminal of the pull-up module ensures reliable shutdown of the pull-up module, thus improving the reliability of image display. Furthermore, by using a callback module to revert the threshold voltage of the first transistor, the pull-up module can be reliably shut down, further improving the reliability of image display.

[0069] For example, such as Figure 2 As shown, after the threshold voltage of the first transistor T1 (i.e., the fourth transistor T4 in the related art) drifts, the callback module 40 can restore the threshold voltage of the first transistor T1, causing the on-state current of the first transistor T1 to rise so as to effectively pull down the voltage of the current node Q(N) to the first low-level signal V. SSQ The low level. Because the pull-up module 10 can be reliably turned off, the power consumption and leakage current of the transistor in the pull-up module 10 decrease, allowing the image to display normally. Figure 5 As shown, after the threshold voltage of the first transistor T1 is reverted using the callback module 40, the voltage of the current node Q(N) recovers from VSSQ+ΔV to VSSQ. Curve S1 represents the voltage of the current node Q(N) without the callback module 40, and curve S2 represents the voltage of the current node Q(N) with the callback module 40.

[0070] For example, the first low-level signal V SSQ The voltage is less than the second low-level signal V. SSG The voltage, the first low-level signal V SSQ The voltage can be, for example, -10V, the second low-level signal V SSG The voltage can be, for example, -5V.

[0071] For example, the second transistor T2 and / or the third transistor T3 can be a dual-gate transistor or a single-gate transistor.

[0072] In one embodiment, such as Figure 4-1 and Figure 4-2 As shown, the callback module 40 includes a fourth transistor T4 and a first capacitor C1. The first terminal of the fourth transistor T4 is electrically connected to the second terminal of the first transistor T1, the second terminal is electrically connected to the back gate of the first transistor T1, and the gate is electrically connected to the gate of the first transistor T1. The first terminal of the first capacitor C1 is electrically connected to the second terminal of the fourth transistor T4, and the second terminal is used to receive a first low-level signal V. SSQ .

[0073] In this embodiment, since the gate of the fourth transistor is electrically connected to the gate of the first transistor, the fourth transistor and the first transistor are simultaneously turned on or off. When there is a residual voltage at this stage node, the voltage of the first capacitor is also a residual voltage, which differs from the voltage at the first terminal of the first transistor, causing a reverse voltage correction of the first transistor's threshold voltage. When there is no residual voltage at this stage node, the voltage of the first capacitor is the same as the voltage at the first terminal of the first transistor, and no reverse voltage correction of the first transistor's threshold voltage is caused. By constructing a correction module for adjusting the threshold voltage of the first transistor using the fourth transistor and the first capacitor, automatic correction can be performed when the threshold voltage of the first transistor drifts, thereby reducing the complexity of the array substrate gate drive circuit control.

[0074] In one embodiment, such as Figure 4-2 As shown, the callback module 40 also includes a fifth transistor T5 and a second capacitor C2. The first terminal of the fifth transistor T5 is electrically connected to the second terminal of the second transistor T2, the second terminal is electrically connected to the back gate of the second transistor T2, and the gate is electrically connected to the gate of the second transistor T2. The first terminal of the second capacitor C2 is electrically connected to the second terminal of the fifth transistor T5, and the second terminal is used to receive the first low-level signal V. SSQ .

[0075] In this embodiment, since the gate of the fifth transistor is electrically connected to the gate of the second transistor, both the fifth and second transistors are simultaneously turned on or off. When there is a residual voltage at this stage node, the voltage of the second capacitor also has a residual voltage, causing a reverse pullback of the threshold voltage of the second transistor. When there is no residual voltage at this stage node, the voltage of the second capacitor does not have a residual voltage, and no reverse pullback of the threshold voltage of the second transistor is caused. By using the fifth transistor and the second capacitor to form a pullback module for adjusting the threshold voltage of the second transistor, automatic pullback can be performed when the threshold voltage of the second transistor drifts, thereby reducing the complexity of the array substrate gate drive circuit control.

[0076] In one embodiment, the callback module 40 further includes a sixth transistor T6 and a third capacitor C3. The first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, the second terminal is electrically connected to the back gate of the third transistor T3, and the gate is electrically connected to the gate of the third transistor T3. The first terminal of the third capacitor C3 is electrically connected to the second terminal of the sixth transistor T6, and the second terminal is used to receive a first low-level signal V. SSQ .

[0077] In this embodiment, since the gate of the sixth transistor is electrically connected to the gate of the third transistor, both the sixth and third transistors are simultaneously turned on or off. When there is a residual voltage at this stage node, the voltage of the third capacitor also has a residual voltage, causing a reverse pullback of the threshold voltage of the third transistor. When there is no residual voltage at this stage node, the voltage of the third capacitor does not have a residual voltage, and no reverse pullback of the threshold voltage of the third transistor is caused. By constructing a pullback module for adjusting the threshold voltage of the third transistor using the sixth transistor and the third capacitor, automatic pullback can be performed when the threshold voltage of the third transistor drifts, thereby reducing the complexity of the array substrate gate drive circuit control.

[0078] In one embodiment, the pull-down sustaining module 30 further includes an inverter 31. The first input terminal of the inverter 31 is electrically connected to the current stage node Q(N), the second input terminal is electrically connected to the previous stage node Q(Ny) of the previous stage array substrate gate driving unit, and the output terminal is electrically connected to the gate of the first transistor T1, the gate of the second transistor T2, the gate of the third transistor T3, and the control terminal of the callback module 40. The control terminal is used to receive the inverted signal LC.

[0079] In this embodiment, by electrically connecting the first and second input terminals of the inverter to the current node and the previous node, respectively, the pull-down sustaining module can be controlled to conduct when pull-down sustaining is required, thereby reducing the complexity of the array substrate gate drive circuit control. Simultaneously, by electrically connecting the second input terminal of the inverter to the previous node, the rising edge of the voltage at the current node can be prevented from overlapping with the falling edge of the voltage at the inverter's output, thus preventing a short circuit and improving the reliability of the array substrate gate drive circuit.

[0080] In one embodiment, the inverter 31 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The first terminal and gate of the seventh transistor T7 are both used to receive the inverted signal LC. The first terminal of the eighth transistor T8 is electrically connected to the second terminal of the seventh transistor T7, and the second terminal is used to receive a first low-level signal V. SSQThe gate is used for electrical connection with the preceding node Q(Ny). The first terminal of the ninth transistor T9 is electrically connected to the second terminal of the seventh transistor T7, and the second terminal is used to receive the first low-level signal V. SSQ The gate of the tenth transistor T10 is electrically connected to the first terminal of the seventh transistor T7. Its second terminal is electrically connected to the gates of the first transistor T1, the second transistor T2, the third transistor T3, and the control terminal of the callback module 40. The gate of the tenth transistor T10 is also electrically connected to the second terminal of the seventh transistor T7. The first terminal of the eleventh transistor T11 is electrically connected to the second terminal of the tenth transistor T10. The second terminal is used to receive the first low-level signal V. SSQ The gate is used for electrical connection with the preceding node Q(Ny). The first terminal of the twelfth transistor T12 is electrically connected to the second terminal of the tenth transistor T10, and the second terminal is used to receive the first low-level signal V. SSQ The gate is electrically connected to the current node Q(N).

[0081] In this embodiment, by electrically connecting the seventh, ninth, tenth, and twelfth transistors to the current-stage node, the pull-down sustaining module can be controlled to conduct when pull-down sustaining is required, thereby reducing the complexity of the array substrate gate drive circuit control. By electrically connecting the seventh, eighth, tenth, and eleventh transistors to the previous-stage node, the rising edge of the voltage at this-stage node and the falling edge of the output voltage can be prevented from overlapping, thus preventing a short circuit and improving the reliability of the array substrate gate drive circuit.

[0082] In one embodiment, each array substrate gate driving unit further includes a pull-up control module 50, a reset module 60, a stage transmission module 70, and a bootstrap module 80. The first terminal of the pull-up control module 50 is used to receive the previous stage scan signal G(Nx) output by the previous stage array substrate gate driving unit, the second terminal is electrically connected to the current stage node Q(N), and the control terminal is used to receive the vertical synchronization signal STV. The first terminal of the reset module 60 is used to receive a first low-level signal V. SSQ The second terminal is electrically connected to the current node Q(N), and the control terminal is used to receive the reset signal RST. The first terminal of the cascade module 70 is electrically connected to the first terminal of the pull-up module 10, the second terminal is used to output the current cascade signal ST(N), and the control terminal is electrically connected to the current node Q(N). The first terminal of the bootstrap module 80 is electrically connected to the current node Q(N), and the second terminal is electrically connected to the second terminal of the pull-up module 10.

[0083] In this embodiment, the pull-up control module receives the previous stage scan signal and, under the control of the vertical synchronization signal, outputs the previous stage scan signal to the current stage node to control the conduction and disconnection of the pull-up module. The reset module receives a first low-level signal and, under the control of the reset signal, resets the voltage of the current stage node, keeping the pull-up module initially disconnected. The stage transmission module receives a clock signal and outputs the current stage transmission signal using the clock signal. By electrically connecting the bootstrap module to the current stage node, the voltage of the current stage node can be boosted and maintained during the output of the current stage scan signal. Through the transmission of different signals and voltage boosting by the pull-up control module, reset module, stage transmission module, and bootstrap module, the current stage scan signal and the current stage transmission signal can be reliably transmitted to the next-stage array substrate gate drive unit, thereby improving the reliability of the array substrate gate drive circuit.

[0084] In one embodiment, the pull-up control module 50 includes a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 receives the previous stage scan signal G(Nx), the second terminal is electrically connected to the current stage node Q(N), and the gate is used to receive the vertical synchronization signal STV. The reset module 60 includes a fourteenth transistor T14. The first terminal of the fourteenth transistor T14 receives a first low-level signal V. SSQ The second terminal is electrically connected to the current stage node Q(N), and the gate is used to receive the reset signal RST. The bootstrap module 70 includes a fifteenth transistor T15. The first terminal of the fifteenth transistor T15 is electrically connected to the first terminal of the pull-up module 10, the second terminal is used to output the current stage bootstrap signal ST(N), and the gate is electrically connected to the current stage node Q(N). The bootstrap module 80 includes a fourth capacitor C4. The first terminal of the fourth capacitor C4 is electrically connected to the current stage node Q(N), and the second terminal is electrically connected to the second terminal of the pull-up module 10.

[0085] In this embodiment, the thirteenth transistor receives the previous stage scan signal and, under the control of the vertical synchronization signal, outputs the previous stage scan signal to the current stage node to control the conduction and disconnection of the pull-up module. The fourteenth transistor receives the first low-level signal and, under the control of the reset signal, resets the voltage of the current stage node, keeping the pull-up module initially disconnected. The fifteenth transistor receives the clock signal and outputs the current stage transmission signal using the clock signal. By electrically connecting the fourth capacitor to the current stage node, the voltage of the current stage node can be boosted and maintained during the output of the current stage scan signal. Through the transmission of different signals and voltage boosting using the thirteenth, fourteenth, and fifteenth transistors and the fourth capacitor, the current stage scan signal and the current stage transmission signal can be reliably transmitted to the next-stage array substrate gate driving unit, thereby improving the reliability of the array substrate gate driving circuit.

[0086] In one embodiment, the pull-up module 10 includes a sixteenth transistor T16. The first terminal of the sixteenth transistor T16 is used to receive a clock signal CK, the second terminal is used to output a current-level scan signal G(N), and its gate is electrically connected to the current-level node Q(N). The pull-down module 20 includes a seventeenth transistor T17. The first terminal of the seventeenth transistor T17 is used to receive a first low-level signal V. SSQ The second terminal is electrically connected to the current stage node Q(N), and the gate is used to receive the subsequent stage transmission signal ST(N+z) output by the gate drive unit of the subsequent array substrate.

[0087] In this embodiment, the clock signal is received by the sixteenth transistor, which can be used to output the current stage scan signal. The first low-level signal is received by the seventeenth transistor, which can pull down the voltage of the current stage node under the control of the subsequent stage transmission signal, thereby turning off the sixteenth transistor. By using the sixteenth and seventeenth transistors for pull-up and pull-down, the current stage scan signal can be reliably transmitted to the next stage array substrate gate driving unit, thereby improving the reliability of the array substrate gate driving circuit.

[0088] For example, the preceding scan signal G(Nx) can be the current scan signal G(N) output by the gate driving unit of the previous stage or multiple stages of the array substrate. The preceding node Q(Ny) can be the current node Q(N) of the gate driving unit of the previous stage or multiple stages of the array substrate. The subsequent stage transmission signal ST(N+z) can be the current stage transmission signal ST(N) output by the gate driving unit of the subsequent stage or multiple stages of the array substrate.

[0089] This disclosure provides an array substrate gate driving circuit, such as... Figure 4-2 As shown, the array substrate gate driving circuit includes multiple cascaded array substrate gate driving units. Each array substrate gate driving unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The first terminal of the first transistor T1 is used to receive a first low-level signal V. SSQ The second terminal of the second transistor T2 is electrically connected to both the current node Q(N) and the first terminal of the fourth transistor T4. Its gate is electrically connected to the gate of the fourth transistor T4, and its back gate is electrically connected to the second terminal of the fourth transistor T4. The first terminal of the second transistor T2 is used to receive the second low-level signal V. SSGThe second terminal is electrically connected to the second terminal of the sixteenth transistor T16 and the first terminal of the fifth transistor T5. The gate is electrically connected to the gate of the fifth transistor T5, and the back gate is electrically connected to the second terminal of the fifth transistor T5. The first terminal of the third transistor T3 is used to receive the first low-level signal V. SSQ The second terminal of transistor T7 is electrically connected to the second terminals of both the sixteenth transistor T16 and the fifteenth transistor T15. Its gate is electrically connected to the gate of the sixth transistor T6, and its back gate is electrically connected to the second terminal of the sixth transistor T6. The first terminal and gate of the seventh transistor T7 are both used to receive the inverted signal LC. Its second terminal is electrically connected to the first terminals of both the eighth transistor T8 and the ninth transistor T9. The second terminal of the eighth transistor T8 is used to receive the first low-level signal V. SSQ The gate is used for electrical connection with the preceding node Q(Ny). The second terminal of the ninth transistor T9 is used to receive the first low-level signal V. SSQ The gate of the tenth transistor T10 is electrically connected to the first terminal of the seventh transistor T7. Its second terminal is electrically connected to the gates of the first transistor T1, the second transistor T2, the third transistor T3, the first terminal of the eleventh transistor T11, and the first terminal of the twelfth transistor T12. Its gate is electrically connected to the second terminal of the seventh transistor T7. The second terminal of the eleventh transistor T11 is used to receive the first low-level signal V. SSQ The gate is used for electrical connection with the preceding node Q(Ny). The second terminal of the twelfth transistor T12 is used to receive the first low-level signal V. SSQ The gate of the thirteenth transistor T13 is electrically connected to node Q(N) of this stage. The first terminal of the thirteenth transistor T13 receives the previous stage scan signal G(Nx), and the second terminal is electrically connected to node Q(N) of this stage. Its gate is used to receive the vertical synchronization signal STV. The first terminal of the fourteenth transistor T14 receives the first low-level signal V. SSQ The second terminal of the fifteenth transistor T15 is electrically connected to the first terminal of the sixteenth transistor T16, and the second terminal is used to output the current stage transmission signal ST(N). Its gate is electrically connected to the current stage node Q(N). The first terminal of the sixteenth transistor T16 is used to receive the clock signal CK, and the second terminal is used to output the current stage scan signal G(N). Its gate is electrically connected to the current stage node Q(N). The first terminal of the seventeenth transistor T17 is used to receive the first low-level signal V. SSQ The second terminal is electrically connected to node Q(N) of this stage, and its gate is used to receive the subsequent stage transmission signal ST(N+z). The first terminal of the first capacitor C1 is electrically connected to the second terminal of the fourth transistor T4, and its second terminal is used to receive the first low-level signal V. SSQ The first terminal of the second capacitor C2 is electrically connected to the second terminal of the fifth transistor T5, and the second terminal is used to receive the first low-level signal V.SSQ The first terminal of the third capacitor C3 is electrically connected to the second terminal of the sixth transistor T6, and the second terminal is used to receive the first low-level signal V. SSQ The first terminal of the fourth capacitor C4 is electrically connected to node Q(N) of this stage, and the second terminal is electrically connected to the second terminal of the sixteenth transistor T16. Through the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the first capacitor C1, the second capacitor C2, and the third capacitor C3, the threshold voltages of the first transistor T1, the second transistor T2, and the third transistor T3 are restored. This allows the first transistor T1, the second transistor T2, and the third transistor T3 to reliably keep the sixteenth transistor T16 off, ensuring normal image display and thus improving the image display effect.

[0090] In one exemplary embodiment, an array substrate is provided, the array substrate including the array substrate gate driving circuit as described above.

[0091] In one exemplary embodiment, a display panel is provided, the display panel including the array substrate as described above.

[0092] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0093] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A gate driving circuit for an array substrate, characterized in that, The array substrate gate drive circuit comprises a plurality of cascaded array substrate gate drive units, each of which comprises: a pull-up module, a first end of the pull-up module being configured to receive a clock signal, and a second end of the pull-up module being configured to output a current stage scanning signal; a pull-down module, a first end of the pull-down module being configured to receive a first low-level signal, and a second end of the pull-down module being electrically connected with a control end of the pull-up module and forming a current stage node; a pull-down maintaining module, a first end of the pull-down maintaining module being configured to receive the first low-level signal, and a second end of the pull-down maintaining module being electrically connected with the current stage node, the pull-down maintaining module comprising at least one double-gate transistor; a callback module, a first end of the callback module being configured to receive the first low-level signal, a second end of the callback module being electrically connected with the second end of the pull-down maintaining module, and a third end of the callback module being electrically connected with a back gate of the double-gate transistor, the callback module being configured to, in a case where a threshold voltage of the double-gate transistor drifts, callback the threshold voltage.

2. The array substrate gate driving circuit according to claim 1, wherein The pull-down maintaining module comprises: a first transistor, a first end of the first transistor being configured to receive the first low-level signal, a second end of the first transistor being electrically connected with the current stage node, a gate of the first transistor being electrically connected with a control end of the callback module, and a back gate of the first transistor being electrically connected with a third end of the callback module; a second transistor, a first end of the second transistor being configured to receive a second low-level signal, a second end of the second transistor being electrically connected with a second end of the pull-up module, and a gate of the second transistor being electrically connected with a gate of the first transistor; a third transistor, a first end of the third transistor being configured to receive the first low-level signal, a second end of the third transistor being electrically connected with the second end of the pull-up module, and a gate of the third transistor being electrically connected with the gate of the first transistor and the gate of the second transistor.

3. The array substrate gate driving circuit according to claim 2, wherein The callback module comprises: a fourth transistor, a first end of the fourth transistor being electrically connected with the second end of the first transistor, a second end of the fourth transistor being electrically connected with the back gate of the first transistor, and a gate of the fourth transistor being electrically connected with the gate of the first transistor; a first capacitor, a first end of the first capacitor being electrically connected with the second end of the fourth transistor, and a second end of the first capacitor being configured to receive the first low-level signal.

4. The array substrate gate driving circuit according to claim 3, wherein The callback module further comprises: a fifth transistor, a first end of the fifth transistor being electrically connected with the second end of the second transistor, a second end of the fifth transistor being electrically connected with a back gate of the second transistor, and a gate of the fifth transistor being electrically connected with the gate of the second transistor; a second capacitor, a first end of the second capacitor being electrically connected with the second end of the fifth transistor, and a second end of the second capacitor being configured to receive the first low-level signal; and / or, A sixth transistor, a first end of the sixth transistor is electrically connected with the second end of the third transistor, a second end of the sixth transistor is electrically connected with the back gate of the third transistor, a gate of the sixth transistor is electrically connected with the gate of the third transistor; A third capacitor, a first end of the third capacitor is electrically connected with the second end of the sixth transistor, and a second end of the third capacitor is used for receiving the first low-level signal.

5. The array substrate gate driving circuit according to claim 2, wherein The pull-down maintaining module further comprises: An inverter, a first input end of the inverter is electrically connected with the node of the current stage, a second input end of the inverter is electrically connected with the node of the previous stage of the array substrate gate drive unit, an output end of the inverter is electrically connected with the gate of the first transistor, the gate of the second transistor, the gate of the third transistor and the control end of the back-off module, and a control end of the inverter is used for receiving an inverted signal.

6. The array substrate gate driver circuit according to claim 5, wherein, The inverter comprises: A seventh transistor, a first end and a gate of the seventh transistor are used for receiving the inverted signal; An eighth transistor, a first end of the eighth transistor is electrically connected with the second end of the seventh transistor, a second end of the eighth transistor is used for receiving the first low-level signal, and a gate of the eighth transistor is electrically connected with the node of the previous stage; A ninth transistor, a first end of the ninth transistor is electrically connected with the second end of the seventh transistor, a second end of the ninth transistor is used for receiving the first low-level signal, and a gate of the ninth transistor is electrically connected with the node of the current stage; A tenth transistor, a first end of the tenth transistor is electrically connected with the first end of the seventh transistor, a second end of the tenth transistor is electrically connected with the gate of the first transistor, the gate of the second transistor, the gate of the third transistor and the control end of the back-off module, and a gate of the tenth transistor is electrically connected with the second end of the seventh transistor; An eleventh transistor, a first end of the eleventh transistor is electrically connected with the second end of the tenth transistor, a second end of the eleventh transistor is used for receiving the first low-level signal, and a gate of the eleventh transistor is electrically connected with the node of the previous stage; A twelfth transistor, a first end of the twelfth transistor is electrically connected with the second end of the tenth transistor, a second end of the twelfth transistor is used for receiving the first low-level signal, and a gate of the twelfth transistor is electrically connected with the node of the current stage.

7. The array substrate gate driver circuit according to any one of claims 1 to 6, wherein, Each array substrate gate drive unit further comprises: A pull-up control module, a first end of the pull-up control module is used for receiving a previous stage scanning signal output by the array substrate gate drive unit of the previous stage, a second end of the pull-up control module is electrically connected with the node of the current stage, and a control end of the pull-up control module is used for receiving a vertical synchronization signal; A reset module, a first end of the reset module is used for receiving the first low-level signal, a second end of the reset module is electrically connected with the node of the current stage, and a control end of the reset module is used for receiving a reset signal. a level transmission module, a first end of the level transmission module being electrically connected with the first end of the pull-up module, a second end of the level transmission module being used for outputting a current stage level transmission signal, a control end of the level transmission module being electrically connected with the current stage node; a bootstrap module, a first end of the bootstrap module being electrically connected with the current stage node, a second end of the bootstrap module being electrically connected with the second end of the pull-up module.

8. The array substrate gate driving circuit according to claim 7, wherein, The pull-up control module comprises: a thirteenth transistor, a first end of the thirteenth transistor being used for receiving the previous stage scanning signal, a second end of the thirteenth transistor being electrically connected with the current stage node, a gate of the thirteenth transistor being used for receiving the vertical synchronization signal; The reset module comprises: a fourteenth transistor, a first end of the fourteenth transistor being used for receiving the first low voltage signal, a second end of the fourteenth transistor being electrically connected with the current stage node, a gate of the fourteenth transistor being used for receiving the reset signal; The level transmission module comprises: a fifteenth transistor, a first end of the fifteenth transistor being electrically connected with the first end of the pull-up module, a second end of the fifteenth transistor being used for outputting the current stage level transmission signal, a gate of the fifteenth transistor being electrically connected with the current stage node; The bootstrap module comprises: a fourth capacitor, a first end of the fourth capacitor being electrically connected with the current stage node, a second end of the fourth capacitor being electrically connected with the second end of the pull-up module; and / or, The pull-up module comprises: a sixteenth transistor, a first end of the sixteenth transistor being used for receiving the clock signal, a second end of the sixteenth transistor being used for outputting the current stage scanning signal, a gate of the sixteenth transistor being electrically connected with the current stage node; The pull-down module comprises: a seventeenth transistor, a first end of the seventeenth transistor being used for receiving the first low voltage signal, a second end of the seventeenth transistor being electrically connected with the current stage node, a gate of the seventeenth transistor being used for receiving a next stage level transmission signal outputted by the array substrate gate drive unit in the next stage.

9. An array substrate, characterized by, The array substrate comprises the array substrate gate drive circuit according to any one of claims 1 to 8.

10. A display panel, characterized by, The display panel comprises the array substrate according to claim 9.

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