Offset compensation method, memory and electronic device thereof

Abstract

The present disclosure provides an offset compensation method, a memory, and electronic devices thereof. The method is applied to a sense amplifier provided with an offset cancellation device. During a precharge phase of the sense amplifier, the gate voltage of the offset cancellation device is controlled to be within a first voltage range so that the offset cancellation device is in a strongly on state. During part or all of the offset cancellation phase of the sense amplifier, the gate voltage of the offset cancellation device is controlled to be within a second voltage range so that the offset cancellation device is in a weakly on state. The minimum value of the first voltage range is greater than the maximum value of the second voltage range.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to an offset compensation method, a memory, and an electronic device thereof. Background Art

[0002] Dynamic random access memory (DRAM) has been widely used in various electronic devices due to its advantages such as high density, low power consumption, and low price. The sense amplifier (SA) is a key component of semiconductor memory. Its primary function is to amplify small signals on the bit line using a pair of N-type field-effect transistors and a pair of P-type field-effect transistors, thereby performing read or write operations. However, due to process and other factors, the operating parameters of each transistor in the sense amplifier vary, resulting in mismatch problems that seriously affect the performance of semiconductor memory. Summary of the Invention

[0003] The present disclosure provides an offset compensation method, a memory and an electronic device thereof.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides an offset compensation method applied to a sense amplifier, wherein the sense amplifier includes a first N-type field effect transistor, a second N-type field effect transistor, a first P-type field effect transistor, and a second P-type field effect transistor connected in a cross-coupled manner, wherein a first offset cancellation device is provided between a gate and a drain of the first N-type field effect transistor, and a second offset cancellation device is provided between a gate and a drain of the second N-type field effect transistor, and the method includes:

[0006] During a precharge phase of the sense amplifier, controlling a gate voltage of the first offset cancellation device and a gate voltage of the second offset cancellation device to be within a first voltage range so that both the first offset cancellation device and the second offset cancellation device are in a strong on state;

[0007] During a portion or all of an offset cancellation phase of the sense amplifier, controlling a gate voltage of the first offset cancellation device and a gate voltage of the second offset cancellation device to be within a second voltage range so that both the first offset cancellation device and the second offset cancellation device are in a weak on state;

[0008] The minimum value of the first voltage range is greater than the maximum value of the second voltage range.

[0009] In some embodiments, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a first voltage range includes:

[0010] In a pre-charging phase of the sense amplifier, the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are both controlled to be a first value; wherein the first value belongs to the first voltage range.

[0011] In some embodiments, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range includes:

[0012] During the entire time period of the offset cancellation phase of the sense amplifier, the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are controlled to be a second value; wherein the second value belongs to the second voltage range.

[0013] In some embodiments, the offset cancellation stage includes a first cancellation stage and a second cancellation stage, wherein the second cancellation stage occurs after the first cancellation stage; and controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range further includes:

[0014] controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be a third value in the first cancellation phase;

[0015] The gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are both controlled to be the first value in the second cancellation phase; wherein the third value belongs to the second voltage range.

[0016] In some embodiments, the offset cancellation stage includes a first cancellation stage and a second cancellation stage, wherein the second cancellation stage occurs after the first cancellation stage; and controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range further includes:

[0017] controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be a fourth value in the first cancellation phase;

[0018] The gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are both controlled to be a fifth value in the second cancellation stage; wherein the fourth value and the fifth value both belong to the second voltage range, and the fourth value is smaller than the fifth value.

[0019] In some embodiments, the method further includes: during the charge sharing stage and the signal amplification stage of the sense amplifier, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a third voltage range, so that the first offset cancellation device and the second offset cancellation device are both in an off state; wherein the maximum value of the third voltage range is less than the minimum value of the second voltage range.

[0020] In some embodiments, both the first offset cancellation device and the second offset cancellation device are N-type field effect transistors.

[0021] In a second aspect, an embodiment of the present disclosure provides a memory, the memory comprising a sense amplifier and a control module, the sense amplifier comprising a first N-type field effect transistor, a second N-type field effect transistor, a first P-type field effect transistor, and a second P-type field effect transistor connected in a cross-coupled manner, wherein a first offset cancellation device is provided between a gate and a drain of the first N-type field effect transistor, and a second offset cancellation device is provided between a gate and a drain of the second N-type field effect transistor;

[0022] The control module is configured to receive a status indication signal and generate a first control signal and a second control signal according to the status indication signal; wherein, when the status indication signal indicates that the sense amplifier is in a pre-charge phase, a voltage value of the first control signal and a voltage value of the second control signal are both within a first voltage range; and when the status indication signal indicates that the sense amplifier is in an offset cancellation phase, a voltage value of the first control signal and a voltage value of the second control signal are both within a second voltage range; wherein a minimum value of the first voltage range is greater than a maximum value of the second voltage range;

[0023] A gate of the first offset cancellation device receives the first control signal, and a gate of the second offset cancellation device receives the second control signal.

[0024] In some embodiments, the status indication signal includes at least two sub-signals;

[0025] The control module is specifically configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a first value when the level states of the two sub-signals of the first state indication signal meet a first condition;

[0026] The first condition indicates that the sense amplifier is in a pre-charging stage, and the first value belongs to the first voltage range.

[0027] In some embodiments, the control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a second value when the level status of the two sub-signals of the status indication signal meets a second condition; wherein the second condition indicates that the sensitive amplifier is in the offset elimination stage, and the second value belongs to the second voltage range.

[0028] In some embodiments, the offset cancellation stage includes a first cancellation stage and a second cancellation stage,

[0029] The control module includes a timer, and is further configured to start the timer when the level states of the two sub-signals of the status indication signal meet a second condition; if the timing duration of the timer is less than or equal to a first threshold, control the voltage value of the first control signal and the voltage value of the second control signal to be a third value; if the timing duration of the timer is greater than the first threshold, control the voltage value of the first control signal and the voltage value of the second control signal to be the first value;

[0030] Among them, the second condition indicates that the sensitive amplifier is in the offset elimination stage; if the timing duration of the timer is less than or equal to the first threshold, it indicates that the sensitive amplifier is in the first elimination stage; if the timing duration of the timer is greater than the first threshold, it indicates that the sensitive amplifier is in the second elimination stage; the third value belongs to the second voltage range.

[0031] In some embodiments, the offset cancellation stage includes a first cancellation stage and a second cancellation stage,

[0032] The control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a fourth value when the level states of the two sub-signals of the first indication signal meet a third condition;

[0033] The control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a fifth value when the level states of the two sub-signals of the status indication signal meet a fourth condition;

[0034] The third condition indicates that the sense amplifier is in the first elimination stage, and the fourth condition indicates that the sense amplifier is in the second elimination stage; the fourth value and the fifth value both belong to the second voltage range, and the fourth value is smaller than the fifth value.

[0035] In some embodiments, the control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be within a third voltage range when the level states of the two sub-signals of the first indication signal meet a fifth condition;

[0036] The fifth condition indicates that the sense amplifier is in a charge sharing stage or a signal amplification stage; and the maximum value of the third voltage range is less than the minimum value of the second voltage range.

[0037] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising the memory as described in the second aspect.

[0038] The embodiments of the present disclosure provide an offset compensation method and a memory. By controlling the on-states of a first offset cancellation device and a second offset cancellation device, the mismatch compensation capability of a sense amplifier can be improved, time loss can be reduced, the accuracy of offset compensation can be increased, and the performance of a semiconductor memory can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A A schematic diagram of a circuit structure of an offset compensation solution provided in an embodiment of the present disclosure;

[0040] Figure 1B A schematic diagram of a circuit structure of an offset compensation stage of a sense amplifier provided by an embodiment of the present disclosure;

[0041] Figure 1C A schematic diagram of the circuit structure of a signal amplification stage of a sensitive amplifier provided by an embodiment of the present disclosure;

[0042] Figure 2 A signal timing diagram 1 provided in an embodiment of the present disclosure;

[0043] Figure 3 A graph showing voltage changes over time for different signals provided in an embodiment of the present disclosure;

[0044] Figure 4 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure;

[0045] Figure 5 A signal timing diagram provided in an embodiment of the present disclosure Figure 2 ;

[0046] Figure 6 A signal timing diagram provided in an embodiment of the present disclosure Figure 3 ;

[0047] Figure 7 A signal timing diagram provided in an embodiment of the present disclosure Figure 4 ;

[0048] Figure 8 A simulation diagram of mismatch improvement provided by an embodiment of the present disclosure;

[0049] Figure 9 A schematic structural diagram of an RC delay circuit on a bit line provided by an embodiment of the present disclosure;

[0050] Figure 10 A graph showing a change in bit line voltage over time provided by an embodiment of the present disclosure;

[0051] Figure 11 A flow chart of an offset compensation method provided in an embodiment of the present disclosure

[0052] Figure 12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the relevant applications and are not intended to limit the relevant applications. It should also be noted that for ease of description, only the portions relevant to the relevant applications are shown in the drawings.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0055] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0056] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0057] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0058] As the geometric size of semiconductor devices continues to decrease, the gate area of ​​Metal-Oxide-Semiconductor Field Effect Transistor (MOS FET) also continues to shrink in accordance with Moore's Law, resulting in the possibility that the sensitive amplifier composed of transistors may have an offset voltage that affects the sensitivity of the circuit. The offset voltage may be caused by a variety of factors, including but not limited to the deviation between the threshold voltages of the corresponding transistors in the cross-coupled inverter, the mismatch between the series resistances on the source / drain nodes of the transistors, the fluctuation of the dopant, the mismatch between the structural dimensions of the corresponding circuit elements, the carrier mobility mismatch, the substrate bias, the conductivity mismatch, the node capacitance mismatch of the corresponding transistor, the change of the metal grains and the increase of the interface trap density. In the embodiments of the present disclosure, for the convenience of description, all the above changes and mismatches are collectively referred to as the "mismatch" of the sensitive amplifier. In DRAM, this mismatch can cause a large number of sensing failures, affect the performance of the memory, and lead to a decrease in yield.

[0059] In order to solve this problem, the present disclosure introduces an offset compensation scheme applied to the sense amplifier. Figure 1A As shown, the circuit structure of this solution includes a bit line (BitLine, BL), a complementary bit line (BitB Line, BLB), a sense amplifier 201, a third N-type field effect transistor 111, a fourth field effect transistor 112, a fifth N-type field effect transistor 117, and a sixth N-type field effect transistor 118. The sense amplifier 201 includes a first N-type field effect transistor 114, a second N-type field effect transistor 116, a first P-type field effect transistor 113, and a second P-type field effect transistor 115.

[0060] Specifically, if Figure 1AAs shown, the bit line BL, the gate of the second N-type field effect transistor 116, the drain of the fifth N-type field effect transistor 117, and the drain of the sixth N-type field effect transistor 118 are connected; the drain of the second N-type field effect transistor 116, the drain of the second P-type field effect transistor 115, the source of the fourth N-type field effect transistor 112, the source of the sixth N-type field effect transistor 118, and the gate of the first P-type field effect transistor 113 are connected; the source of the first P-type field effect transistor 113, the source of the second P-type field effect transistor 115 are connected to the first reference control signal SAP; the source of the first N-type field effect transistor 114, the source of the second N-type field effect transistor 116 are connected to the second reference control signal SAN. The drain of the first N-type field-effect transistor 114, the source of the fifth N-type field-effect transistor 117, the source of the third N-type field-effect transistor 111, the drain of the first P-type field-effect transistor 113, and the gate of the second P-type field-effect transistor 115 are connected. The complementary bit line BLB, the gate of the first N-type field-effect transistor 114, the drain of the fourth N-type field-effect transistor 112, and the drain of the third N-type field-effect transistor 111 are connected. The gate of the third N-type field-effect transistor 111 and the gate of the sixth N-type field-effect transistor 118 are both used to receive the offset control signal OCS. The gate of the fourth N-type field-effect transistor 112 and the gate of the fifth N-type field-effect transistor 117 are both used to receive the isolation control signal ISO.

[0061] In addition, parasitic capacitance and parasitic resistance may exist on the bit line BL and the complementary bit line BLB ( Figure 1A The capacitance of the parasitic capacitor and the resistance of the parasitic resistor are determined by the circuit layout and the characteristics of each component.

[0062] When the sense amplifier 201 processes the signal on the bit line BL, it may include an offset compensation phase (OC, also known as an offset cancellation phase), a charge sharing phase (CS), a signal amplification phase (MS), and a precharge phase (PCG or PRE). The precharge phase is used to maintain the voltage of each node in the sense amplifier 201 at a preset potential; the offset compensation phase is used to perform offset compensation operations on the transistors in the sense amplifier 201; the charge sharing phase is used to transmit the input signal to the sense amplifier 201; and the signal amplification phase is used to amplify the input signal and write the amplified signal into or read it from the target memory cell.

[0063] When the sense amplifier 201 is in the offset compensation stage, the third N-type field effect transistor 111 and the sixth N-type field effect transistor 118 are turned on, and the fourth N-type field effect transistor 112 and the fifth N-type field effect transistor 117 are turned off. The circuit formed is as follows: Figure 1BAs shown, the gate and drain of the first N-type field effect transistor 114 are connected, and the gate and drain of the second N-type field effect transistor 116 are connected. In this way, the mismatch between the pair of N-type field effect transistors can be compensated, thereby improving the working performance of the sense amplifier 201.

[0064] When the sense amplifier 201 is in the signal amplification stage, the third N-type field effect transistor 111 and the sixth N-type field effect transistor 118 are turned off, and the fourth N-type field effect transistor 112 and the fifth N-type field effect transistor 117 are turned on. The circuit formed is as follows Figure 1C As shown, the gate of the first N-type field effect transistor 114 is connected to the drain of the second N-type field effect transistor 116, and the gate of the second N-type field effect transistor 116 is connected to the drain of the first N-type field effect transistor 114. In this way, the sense amplifier 10 can better amplify the signal by sensing the voltage difference between the bit line BL and the complementary bit line BLB.

[0065] In addition, the sense amplifier 201 requires different level states of different signals in different working phases to achieve offset cancellation. Figure 2 Figure 2 is a signal timing diagram of the sense amplifier 201 in different operating stages, where WL represents the word line start signal. In the precharge stage (PCG stage), the offset control signal OCS is high (logic 1), the word line start signal WL is low (logic 0), the first reference control signal SAP is low, and the second reference control signal SAN is high. In the offset compensation stage (OC stage), the offset control signal OCS is high, the word line start signal WL is low, the first reference control signal SAP is high, and the second reference control signal SAN is low. In the charge sharing stage (CS stage), the offset control signal OCS is low, the word line start signal WL is high, the first reference control signal SAP is low, and the second reference control signal SAN is high. In the signal amplification stage (MS stage), the offset control signal OCS is low, the word line start signal WL is high, the first reference control signal SAP is high, and the second reference control signal SAN is low. In this way, by controlling the level states of different signals, the mismatch of the MOS transistors in the sense amplifier 201 can be improved.

[0066] However, the above offset compensation scheme has some unavoidable problems. Figure 3 The horizontal axis represents time, and the vertical axis represents voltage, which shows a curve of each voltage changing with time during the offset compensation stage of the sense amplifier 201. Figure 3 The four curves from top to bottom represent the offset control signal OCS, the bit line BL, the complementary bit line BLB and the ground signal. On the one hand, as time goes on, due to the cross-coupling of the two P-type field effect transistors (i.e. Figure 1ADue to the latch feedback of the first P-type field effect transistor 113 and the second P-type field effect transistor 115 in the CMOS process, the voltage on the bit line BL and the voltage on the complementary bit line BLB gradually decrease from the initial 0.5V and become asymmetric. In addition, there is a delay (also known as RC delay) on the bit line BL due to the charging and discharging of the resistor and capacitor, which causes some areas of the sense amplifier 201 to be over-compensated or under-compensated. Therefore, determining the offset compensation time is also a key factor in the offset compensation scheme. On the other hand, during the offset compensation stage, a relatively serious time loss occurs, which causes the delay time (RAS to CAS Delay, tRCD) of the memory row address to the column address to increase. tRCD is a key performance parameter of DRAM.

[0067] Therefore, although the offset compensation scheme is adopted to improve the voltage mismatch, time loss occurs and the transmission time of tRCD becomes slower, affecting the performance of the memory.

[0068] Further, in one embodiment of the present disclosure, see Figure 4 , which shows the composition structure of a memory 20, the memory 20 includes a sense amplifier 201 and a control module 202. The sense amplifier 201 includes a first N-type field effect transistor 114, a second N-type field effect transistor 116, a first P-type field effect transistor 113, and a second P-type field effect transistor 115 connected in a cross-coupled manner. A first offset cancellation device 121 is provided between the gate and drain of the first N-type field effect transistor 114, and a second offset cancellation device 122 is provided between the gate and drain of the second N-type field effect transistor 116.

[0069] The control module 202 is configured to receive a state indication signal and generate a first control signal and a second control signal based on the state indication signal; wherein, when the state indication signal indicates that the sense amplifier 201 is in a pre-charge phase, the voltage value of the first control signal and the voltage value of the second control signal are both within a first voltage range; and when the state indication signal indicates that the sense amplifier 201 is in an offset compensation phase, the voltage value of the first control signal and the voltage value of the second control signal are both within a second voltage range; wherein the minimum value of the first voltage range is greater than the maximum value of the second voltage range;

[0070] A gate of the first offset cancellation device 121 receives a first control signal, and a gate of the second offset cancellation device 122 receives a second control signal.

[0071] It should be noted that the memory 20 provided in the embodiment of the present disclosure can be applied in various offset compensation scenarios, such as a sense amplifier in a DRAM.

[0072] It should be noted that if Figure 4As shown, the first signal terminal and the second signal terminal can transmit the signal to be processed to the sense amplifier 201 for reading or writing through the sense amplifier 201. Specifically, the first signal terminal can be the complementary bit line BLB, the second signal terminal can be the bit line BL, and the sense amplifier 201 can perform operations such as amplifying the signals on the bit line BL and the complementary bit line BLB.

[0073] It should be noted that the first offset cancellation device 121 can be an N-type field effect transistor or a P-type field effect transistor; the second offset cancellation device 122 can be an N-type field effect transistor or a P-type field effect transistor. The same function can be achieved by changing the connection relationship of the circuit in a specific application scenario, and no specific limitation is made here.

[0074] Furthermore, in the embodiment of the present disclosure, the status indication signal has two sources:

[0075] In the first case, the status indication signal originates from the sense amplifier 201. The sense amplifier 201 decodes and processes command signals corresponding to different operating stages to generate different status indication signals. For example, if the sense amplifier 201 is in the pre-charge stage, the control module 202 receives the command signal corresponding to the pre-charge stage as the status indication signal, thereby controlling the voltage range of the first and second control signals to ensure operation of the sense amplifier 201.

[0076] In the second case, the status indication signal originates from memory 20. A decoding unit within memory 20 decodes the activation command signal ACT and the pre-charge command signal PRE to obtain command signals required by the sense amplifier 201 at different operating stages, further generating different status indication signals. The decoded activation command signal ACT can include the offset compensation phase, charge sharing phase, and signal amplification phase of the sense amplifier 201; the decoded pre-charge command signal PRE can include the pre-charge phase of the sense amplifier 201.

[0077] In other words, the state indication signals have different sources and there are multiple state indication signals, each of which represents the operating stage of the sense amplifier 201. The state indication signals are used to generate the first control signal and the second control signal, thereby controlling the voltage values ​​of the first offset cancellation device 121 and the second offset cancellation device 122, making the control more flexible.

[0078] In this way, by controlling the voltage values ​​of the first control signal and the second control signal in different working stages of the sense amplifier 201, the loop feedback effect of the PMOS can be better reduced, thereby improving the mismatch of the NMOS and enhancing the performance of the memory.

[0079] In some embodiments, the status indication signal includes at least two sub-signals;

[0080] The control module 202 is specifically configured to control the voltage value of the first control signal and the voltage value of the second control signal to be the first value when the level states of the two sub-signals of the status indication signal meet the first condition;

[0081] The first condition indicates that the sense amplifier 201 is in a pre-charging stage, and the first value belongs to a first voltage range.

[0082] It should be noted that the level states of the two sub-signals of the status indication signal include four different combinations of 00, 01, 10 and 11. The above-mentioned first condition can be 00, 01, 10 or 11, or a combination of any two or any three. The embodiment of this disclosure does not make specific limitations.

[0083] That is, if the level states of the two sub-signals of the status indication signal meet any one, any two, or any three of the above-mentioned conditions, the sense amplifier 201 is in the pre-charging stage, and the voltage value of the first control signal and the voltage value of the second control signal are both the first value, so that the gates of the first offset cancellation device 121 and the second offset cancellation device 122 receive the first value, that is, the voltage value of the offset control signal OCS is the first value.

[0084] It should be noted that the state indication signal is used to regulate the voltage value of the first control signal and the voltage value of the second control signal, that is, to adjust the gate voltage of the first offset cancellation device 121 and the gate voltage of the second offset cancellation device 122 (i.e. Figure 1A The voltage value of the first control signal corresponds to the gate voltage of the first offset cancellation device 121, and the voltage value of the second control signal corresponds to the gate voltage of the second offset cancellation device 122. It should be understood that the first value here is a high level.

[0085] The embodiment of the present disclosure improves the mismatch of the sense amplifier 201 by adjusting the gate voltage of the first offset cancellation device 121 and the gate voltage of the second offset cancellation device 122 , thereby improving the performance of the memory.

[0086] In some embodiments, as Figure 5 As shown, the control module 202 is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be the second value when the level states of the two sub-signals of the status indication signal meet the second condition;

[0087] The second condition indicates that the sense amplifier 202 is in the offset cancellation phase, and the second value belongs to the second voltage range.

[0088] It should be noted that, as previously described, the second condition can be any one, any two, or a combination of any three of 00, 01, 10, and 11. For example, the second condition is 10; when the level states of the two sub-signals of the status indication signal are 10, the sense amplifier 201 is in the offset cancellation stage. It should be understood that the second condition and the first condition are different, corresponding to different operating stages of the sense amplifier 201. If the first condition is 00, the second condition can be 01, 10, or 11.

[0089] like Figure 5 As shown, Figure 5 Figure 2 is a schematic diagram of the signal timing of sense amplifier 201 in different operating stages. The offset control signal OCS represents the first and second control signals, WL represents the aforementioned word line enable signal, SAP represents the aforementioned first power control signal, and SAN represents the aforementioned second power control signal. For ease of description, the period before the offset compensation phase begins is referred to as the standby phase. This standby phase is essentially the precharge phase, and the pulse variations of the two phases remain consistent.

[0090] During the standby phase, control module 202 maintains the voltage of offset control signal OCS at the first value (logic 1), the voltage of wordline-on signal WL and the voltage of first reference control signal SAP at a low level (logic 0), and the voltage of second reference control signal SAN at the first value. At this point, all circuit nodes in sense amplifier 201 are at the same voltage, preparing for offset compensation.

[0091] In the offset cancellation phase, the control module 202 adjusts the voltage value of the offset control signal OCS from a first value (assuming the first value is 1) to a second value (the second value is greater than 0 and less than 1), the voltage value of the word line start signal WL remains at 0, the voltage value of the first reference control signal SAP changes from 0 to 1, and the voltage value of the second reference control signal SAN changes from 1 to 0. Therefore, if Figure 1A As shown, at this time, the fourth N-type field effect transistor 112 and the fifth N-type field effect transistor 117 corresponding to the word line are turned off, while the first N-type field effect transistor 114, the second N-type field effect transistor 116, the first P-type field effect transistor 113 and the second P-type field effect transistor 115 are turned on, and the third N-type field effect transistor 111 and the sixth N-type field effect transistor 118 are also turned on, thereby forming Figure 1B The structure shown. It should be understood that Figure 1A The third N-type field effect tube 111 is equivalent to Figure 4 The first offset cancellation device 121, Figure 1A The sixth N-type field effect transistor 118 is equivalent to Figure 4The second offset cancellation device 122 in the sense amplifier 201 is configured to perform an offset cancellation operation within the sense amplifier 201 by controlling the gate voltage of the first offset cancellation device 121 and the gate voltage of the second offset cancellation device 122 via the second control signal.

[0092] After the offset cancellation phase ends, since the first offset cancellation device 121 and the second offset cancellation device 122 are in the off state during the charge sharing phase, the voltage value of the offset control signal OCS changes from the second value to 0, and the word line start signal WL changes from 0 to 1, so that the sense amplifier 201 enters the charge sharing phase. At this time, the first reference control signal SAP changes from 1 to 0, and the second reference control signal SAN changes from 0 to 1.

[0093] After the charge sharing stage ends, the sense amplifier 201 enters the signal amplification stage. Since the first offset cancellation device 121 and the second offset cancellation device 122 are in the off state during the signal amplification stage, the voltage value of the offset control signal OCS is 0, and the voltage value of the word line start signal WL changes from 0 to 1, so that the sense amplifier 201 enters the charge sharing stage. At this time, the voltage value of the first reference control signal SAP changes from 1 to 0, and the voltage value of the second reference control signal SAN changes from 0 to 1, thereby completing the signal amplification on the bit line BL and the complementary bit line BLB.

[0094] After the signal amplification phase ends, the sense amplifier 201 re-enters the pre-charge phase. The control module 202 restores the voltage value of the offset control signal OCS to 1, restores the voltage value of the word line start signal WL and the voltage value of the first reference control signal SAP to 0, and restores the voltage value of the second reference control signal SAN to 1. At this time, the bit line BL and the complementary bit line BLB will also be restored to the same voltage value.

[0095] After the pre-charging stage is finished, the sense amplifier 201 enters the standby stage again to prepare for the next operation.

[0096] In the embodiment of the present disclosure, the control module 202 controls the voltage value of the first control signal and the voltage value of the second control signal, thereby controlling the gate voltage of the first offset cancellation device 121 and the gate voltage of the second offset cancellation device 122, thereby achieving offset cancellation of the sense amplifier 201. The specific effects achieved by this method are as follows: Figure 8 As shown, the X-axis represents the mismatch of the N-type field effect transistor (NMOS), and the Y-axis represents the mismatch of the P-type field effect transistor (PMOS). Figure 8 A in the figure represents the mismatch value of the original sense amplifier. At this time, the mismatch of NMOS and the mismatch of PMOS are both 1. When the original sense amplifier undergoes traditional offset compensation, as shown in Figure 8In Figure B, compared to the original sense amplifier, the mismatch of NMOS is reduced to 65%, and the mismatch of PMOS remains basically unchanged. In order to further reduce the mismatch of NMOS, as shown in Figure 4, the mismatch of NMOS is reduced to 65%, and the mismatch of PMOS remains basically unchanged. Figure 8 By reducing the voltage value of the offset control signal OCS by the control module 202 of the embodiment of the present disclosure, the mismatch of the NMOS can be reduced to 30% of the original sense amplifier, and the mismatch of the PMOS is slightly increased. Figure 8 As shown in Figure C, by extending the precharge time, the mismatch of NMOS can also be reduced. The mismatch of NMOS can be reduced from the original 1 to 45%, and the mismatch of PMOS increases by about 10%.

[0097] Therefore, through Figure 8 It can be seen that increasing the precharge time and reducing the voltage of the offset control signal OCS during the offset cancellation phase can effectively improve the NMOS mismatch, thereby improving the mismatch of the entire sense amplifier. Obviously, reducing the voltage of the offset control signal OCS has the best effect on improving the mismatch of the sense amplifier 201. It should be understood that for the entire sense amplifier 201, compared to the significant improvement in the NMOS mismatch, the slight increase in the PMOS mismatch has little impact on the overall improvement in the mismatch of the sense amplifier 201.

[0098] Therefore, reducing the voltage of the offset control signal OCS by the control module 202 can improve the overall mismatch problem of the sense amplifier 201 and enhance the performance of the memory. In other words, the embodiment of the present disclosure can improve the mismatch of the sense amplifier 201 by reducing the gate voltage of the first offset cancellation device 121 and the gate voltage of the second offset cancellation device 122. This method is simple to operate, easy to control, and more precise.

[0099] However, although the above method can improve the mismatch of the sense amplifier 201 during the offset cancellation phase, the resistance-capacitance delay (RC Delay) problem still exists on the bit line BL and the complementary bit line BLB, where R refers to resistance and C refers to capacitance. When a pulse signal is applied to the RC delay circuit, a delay will be generated after passing through the resistor R and the capacitor C. Specifically, when the pulse signal passes through the resistor R, the resistor R slows down the current, thereby forming a delay. When the pulse signal passes through the capacitor C, the capacitor C can store energy and release the energy over time, thereby forming a delay. Especially for large-capacity memories, the physical distance between storage cells with different addresses is significantly different, resulting in significant differences in the length of the read and write transmission paths. Due to the long transmission path, the far end of the bit line BL will have more parasitic resistance and parasitic capacitance than the near end of the bit line BL. Therefore, in order to ensure that there is sufficient read and write voltage at the far end of the bit line BL, it is usually necessary to set the required voltage value based on the far end of the bit line BL where there are more parasitic resistance and parasitic capacitance. However, such a solution will exceed the required voltage value for the proximal end of the bit line BL having smaller parasitic resistance and parasitic capacitance, which may result in a shorter lifespan of the proximal end of the bit line BL, thereby affecting the reliability of the memory.

[0100] Therefore, the embodiment of the present disclosure provides a method for reducing the difference between the near end and the far end of the bit line BL by using a two-step pulse to improve the uniformity of the bit line BL load and reduce the time of offset compensation (noise elimination). The specific implementation is described below.

[0101] In some embodiments, the offset cancellation phase includes a first cancellation phase and a second cancellation phase.

[0102] like Figure 6 As shown, the control module 202 includes a timer and is further configured to start the timer when the level states of the two sub-signals of the status indication signal meet the second condition; if the timing duration of the timer is less than or equal to the first threshold, the voltage value of the first control signal and the voltage value of the second control signal are controlled to be the third value; if the timing duration of the timer is greater than the first threshold, the voltage value of the first control signal and the voltage value of the second control signal are controlled to be the first value;

[0103] The second condition indicates that the sense amplifier 201 is in the offset cancellation stage. If the timing duration of the timer is less than or equal to the first threshold, the sense amplifier 201 is in the first cancellation stage. If the timing duration of the timer is greater than the first threshold, the sense amplifier 201 is in the second cancellation stage. The third value belongs to the second voltage range.

[0104] It should be noted that the third value may be the same as or different from the second value.

[0105] It should be noted that Figure 6 The voltage value of the offset control signal OCS is composed of the voltage value of the first control signal and the voltage value of the second control signal. Figure 6 The status of each signal can be referred to Figure 5 In particular, Figure 6 The change rules of each signal in the standby stage, charge sharing stage, signal amplification stage and pre-charge stage are similar to Figure 5 Similarly, the following only describes the working state of the offset control signal OCS in the offset cancellation stage.

[0106] like Figure 6 As shown, during the entire offset cancellation phase, the voltage value of the offset control signal OCS is not constant, but rather goes through two phases: a first cancellation phase and a second cancellation phase. In the first cancellation phase, the control module 202 adjusts the first and second control signals to a third value. In the second cancellation phase, the control module 202 restores the first and second control signals to their first values. It should be noted that the "adjustment" mentioned here is relative to the previous operating state, so "adjustment" can mean either an increase or a decrease. The voltage value of the offset control signal OCS can be increased to 1 (the first value) at the highest, or decreased to 0 at the lowest.

[0107] In other words, since the previous operating phase of the offset cancellation phase of the sense amplifier 201 is the standby phase, that is, the voltage values ​​of the first control signal and the second control signal are both the first value, and the third value is less than the first value, it can be said that in the first cancellation phase, the voltage values ​​of the first control signal and the second control signal are reduced to the third value, and in the second cancellation phase, the voltage values ​​of the first control signal and the second control signal are increased to the first value.

[0108] It should also be noted that as soon as the sense amplifier 201 enters the offset cancellation phase, a timer begins counting the offset cancellation time. By comparing the timer with a predetermined first threshold, the control module 202 controls the output voltage values ​​of the first control signal and the second control signal to be either the first value or the third value. When the timer duration is less than or equal to the first threshold, the sense amplifier 201 is in the first cancellation phase, and the voltage values ​​of the first control signal and the second control signal are the third value. When the timer duration is greater than the first threshold, the sense amplifier 201 is in the second cancellation phase, and the voltage values ​​of the first control signal and the second control signal are the first value.

[0109] By setting a timer, control module 202 can more accurately determine whether sense amplifier 201 is in the first or second offset cancellation phase of the offset cancellation stage, thereby better controlling the voltage values ​​of the first control signal and the second control signal. This control method enables first offset cancellation device 121 and second offset cancellation device 122 to achieve better offset cancellation effects, further improving mismatch in sense amplifier 201 and shortening the required offset cancellation time.

[0110] In some embodiments, as Figure 7 As shown, the offset elimination stage includes a first elimination stage and a second elimination stage.

[0111] The control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a fourth value when the level states of the two sub-signals of the status indication signal meet the third condition;

[0112] The control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a fifth value when the level states of the two sub-signals of the status indication signal meet the fourth condition;

[0113] The third condition indicates that the sense amplifier is in the first elimination stage, and the fourth condition indicates that the sense amplifier is in the second elimination stage; the fourth value and the fifth value both belong to the second voltage range, and the fourth value is smaller than the fifth value.

[0114] It should be noted that the third condition and the fourth condition are different, and the third condition and the fourth condition can also be any one, any two, or a combination of any three of 00, 01, 10, and 11. For example, if the third condition is 00, 01, 10, the fourth condition can be 01, 10, 11.

[0115] It should also be noted that Figure 8 The status of each signal can be referred to Figure 5 or Figure 6 In particular, Figure 8 The change rules of each signal in the standby stage, offset elimination stage, charge sharing stage, signal amplification stage and pre-charge stage are similar to Figure 5 and Figure 6 Similarly, the following only describes the working state of the offset control signal OCS in the offset cancellation stage.

[0116] like Figure 7As shown, during the first offset cancellation phase, control module 202 adjusts the first and second control signals to the fourth value. During the second offset cancellation phase, control module 202 adjusts the first and second control signals to the fifth value. Since both the fourth and fifth values ​​are smaller than the first value, and the fourth value is smaller than the fifth value, it can be said that during the first cancellation phase, the voltage values ​​of the first and second control signals are reduced from the original first value to the fourth value. During the second cancellation phase, the voltage values ​​of the first and second control signals are increased from the fourth value to the fifth value.

[0117] Therefore, by controlling the voltage values ​​of the first control signal and the second control signal in the first elimination stage and the second elimination stage to be within the second voltage range, the time loss in the offset elimination stage can be significantly reduced, and at the same time, the mismatch of the sense amplifier 201 can be more effectively improved, thereby improving the stability of the sense amplifier 201.

[0118] In some embodiments, the control module 202 is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be within a third voltage range when the level states of the two sub-signals of the status indication signal meet the fifth condition;

[0119] The fifth condition indicates that the sense amplifier is in the charge sharing stage or the signal amplification stage; and the maximum value of the third voltage range is less than the minimum value of the second voltage range.

[0120] As mentioned above, the fifth condition can also be any combination of 00, 01, 10 and 11, which is used to indicate that the sense amplifier is in the off state. The first condition, second condition, third condition, fourth condition and fifth condition are all different and can be flexibly set according to needs and parameters.

[0121] It should be noted that the offset cancellation function cannot be achieved during the charge sharing stage and the signal amplification stage of the sense amplifier 201. When the sense amplifier 201 is in the offset cancellation stage, the offset cancellation function can be achieved by controlling the voltage values ​​of the first control signal and the second control signal.

[0122] It should also be noted that the first elimination phase and the second elimination phase correspond to using a two-step pulse to reduce the voltage value of the offset control signal OCS. This two-step pulse method can improve the uniformity of the bit line BL load. Figure 9 As shown, by setting a two-step pulse in the offset cancellation stage to generate overdamping, the difference between the near end and the far end of the bit line BL can be reduced, making the load of the bit line BL of each memory bank 14 on the resistor 15 and the capacitor 16 more uniform. It should be understood that Figure 9Only one resistor 15 and one capacitor 16 are shown in the figure, but there are actually multiple resistors and capacitors on the bit line BL.

[0123] At the same time, the two-step pulse method can also reduce the time of offset cancellation (also called noise cancellation, Noise cancellation, referred to as NC). Figure 10 As shown, the dotted line represents the distal end of the bit line BL, and the solid line represents the proximal end of the bit line BL. Figure 10 The upper part shows the variation of the near-end voltage and far-end voltage of the bit line BL with time under normal pulse conditions during the offset cancellation phase (there is only one pulse during the offset cancellation phase). Figure 10 The lower half of FIG is a diagram showing how the near-end voltage and far-end voltage of the bit line BL change with time when the offset elimination phase is a two-step pulse according to the embodiment of the present disclosure. Figure 10 It can be seen that compared with the normal pulse case, the two-step pulse method can reduce the time required for offset elimination and avoid time loss.

[0124] In summary, an embodiment of the present disclosure provides a memory including a sense amplifier and a control module. The control module receives a status indication signal representing the working stage of the sense amplifier, and generates a first control signal and a second control signal based on the status indication signal, thereby controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to achieve the effect of offset cancellation of the sense amplifier.

[0125] In another embodiment of the present disclosure, see Figure 11 , which shows a flow chart of an offset compensation method provided by an embodiment of the present disclosure, which is applied to a sense amplifier. The sense amplifier includes a first N-type field effect transistor, a second N-type field effect transistor, a first P-type field effect transistor, and a second P-type field effect transistor connected in a cross-coupled manner. A first offset cancellation device is provided between the gate and the drain of the first N-type field effect transistor, and a second offset cancellation device is provided between the gate and the drain of the second N-type field effect transistor. The method includes:

[0126] S301: In a pre-charging phase of the sense amplifier, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be in a first voltage range, so that both the first offset cancellation device and the second offset cancellation device are in a strong on state.

[0127] S302: During a portion or all of an offset cancellation phase of the sense amplifier, controlling a gate voltage of a first offset cancellation device and a gate voltage of a second offset cancellation device to be within a second voltage range so that both the first offset cancellation device and the second offset cancellation device are in a weak on state; wherein a minimum value of the first voltage range is greater than a maximum value of the second voltage range.

[0128] It should be noted that the offset compensation method provided in the embodiment of the present disclosure improves the mismatch of the sense amplifier in the offset cancellation stage by controlling the degree of on-state of the first offset cancellation device and the second offset cancellation device, thereby improving the performance of the memory.

[0129] It should be noted that for the first offset cancellation device 121, if the first offset cancellation device 121 is in a strongly on state, its impedance is smaller; if the first offset cancellation device 121 is in a weakly on state, its impedance is larger. The second offset cancellation device can also be understood similarly and will not be described in detail here.

[0130] It should also be noted that controlling the turn-on levels of the first and second offset cancellation devices is generally achieved by controlling the gate voltages of the first and second offset cancellation devices. The first voltage range corresponds to a strongly turned-on state, while the second voltage range corresponds to a weakly turned-on state. The terms "strong" and "weak" are relative terms, and the first and second voltage ranges are not exclusive.

[0131] In some embodiments, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a first voltage range includes:

[0132] In a pre-charging phase of the sense amplifier, the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are both controlled to be a first value; wherein the first value belongs to a first voltage range.

[0133] It should be noted that the first voltage range includes multiple voltage values. That is, in the pre-charge phase of the sense amplifier, the first offset cancellation device and the second offset cancellation device are always in a strong on state.

[0134] In some embodiments, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range includes:

[0135] During the entire time period of the offset cancellation phase of the sense amplifier, the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are controlled to be a second value; wherein the second value belongs to a second voltage range.

[0136] It should be noted that, since the minimum value of the first voltage range is greater than the maximum value of the second voltage range, the second value is smaller than the first value. That is, during the offset cancellation phase, by reducing the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device from the first value to the second value during the precharge phase, the first offset cancellation device and the second offset cancellation device are both controlled to be in a weakly on state. Specifically, if the first value is 1 and the second value is 0.8, when the sense amplifier is in the offset cancellation phase, the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are both reduced from 1 to 0.8. Furthermore, the second value here is not unique; different second values ​​correspond to different weakly on states for the first offset cancellation device and the second offset cancellation device. This enriches the circuit design, simplifies the operation, and facilitates control.

[0137] In some embodiments, the offset cancellation stage includes a first cancellation stage and a second cancellation stage, wherein the second cancellation stage occurs after the first cancellation stage; and controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range further includes:

[0138] controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be a third value in the first cancellation phase;

[0139] The gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are both controlled to be the first value in the second cancellation phase; wherein the third value belongs to the second voltage range.

[0140] That is, when the sense amplifier enters the offset cancellation phase after the standby phase, controlling the first and second offset cancellation devices simply requires adjusting the on-states of the first and second offset cancellation devices in the first cancellation phase to the same weak on-state, i.e., the gate voltages of the first and second offset cancellation devices are both at the third value in the first cancellation phase. Simultaneously, adjusting the weak on-states of the first and second offset cancellation devices in the first cancellation phase to strong on-states, i.e., the gate voltages of the first and second offset cancellation devices are both at the first value in the second cancellation phase. This method differs from the above-described method in that the offset cancellation phase is divided into two phases: the on-states of the first and second offset cancellation devices in the first cancellation phase are the same, the on-states of the first and second offset cancellation devices in the second cancellation phase are the same, the on-states of the first and second offset cancellation devices are different, and the on-states of the second offset cancellation device in the first and second cancellation phases are different, with the degree of on-state in the first cancellation phase being less than the degree of on-state in the second cancellation phase.

[0141] In some embodiments, the offset cancellation stage includes a first cancellation stage and a second cancellation stage, wherein the second cancellation stage occurs after the first cancellation stage; and controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range further includes:

[0142] controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be a fourth value in the first cancellation phase;

[0143] The gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are both controlled to be a fifth value in the second cancellation phase; wherein the fourth value and the fifth value both belong to the second voltage range, and the fourth value is smaller than the fifth value.

[0144] Similarly, when the sense amplifier enters the offset cancellation phase after the standby phase, the first and second offset cancellation devices are controlled. First, the on-states of the first and second offset cancellation devices in the first cancellation phase need to be adjusted to a first weak on-state, i.e., the gate voltages of the first and second offset cancellation devices are both at the fourth value in the first cancellation phase. Then, the on-states of the first and second offset cancellation devices in the second cancellation phase need to be adjusted from the first weak on-state to a second weak on-state, i.e., the gate voltages of the first and second offset cancellation devices are both at the fifth value in the second cancellation phase. In particular, the fourth and fifth values ​​are not equal, so the first and second weak on-states are different.

[0145] In some embodiments, the method further comprises:

[0146] During the charge sharing stage and the signal amplification stage of the sense amplifier, the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are controlled to be within a third voltage range so that the first offset cancellation device and the second offset cancellation device are both in an off state; wherein the maximum value of the third voltage range is less than the minimum value of the second voltage range.

[0147] It should be noted that the first offset cancellation device and the second offset cancellation device have different turn-on states at different stages of the sense amplifier 201. In particular, the weak turn-on state of the first offset cancellation device and the weak turn-on state of the second offset cancellation device can be the same weak turn-on state or different weak turn-on states.

[0148] During the operating phase of the sense amplifier, the first and second offset cancellation devices are only in the on state during the precharge and offset compensation phases, and are in the off state during the charge sharing and signal amplification phases. Therefore, the first and second offset cancellation devices generally have three states: a strongly on state, a weakly on state, and an off state, with the degree of on-state decreasing in descending order. During the standby and precharge phases of the sense amplifier, the first and second offset cancellation devices are controlled to be in the strongly on state, i.e., the gate voltages of the first and second offset cancellation devices are at a first value. During the offset cancellation phase of the sense amplifier, the first and second offset cancellation devices are controlled to be in the weakly on state, i.e., the gate voltages of the first and second offset cancellation devices are within a second voltage range (second, third, fourth, and fifth values). During the charge sharing and signal amplification phases of the sense amplifier, the first and second offset cancellation devices are controlled to be in the off state, i.e., the gate voltages of the first and second offset cancellation devices are within a third voltage range. This method clarifies control and improves the effectiveness of mismatch compensation.

[0149] In some embodiments, the first offset cancellation device and the second offset cancellation device are both N-type field effect transistors.

[0150] Since N-type FETs conduct when their gates are high, and P-type FETs conduct when their gates are low, in another embodiment, first offset cancellation device 121 and second offset cancellation device 122 may be P-type FETs. Therefore, either N-type or P-type FETs can be used as offset cancellation devices. The specific selection criteria are determined by the circuit design and connection method, thereby increasing the flexibility of the circuit structure.

[0151] In summary, the embodiments of the present disclosure provide an offset compensation method, which controls the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to control the on-state of the first offset cancellation device and the second offset cancellation device, thereby effectively improving the mismatch of the sensitive amplifier, reducing the time loss of offset cancellation, and improving the stability of the device.

[0152] In yet another embodiment of the present disclosure, Figure 12 As shown, it shows a schematic diagram of the composition structure of an electronic device 40 provided by an embodiment of the present disclosure. The electronic device 40 may include the memory 20 of the aforementioned embodiment.

[0153] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure.

[0154] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0155] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0156] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0157] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0158] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0159] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for offset compensation, characterized in that: The method is applied to a sense amplifier, the sense amplifier including a first N-type field effect transistor, a second N-type field effect transistor, a first P-type field effect transistor, and a second P-type field effect transistor connected in a cross-coupled manner, wherein a first offset cancellation device is provided between the gate and the drain of the first N-type field effect transistor, and a second offset cancellation device is provided between the gate and the drain of the second N-type field effect transistor, and the method includes: During a precharge phase of the sense amplifier, controlling a gate voltage of the first offset cancellation device and a gate voltage of the second offset cancellation device to be within a first voltage range so that both the first offset cancellation device and the second offset cancellation device are in a strong on state; During a portion or all of an offset cancellation phase of the sense amplifier, controlling a gate voltage of the first offset cancellation device and a gate voltage of the second offset cancellation device to be within a second voltage range so that both the first offset cancellation device and the second offset cancellation device are in a weak on state; The minimum value of the first voltage range is greater than the maximum value of the second voltage range.

2. The offset compensation method according to claim 1, wherein: The controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a first voltage range comprises: During a pre-charging phase of the sense amplifier, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be a first value; The first value belongs to the first voltage range.

3. The offset compensation method according to claim 2, wherein: The controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range comprises: During the entire time period of the offset cancellation phase of the sense amplifier, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be a second value; The second value belongs to the second voltage range.

4. The offset compensation method according to claim 2, wherein: The offset elimination phase includes a first elimination phase and a second elimination phase, wherein the second elimination phase occurs after the first elimination phase; The controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range further includes: controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be a third value in the first cancellation phase; controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be the first value in the second cancellation phase; The third value belongs to the second voltage range.

5. The offset compensation method according to claim 3, wherein: The offset elimination phase includes a first elimination phase and a second elimination phase, wherein the second elimination phase occurs after the first elimination phase; The controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a second voltage range further includes: controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be a fourth value in the first cancellation phase; The gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device are both controlled to be a fifth value in the second cancellation stage; wherein the fourth value and the fifth value both belong to the second voltage range, and the fourth value is smaller than the fifth value.

6. The offset compensation method according to any one of claims 1 to 5, characterized in that: The method further comprises: During the charge sharing stage and the signal amplification stage of the sense amplifier, controlling the gate voltage of the first offset cancellation device and the gate voltage of the second offset cancellation device to be within a third voltage range, so that the first offset cancellation device and the second offset cancellation device are both in an off state; The maximum value of the third voltage range is smaller than the minimum value of the second voltage range.

7. The offset compensation method according to any one of claims 1 to 5, characterized in that: The first offset cancellation device and the second offset cancellation device are both N-type field effect transistors.

8. A memory, characterized in that: The memory includes a sense amplifier and a control module, the sense amplifier includes a first N-type field effect transistor, a second N-type field effect transistor, a first P-type field effect transistor, and a second P-type field effect transistor connected in a cross-coupled manner, a first offset cancellation device is provided between the gate and the drain of the first N-type field effect transistor, and a second offset cancellation device is provided between the gate and the drain of the second N-type field effect transistor; The control module is configured to receive a status indication signal and generate a first control signal and a second control signal according to the status indication signal; wherein, when the status indication signal indicates that the sense amplifier is in a pre-charge phase, a voltage value of the first control signal and a voltage value of the second control signal are both within a first voltage range; and when the status indication signal indicates that the sense amplifier is in an offset cancellation phase, a voltage value of the first control signal and a voltage value of the second control signal are both within a second voltage range; wherein a minimum value of the first voltage range is greater than a maximum value of the second voltage range; A gate of the first offset cancellation device receives the first control signal, and a gate of the second offset cancellation device receives the second control signal.

9. The memory according to claim 8, wherein: The status indication signal includes at least two sub-signals; The control module is specifically configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a first value when the level states of the two sub-signals of the status indication signal meet a first condition; The first condition indicates that the sense amplifier is in a pre-charging stage, and the first value belongs to the first voltage range.

10. The memory according to claim 8, wherein The control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a second value when the level states of the two sub-signals of the status indication signal meet a second condition; The second condition indicates that the sense amplifier is in an offset cancellation phase, and the second value belongs to the second voltage range.

11. The memory according to claim 9, wherein: The offset elimination stage includes a first elimination stage and a second elimination stage, The control module includes a timer, and is further configured to start the timer when the level states of the two sub-signals of the status indication signal meet a second condition; if the timing duration of the timer is less than or equal to a first threshold, control the voltage value of the first control signal and the voltage value of the second control signal to be a third value; if the timing duration of the timer is greater than the first threshold, control the voltage value of the first control signal and the voltage value of the second control signal to be the first value; Among them, the second condition indicates that the sensitive amplifier is in the offset elimination stage; if the timing duration of the timer is less than or equal to the first threshold, it indicates that the sensitive amplifier is in the first elimination stage; if the timing duration of the timer is greater than the first threshold, it indicates that the sensitive amplifier is in the second elimination stage; the third value belongs to the second voltage range.

12. The memory according to claim 8, wherein: The offset elimination stage includes a first elimination stage and a second elimination stage, The control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a fourth value when the level states of the two sub-signals of the status indication signal meet a third condition; The control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be a fifth value when the level states of the two sub-signals of the status indication signal meet a fourth condition; The third condition indicates that the sense amplifier is in the first elimination stage, and the fourth condition indicates that the sense amplifier is in the second elimination stage; the fourth value and the fifth value both belong to the second voltage range, and the fourth value is smaller than the fifth value.

13. The memory according to claim 8, wherein: The control module is further configured to control the voltage value of the first control signal and the voltage value of the second control signal to be within a third voltage range when the level states of the two sub-signals of the status indication signal meet a fifth condition; The fifth condition indicates that the sense amplifier is in a charge sharing stage or a signal amplification stage; and the maximum value of the third voltage range is less than the minimum value of the second voltage range.

14. An electronic device, characterized in that: The method comprises the memory according to any one of claims 8 to 13.

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