A current limiting detection circuit and a switching power supply control chip

Abstract

The present invention relates to the technical field of integrated circuits. The present invention provides a current limiting detection circuit and a switch power supply control chip, wherein the current limiting detection circuit comprises: a power tube, a sampling tube, an input transconductance amplifier, a current mirror, a voltage comparator, a first resistor, a second resistor and a third resistor; the positive input end of the voltage comparator is connected to the source of the power tube, and the negative input end is connected to the source of the sampling tube; the first resistor is connected in series in the direction of the substrate current of the sampling tube; the first end of the second resistor and the first end of the third resistor are respectively connected to the two input ends of the input transconductance amplifier; the second end of the second resistor and the second end of the third resistor are respectively connected to the two ends of the first resistor; the output end of the input transconductance amplifier is connected to the first end of the third resistor; the voltage comparator is used to output a comparison signal according to the voltage corresponding to the sampling current and the voltage corresponding to the threshold current.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a current limiting detection circuit and a switching power supply control chip. Background Art

[0002] In modern electronic systems, power supply is an important part. The DC-DC converter is a common part of the power supply, and its function is to efficiently convert a DC voltage to another lower or higher voltage. In the DC-DC topology, the synchronous BUCK / BOOST circuit requires a low-side power tube and its matching low-side drive circuit.

[0003] In order to protect the low-side power tube, a current limiting protection circuit is generally integrated in the low-side driver. When it detects that the current of the low-side power tube is greater than the threshold, the power tube is turned off to prevent the current from rising further. A common overcurrent detection circuit is Figure 1 As shown, the current flows from the ground through the power tube M N_PWR , power tube M N_PWR The drain voltage is V SW . Sampling tube M N_SNS Yes and power tube M N_PWR In order to reduce the power consumption of the current limiting protection circuit, the sampling tube here is composed of multiple tubes connected in series (N×M N_SNS ), increase the mirror ratio.

[0004] Figure 1 In each tube M N_SNS Is with power tube M N_PWR A mirror tube with a certain ratio (1:K). N_PWR When current flows from source to drain, assuming that the negative input voltage V COMP The voltage is 0V,

[0005]

[0006]

[0007] For sampling tube M N_SNSA Source current, For power tube M N_PWR Source current, K N =μ×Cox, μ is the electron mobility, Cox is the capacitance per unit area of ​​the MOS gate, is the sampling tube width-to-length ratio, is the width-to-length ratio of the power tube, is the gate voltage of the sampling tube / power tube, is the threshold voltage, V SWIt is the drain voltage of the sampling tube / power tube.

[0008] When the comparator COMP_LSLMT flips, the corresponding power tube M N_PWR The current threshold is:

[0009]

[0010] That is, assuming that the negative input voltage V COMP is 0V, then the sampling tube M N_SNS A current of 1 / (N×K) will flow through. If the current flowing through MOS tube M5 is greater than (1 / (N×K)) ×I S2 , then the negative input voltage V COMP will rise, and the comparator COMP_LSLMT output will turn high. Otherwise, the comparator COMP_LSLMT output will be low.

[0011] There is a problem with this circuit. The substrate current is not taken into account, which makes the actual sampling current inaccurate. When the substrate current of the power tube and the sampling tube exists, the inaccurate sampling current will make the current flowing through the power tube different from the set threshold current when the actual circuit output flips, so the accuracy of the current limiting will be affected to a considerable extent.

[0012] Therefore, how to correct the influence of substrate current on sampling current, improve the accuracy of sampling current, and further improve the current limiting accuracy of power tube is a problem that needs to be solved at present. Summary of the invention

[0013] The purpose of the present invention is to provide a current limiting detection circuit and a switching power supply control chip, which can correct the influence of substrate current on sampling current, improve the accuracy of sampling current, and further improve the current limiting accuracy of power tube.

[0014] In order to achieve the above object, the present invention provides a current limiting detection circuit, comprising:

[0015] A power tube, a sampling tube, an input transconductance amplifier, a current mirror, a voltage comparator, a first resistor, a second resistor and a third resistor;

[0016] The sampling tube is used to sample the current of the power tube;

[0017] The positive input terminal of the voltage comparator is connected to the source of the power tube, and the negative input terminal is connected to the source of the sampling tube;

[0018] The first resistor is connected in series on the substrate current direction of the sampling tube, and is used to sample the substrate current of the sampling tube, and convert the substrate current into a voltage, which is input into the input transconductance amplifier;

[0019] The first end of the second resistor and the first end of the third resistor are respectively connected to the two input ends of the input transconductance amplifier; the second end of the second resistor and the second end of the third resistor are respectively connected to the two ends of the first resistor; the output end of the input transconductance amplifier is connected to the first end of the third resistor;

[0020] The voltage comparator is used to output a comparison signal according to the voltage corresponding to the sampling current and the voltage corresponding to the threshold current; the sampling current is the sum of the source current of the sampling tube and the substrate current of the sampling tube.

[0021] In an optional solution, the current mirror includes: a first PMOS tube, a second PMOS tube, a fifth PMOS tube and a sixth PMOS tube;

[0022] The source of the first PMOS tube is connected to the drain and gate of the second PMOS tube, the gate and drain of the first PMOS tube are short-circuited and connected to the gate of the sixth PMOS tube and grounded;

[0023] The gate and drain of the second PMOS tube are short-circuited and connected to the gate of the fifth PMOS tube;

[0024] The drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube; the source of the fifth PMOS tube and the source of the second PMOS tube are connected to a power supply voltage;

[0025] The drain of the sixth PMOS tube is connected to the negative input terminal of the voltage comparator and the source of the sampling tube.

[0026] In an optional solution, the input transconductance amplifier includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a third PMOS tube and a fourth PMOS tube;

[0027] The gate of the third PMOS tube is connected to the gate of the fourth PMOS tube and the gate of the second PMOS tube; the source of the third PMOS tube and the source of the fourth PMOS tube are connected to a power supply voltage;

[0028] The drain of the third PMOS tube is connected to the drain of the first NMOS tube and the gate of the third NMOS tube;

[0029] The drain of the fourth PMOS tube is connected to the drain and gate of the second NMOS tube;

[0030] The gate of the first NMOS tube is connected to the gate of the second NMOS tube, the source of the first NMOS tube is connected to the first end of the second resistor; the source of the second NMOS tube is connected to the first end of the third resistor;

[0031] The drain of the third NMOS tube is connected to the source of the sixth PMOS tube and the drain of the fifth PMOS tube, and the source of the third NMOS tube is connected to the first end of the third resistor.

[0032] In an optional solution, the gate of the sampling tube is connected to the gate of the power tube; the drain of the sampling tube is connected to the drain of the power tube; and the substrate of the power tube is connected to the positive input terminal of the voltage comparator and the ground.

[0033] In an optional solution, one end of the first resistor is connected to the substrate of the sampling tube, and the other end is grounded.

[0034] In an optional solution, the sampling tube is a single MOS tube or a plurality of MOS tubes connected in series.

[0035] In an optional solution, the second resistor and the third resistor have the same resistance value.

[0036] The present invention also provides a switching power supply control chip, comprising the above-mentioned current limiting detection circuit, and also comprising a control module for controlling the operation of the power tube according to the control signal output by the voltage comparator.

[0037] The beneficial effects of the present invention are:

[0038] The present invention can correct the influence of the sampling tube / power tube substrate current on the sampling current, improve the accuracy of the sampling current, and further improve the current limiting accuracy of the power tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0040] Figure 1 is a circuit diagram of an existing current limiting detection circuit.

[0041] Figure 2 This is a schematic diagram of a high-voltage NMOS tube.

[0042] Figure 3 It is a schematic diagram of substrate current in an existing current limiting detection circuit.

[0043] Figure 4 A typical current limiting circuit diagram after considering the substrate current for an existing current limiting detection circuit.

[0044] Figure 5 FIG. 4 is a circuit diagram of a current limiting detection circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0046] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0047] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] Example 1

[0050] Reference Figures 1 to 5 , this embodiment provides a current limiting detection circuit, including:

[0051] Power tube M N_PWR 、Sampling tube M N_SNS , an input transconductance amplifier, a current mirror, a voltage comparator COMP_LSLMT, a first resistor R1, a second resistor R2 and a third resistor R3; the sampling tube M N_SNS For sampling the power tube M N_PWR The positive input terminal of the voltage comparator COMP_LSLMT is connected to the power tube M N_PWR The negative input terminal is connected to the sampling tube M N_SNS The first resistor R1 is connected in series with the sampling tube M N_SNS The substrate current is directed upward, and the sampling tube M is used to sample N_SNS The substrate current is converted into a voltage and input into the input transconductance amplifier;

[0052] The first end of the second resistor R2 and the first end of the third resistor R3 are respectively connected to the two input ends of the input transconductance amplifier; the second end of the second resistor R2 and the second end of the third resistor R3 are respectively connected to the two ends of the first resistor R1; the output end of the input transconductance amplifier is connected to the first end of the third resistor R3; the voltage comparator COMP_LSLMT is used to output a comparison signal according to the voltage corresponding to the sampling current and the voltage corresponding to the threshold current; the sampling current is the sampling tube M N_SNS The source current and the sampling tube M N_SNS The sum of the substrate currents.

[0053] Specifically, in this embodiment, the current mirror includes: a first PMOS tube M P1 , the second PMOS tube M P2 , the fifth PMOS tube M P5and the sixth PMOS tube M P6 ; The first PMOS tube M P1 The source of the second PMOS tube M P2 The drain and gate of the first PMOS tube M P1 The gate and drain of the PMOS tube M are short-circuited and connected to the sixth PMOS tube M P6 The gate of the second PMOS tube M is connected to the ground; P2 The gate and drain of the PMOS tube M are short-circuited and connected to the fifth PMOS tube M P5 The gate of the fifth PMOS tube M P5 The drain of the sixth PMOS tube M is connected to the P6 The source of the fifth PMOS tube M P5 The source of the second PMOS tube M P2 The source of the sixth PMOS tube M is connected to the supply voltage; P6 The drain of the voltage comparator COMP_LSLMT is connected to the negative input terminal and the sampling tube M N_SNS The source.

[0054] In this embodiment, the input transconductance amplifier includes: a first NMOS transistor M N1 , the second NMOS tube M N2 , the third NMOS tube M N3 , the third PMOS tube M P3 And the fourth PMOS tube M P4 The third PMOS tube M P3 The gate of the fourth PMOS tube M is connected to P4 The gate and the second PMOS tube M P2 The gate of the third PMOS tube M P3 The source of the fourth PMOS tube M P4 The source of the third PMOS tube M is connected to the supply voltage; P3 The drain of the first NMOS tube M N1 The drain of the third NMOS tube M N3 The gate of the fourth PMOS tube M P4 The drain of the second NMOS tube M N2 The drain and gate of the first NMOS tube M N1 The gate of the second NMOS tube M N2 The gate of the first NMOS tube M N1 The source of the second NMOS transistor M is connected to the first end of the second resistor R2; N2 The source of the third NMOS tube M is connected to the first end of the third resistor R3;N3 The drain of the fifth PMOS tube M is connected to the P5 The drain of the sixth PMOS tube M P6 The source of the third NMOS tube M N3 The source of the input transconductance amplifier is connected to the first end of the third resistor R3. P5 Current based compensation.

[0055] The sampling tube M N_SNS The gate of the power tube M N_PWR The sampling tube M N_SNS The drain of the power tube M N_PWR The drain of the power tube M N_PWR The substrate is connected to the positive input terminal of the voltage comparator COMP_LSLMT and the ground. One end of the first resistor R1 is connected to the sampling tube M N_SNS The sampling tube M N_SNS Multiple MOS tubes are connected in series.

[0056] The purpose of the current limiting detection circuit of this embodiment is to correct the influence of the sampling tube / power tube substrate current on the sampling current, improve the accuracy of the sampling current, and further improve the accuracy of the voltage comparator flipping. How to control the power tube after the voltage comparator flips is not within the scope of discussion of this embodiment. Those skilled in the art know how to design a circuit for drive control. Regarding the comparison of the voltage comparator, a threshold current is given (the threshold current is the set value for the voltage comparator to flip). This threshold current flows on the sampling tube and generates a threshold voltage V TH , the voltage comparator compares the threshold voltage V TH With real-time sampling tube V DS Voltage (the voltage corresponding to the sampling current flowing through the sampling tube, equivalent to the V DS Voltage), if the sampling tube is V DS The voltage reaches the threshold voltage V TH , the voltage comparator flips. Since the current actually flowing through the sampling tube also includes the substrate current, the current flowing through the power tube when the actual comparator flips is different from the set threshold current. The purpose of this embodiment is to correct this deviation.

[0057] The following introduces the principle that this circuit can improve the current limiting accuracy of the power tube.

[0058] A typical BCD process high voltage MOS tube is as follows Figure 2 When the withstand voltage of the MOS tube is greater than or equal to 40V, its drain terminal D and the external deep N well (DNW) are usually required to be connected together. Figure 2It shows that each end of the MOS tube corresponds to Figure 1 You can see the name of V SW It is connected to the D and DNW terminals of the MOS tube at the same time. The current flowing from the S terminal to the D terminal is I S1 (corresponding to the current flowing into the sampling tube) and I S2 (corresponding to the current flowing into the power tube), the current flowing from the substrate SUB to DNW is I SUB1 (corresponding to the current flowing into the sampling tube substrate) and I SUB2 (corresponding to the current flowing into the substrate of the power tube). SUB1 In fact, it is composed of multiple substrate currents superimposed, I SUB1 Including I SUB1A ,I SUB1B ,I SUB1C ,I SUB1D ,I SUB1E For the convenience of demonstration, 5 tubes are connected in series as 5×M N_SNS For example, Figure 3 As shown:

[0059]

[0060]

[0061] I D1 Represents the drain current of the sampling tube, I D2 Indicates the drain current of the power tube.

[0062] If the current limit threshold is set small, the SUB-DNW diodes of the power tube and the sampling tube are not turned on, and the substrate current problem does not need to be considered, which is the case for the typical solution. When the current limit threshold is set large, or the circuit needs to work at high temperature, the substrate current cannot be ignored.

[0063] Single sampling tube M N_SNS With power tube M N_PWR The size ratio of is 1:K, then the sampling tube M N_SNSA ~M N_SNSE The mirror tube and power tube M in series N_PWR The ratio is 1:5K. N_SNSA ~M N_SNSE The SUB-DNW voltages (referring to the forward voltage drop of the SUB-DNW diode) of these tubes are inconsistent, so I SUB1E >I SUB1D >I SUB1C >I SUB1B >I SUB1A Assume that the sampling tube M N_SNSA ~M N_SNSE The SUB-DNW junction area of ​​each tube (such as Figure 2The PN junction area of ​​the diode DNW and PSUB formed in the middle) and the power tube M N_PWR The ratio of the SUB-DNW junction area is also maintained at 1:K, then there is a sampling tube M N_SNSE The SUB current of the tube I SUB1E with I SUB2 Mirror image ratio 1: K, I SUB1 with I SUB2 The ratio is greater than 1:K. At this time, I SUB1 +I S1 with I SUB2 +I S2 The ratio is significantly greater than 1:5 K. Therefore, qualitatively speaking, the substrate current causes the mirror ratio to change.

[0064] The following circuit analysis shows that the substrate current I SUB The actual sampling after Figure 4 As shown:

[0065] Assume V COMP =0, the sampling tube voltage and I S1 The relationship is:

[0066]

[0067] Sampling tube voltage and I S2 The relationship is:

[0068]

[0069] At this time, the current threshold is:

[0070]

[0071] It can be seen that the current threshold is raised. In practical applications, with the changes in temperature, process and power supply voltage, the substrate current will have deviations with different trends. These deviations make it impossible to accurately set the current limit threshold using a simple current mirror.

[0072] In order to solve this problem, as described above, this embodiment proposes Figure 5 The circuit shown in FIG. 1 is shown in FIG. 1 , wherein the resistance of the second resistor and the third resistor are the same, that is, R2=R3, and I MP3 =I MP4 When there is a voltage drop across the first resistor R1, a compensation current I COMP .

[0073]

[0074] The actual current flowing through the sampling tube for

[0075]

[0076] The current of the power tube when the voltage comparator flips for

[0077]

[0078]

[0079]

[0080] Adjust the first resistor R1, the second resistor R2, and the third resistor R3 so that

[0081]

[0082] Since the substrate current at both ends of the equation has the same drift trend with process, power supply and temperature, the influence of substrate current can be eliminated, and the effectiveness of the circuit is not affected by process, power supply and temperature. This circuit does not require off-chip devices, and all circuits are integrated.

[0083] Another embodiment of the present invention provides a switching power supply control chip, including the above-mentioned current limiting detection circuit, and also includes a control module for controlling the operation of the power tube according to the control signal output by the voltage comparator.

[0084] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A current limiting detection circuit, characterized in that: include: A power tube, a sampling tube, an input transconductance amplifier, a current mirror, a voltage comparator, a first resistor, a second resistor and a third resistor; The sampling tube is used to sample the current of the power tube; The positive input terminal of the voltage comparator is connected to the source of the power tube, and the negative input terminal is connected to the source of the sampling tube; The first resistor is connected in series on the substrate current direction of the sampling tube, and is used to sample the substrate current of the sampling tube, and convert the substrate current into a voltage, which is input into the input transconductance amplifier; The first end of the second resistor and the first end of the third resistor are respectively connected to the two input ends of the input transconductance amplifier; the second end of the second resistor and the second end of the third resistor are respectively connected to the two ends of the first resistor; the output end of the input transconductance amplifier is connected to the first end of the third resistor; The voltage comparator is used to output a comparison signal according to the voltage corresponding to the sampling current and the voltage corresponding to the threshold current; The sampling current is the sum of the source current of the sampling tube and the substrate current of the sampling tube; The current mirror comprises: a first PMOS tube, a second PMOS tube, a fifth PMOS tube and a sixth PMOS tube; The source of the first PMOS tube is connected to the drain and gate of the second PMOS tube, the gate and drain of the first PMOS tube are short-circuited and connected to the gate of the sixth PMOS tube and grounded; The gate and drain of the second PMOS tube are short-circuited and connected to the gate of the fifth PMOS tube; The drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube; the source of the fifth PMOS tube and the source of the second PMOS tube are connected to a power supply voltage; The drain of the sixth PMOS tube is connected to the negative input terminal of the voltage comparator and the source of the sampling tube; The input transconductance amplifier comprises: a first NMOS tube, a second NMOS tube, a third NMOS tube, a third PMOS tube and a fourth PMOS tube; The gate of the third PMOS tube is connected to the gate of the fourth PMOS tube and the gate of the second PMOS tube; the source of the third PMOS tube and the source of the fourth PMOS tube are connected to a power supply voltage; The drain of the third PMOS tube is connected to the drain of the first NMOS tube and the gate of the third NMOS tube; The drain of the fourth PMOS tube is connected to the drain and gate of the second NMOS tube; The gate of the first NMOS tube is connected to the gate of the second NMOS tube, the source of the first NMOS tube is connected to the first end of the second resistor; the source of the second NMOS tube is connected to the first end of the third resistor; The drain of the third NMOS tube is connected to the source of the sixth PMOS tube and the drain of the fifth PMOS tube, and the source of the third NMOS tube is connected to the first end of the third resistor.

2. The current limiting detection circuit according to claim 1, characterized in that: The gate of the sampling tube is connected to the gate of the power tube; the drain of the sampling tube is connected to the drain of the power tube; the substrate of the power tube is connected to the positive input terminal of the voltage comparator and the ground.

3. The current limiting detection circuit according to claim 1, characterized in that: One end of the first resistor is connected to the substrate of the sampling tube, and the other end is grounded.

4. The current limiting detection circuit according to claim 1, characterized in that: The sampling tube is a single MOS tube or a plurality of MOS tubes connected in series.

5. The current limiting detection circuit according to claim 1, characterized in that: The second resistor and the third resistor have the same resistance value.

6. A switching power supply control chip, characterized in that: It comprises the current limiting detection circuit as described in any one of claims 1 to 5, and also comprises a control module for controlling the operation of the power tube according to the control signal output by the voltage comparator.

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