A deadlock prevention charge pump circuit

Abstract

An embodiment of the present invention discloses a deadlock prevention charge pump circuit, which includes a hysteresis comparator. When the source switch charge pump circuit is in a deadlock state, the hysteresis comparator is used to collect the output voltage of the source switch charge pump circuit, compare the output voltage with a preset reference voltage, and when the output voltage is greater than the reference voltage, output a control voltage to control the operational amplifier to stop working and turn on the current source transistor M4. By using a source switch charge pump, the circuit operating speed can be increased, the static power loss can be reduced, the channel charge injection of the switch can be avoided, and the charge sharing effect can be reduced. In the embodiment, an operational amplifier is used to increase the impedance, reduce the current mismatch, and a hysteresis comparator is added, which can realize automatic detection, comparison and calibration. When the voltage at the output end of the charge pump circuit deviates from the expected range, the working mode of the circuit is adaptively changed to avoid being locked at the power supply voltage, improving the reliability of the circuit and expanding the adaptability of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a deadlock prevention charge pump circuit. Background Art

[0002] At present, in modern wireless communication systems, the receivers of communication devices not only have higher and higher requirements for the performance of phase-locked loops, but also require extremely high adaptability and reliability. As one of the key components of the phase-locked loop, the performance of the charge pump directly affects the working state of the phase-locked loop. The core idea of the high-performance charge pump structure in the prior art is to reduce the non-ideal effects existing in the charge pump, such as charge sharing and channel charge injection effects.

[0003] Such as Figure 1 a topological structure of a drain switch charge pump shown, which attempts to solve the charge sharing problem. Figure 2 is a topological structure of a source switch charge pump, which increases the output resistance of the current source and attempts to solve the mismatch between PMOS and NMOS current sources. There are also other topological structures for the charge pump circuit. In addition to the single-ended structure, there is also a fully differential charge pump circuit to achieve the best current matching. In summary, the topological structures of the charge pump are all to improve the working performance of the charge pump and achieve a high-performance charge pump. However, since the charge pump circuit is widely used, if only focusing on the performance improvement and not paying attention to the adaptability and reliability of the charge pump circuit, its application scope will be limited.

[0004] Figure 3 shows the circuit situation of a high-performance charge pump circuit applied in a phase-locked loop. During the loop locking process of the phase-locked loop, the charge pump will continuously work in the charging and discharging states until the loop is locked. Figure 3 The high-performance charge pump of Figure 2 adopts the source switch charge pump structure shown. When the input up of the charge pump is high and DN is low, the charge pump works in the charging state at this time. When the charge pump continuously works in the charging state, the output voltage of the charge pump will be charged to a high level. When the output voltage of the charge pump approaches the power supply voltage, in Figure 2 , due to the feedback effect of the operational amplifier, the drain voltage of M3 will also be at a high level, then the gate voltage of M4 will be at a low level so that the M4 transistor is turned off. After that, even if the input UP of the charge pump is low and DN is high, in the discharging state, due to the turn-off of the current source M4 transistor, the charge pump cannot form a discharging path, and the voltage at the output end will maintain a high level, presenting a "deadlock" state. This situation brings limitations to the application of the high-performance charge pump circuit. Summary of the Invention

[0005] In view of the above defects, an embodiment of the present invention discloses a deadlock prevention charge pump circuit, which helps the charge pump circuit to perform automatic detection and comparison to prevent deadlock.

[0006] In the first aspect of the embodiments of the present invention, a deadlock prevention charge pump circuit is disclosed, including: a source switch charge pump circuit and a hysteresis comparator. The source switch charge pump circuit includes an operational amplifier and a current source transistor M4. The hysteresis comparator is connected to the output terminal of the source switch charge pump circuit and the operational amplifier. The hysteresis comparator is configured to collect the output terminal voltage of the source switch charge pump circuit when the source switch charge pump circuit is in a deadlock state, compare the output terminal voltage with a preset reference voltage, and when the output terminal voltage is greater than the reference voltage, output a control voltage to control the operational amplifier to stop working and turn on the current source transistor M4.

[0007] As an optional implementation manner, in the first aspect of the embodiments of the present invention, the source switch charge pump circuit further includes a charge and discharge module, a charge and discharge control module, and a control switch SW5. The charge and discharge module is configured to connect to a power supply voltage VDD. The charge and discharge control module is connected to the charge and discharge module, the hysteresis comparator, and the operational amplifier. The charge and discharge module is connected to the hysteresis comparator and the operational amplifier. One end of the control switch SW5 is connected to the operational amplifier, and the other end is respectively connected to the charge and discharge control module and the charge and discharge module.

[0008] As an optional implementation manner, in the first aspect of the embodiments of the present invention, the charge and discharge module includes a current mirror transistor M0, a current source transistor M1, and a current source transistor M3. The source electrodes of the current mirror transistor M0 and the current source transistor M1 are both connected to the power supply voltage VDD. The gate electrodes of the current mirror transistor M0 and the current source transistor M1 are connected. The drain electrodes of the current mirror transistor M0 and the current source transistor M1 are respectively connected to one end of the control switch SW5, the non-inverting input terminal of the operational amplifier, and the drain electrode of the current source transistor M3. The source electrode of the current source transistor M3 is grounded. The gate electrode of the current source transistor M3, the other end of the control switch SW5, and the output terminal of the operational amplifier are all connected to the charge and discharge control module.

[0009] As an optional implementation manner, in the first aspect of the embodiments of the present invention, the charge and discharge module further includes a normally closed switch SW0, a normally closed switch SW1, and a normally closed switch SW2. The source electrode of the current mirror transistor M0 is connected to the power supply voltage VDD through the normally closed switch SW0. The source electrode of the current source transistor M1 is connected to the power supply voltage VDD through the normally closed switch SW1. The source electrode of the current source transistor M3 is grounded through the normally closed switch SW2.

[0010] As an alternative embodiment, in the first aspect of the embodiments of the present invention, the charge and discharge control module includes a current source transistor M2 and a control switch SW3. The source of the current source transistor M2 is connected to the power supply voltage VDD through the control switch SW3. The drain of the current source transistor M2 serves as the output terminal of the source switch charge pump circuit and is respectively connected to the inverting input terminal of the operational amplifier, the hysteresis comparator, and the drain of the current source transistor M4. The gate of the current source transistor M2 is connected to the drain of the current mirror transistor M0.

[0011] As an alternative embodiment, in the first aspect of the embodiments of the present invention, the charge and discharge control module further includes a control switch SW4 and the current source transistor M4. The source of the current source transistor M4 is grounded through the control switch SW4, and the gate of the current source transistor M4 is respectively connected to the output terminal of the operational amplifier and the other end of the control switch SW5.

[0012] As an alternative embodiment, in the first aspect of the embodiments of the present invention, the positive input terminal of the hysteresis comparator is connected to the output terminal of the source switch charge pump circuit, the negative input terminal of the hysteresis comparator is connected to the reference voltage, and the output terminal of the hysteresis comparator is connected to the operational amplifier.

[0013] As an alternative embodiment, in the first aspect of the embodiments of the present invention, the hysteresis comparator includes MOS transistors M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, and M16. The gate of MOS transistor M5 is connected to the gate of MOS transistor M6, and the gate of MOS transistor M7 is connected to the gate of MOS transistor M8. The sources of MOS transistors M5, M6, M7, M8, M11, the drain of M14, and the source of M15 are all connected to the power supply voltage VDD. The drains of MOS transistors M5, M6, M7, and M8 are respectively connected to the drains of MOS transistors M9 and M10. The sources of MOS transistors M9 and M10 are both connected to the drain of MOS transistor M13. The source of MOS transistor M13 is grounded, and the gate of MOS transistor M13 is connected to the gate of MOS transistor M14. The drain of MOS transistor M11 is connected to the drain of MOS transistor M12. The gate of MOS transistor M11 is connected to the gate of MOS transistor M5. The gate of MOS transistor M12 is connected to the gate of MOS transistor M16. The sources of MOS transistors M12, the drain of M16, and the drain of M14 are all grounded. The drain of MOS transistor M16 is connected to the drain of MOS transistor M15. The gate of MOS transistor M15 is connected to the gate of MOS transistor M8. The gate of MOS transistor M9 is connected to a reference voltage. The gate of MOS transistor M10 is connected to the output of the source-switching charge pump circuit. An operational amplifier is also connected between the drains of MOS transistors M15 and M16.

[0014] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0015] In the embodiments of the present invention, a source-switching charge pump is adopted, which can improve the circuit working speed, reduce the static loss, avoid the channel charge injection of the switch, and reduce the influence of charge sharing. In the source-switching charge pump circuit of the embodiment, an operational amplifier is used to increase the impedance and reduce the current mismatch, so as to realize a high-performance charge pump. In addition, a hysteresis comparator is added in the embodiment, which can realize automatic detection, comparison, and calibration. When the voltage at the output end of the charge pump circuit deviates to the expected range, the working mode of the circuit is adaptively changed to avoid being locked at the power supply voltage, thereby avoiding logic errors, improving the reliability of the circuit, and expanding the adaptability of the circuit. Description of the Drawings

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0017] Figure 1 is the topological circuit diagram of a drain-switching charge pump of the prior art;

[0018] Figure 2 is the topological circuit diagram of a source-switching charge pump of the prior art;

[0019] Figure 3 is the circuit diagram of a phase-locked loop with a charge pump of the prior art;

[0020] Figure 4 is the schematic diagram of the circuit structure of a deadlock prevention charge pump circuit provided by an embodiment of the present invention;

[0021] Figure 5 is the schematic diagram of the circuit structure of a hysteresis comparator provided by an embodiment of the present invention. Detailed implementation manners

[0022] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0023] It should be noted that the terms "first", "second", "third", "fourth", etc. in the specification and claims of the present invention are used to distinguish different objects, rather than to describe a specific order. The terms "include" and "have" in the embodiments of the present invention and any variations thereof are intended to cover non-exclusive inclusion. Exemplarily, a process, method, system, product, or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0024] An embodiment of the present invention discloses a deadlock prevention charge pump circuit. In the embodiment, a source switch charge pump is adopted, which can improve the circuit operating speed, reduce static power loss, avoid channel charge injection of the switch, and reduce the influence of charge sharing. In the source switch charge pump circuit of the embodiment, an operational amplifier is used to increase the impedance and reduce current mismatch, so as to implement a high-performance charge pump. Moreover, a hysteresis comparator is added in the embodiment, which can realize automatic detection, comparison and calibration. When the voltage at the output end of the charge pump circuit deviates to the expected range, the working mode of the circuit is adaptively changed to avoid being locked at the power supply voltage, thereby avoiding logic errors, improving the reliability of the circuit, and expanding the adaptability of the circuit.

[0025] Embodiment 1

[0026] Please refer to Figure 4 , Figure 4 which is a schematic diagram of the circuit structure of a deadlock prevention charge pump circuit disclosed in an embodiment of the present invention. As Figure 4 shown, the deadlock prevention charge pump circuit includes a source switch charge pump circuit and a hysteresis comparator CMP. The source switch charge pump circuit includes an operational amplifier OP and a current source transistor M4. The hysteresis comparator is connected to the output end of the source switch charge pump circuit and the operational amplifier OP. The hysteresis comparator CMP is used to collect the output voltage of the source switch charge pump circuit when the source switch charge pump circuit is in a deadlock state, compare the output voltage with a preset reference voltage, and when the output voltage is greater than the reference voltage, output a control voltage to control the operational amplifier OP to stop working and turn on the current source transistor M4.

[0027] The embodiment introduces detection, comparison and calibration functions into the circuit, which are realized by the hysteresis comparator CMP. A hysteresis comparator with an internal positive feedback structure is selected. The threshold voltage of the hysteresis comparator can be designed according to actual use. It has a higher noise tolerance and avoids being caused by noise voltage and PVT (temperature) fluctuations. The calibration function changes its own working state through the output voltage of the hysteresis comparator. When the charge pump is in a deadlock state, the source switch charge pump circuit detects the voltage at its own output end to judge whether it is within the expected range. If the output point voltage is within the expected range, it means that it is in a normal working state. Then, the output voltage is compared with the reference voltage of the hysteresis comparator, and a control voltage is returned to its own core module. At this time, the control voltage does not affect the working state of the charge pump. If the output voltage of the charge pump deviates from the expected range and even approaches the power supply voltage, it represents a deadlock state. At this time, the hysteresis comparator compares the output voltage of the charge pump with the reference voltage and returns a control voltage to change the working state of the charge pump, avoiding the current source transistor M4 working in the cut-off state and preventing the charge pump from deadlocking.

[0028] The embodiment aims to solve the deadlock problem that traditional charge pumps may encounter under specific conditions, that is, the output voltage of the charge pump cannot rise or fall further, resulting in limited or ineffective circuit functions. By integrating a source-switching charge pump circuit with a hysteresis comparator, the circuit can automatically take corrective measures when detecting the deadlock state and restore the normal operation of the charge pump.

[0029] Among them, the source-switching charge pump circuit further includes a charge and discharge module, a charge and discharge control module, and a control switch SW5. The charge and discharge module is used to connect to the power supply voltage VDD. The charge and discharge control module is connected to the charge and discharge module, the hysteresis comparator, and the operational amplifier. The charge and discharge module is connected to the hysteresis comparator and the operational amplifier. One end of the control switch SW5 is connected to the operational amplifier, and the other end is respectively connected to the charge and discharge control module and the charge and discharge module.

[0030] The operational amplifier OP serves as the core control element and is responsible for adjusting the output voltage according to the input signal. The current source transistor M4 in the charge pump circuit is used to provide a stable current source to drive charge transfer. By adjusting the output of the operational amplifier, the switching state of the current source transistor M4 is controlled, thereby realizing the regulation of the output voltage of the charge pump. The hysteresis comparator sets two threshold voltages, including an upper threshold and a lower threshold, such that the output of the comparator changes state when the input voltage crosses these two thresholds, but the transition points are different, forming a hysteresis effect. In the embodiment, the hysteresis comparator is used to monitor the output voltage of the source-switching charge pump circuit. When the output voltage reaches or exceeds the preset upper threshold (i.e., the reference voltage), it indicates that the charge pump may have entered the deadlock state. When the charge pump is operating normally and the output voltage fluctuates within the preset range, the hysteresis comparator does not trigger any action, and the charge pump circuit continues to operate in the established manner. Once the charge pump enters the deadlock state, the output voltage no longer changes with the input signal or the control signal and gradually rises above the preset reference voltage. After the hysteresis comparator detects this change, it outputs a control voltage, which acts on the operational amplifier or other control elements in the circuit, causing the operational amplifier to stop working and simultaneously turning on the current source transistor M4.

[0031] Furthermore, the charge and discharge module includes a current mirror transistor M0, a current source transistor M1, and a current source transistor M3. The source electrodes of the current mirror transistor M0 and the current source transistor M1 are both connected to the power supply voltage VDD. The gate electrodes of the current mirror transistor M0 and the current source transistor M1 are connected. The drain electrodes of the current mirror transistor M0 and the current source transistor M1 are respectively connected to one end of the control switch SW5, the non-inverting input terminal of the operational amplifier OP, and the drain electrode of the current source transistor M3. The source electrode of the current source transistor M3 is grounded. The gate electrode of the current source transistor M3, the other end of the control switch SW5, and the output terminal of the operational amplifier OP are all connected to the charge and discharge control module.

[0032] The gate of the current mirror transistor M0 is connected to the gate of the current source transistor M1 to form a current mirror structure, such that the currents of M0 and M1 maintain a certain ratio. And similar to the current mirror transistor M0, the source of the current source transistor M1 is also connected to the power supply voltage VDD, and its gate is connected to the gate of M0 to ensure that the currents of the two are equal or in proportion. The source of the current source transistor M3 is grounded to form a return path for the current.

[0033] Further, the charge and discharge module further includes a normally closed switch SW0, a normally closed switch SW1, and a normally closed switch SW2. The source of the current mirror transistor M0 is connected to the power supply voltage VDD through the normally closed switch SW0, the source of the current source transistor M1 is connected to the power supply voltage VDD through the normally closed switch SW1, and the source of the current source transistor M3 is grounded through the normally closed switch SW2.

[0034] Under normal circumstances, SW0 is closed, enabling the source of M0 to be stably connected to the power supply voltage VDD, thereby ensuring that M0 can operate normally. If it is necessary to disconnect the connection between M0 and VDD (for example, during fault detection, maintenance, or component replacement), it can be achieved by controlling SW0. Similar to SW0, SW1 is also normally closed, ensuring that the source of M1 can be stably connected to the power supply voltage VDD. This enables M1 to operate stably under normal circumstances and provide the required current. When needed, SW1 can be opened to disconnect the connection between M1 and VDD. SW2 connects the source of M3 to the ground, which is the basis for M3 to act as a current source or a current sink. Since SW2 is normally closed, it ensures that the current path of M3 is complete during normal operation. If it is necessary to change the grounding state of M3 (which may be relatively rare in practical applications), it can be achieved by controlling SW2. Among the above three normally closed switches, SW0, SW1, and SW2 mainly play the roles of connection protection and ensuring circuit stability, providing redundancy and flexibility for the circuit, but do not need to be frequently operated under normal circumstances. In the practical application of the charge and discharge module, the charge and discharge process is usually controlled by adjusting the gate voltage of the current source transistor M3, controlling the switching state of the switch SW5, and the output signal of the operational amplifier. The normally closed switches SW0, SW1, and SW2 remain closed during these operations to ensure that the basic connections of the circuit remain unchanged.

[0035] The charge and discharge control module realizes the precise control of the charge and discharge process of the charge pump circuit by precisely controlling the operating state of the current source M2, and by monitoring and adjusting the output voltage using the operational amplifier OP and the hysteresis comparator CMP. The current mirror transistor M2 acts as a controllable current source and adjusts the current magnitude from its source to drain according to the gate voltage. Its source is connected to VDD through the control switch SW3, that is, the control switch SW3 can control the on / off of this connection, thereby controlling whether the current mirror transistor M2 starts to work.

[0036] The charge and discharge control module further includes a control switch SW4 and the current source transistor M4. The source of the current source transistor M4 is grounded through the control switch SW4. The gate of the current source transistor M4 is connected to the output terminal of the operational amplifier OP and the other end of the control switch SW5 respectively. Among them, the control switch SW4 controls whether the source of the current source transistor M4 is grounded. By controlling the on / off of SW4, the working state of M4 can be adjusted, thereby affecting the output characteristics of the entire charge and discharge control module. One end of it is connected to the source of the current source transistor M4, and the other end is grounded. When SW4 is closed, the source of M4 is grounded and M4 starts to work; when SW4 is opened, the source of M4 is disconnected from the ground and M4 stops working. The current source transistor M4, as another controllable current source, works in cooperation with the current source transistor M2 to jointly control the magnitude and direction of the current in the charge and discharge process. The gate of M4 is connected to the output terminal of the operational amplifier OP and the other end of the control switch SW5 respectively, so that the gate voltage of M4 is jointly affected by the output signal of the operational amplifier OP and the state of the control switch SW5. The output signal of the operational amplifier may be used to adjust the gate voltage of M4, thereby controlling the magnitude of the current of M4; while the state of SW5 can be used to change the working mode of M4 or turn off M4 under specific conditions.

[0037] The core of the embodiment is to add a hysteresis comparator CMP to realize the detection, comparison and calibration of the circuit. The introduction of the hysteresis comparator provides an important stability control function for the circuit. The positive input terminal of the hysteresis comparator CMP is connected to the output terminal of the source switch charge pump circuit, the negative input terminal of the hysteresis comparator CMP is connected to the reference voltage, and the output terminal of the hysteresis comparator CMP is connected to the operational amplifier. The hysteresis comparator has two different threshold voltages: one for rising edge triggering (i.e., when the input voltage changes from low to high), and the other for falling edge triggering (i.e., when the input voltage changes from high to low), which helps to prevent the circuit from frequently switching states due to noise or small voltage fluctuations near the threshold. The hysteresis comparator is connected to the output terminal of the source switch charge pump circuit to monitor the output voltage of the charge pump circuit and generate an output signal according to the comparison result between this voltage and the reference voltage. The reference voltage is a fixed reference voltage used to compare with the output voltage of the charge pump circuit.

[0038] The hysteresis comparator CMP includes MOS transistors M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, and M16. The gates of MOS transistors M5 and M6 are connected, and the gates of MOS transistors M7 and M8 are connected. The sources of MOS transistors M5, M6, M7, M8, M11, the drain of MOS transistor M14, and the source of MOS transistor M15 are all connected to the power supply voltage VDD. The drains of MOS transistors M5, M6, M7, and M8 are respectively connected to the drains of MOS transistors M9 and M10. The sources of MOS transistors M9 and M10 are both connected to the drain of MOS transistor M13. The source of MOS transistor M13 is grounded, and the gate of MOS transistor M13 is connected to the gate of MOS transistor M14. The drain of MOS transistor M11 is connected to the drain of MOS transistor M12. The gate of MOS transistor M11 is connected to the gate of MOS transistor M5. The gate of MOS transistor M12 is connected to the gate of MOS transistor M16. The sources of MOS transistor M12, the drain of MOS transistor M16, and the drain of MOS transistor M14 are all grounded. The drain of MOS transistor M16 is connected to the drain of MOS transistor M15. The gate of MOS transistor M15 is connected to the gate of MOS transistor M8. The gate of MOS transistor M9 is connected to a reference voltage. The gate of MOS transistor M10 is connected to the output of the source switch charge pump circuit. An operational amplifier is also connected between the drains of MOS transistors M15 and M16.

[0039] The hysteresis comparator CMP of the embodiment generates a hysteresis response through the switching characteristics of MOS transistors and a positive feedback mechanism. Among them, MOS transistors M5 and M6 serve as a differential pair input stage. Their gates are connected and receive an input signal, and their sources are connected to the power supply voltage VDD. MOS transistors M7 and M8 are used for biasing or reference voltage generation. MOS transistors M9 and M10 form a cross-coupled pair. Their drains are connected to each other and to the drains of M5 and M6, enabling M9 and M10 to enhance positive feedback with each other, thereby generating a hysteresis effect. In the figure, vo is the output terminal of the hysteresis comparator, which is respectively connected to the vctr terminal of the switch and the control terminal of the operational amplifier. vi1 and vi2 both serve as input terminals of the hysteresis comparator. vi1 is connected to the reference voltage vref, and vi2 is connected to the output of the charge pump.

[0040] In the embodiment, normally-closed switches corresponding to the sources of M2 and M4 are used, and the current mirror matching is better. An operational amplifier is used to increase the output impedance and reduce the current mismatch, thereby implementing a high-performance charge pump. On this basis, detection, comparison, and calibration functions are added. When the voltage at the output end of the charge pump deviates from the expected range, the working mode of the circuit is adaptively changed, and it will not be locked at the power supply voltage, thus avoiding logical errors, improving the reliability of the circuit, and expanding the adaptability of the circuit.

[0041] The embodiment consists of normally-closed switches SW0, SW1, SW2, a switch SW3 controlled by the UP terminal, a switch SW4 controlled by the DN terminal, a switch SW5 controlled by the vctr terminal, a current mirror transistor M0, current source transistors M1, M2, M3, M4, a hysteresis comparator CMP, and an operational amplifier OP. When the voltage at the output end out of the charge pump deviates from the expected voltage range or is at a relatively high voltage value, such as close to the power supply voltage VDD, the charge pump is in a "deadlock" state at this time. Then, the hysteresis comparator CMP will detect the voltage at the output end out and compare it with the reference voltage vref. The value of the reference voltage vref is designed according to the expected output voltage range of the charge pump. When the out voltage is greater than the vref voltage, a voltage named vctr will be output. This voltage makes the operational amplifier OP not work and makes the controlled switch sw5 conduct. Thus, the vp terminal and the vg terminal are connected, and M3 also becomes a diode-connected MOS transistor. M3 will bias the gate voltage of M4, and M0 to 4 become a simple current mirror circuit, avoiding the cut-off of the current source transistor M4. When the voltages of the input terminals UP and DN are switched such that UP is at a low level and DN is at a high level, M4 can complete the discharging function and pull down the voltage at the output end out. Finally, the charge pump circuit realizes the self-calibration function and gets itself out of the "deadlock" state. When the voltage at the output end out is within the expected range, the operational amplifier OP works normally, and the control voltage vctr output by the hysteresis comparator CMP makes the switch SW5 open and not connected to the circuit. At this time, the charge pump also works normally in the charging, discharging, and neither charging nor discharging states according to the values of the input terminals UP and DN.

[0042] Embodiment 2

[0043] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of a hysteresis comparator disclosed in an embodiment of the present invention. As Figure 5As shown, the hysteresis comparator circuit may include: MOS transistors M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, and M16. The gate of MOS transistor M5 is connected to the gate of MOS transistor M6, and the gate of MOS transistor M7 is connected to the gate of MOS transistor M8. The sources of MOS transistors M5, M6, M7, M8, M11, the drain of MOS transistor M14, and the source of MOS transistor M15 are all connected to the power supply voltage VDD. The drains of MOS transistors M5, M6, M7, and M8 are respectively connected to the drains of MOS transistors M9 and M10. The sources of MOS transistors M9 and M10 are both connected to the drain of MOS transistor M13. The source of MOS transistor M13 is grounded, and the gate of MOS transistor M13 is connected to the gate of MOS transistor M14. The drain of MOS transistor M11 is connected to the drain of MOS transistor M12. The gate of MOS transistor M11 is connected to the gate of MOS transistor M5. The gate of MOS transistor M12 is connected to the gate of MOS transistor M16. The sources of MOS transistors M12, the drain of MOS transistor M16, and the drain of MOS transistor M14 are all grounded. The drain of MOS transistor M16 is connected to the drain of MOS transistor M15. The gate of MOS transistor M15 is connected to the gate of MOS transistor M8. The gate of MOS transistor M9 is connected to a reference voltage. The gate of MOS transistor M10 is connected to the output terminal of the source switch charge pump circuit. An operational amplifier is also connected between the drains of MOS transistors M15 and M16.

[0044] In various embodiments of the present invention, it should be understood that the magnitudes of the sequence numbers of the various processes do not necessarily imply the order of execution. The order of execution of the various processes should be determined according to their functions and internal logics, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0045] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0046] In addition, in each embodiment of the present invention, the various functional units may be integrated in one processing unit, or each unit may exist physically separately, or two or more units may be integrated in one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0047] In the embodiments provided by the present invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0048] The above has introduced in detail the XX method, device, electronic device and storage medium disclosed in the embodiments of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. An anti-deadlock charge pump circuit, characterized in that: The invention comprises a source switch charge pump circuit and a hysteresis comparator, wherein the source switch charge pump circuit comprises an operational amplifier and a current source tube M4, wherein the hysteresis comparator is connected to the output end of the source switch charge pump circuit and the operational amplifier, wherein the hysteresis comparator is used to collect the output end voltage of the source switch charge pump circuit when the source switch charge pump circuit is in a deadlock state, and compare the output end voltage with a preset reference voltage, and when the output end voltage is greater than the reference voltage, output a control voltage to control the operational amplifier to stop working and turn on the current source tube M4; the source switch charge pump circuit also comprises a charge and discharge module, a charge and discharge control module and a control switch SW5, wherein the charge and discharge module is used to access a power supply voltage VDD, wherein the charge and discharge control module is connected to the charge and discharge module, the hysteresis comparator and the operational amplifier, wherein the charge and discharge module is connected to the hysteresis comparator and the operational amplifier, wherein one end of the control switch SW5 is connected to the operational amplifier, The other end is respectively connected to the charge and discharge control module and the charge and discharge module; the charge and discharge module includes a current mirror tube M0, a current source tube M1, a current source tube M3, a normally closed switch SW0, a normally closed switch SW1 and a normally closed switch SW2, the source of the current mirror tube M0 and the source of the current source tube M1 are both connected to the power supply voltage VDD, the gate of the current mirror tube M0 and the gate of the current source tube M1 are connected, the drain of the current mirror tube M0 and the drain of the current source tube M1 are respectively connected to one end of the control switch SW5, the in-phase input end of the operational amplifier and the drain of the current source tube M3, the source of the current source tube M3 is grounded, the gate of the current source tube M3, the other end of the control switch SW5 and the output end of the operational amplifier are all connected to the charge and discharge control module; the source of the current mirror tube M0 is connected to the power supply voltage VDD through the normally closed switch SW0, the source of the current source tube M1 is connected to the power supply voltage VDD through the normally closed switch SW1, and the source of the current source tube M3 is grounded through the normally closed switch SW2.

2. The anti-deadlock charge pump circuit according to claim 1, characterized in that: The charge and discharge control module includes a current source tube M2 and a control switch SW3. The source of the current source tube M2 is connected to the power supply voltage VDD through the control switch SW3. The drain of the current source tube M2 is connected to the inverting input terminal of the operational amplifier, the hysteresis comparator and the drain of the current source tube M4 as the output end of the source switch charge pump circuit. The gate of the current source tube M2 is connected to the drain of the current mirror tube M0.

3. The anti-deadlock charge pump circuit according to claim 2, characterized in that: The charge and discharge control module further includes a control switch SW4 and the current source tube M4. The source of the current source tube M4 is grounded through the control switch SW4. The gate of the current source tube M4 is connected to the output end of the operational amplifier and the other end of the control switch SW5.

4. The anti-deadlock charge pump circuit according to claim 1, characterized in that: The positive input terminal of the hysteresis comparator is connected to the output terminal of the source switch charge pump circuit, the negative input terminal of the hysteresis comparator is connected to the reference voltage, and the output terminal of the hysteresis comparator is connected to the operational amplifier.

5. The anti-deadlock charge pump circuit according to claim 4, characterized in that: The hysteresis comparator includes MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15 and MOS tube M16. The gate of the MOS tube M5 is connected to the gate of the MOS tube M6, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8. The source of the MOS tube M5, the source of the MOS tube M6, the source of the MOS tube M7, the source of the MOS tube M8, the source of the MOS tube M11, the drain of the MOS tube M14 and the source of the MOS tube M15 are all connected to the power supply voltage VDD. The drain of the MOS tube M5, the drain of the MOS tube M6, the drain of the MOS tube M7 and the drain of the MOS tube M8 are all connected to the drain of the MOS tube M9 and the drain of the MOS tube M10 respectively. The source of the MOS tube M9 and the source of the MOS tube are both connected to the drain of the MOS tube M13, the source of the MOS tube M13 is grounded, the gate of the MOS tube M13 is connected to the gate of the MOS tube M14, the drain of the MOS tube M11 is connected to the drain of the MOS tube M12, the gate of the MOS tube M11 is connected to the gate of the MOS tube M5, the gate of the MOS tube M12 is connected to the gate of the MOS tube M16, the source of the MOS tube M12, the drain of the MOS tube M16 and the drain of the MOS tube M14 are all grounded, the drain of the MOS tube M16 is connected to the drain of the MOS tube M15, the gate of the MOS tube M15 is connected to the gate of the MOS tube M8, the gate of the MOS tube M9 is connected to the reference voltage, the gate of the MOS tube M10 is connected to the output end of the source switch charge pump circuit, and the drain of the MOS tube M15 and the drain of the MOS tube M16 are also connected to an operational amplifier.

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