A CMOS ultra-wideband low noise amplifier based on noise cancellation structure

Abstract

The present invention discloses a CMOS ultra-wideband low-noise amplifier based on a noise cancellation structure, which belongs to the technical field of radio frequency integrated circuits, and includes an input impedance matching circuit, a noise cancellation common-gate common-source amplifier circuit, a common-source common-gate amplifier circuit and an output matching circuit, wherein the input impedance matching circuit includes a radio frequency signal input terminal and a first node N1 for inputting a radio frequency signal, and the output matching circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, wherein the first transistor M1 is electrically connected to the second node N2 and the third node N3, respectively, the second transistor M2 is electrically connected to the second node N2 and the third node N3, respectively, and the third transistor M3 is electrically connected to the second node N2 and the third node N3, respectively. The present invention can simultaneously achieve good input impedance matching and good noise performance.

Description

Technical Field

[0001] The invention relates to the technical field of radio frequency integrated circuits, and in particular to a CMOS ultra-wideband low noise amplifier based on a noise cancellation structure. Background Art

[0002] Phased array radars have solved many inherent problems of traditional radars with their faster response rate, higher resolution accuracy, and better anti-interference capabilities. Active phased arrays have become a research hotspot in the industry due to their advantages in efficiency, power, and performance. Compared with other semiconductor processes, silicon-based CMOS processes can achieve lower manufacturing costs and higher integration, so the semiconductor industry has continued to conduct in-depth research on the application of CMOS in RF integrated circuits, which provides new opportunities for achieving high integration and reduced size of active phased array RF front ends.

[0003] With the rapid advancement of social informatization, wireless communication has developed rapidly due to its high reliability in complex communication environments and the low cost of not having to maintain and upgrade wired communication networks, bringing great convenience to human life. With the further development of wireless communication, people have put forward higher requirements for data communication speed and data communication capacity, and thus, ultra-wideband wireless communication has been widely used.

[0004] Ultra-wideband wireless communication meets the needs of communication speed and communication capacity, and requires the transceiver system to always be able to achieve good performance indicators within a wide high-frequency band, which brings challenges to the design of RF front-end circuits. The low-noise amplifier is the first-level active module of the receiver link, mainly used to amplify useful RF signals and suppress useless noise signals. With the development of technology, the low-noise amplifier is required to achieve better port impedance matching, sufficiently high and flat gain, excellent low-noise performance and low power consumption.

[0005] A Chinese patent document with publication number CN117978100A and publication date May 3, 2024 discloses an ultra-wideband high-gain flatness high-linearity low-noise amplifier, including a radio frequency input module, a noise cancellation module, a current multiplexing module, a gain tuning module, and a radio frequency output module, characterized in that: the gain tuning module is arranged between the noise cancellation module and the radio frequency input module; the noise cancellation module is arranged between the radio frequency output module and the radio frequency input module, and between the gain tuning module and the radio frequency output module; the first transistor M1 in the radio frequency input module and the second transistor M2 in the noise cancellation module constitute a current multiplexing module; wherein:

[0006] The radio frequency input module realizes signal input and ultra-wideband input matching;

[0007] The gain tuning module realizes high gain flatness within an ultra-wide band;

[0008] The noise cancellation module realizes the reduction of the circuit noise coefficient;

[0009] The current multiplexing module realizes the reduction of circuit power consumption;

[0010] The radio frequency output module realizes improved circuit isolation, ultra-wideband output matching and signal output.

[0011] The ultra-wideband high-gain flatness high-linearity low-noise amplifier disclosed in the patent document decouples the input matching of the common-gate transistor M1 from the noise coefficient through noise cancellation, and uses a current multiplexing module to save power consumption when the noise cancellation module is used. However, it is difficult to achieve good input impedance matching and good noise performance at the same time. Summary of the invention

[0012] In order to overcome the above-mentioned defects of the prior art, the present invention provides a CMOS ultra-wideband low noise amplifier based on a noise cancellation structure, which can achieve good input impedance matching and good noise performance at the same time.

[0013] The present invention is achieved through the following technical solutions:

[0014] A CMOS ultra-wideband low-noise amplifier based on a noise cancellation structure includes an input impedance matching circuit, a noise cancellation common-gate common-source amplifier circuit, a common-source common-gate amplifier circuit and an output matching circuit. The input impedance matching circuit includes a radio frequency signal input terminal and the first node N1, for inputting a radio frequency signal, the output matching circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, the first transistor M1 is electrically connected to the second node N2 and the third node N3 respectively, the second transistor M2 is electrically connected to the second node N2 and the third node N3 respectively, the third transistor M3 is electrically connected to the second node N2 and the third node N3 respectively, the noise elimination common-gate common-source amplifier circuit includes a first inter-stage matching module consisting of an electrically connected fourth transistor M4, a third inductor L3, a first transformer primary winding T1-1, a fifth transistor M5, a second transformer primary winding T1-2, a fourth inductor L4 and a first transformer secondary winding and a first transformer third winding T1-3, the The common-source common-gate amplifier circuit is electrically connected to the first inter-stage matching module, and the common-source common-gate amplifier circuit adopts a dual-branch matching network topology structure, including a sixth transistor M6, a seventh transistor M7, a second resistor R2, a third resistor R3 and a sixth inductor L6, a first end of the second resistor R2 is electrically connected to the seventh node N7, a second end of the second resistor R2 is connected to the second fixed voltage signal terminal VDD2, a first end of the third resistor R3 is electrically connected to the tenth node N10, a second end of the third resistor R3 is electrically connected to the sixth node N6, a first end of the sixth inductor L6 is connected to the gate of the sixth transistor M6, a second end of the sixth inductor L6 is electrically connected to the seventh node N7, and a drain of the sixth transistor M6 is connected to the RF signal output terminal , used to output the RF signal after noise processing.

[0015] The input impedance matching circuit further includes a first capacitor C1 and a first inductor L1, wherein a first end of the first inductor L1 is electrically connected to a first node N1, a second end of the first inductor L1 is electrically connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is electrically connected to a RF signal input terminal. Electrical connection.

[0016] The source terminal of the first transistor M1 is electrically connected to the second node N2 , the drain terminal of the first transistor M1 is electrically connected to the third node N3 , and the gate terminal of the first transistor M1 is connected to the first fixed voltage signal terminal VDD1 .

[0017] The gate terminal of the second transistor M2 is electrically connected to the second node N2, the source terminal of the second transistor M2 is connected to the second fixed voltage signal terminal VDD2, and the drain terminal of the second transistor M2 is electrically connected to the third node N3.

[0018] The gate terminal of the third transistor M3 is electrically connected to the second node N2, the drain terminal of the third transistor M3 is electrically connected to the third node N3, and the source terminal of the third transistor M3 is connected to the ground terminal GND.

[0019] The noise elimination common-gate common-source amplifier circuit also includes a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the source end of the fourth transistor M4, a second end of the second capacitor C2 is electrically connected to the first node N1, a gate of the fourth transistor M4 is connected to the bias signal end VB2, a drain of the fourth transistor M4 is electrically connected to the first end of the primary winding T1-1 of the first transformer, a second end of the primary winding T1-1 of the first transformer is electrically connected to the third fixed voltage signal end VDD3, and a source of the fourth transistor M4 is electrically connected to the fourth node N4.

[0020] The source of the fourth transistor M4 includes a third inductor L3 , a first end of the third inductor L3 is electrically connected to the fourth node N4 , and a second end of the third inductor L3 is connected to the ground GND.

[0021] The noise-cancelling common-gate common-source amplifier circuit also includes a second inductor L2, a first end of the second inductor L2 is electrically connected to the gate end of the fifth transistor M5, a second end of the second inductor L2 is electrically connected to the third node N3, a drain of the fifth transistor M5 is electrically connected to the first end of the second transformer primary winding T1-2, and a second end of the second transformer primary winding T1-2 is electrically connected to the fourth fixed voltage signal end VDD4.

[0022] The first inter-stage matching module also includes a third capacitor C3, a first end of the third capacitor C3 is electrically connected to the fifth node N5, a first end of the third capacitor C3 is connected to the bias voltage signal terminal VB1, a second end of the third capacitor C3 is electrically connected to the first end of the third winding T1-3 of the first transformer, and a second end of the third winding T1-3 of the first transformer is electrically connected to the fifth node N5.

[0023] The common-source common-gate amplifier circuit also includes a seventh inductor L7, an eighth inductor L8, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6, a first end of the seventh inductor L7 is electrically connected to a ninth node N9, a second end of the seventh inductor L7 is connected to a source of the sixth transistor M6, a first end of the eighth inductor L8 is connected to a gate of the seventh transistor M7, a second end of the eighth inductor L8 is electrically connected to the sixth node N6, a first end of the fourth capacitor C4 is electrically connected to a ninth node N9, a second end of the fourth capacitor C4 is electrically connected to a seventh node N7, a first end of the fifth capacitor C5 is electrically connected to a tenth node N10, a second end of the fifth capacitor C5 is electrically connected to a third resistor R3, a first end of the sixth capacitor C6 is electrically connected to a radio frequency signal output terminal The second end of the sixth capacitor C6 is electrically connected to the eighth node N8.

[0024] The output matching circuit further includes a fourth resistor R4 and a fifth inductor L5, wherein a first end of the fourth resistor R4 is electrically connected to the eighth node N8, a second end of the fourth resistor R4 is connected to a first end of the fifth inductor L5, and a second end of the fifth inductor L5 is connected to a sixth fixed voltage signal terminal VDD6.

[0025] The first inter-stage matching module further includes a fifth resistor R5 , a first end of the fifth resistor R5 is electrically connected to the fifth node N5 , and a second end of the fifth resistor R5 is connected to the bias voltage signal terminal VB1 .

[0026] The second capacitor C2 and the sixth capacitor C6 are both DC blocking capacitors.

[0027] The CMOS mentioned in the present invention refers to complementary metal oxide semiconductor.

[0028] The beneficial effects of the present invention are mainly manifested in the following aspects:

[0029] 1. Compared with the prior art, the present invention can achieve good input impedance matching and good noise performance at the same time.

[0030] 2. In the present invention, the first inter-stage matching module composed of the secondary winding of the first transformer and the tertiary winding T1-3 of the first transformer can achieve inter-stage matching. Compared with using an additional transformer for inter-stage matching, it can save layout area and introduce less noise.

[0031] 3. In the present invention, the common-source and common-gate amplifier circuit adopts a dual-branch matching network topology to form a second-order broadband bandpass filter. The input impedance of the second-stage matching network is designed to be determined by the parallel equivalent impedance of the low frequency and the high frequency, respectively, which increases the adjustability of the circuit and presents a good resistivity.

[0032] 4. Compared with the prior art, the present invention adopts the common-source and common-gate amplifier circuit with inter-stage inductance tuning and gate inductance feedback, which offsets the parasitic capacitance between the common-source and common-gate nodes, provides gain and reduces the noise of the circuit.

[0033] 5. In the present invention, the input impedance matching circuit also includes a first capacitor C1 and a first inductor L1, the first end of the first inductor L1 is electrically connected to the first node N1, the second end of the first inductor L1 is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is electrically connected to the RF signal input end, which can reduce the thermal noise introduced by the resistor.

[0034] 6. In the present invention, the second capacitor C2 and the sixth capacitor C6 are both DC blocking capacitors. The second capacitor C2 can block DC signals to prevent affecting the first transistor M1 and avoid changing the working state of the first transistor M1. The sixth capacitor C6 can achieve output matching while blocking the RF signal output terminal from outputting DC signals to prevent the DC signal from affecting the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementations, wherein:

[0036] Figure 1 It is a structural schematic diagram of the present invention;

[0037] Figure 2 This is a schematic diagram of the noise cancellation principle of the present invention;

[0038] Figure 3 This is a schematic diagram of input and output matching simulation of the present invention;

[0039] Figure 4 It is a gain simulation schematic diagram of the present invention;

[0040] Figure 5 A schematic diagram of noise coefficient comparison simulation of the present invention;

[0041] Figure 6 Schematic diagram of isolation simulation of the present invention. DETAILED DESCRIPTION

[0042] Example 1

[0043] See also Figure 1 and Figure 2 A CMOS ultra-wideband low-noise amplifier based on a noise cancellation structure includes an input impedance matching circuit, a noise cancellation common-gate common-source amplifier circuit, a common-source common-gate amplifier circuit and an output matching circuit. The input impedance matching circuit includes a radio frequency signal input terminal and the first node N1, for inputting a radio frequency signal, the output matching circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, the first transistor M1 is electrically connected to the second node N2 and the third node N3 respectively, the second transistor M2 is electrically connected to the second node N2 and the third node N3 respectively, the third transistor M3 is electrically connected to the second node N2 and the third node N3 respectively, the noise elimination common-gate common-source amplifier circuit includes a first inter-stage matching module consisting of an electrically connected fourth transistor M4, a third inductor L3, a first transformer primary winding T1-1, a fifth transistor M5, a second transformer primary winding T1-2, a fourth inductor L4 and a first transformer secondary winding and a first transformer third winding T1-3, the The common-source common-gate amplifier circuit is electrically connected to the first inter-stage matching module, and the common-source common-gate amplifier circuit adopts a dual-branch matching network topology structure, including a sixth transistor M6, a seventh transistor M7, a second resistor R2, a third resistor R3 and a sixth inductor L6, a first end of the second resistor R2 is electrically connected to the seventh node N7, a second end of the second resistor R2 is connected to the second fixed voltage signal terminal VDD2, a first end of the third resistor R3 is electrically connected to the tenth node N10, a second end of the third resistor R3 is electrically connected to the sixth node N6, a first end of the sixth inductor L6 is connected to the gate of the sixth transistor M6, a second end of the sixth inductor L6 is electrically connected to the seventh node N7, and a drain of the sixth transistor M6 is connected to the RF signal output terminal , used to output the RF signal after noise processing.

[0044] This embodiment is the most basic implementation method, and compared with the prior art, it can achieve good input impedance matching and good noise performance at the same time.

[0045] Example 2

[0046] See also Figure 1 and Figure 2 A CMOS ultra-wideband low-noise amplifier based on a noise cancellation structure includes an input impedance matching circuit, a noise cancellation common-gate common-source amplifier circuit, a common-source common-gate amplifier circuit and an output matching circuit. The input impedance matching circuit includes a radio frequency signal input terminal and the first node N1, for inputting a radio frequency signal, the output matching circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, the first transistor M1 is electrically connected to the second node N2 and the third node N3 respectively, the second transistor M2 is electrically connected to the second node N2 and the third node N3 respectively, the third transistor M3 is electrically connected to the second node N2 and the third node N3 respectively, the noise elimination common-gate common-source amplifier circuit includes a first inter-stage matching module consisting of an electrically connected fourth transistor M4, a third inductor L3, a first transformer primary winding T1-1, a fifth transistor M5, a second transformer primary winding T1-2, a fourth inductor L4 and a first transformer secondary winding and a first transformer third winding T1-3, the The common-source common-gate amplifier circuit is electrically connected to the first inter-stage matching module, and the common-source common-gate amplifier circuit adopts a dual-branch matching network topology structure, including a sixth transistor M6, a seventh transistor M7, a second resistor R2, a third resistor R3 and a sixth inductor L6, a first end of the second resistor R2 is electrically connected to the seventh node N7, a second end of the second resistor R2 is connected to the second fixed voltage signal terminal VDD2, a first end of the third resistor R3 is electrically connected to the tenth node N10, a second end of the third resistor R3 is electrically connected to the sixth node N6, a first end of the sixth inductor L6 is connected to the gate of the sixth transistor M6, a second end of the sixth inductor L6 is electrically connected to the seventh node N7, and a drain of the sixth transistor M6 is connected to the RF signal output terminal , used to output the RF signal after noise processing.

[0047] Preferably, the input impedance matching circuit further includes a first capacitor C1 and a first inductor L1, wherein the first end of the first inductor L1 is electrically connected to the first node N1, the second end of the first inductor L1 is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is electrically connected to the RF signal input terminal. Electrical connection.

[0048] The source terminal of the first transistor M1 is electrically connected to the second node N2 , the drain terminal of the first transistor M1 is electrically connected to the third node N3 , and the gate terminal of the first transistor M1 is connected to the first fixed voltage signal terminal VDD1 .

[0049] The gate terminal of the second transistor M2 is electrically connected to the second node N2, the source terminal of the second transistor M2 is connected to the second fixed voltage signal terminal VDD2, and the drain terminal of the second transistor M2 is electrically connected to the third node N3.

[0050] This embodiment is a preferred implementation method. The first inter-stage matching module composed of the secondary winding of the first transformer and the third winding T1-3 of the first transformer can achieve inter-stage matching. Compared with using additional transformers for inter-stage matching, it can save layout area and introduce less noise.

[0051] Example 3

[0052] See also Figure 1 and Figure 2 A CMOS ultra-wideband low-noise amplifier based on a noise cancellation structure includes an input impedance matching circuit, a noise cancellation common-gate common-source amplifier circuit, a common-source common-gate amplifier circuit and an output matching circuit. The input impedance matching circuit includes a radio frequency signal input terminal and the first node N1, for inputting a radio frequency signal, the output matching circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, the first transistor M1 is electrically connected to the second node N2 and the third node N3 respectively, the second transistor M2 is electrically connected to the second node N2 and the third node N3 respectively, the third transistor M3 is electrically connected to the second node N2 and the third node N3 respectively, the noise elimination common-gate common-source amplifier circuit includes a first inter-stage matching module consisting of an electrically connected fourth transistor M4, a third inductor L3, a first transformer primary winding T1-1, a fifth transistor M5, a second transformer primary winding T1-2, a fourth inductor L4 and a first transformer secondary winding and a first transformer third winding T1-3, the The common-source common-gate amplifier circuit is electrically connected to the first inter-stage matching module, and the common-source common-gate amplifier circuit adopts a dual-branch matching network topology structure, including a sixth transistor M6, a seventh transistor M7, a second resistor R2, a third resistor R3 and a sixth inductor L6, a first end of the second resistor R2 is electrically connected to the seventh node N7, a second end of the second resistor R2 is connected to the second fixed voltage signal terminal VDD2, a first end of the third resistor R3 is electrically connected to the tenth node N10, a second end of the third resistor R3 is electrically connected to the sixth node N6, a first end of the sixth inductor L6 is connected to the gate of the sixth transistor M6, a second end of the sixth inductor L6 is electrically connected to the seventh node N7, and a drain of the sixth transistor M6 is connected to the RF signal output terminal , used to output the RF signal after noise processing.

[0053] The input impedance matching circuit further includes a first capacitor C1 and a first inductor L1, wherein a first end of the first inductor L1 is electrically connected to a first node N1, a second end of the first inductor L1 is electrically connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is electrically connected to a RF signal input terminal. Electrical connection.

[0054] The source terminal of the first transistor M1 is electrically connected to the second node N2 , the drain terminal of the first transistor M1 is electrically connected to the third node N3 , and the gate terminal of the first transistor M1 is connected to the first fixed voltage signal terminal VDD1 .

[0055] The gate terminal of the second transistor M2 is electrically connected to the second node N2, the source terminal of the second transistor M2 is connected to the second fixed voltage signal terminal VDD2, and the drain terminal of the second transistor M2 is electrically connected to the third node N3.

[0056] The gate terminal of the third transistor M3 is electrically connected to the second node N2, the drain terminal of the third transistor M3 is electrically connected to the third node N3, and the source terminal of the third transistor M3 is connected to the ground terminal GND.

[0057] Further preferably, the noise elimination common-gate common-source amplifier circuit also includes a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the source end of the fourth transistor M4, a second end of the second capacitor C2 is electrically connected to the first node N1, a gate of the fourth transistor M4 is connected to the bias signal end VB2, a drain of the fourth transistor M4 is electrically connected to the first end of the primary winding T1-1 of the first transformer, a second end of the primary winding T1-1 of the first transformer is electrically connected to the third fixed voltage signal end VDD3, and a source of the fourth transistor M4 is electrically connected to the fourth node N4.

[0058] This embodiment is another preferred implementation method. The common-source and common-gate amplifier circuit adopts a dual-branch matching network topology to form a second-order broadband bandpass filter. The input impedance of the second-stage matching network is designed to be determined by the parallel equivalent impedance of the low frequency and high frequency, respectively, which increases the adjustability of the circuit and presents good resistivity.

[0059] Example 4

[0060] See also Figure 1 and Figure 2 A CMOS ultra-wideband low-noise amplifier based on a noise cancellation structure includes an input impedance matching circuit, a noise cancellation common-gate common-source amplifier circuit, a common-source common-gate amplifier circuit and an output matching circuit. The input impedance matching circuit includes a radio frequency signal input terminal and the first node N1, for inputting a radio frequency signal, the output matching circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, the first transistor M1 is electrically connected to the second node N2 and the third node N3 respectively, the second transistor M2 is electrically connected to the second node N2 and the third node N3 respectively, the third transistor M3 is electrically connected to the second node N2 and the third node N3 respectively, the noise elimination common-gate common-source amplifier circuit includes a first inter-stage matching module consisting of an electrically connected fourth transistor M4, a third inductor L3, a first transformer primary winding T1-1, a fifth transistor M5, a second transformer primary winding T1-2, a fourth inductor L4 and a first transformer secondary winding and a first transformer third winding T1-3, the The common-source common-gate amplifier circuit is electrically connected to the first inter-stage matching module, and the common-source common-gate amplifier circuit adopts a dual-branch matching network topology structure, including a sixth transistor M6, a seventh transistor M7, a second resistor R2, a third resistor R3 and a sixth inductor L6, a first end of the second resistor R2 is electrically connected to the seventh node N7, a second end of the second resistor R2 is connected to the second fixed voltage signal terminal VDD2, a first end of the third resistor R3 is electrically connected to the tenth node N10, a second end of the third resistor R3 is electrically connected to the sixth node N6, a first end of the sixth inductor L6 is connected to the gate of the sixth transistor M6, a second end of the sixth inductor L6 is electrically connected to the seventh node N7, and a drain of the sixth transistor M6 is connected to the RF signal output terminal , used to output the RF signal after noise processing.

[0061] The input impedance matching circuit further includes a first capacitor C1 and a first inductor L1, wherein a first end of the first inductor L1 is electrically connected to a first node N1, a second end of the first inductor L1 is electrically connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is electrically connected to a RF signal input terminal. Electrical connection.

[0062] The source terminal of the first transistor M1 is electrically connected to the second node N2 , the drain terminal of the first transistor M1 is electrically connected to the third node N3 , and the gate terminal of the first transistor M1 is connected to the first fixed voltage signal terminal VDD1 .

[0063] The gate terminal of the second transistor M2 is electrically connected to the second node N2, the source terminal of the second transistor M2 is connected to the second fixed voltage signal terminal VDD2, and the drain terminal of the second transistor M2 is electrically connected to the third node N3.

[0064] The gate terminal of the third transistor M3 is electrically connected to the second node N2, the drain terminal of the third transistor M3 is electrically connected to the third node N3, and the source terminal of the third transistor M3 is connected to the ground terminal GND.

[0065] The noise elimination common-gate common-source amplifier circuit also includes a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the source end of the fourth transistor M4, a second end of the second capacitor C2 is electrically connected to the first node N1, a gate of the fourth transistor M4 is connected to the bias signal end VB2, a drain of the fourth transistor M4 is electrically connected to the first end of the primary winding T1-1 of the first transformer, a second end of the primary winding T1-1 of the first transformer is electrically connected to the third fixed voltage signal end VDD3, and a source of the fourth transistor M4 is electrically connected to the fourth node N4.

[0066] The source of the fourth transistor M4 includes a third inductor L3 , a first end of the third inductor L3 is electrically connected to the fourth node N4 , and a second end of the third inductor L3 is connected to the ground GND.

[0067] The noise-cancelling common-gate common-source amplifier circuit also includes a second inductor L2, a first end of the second inductor L2 is electrically connected to the gate end of the fifth transistor M5, a second end of the second inductor L2 is electrically connected to the third node N3, a drain of the fifth transistor M5 is electrically connected to the first end of the second transformer primary winding T1-2, and a second end of the second transformer primary winding T1-2 is electrically connected to the fourth fixed voltage signal end VDD4.

[0068] The first inter-stage matching module also includes a third capacitor C3, a first end of the third capacitor C3 is electrically connected to the fifth node N5, a first end of the third capacitor C3 is connected to the bias voltage signal terminal VB1, a second end of the third capacitor C3 is electrically connected to the first end of the third winding T1-3 of the first transformer, and a second end of the third winding T1-3 of the first transformer is electrically connected to the fifth node N5.

[0069] The common-source common-gate amplifier circuit also includes a seventh inductor L7, an eighth inductor L8, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6, a first end of the seventh inductor L7 is electrically connected to a ninth node N9, a second end of the seventh inductor L7 is connected to a source of the sixth transistor M6, a first end of the eighth inductor L8 is connected to a gate of the seventh transistor M7, a second end of the eighth inductor L8 is electrically connected to the sixth node N6, a first end of the fourth capacitor C4 is electrically connected to a ninth node N9, a second end of the fourth capacitor C4 is electrically connected to a seventh node N7, a first end of the fifth capacitor C5 is electrically connected to a tenth node N10, a second end of the fifth capacitor C5 is electrically connected to a third resistor R3, a first end of the sixth capacitor C6 is electrically connected to a radio frequency signal output terminal The second end of the sixth capacitor C6 is electrically connected to the eighth node N8.

[0070] This embodiment is another preferred implementation method. Compared with the prior art, the common-source and common-gate amplifier circuit using inter-stage inductance tuning and gate inductance feedback offsets the parasitic capacitance between the common-source and common-gate nodes, provides gain and reduces circuit noise.

[0071] Example 5

[0072] See also Figure 1 and Figure 2 A CMOS ultra-wideband low-noise amplifier based on a noise cancellation structure includes an input impedance matching circuit, a noise cancellation common-gate common-source amplifier circuit, a common-source common-gate amplifier circuit and an output matching circuit. The input impedance matching circuit includes a radio frequency signal input terminal and the first node N1, for inputting a radio frequency signal, the output matching circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, the first transistor M1 is electrically connected to the second node N2 and the third node N3 respectively, the second transistor M2 is electrically connected to the second node N2 and the third node N3 respectively, the third transistor M3 is electrically connected to the second node N2 and the third node N3 respectively, the noise elimination common-gate common-source amplifier circuit includes a first inter-stage matching module consisting of an electrically connected fourth transistor M4, a third inductor L3, a first transformer primary winding T1-1, a fifth transistor M5, a second transformer primary winding T1-2, a fourth inductor L4 and a first transformer secondary winding and a first transformer third winding T1-3, the The common-source common-gate amplifier circuit is electrically connected to the first inter-stage matching module, and the common-source common-gate amplifier circuit adopts a dual-branch matching network topology structure, including a sixth transistor M6, a seventh transistor M7, a second resistor R2, a third resistor R3 and a sixth inductor L6, a first end of the second resistor R2 is electrically connected to the seventh node N7, a second end of the second resistor R2 is connected to the second fixed voltage signal terminal VDD2, a first end of the third resistor R3 is electrically connected to the tenth node N10, a second end of the third resistor R3 is electrically connected to the sixth node N6, a first end of the sixth inductor L6 is connected to the gate of the sixth transistor M6, a second end of the sixth inductor L6 is electrically connected to the seventh node N7, and a drain of the sixth transistor M6 is connected to the RF signal output terminal , used to output the RF signal after noise processing.

[0073] The input impedance matching circuit further includes a first capacitor C1 and a first inductor L1, wherein a first end of the first inductor L1 is electrically connected to a first node N1, a second end of the first inductor L1 is electrically connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is electrically connected to a RF signal input terminal. Electrical connection.

[0074] The source terminal of the first transistor M1 is electrically connected to the second node N2 , the drain terminal of the first transistor M1 is electrically connected to the third node N3 , and the gate terminal of the first transistor M1 is connected to the first fixed voltage signal terminal VDD1 .

[0075] The gate terminal of the second transistor M2 is electrically connected to the second node N2, the source terminal of the second transistor M2 is connected to the second fixed voltage signal terminal VDD2, and the drain terminal of the second transistor M2 is electrically connected to the third node N3.

[0076] The gate terminal of the third transistor M3 is electrically connected to the second node N2, the drain terminal of the third transistor M3 is electrically connected to the third node N3, and the source terminal of the third transistor M3 is connected to the ground terminal GND.

[0077] The noise elimination common-gate common-source amplifier circuit also includes a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the source end of the fourth transistor M4, a second end of the second capacitor C2 is electrically connected to the first node N1, a gate of the fourth transistor M4 is connected to the bias signal end VB2, a drain of the fourth transistor M4 is electrically connected to the first end of the primary winding T1-1 of the first transformer, a second end of the primary winding T1-1 of the first transformer is electrically connected to the third fixed voltage signal end VDD3, and a source of the fourth transistor M4 is electrically connected to the fourth node N4.

[0078] The source of the fourth transistor M4 includes a third inductor L3 , a first end of the third inductor L3 is electrically connected to the fourth node N4 , and a second end of the third inductor L3 is connected to the ground GND.

[0079] The noise-cancelling common-gate common-source amplifier circuit also includes a second inductor L2, a first end of the second inductor L2 is electrically connected to the gate end of the fifth transistor M5, a second end of the second inductor L2 is electrically connected to the third node N3, a drain of the fifth transistor M5 is electrically connected to the first end of the second transformer primary winding T1-2, and a second end of the second transformer primary winding T1-2 is electrically connected to the fourth fixed voltage signal end VDD4.

[0080] The first inter-stage matching module also includes a third capacitor C3, a first end of the third capacitor C3 is electrically connected to the fifth node N5, a first end of the third capacitor C3 is connected to the bias voltage signal terminal VB1, a second end of the third capacitor C3 is electrically connected to the first end of the third winding T1-3 of the first transformer, and a second end of the third winding T1-3 of the first transformer is electrically connected to the fifth node N5.

[0081] Further preferably, the common-source and common-gate amplifier circuit also includes a seventh inductor L7, an eighth inductor L8, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6, a first end of the seventh inductor L7 is electrically connected to the ninth node N9, a second end of the seventh inductor L7 is connected to the source of the sixth transistor M6, a first end of the eighth inductor L8 is connected to the gate of the seventh transistor M7, a second end of the eighth inductor L8 is electrically connected to the sixth node N6, a first end of the fourth capacitor C4 is electrically connected to the ninth node N9, a second end of the fourth capacitor C4 is electrically connected to the seventh node N7, a first end of the fifth capacitor C5 is electrically connected to the tenth node N10, a second end of the fifth capacitor C5 is electrically connected to the third resistor R3, a first end of the sixth capacitor C6 is electrically connected to the RF signal output terminal The second end of the sixth capacitor C6 is electrically connected to the eighth node N8.

[0082] The output matching circuit further includes a fourth resistor R4 and a fifth inductor L5, wherein a first end of the fourth resistor R4 is electrically connected to the eighth node N8, a second end of the fourth resistor R4 is connected to a first end of the fifth inductor L5, and a second end of the fifth inductor L5 is connected to a sixth fixed voltage signal terminal VDD6.

[0083] The first inter-stage matching module further includes a fifth resistor R5 , a first end of the fifth resistor R5 is electrically connected to the fifth node N5 , and a second end of the fifth resistor R5 is connected to the bias voltage signal end VB1 .

[0084] The second capacitor C2 and the sixth capacitor C6 are both DC blocking capacitors.

[0085] This embodiment is the best implementation mode. The input impedance matching circuit also includes a first capacitor C1 and a first inductor L1. The first end of the first inductor L1 is electrically connected to the first node N1, the second end of the first inductor L1 is electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is electrically connected to the RF signal input terminal, which can reduce the thermal noise introduced by the resistor.

[0086] The second capacitor C2 and the sixth capacitor C6 are both DC blocking capacitors. The second capacitor C2 can block DC signals to prevent affecting the first transistor M1 and changing the working state of the first transistor M1. The sixth capacitor C6 can achieve output matching while blocking the RF signal output terminal from outputting DC signals to prevent the DC signal from affecting the circuit.

[0087] The following is an explanation through simulation experiments:

[0088] Simulation conditions:

[0089] In the frequency band range of 6 GHz to 18 GHz, a 40 nm CMOS process model of SMIC is used, the first fixed voltage signal terminal to the sixth fixed voltage signal terminal are all 1.1 V, and a simulation tool is used to simulate the entire circuit.

[0090] Simulation content:

[0091] Simulation 1: Under the above conditions, the input and output matching of the amplifier circuit proposed in the present invention is simulated. Figure 3 .

[0092] Depend on Figure 3 It can be seen that the present invention can achieve better input matching S11 and output matching S22, wherein the input matching S11 is less than -10dB, which is the reflection coefficient of port 1 when port 2 is matched; the output matching S22 is less than -10dB, which is the reflection coefficient of port 2 when port 1 is matched.

[0093] Simulation 2, under the above conditions, the gain S21 of the circuit of the present invention is simulated, see Figure 4 .

[0094] Depend on Figure 4 It can be seen that the present invention can achieve a relatively high gain, and the gain S21 is 21.9dB-24.6dB in the simulation frequency band.

[0095] Simulation 3, under the above conditions, the noise coefficient of the circuit of the present invention is compared and simulated, see Figure 5 .

[0096] Depend on Figure 5 It can be seen that the noise figure in the simulation frequency band is 3.6dB-3.9dB, which can achieve good noise performance in a wider bandwidth.

[0097] Simulation 4, under the above conditions, the isolation S12 of the circuit of the present invention is simulated, see Figure 6 .

[0098] Depend on Figure 6 It can be seen that: within the simulation frequency band, the isolation S12 is less than -62dB, which has good isolation. The isolation S12 is the transmission coefficient from port 2 to port 1 when port 1 is matched.

Claims

1. A CMOS ultra-wideband low noise amplifier based on a noise cancellation structure, characterized in that: It includes an input impedance matching circuit, a noise elimination common gate and common source amplifier circuit, a common source and common gate amplifier circuit and an output matching circuit. The input impedance matching circuit includes a radio frequency signal input terminal and the first node N1, for inputting a radio frequency signal, the output matching circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, the first transistor M1 is electrically connected to the second node N2 and the third node N3 respectively, the second transistor M2 is electrically connected to the second node N2 and the third node N3 respectively, the third transistor M3 is electrically connected to the second node N2 and the third node N3 respectively, the noise elimination common-gate common-source amplifier circuit includes a first inter-stage matching module composed of an electrically connected fourth transistor M4, a third inductor L3, a first transformer primary winding T1-1, a fifth transistor M5, a first transformer secondary winding and a second transformer primary winding T1-2, a fourth inductor L4 and a first transformer third winding T1-3, the The common-source common-gate amplifier circuit is electrically connected to the first inter-stage matching module, and the common-source common-gate amplifier circuit adopts a dual-branch matching network topology structure, including a sixth transistor M6, a seventh transistor M7, a second resistor R2, a third resistor R3 and a sixth inductor L6, a first end of the second resistor R2 is electrically connected to the seventh node N7, a second end of the second resistor R2 is connected to the second fixed voltage signal terminal VDD2, a first end of the third resistor R3 is electrically connected to the tenth node N10, a second end of the third resistor R3 is electrically connected to the sixth node N6, a first end of the sixth inductor L6 is connected to the gate of the sixth transistor M6, a second end of the sixth inductor L6 is electrically connected to the seventh node N7, and a drain of the sixth transistor M6 is connected to the RF signal output terminal , used to output the RF signal after noise processing; The input impedance matching circuit further includes a first capacitor C1 and a first inductor L1, wherein a first end of the first inductor L1 is electrically connected to a first node N1, a second end of the first inductor L1 is electrically connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is electrically connected to a RF signal input terminal. Electrical connection; The noise elimination common-gate common-source amplifier circuit also includes a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the source end of the fourth transistor M4, a second end of the second capacitor C2 is electrically connected to the first node N1, a gate of the fourth transistor M4 is connected to the bias signal end VB2, a drain of the fourth transistor M4 is electrically connected to the first end of the primary winding T1-1 of the first transformer, a second end of the primary winding T1-1 of the first transformer is electrically connected to the third fixed voltage signal end VDD3, and a source of the fourth transistor M4 is electrically connected to the fourth node N4; The source of the fourth transistor M4 includes a third inductor L3, a first end of the third inductor L3 is electrically connected to the fourth node N4, and a second end of the third inductor L3 is connected to the ground terminal GND; The noise elimination common-gate common-source amplifier circuit also includes a second inductor L2, a first end of the second inductor L2 is electrically connected to the gate end of the fifth transistor M5, a second end of the second inductor L2 is electrically connected to the third node N3, a drain of the fifth transistor M5 is electrically connected to the first end of the secondary winding of the first transformer and the first end of the primary winding T1-2 of the second transformer, and a second end of the secondary winding of the first transformer and the second primary winding T1-2 of the second transformer is electrically connected to the fourth fixed voltage signal end VDD4; The output matching circuit further includes a fourth resistor R4 and a fifth inductor L5, wherein a first end of the fourth resistor R4 is electrically connected to the eighth node N8, a second end of the fourth resistor R4 is connected to a first end of the fifth inductor L5, and a second end of the fifth inductor L5 is connected to a sixth fixed voltage signal terminal VDD6.

2. The CMOS ultra-wideband low noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The source terminal of the first transistor M1 is electrically connected to the second node N2 , the drain terminal of the first transistor M1 is electrically connected to the third node N3 , and the gate terminal of the first transistor M1 is connected to the first fixed voltage signal terminal VDD1 .

3. The CMOS ultra-wideband low noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The gate terminal of the second transistor M2 is electrically connected to the second node N2, the source terminal of the second transistor M2 is connected to the second fixed voltage signal terminal VDD2, and the drain terminal of the second transistor M2 is electrically connected to the third node N3.

4. The CMOS ultra-wideband low noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The gate terminal of the third transistor M3 is electrically connected to the second node N2, the drain terminal of the third transistor M3 is electrically connected to the third node N3, and the source terminal of the third transistor M3 is connected to the ground terminal GND.

5. The CMOS ultra-wideband low noise amplifier based on a noise cancellation structure according to claim 1, characterized in that: The first inter-stage matching module also includes a third capacitor C3, a first end of the third capacitor C3 is electrically connected to the fifth node N5, a first end of the third capacitor C3 is connected to the bias voltage signal terminal VB1, a second end of the third capacitor C3 is electrically connected to the first end of the third winding T1-3 of the first transformer, and a second end of the third winding T1-3 of the first transformer is electrically connected to the fifth node N5.

6. The CMOS ultra-wideband low noise amplifier based on a noise cancellation structure according to claim 5, characterized in that: The common-source common-gate amplifier circuit also includes a seventh inductor L7, an eighth inductor L8, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6, a first end of the seventh inductor L7 is electrically connected to a ninth node N9, a second end of the seventh inductor L7 is connected to a source of the sixth transistor M6, a first end of the eighth inductor L8 is connected to a gate of the seventh transistor M7, a second end of the eighth inductor L8 is electrically connected to the sixth node N6, a first end of the fourth capacitor C4 is electrically connected to a ninth node N9, a second end of the fourth capacitor C4 is electrically connected to a seventh node N7, a first end of the fifth capacitor C5 is electrically connected to a tenth node N10, a second end of the fifth capacitor C5 is electrically connected to a third resistor R3, a first end of the sixth capacitor C6 is electrically connected to a radio frequency signal output terminal The second end of the sixth capacitor C6 is electrically connected to the eighth node N8.

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