Viterbi decoding method, device, terminal and medium for reducing false detection probability

Abstract

The present application provides a Viterbi decoding method, device, terminal and medium for reducing the false detection probability. The method includes: a soft bit sequence observed at a channel input end is subjected to Viterbi decoding of a surround structure to obtain a preliminary decoding sequence; the preliminary decoding sequence is pre-checked, and after the preliminary decoding sequence passes the pre-check, the preliminary decoding sequence is subjected to a cyclic redundancy check; when the preliminary decoding sequence passes the cyclic redundancy check, an anti-false detection check is performed on it, and the decoding sequence that passes the anti-false detection check is output as the final decoding result. The present application improves the decoding performance through surround Viterbi decoding, making it close to the maximum likelihood performance, and reduces the false detection probability through pre-checking and anti-false detection checking.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a Viterbi decoding method, device, terminal and medium for reducing false detection probability. Background Art

[0002] The essence of communication is the process of information from the source to the destination through the channel. Channel coding plays an important role in restoring information at the receiving end. 3GPP stipulates that the channel coding of LTE control channel and broadcast channel adopts tail-biting convolutional code with 6 registers, code rate 1 / 3 and constraint length 7. The so-called tail-biting convolutional code is to initialize the register with the information bit whose last length of the data block is equal to the length of the encoder register. When all the data passes through the encoder, the end state of the encoder is the same as the initial state of the encoder, so that the beginning and the end are connected.

[0003] The encoder of the convolutional code has memory. Within a certain period of time, the output of the encoder depends not only on the input at that moment, but also on the input before it. As a suboptimal decoding algorithm for convolutional codes, Viterbi has a variety of implementation structures. The commonly used decoding structure is one-time decoding, that is, no processing is done on the input soft bit sequence, and the maximum likelihood path is found from the beginning to the end of the sequence according to the encoding path, so as to obtain the decoded bit sequence.

[0004] Although the one-shot decoding structure has the advantage of fast decoding speed, the performance of the one-shot decoding structure is not ideal and is far from the maximum likelihood decoding. WAVA (Wrap-Around Viterbi Algorithm) improves the decoding performance by wrapping around, making it close to the maximum likelihood performance, but due to the existence of wrapping, the probability of false detection in decoding is also doubled. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a Viterbi decoding method, device, terminal and medium for reducing the false detection probability, so as to solve the problem of high false detection probability of WAVA decoding structure.

[0006] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a Viterbi decoding method for reducing the false detection probability, comprising: performing surround Viterbi decoding on an acquired sequence to be decoded to obtain a preliminary decoding sequence; performing a pre-check on the preliminary decoding sequence, and after the preliminary decoding sequence passes the pre-check, performing a cyclic redundancy check on the preliminary decoding sequence; when the preliminary decoding sequence passes the cyclic redundancy check, performing an anti-false detection check on it, and outputting the decoding sequence that passes the anti-false detection check as the final decoding result.

[0007] In some embodiments of the first aspect of the present application, the specific process of performing a surround Viterbi decoding process on a sequence to be decoded observed by a receiving end includes: based on the sequence to be decoded, calculating the branch metric and the path metric of the state transition, and obtaining the path information of the state transition; based on the node backtracking truncation rule, using the path metric and the path information, according to the set backtracking length, performing multiple node backtracking truncation operations to obtain a preliminary decoding sequence.

[0008] In some embodiments of the first aspect of the present application, the node backtracking truncation rule includes: when the current node backtracking truncation operation is the first operation, according to the set backtracking length, using the path metric, determine the starting node of the current node backtracking truncation operation; starting from the determined starting node, use the path information to perform optimal path backtracking, and after the backtracking is completed, according to the set reliable decoding length, truncate the decoding sequence obtained after the backtracking is completed; when the current node backtracking truncation operation is not the first operation, according to the set backtracking length and the node position of the last operation truncation, use the path metric to determine the starting node of the current node backtracking truncation operation; starting from the determined starting node, use the path information to perform optimal path backtracking, and after the backtracking is completed, according to the set reliable decoding length, truncate the decoding sequence obtained after the backtracking is completed.

[0009] In some embodiments of the first aspect of the present application, the pre-verification method includes: making an identical judgment on the bits whose head and tail lengths of the preliminary decoding sequence are equal to the number of shift registers; if they are judged to be identical, the preliminary decoding sequence passes the pre-verification; if they are judged to be unequal, the preliminary decoding sequence fails the pre-verification.

[0010] In some embodiments of the first aspect of the present application, the specific process of the anti-false detection check includes: encoding the preliminary decoding sequence to obtain an encoded bit sequence; mapping the encoded bit sequence to obtain a mapped sequence; correlating the sequence to be decoded and the mapped sequence to obtain a correlated sequence; performing reliability judgment based on the correlated sequence and the sequence to be decoded to obtain a corresponding reliability judgment result; if the result of the reliability judgment is passed, the decoding sequence is output as the final decoding result; if the result of the reliability judgment is failed, the decoding fails.

[0011] In some embodiments of the first aspect of the present application, reliability judgment is performed based on the related sequences and the sequences to be decoded to obtain a corresponding reliability judgment result, including: calculating the sum of the related sequences and calculating the sum of the absolute values ​​of the sequences to be decoded; based on the sum of the related sequences and the sum of the absolute values ​​of the sequences to be decoded, calculating the division result between the two; if the division result is greater than a set threshold value, obtaining a corresponding passed reliability judgment result; if the division result is less than the set threshold value, obtaining a corresponding failed reliability judgment result.

[0012] In some embodiments of the first aspect of the present application, the method further includes: when the preliminary decoding sequence fails the pre-check or the cyclic redundancy check, performing Viterbi decoding on the decoding sequence again until a set maximum number of iterations is reached.

[0013] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a Viterbi decoding device for reducing the false detection probability, including: a decoding module, used to perform Viterbi decoding on a sequence to be decoded observed by a receiving end to obtain a preliminary decoding sequence; a pre-check module, used to perform a pre-check on the preliminary decoding sequence; a cyclic redundancy check module, used to perform a cyclic redundancy check on the preliminary decoding sequence after the preliminary decoding sequence passes the pre-check; an anti-false detection module, used to perform an anti-false detection check on the preliminary decoding sequence when the preliminary decoding sequence passes the cyclic redundancy check, and output the decoding sequence that passes the anti-false detection check as the final decoding result.

[0014] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the Viterbi decoding method for reducing the false detection probability is implemented.

[0015] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the Viterbi decoding method for reducing the false detection probability.

[0016] As described above, the Viterbi decoding method, device, terminal and medium for reducing false detection probability of the present application have the following beneficial effects:

[0017] The present application improves the decoding performance by surrounding Viterbi decoding, making it close to the maximum likelihood performance, and reduces the false detection probability by pre-checking and anti-false detection checking. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1Shown is a flow chart of a Viterbi decoding method for reducing false detection probability in an embodiment of the present application.

[0019] Figure 2 Shown is a schematic diagram of the encoder structure in one embodiment of the present application.

[0020] Figure 3 Shown is a schematic diagram of a butterfly structure in an embodiment of the present application.

[0021] Figure 4 It is a schematic diagram of obtaining a preliminary decoding sequence according to an embodiment of the present application.

[0022] Figure 5 Shown is a schematic diagram of a grid diagram in an embodiment of the present application.

[0023] Figure 6 Shown is a process schematic diagram of a backtracking truncation operation in a specific embodiment of the present application.

[0024] Figure 7 Shown is a schematic diagram of the process of preventing false detection in one embodiment of the present application.

[0025] Figure 8 Shown is a schematic block diagram of a Viterbi decoding method for reducing false detection probability in an embodiment of the present application.

[0026] Fig. 9 Shown is a schematic diagram of the structure of an electronic terminal in one embodiment of the present application. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0029] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0030] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0031] The present application provides a Viterbi decoding method, device, terminal and medium for reducing the false detection probability. The method includes: a soft bit sequence observed at a channel input end is subjected to Viterbi decoding of a surround structure to obtain a preliminary decoding sequence; the preliminary decoding sequence is pre-checked, and after the preliminary decoding sequence passes the pre-check, the preliminary decoding sequence is subjected to a cyclic redundancy check; when the preliminary decoding sequence passes the cyclic redundancy check, an anti-false detection check is performed on it, and the decoding sequence that passes the anti-false detection check is output as the final decoding result. The present application improves the decoding performance through surround Viterbi decoding, making it close to the maximum likelihood performance, and reduces the false detection probability through pre-checking and anti-false detection checking.

[0032] To facilitate understanding of the embodiments of the present application, first Figure 1 Detailed description. Figure 1 The flowchart of a Viterbi decoding method for reducing the false detection probability in an embodiment of the present invention is shown. The Viterbi decoding method for reducing the false detection probability in this embodiment mainly includes the following steps:

[0033] Step S11: performing a surround Viterbi decoding process on the acquired sequence to be decoded to obtain a preliminary decoding sequence.

[0034] In one embodiment, in 3GPP, the channel coding of the LTE control channel and the broadcast channel adopts a tail-biting convolutional code with 6 registers, a code rate of 1 / 3, and a constraint length of 7. The tail-biting convolutional code is to use the information bits whose last length of the data block is equal to the length of the encoder register to initialize the register. After the data passes through the encoder, the end state of the encoder is the same as the initial state of the encoder, connected end to end. That is, when a sequence after a code block is repeated multiple times is decoded, any bit sequence in the decoded bit sequence whose length is equal to the length of the code block can be considered as a complete decoding bit output. In this embodiment, the transmitting end adopts the following method: Figure 2 The encoder shown converts the original data (bit stream) into coded data with error detection and correction capabilities and sends it to the receiving end; the decoder in the receiving end decodes the sequence to be decoded observed by the receiving end to restore the original data of the sending end.

[0035] In one embodiment, the sequence to be decoded is an LLR sequence.

[0036] It should be understood that LLR (Log-Likelihood Ratio) is the logarithm of the probability ratio of the transmitted bit being 0 and 1 under the premise of known observation quantity, which is a representation method of log-likelihood domain.

[0037] In one embodiment, the specific process of performing Viterbi decoding on the sequence to be decoded observed by the receiving end includes: based on the sequence to be decoded, calculating the branch metric and path metric of the state transition, and recording the path information of the state transition; based on the node backtracking truncation rule, using the path metric and path information, according to the set backtracking length, performing multiple node backtracking truncation operations to obtain a preliminary decoding sequence.

[0038] In one embodiment, the node backtracking truncation rule includes: when the current node backtracking truncation operation is the first operation, according to the set backtracking length, using the path metric, determining the starting node of the current node backtracking truncation operation; starting from the determined starting node, using the path information to perform optimal path backtracking, and after the backtracking is completed, according to the set reliable decoding length, truncating the decoding sequence obtained after the backtracking is completed; when the current node backtracking truncation operation is not the first operation, according to the set backtracking length and the node position of the last operation truncation, using the path metric, determining the starting node of the current node backtracking truncation operation; starting from the determined starting node, using the path information to perform optimal path backtracking, and after the backtracking is completed, according to the set reliable decoding length, truncating the decoding sequence obtained after the backtracking is completed.

[0039] The specific process of Viterbi decoding will be explained below with reference to the accompanying drawings:

[0040] In this embodiment, the structure of the encoder is as follows Figure 2 The original input data is represented as The encoding process of the convolutional code in 3GPP is equivalent to the state transition process. State transition means that the encoder register state changes from time k to time k. Migrate to time k+1 Viterbi decoding is a process of finding the most likely state transition path to obtain the best possible coded input bit sequence.

[0041] Assume that the sequence observed by the receiver is:

[0042]

[0043] In the state transition, the bit combination obtained after encoding at time k is There are 8 possibilities, each bit corresponds to a received soft bit , .

[0044] It should be understood that received soft bits (soft Bits) refer to signal bits received at a receiving end, and these bits contain amplitude information of the original signal.

[0045] During the Viterbi decoding process, the main calculation is to calculate the branch metrics at each state transition and update the path metrics of each state.

[0046] Figure 2 The encoder shown in the figure has a total of 6 registers (each box in the figure represents a register), so there are a total of There are 128 paths for state transitions in total. In the Trellis Diagram of the Viterbi algorithm, each state can be seen as a node, and the paths are the edges connecting these nodes. Each state can be reached from two different states at the previous moment, and the corresponding two paths form a butterfly structure.

[0047] Branch Metric BM (Branch Metric), that is, the probability metric of migrating from one state to the next state, is expressed as For time k, the branch metric is calculated using the following formula 1:

[0048] ;(Formula 1)

[0049] in, ; , branch metric index , the value range is 0~7;

[0050] Further, Calculated from the current register state, that is

[0051]

[0052] , , , , as well as Expressed as Figure 2 The current state of the registers in .

[0053] Furthermore, the path metric is calculated based on the calculated branch metric. The path metric PM (Path Metric) is the probability metric of reaching a certain state after migrating multiple steps from a certain state, expressed as , the total path metric is a probabilistic metric of all states from the initial state to the end, expressed as .

[0054] For example, Figure 3 A path migration butterfly structure is shown. If the state of the register at time k is , when the input bit is 0, at time k+1 the register state transitions to , the branch metric from time k to time k+1 is M; if the state of the register at time k is , when the input bit is 1, at time k+1 the register state transitions to , the branch metric from time k to time k+1 is -M; if the state of the register at time k is , when the input bit is 0, at time k+1 the register state transitions to ; If the state of the register at time k is , when the input bit is 1, at time k+1 the register state transitions to .

[0055] The register state at time k Recorded as srcState0, the corresponding path metric is ; Set the register status at time k+1 Recorded as dstState0, the corresponding path metric is ; Set the register status at time k Recorded as srcState1, the corresponding path metric is ; Set the register status at time k+1 Recorded as dstState1, the corresponding path metric is The path update is shown in Table 1 below:

[0056] Table 1. Path metric updates

[0057]

[0058] The path metric corresponding to dstState0 at time k+1 ;

[0059] The path metric corresponding to dstState1 at time k+1 .

[0060] After the path metric of each state is updated, the corresponding survival path is obtained.

[0061] Furthermore, the migration process is described using path information.

[0062] For each butterfly structure, if the register state at the current moment is reached by the state at the previous moment located above in the diagram of the butterfly structure, the path information is 0; if the register state at the current moment is reached by the state at the previous moment located below in the diagram of the butterfly structure, the path information is 1.

[0063] For example, if the register state dstState0 at time k+1 is migrated from the register state srcState0 at time k (register state srcState0 is located at the top in the figure), the path information is 0; if the register state dstState0 at time k+1 is migrated from the register state srcState1 at time k (register state srcState1 is located at the bottom in the figure), the path information is 1; if the register state dstState1 at time k+1 is migrated from the register state srcState0 at time k, the path information is 0; if the register state dstState1 at time k+1 is migrated from the register state srcState1 at time k, the path information is 0. The path information record is shown in Table 2:

[0064] Table 2. Path information record

[0065]

[0066] Furthermore, the backtracking length is set. Whenever the number of state transitions meets the backtracking length, a node backtracking truncation operation is performed until all moments are backtracked. The decoded bit length obtained after all moments are backtracked is generally greater than the bit length k of the original data. Figure 4 As shown, the latest k bits are taken for subsequent verification operations.

[0067] It should be understood that the determination of the traceback length needs to take into account the memory length of the convolutional code. For LTE, the traceback length needs to be greater than 40 and is generally set to 56. The convolutional code in 3GPP has a constraint length of L=7, which means that the signal memory is 7. In the grid diagram, Figure 5 As shown, let Q represent the number of nodes, and By comparing the survivor paths, it is found that at bit positions Q-5L and smaller, all survivor paths are identical with probability approaching 1. In Viterbi decoding, the decision on each information bit must be made after a delay of 5L bits, so the survivor paths are truncated to the 5L nearest bits, so variable delays in bit detection should be avoided. If the delay is at least 5L, the performance loss caused by the quasi-optimal detection process can be ignored.

[0068] The following uses the backtracking length of 56 and the reliable decoding length of 16 as an example to illustrate the backtracking truncation process. In this example, the backtracking length is set to 40. When the number of decoded bits reaches the backtracking length, that is, 56 bits, backtracking is performed and the first 16 bits of decoding results are output, and the last 40 bits are considered to be unreliable results.

[0069] like Figure 6 As shown in the figure, when the state migrates from time 0 to time 55, that is, after calculating the path metrics of all states in time 55, the number of state migrations is equal to the backtracking length. The first node backtracking truncation operation is performed, and the starting node of the first node backtracking truncation operation is determined according to the maximum value in the path metric. Starting from the determined starting node, the path information is used to backtrack along the survival path, and nodes 0 to 55 are obtained. Nodes 0 to 15 are retained and output as the decoding result, and nodes 16 to 55 are considered unreliable nodes and discarded. Since the node truncation position of the first node backtracking truncation operation is at node 15, when the state migrates to time 71, the number of state migrations is equal to the backtracking length again, and the second node backtracking truncation operation is performed. The starting node of the second node backtracking truncation operation is determined according to the maximum value in the path metric. Starting from the determined starting node, the path information is used to backtrack along the survival path, and nodes 16 to 77 are obtained. Nodes 16 to 31 are retained and output as the decoding result, and nodes 32 to 71 are considered unreliable nodes and discarded. Then, the node backtracking truncation operation is repeated until all moments are backtracked.

[0070] The backtracking process of two adjacent moments is explained by way of example:

[0071] like Figure 3 As shown, if the state at time k+1 is , the path information is 0, which means the register status at time k is ;

[0072] If the state at time k+1 is , the path information is 1, which means the register status at time k is ;

[0073] If the state at time k+1 is , the path information is 0, which means the register status at time k is ;

[0074] If the state at time k+1 is , the path information is 1, which means the register status at time k is .

[0075] It should be noted that due to the characteristics of tail-biting convolutional codes, only a circular buffer with a length equal to the length of the sequence to be decoded is needed to store the decoded bits obtained after backtracking until the decoding is successful. Compared with the ordinary Viterbi decoding method, the wrap-around Viterbi decoding method does not increase resource consumption, while improving the decoding accuracy of the starting position bits in the code block under low signal-to-noise ratio.

[0076] Furthermore, because the total number of decoding nodes is higher than the length of the sequence to be decoded (usually set to 4 times the length of the sequence to be decoded), and the length of the cyclic buffer is the same as the length of the sequence to be decoded, the storage bits in the cyclic buffer need to be cyclically covered in the storage of the decoded bits.

[0077] Step S12: performing a pre-check on the preliminary decoding sequence, and after the preliminary decoding sequence passes the pre-check, performing a cyclic redundancy check on the preliminary decoding sequence.

[0078] In one embodiment, the pre-check method includes: judging whether the first and last lengths of the preliminary decoding sequence are equal to the number of bits of the shift register; if they are judged to be the same, the preliminary decoding sequence passes the pre-check; if they are judged to be different, the preliminary decoding sequence fails the pre-check.

[0079] Specifically, the preliminary decoding sequence is expressed as , The number of shift registers depends on the number of shift registers in the encoder. Figure 2 As shown in the figure, there are 6 bits. Therefore, according to the characteristics of tail-biting convolutional codes, the first 6 bits and the last 6 bits of the decoded sequence should correspond to each other. The preliminary decoded sequence can be obtained by the method shown in the following formula 2: To perform a pre-check:

[0080] ;(Formula 2)

[0081] Wherein, k is the number of bits of the preliminary decoding sequence.

[0082] If the first and last lengths of the preliminary decoding sequence are equal to the number of bits of the shift register as determined by formula 2, the preliminary decoding sequence passes the pre-check; if the first and last lengths of the preliminary decoding sequence are not equal to the number of bits of the shift register, the preliminary decoding sequence fails the pre-check.

[0083] It should be noted that the probability of false detection can be reduced through pre-verification.

[0084] In one embodiment, a cyclic redundancy check (CRC) is a commonly used error detection technology used to detect unexpected changes during data transmission or storage. The CRC check is performed by treating the data as a very large polynomial and dividing the polynomial with a fixed divisor (usually called a generator polynomial). The remainder is the CRC check value. The sender appends this check value to the end of the data. After receiving the data, the receiver performs a division operation with the same generator polynomial. If the remainder is zero, the data is considered to be correct.

[0085] Step S13: When the preliminary decoding sequence passes the cyclic redundancy check, an anti-false check is performed on it, and the decoding sequence that passes the anti-false check is output as the final decoding result.

[0086] In one embodiment, the specific process of the anti-false detection verification includes: encoding the preliminary decoding sequence to obtain an encoded bit sequence; mapping the encoded bit sequence to obtain a mapped sequence; correlating the sequence to be decoded and the mapped sequence to obtain a correlated sequence; performing reliability judgment based on the correlated sequence and the sequence to be decoded to obtain a corresponding reliability judgment result; if the result of the reliability judgment is passed, the decoding sequence is output as the final decoding result; if the result of the reliability judgment is failed, the decoding fails.

[0087] In one embodiment, reliability judgment is performed based on the related sequence and the sequence to be decoded to obtain a corresponding reliability judgment result, including: calculating the sum of the related sequences and the sum of the absolute values ​​of the sequences to be decoded; based on the sum of the related sequences and the sum of the absolute values ​​of the sequences to be decoded, calculating the division result between the two; if the division result is greater than a set threshold value, obtaining a corresponding passed reliability judgment result; if the division result is less than the set threshold value, obtaining a corresponding failed reliability judgment result.

[0088] The following will explain the specific process of anti-false detection verification with the help of the attached drawings:

[0089] The first step, such as Figure 7As shown, the preliminary decoded sequence (including CRC) is sent to the encoder for secondary encoding.

[0090] In the second step, the bit sequence obtained after the secondary encoding is mapped in the manner shown in the following formula 3 to obtain a mapped sequence:

[0091] ;(Formula 3)

[0092] in, Represented as a sequence after mapping, It is represented as the bit sequence obtained after secondary encoding.

[0093] The third step is Figure 7 As shown, correlation processing is performed on the sequence to be decoded and the mapped sequence to obtain a correlation sequence.

[0094] Specifically, the sequence to be decoded is a soft bit sequence, and the following formula 4 is used for correlation processing:

[0095] ;(Formula 4)

[0096] in, is represented as a related sequence, It is represented as a soft bit sequence.

[0097] In the fourth step, the sum of the related sequences is calculated using the following formula 5:

[0098] ;(Formula 5)

[0099] in, Expressed as the sum of related sequences.

[0100] The fifth step is to calculate the sum of the absolute values ​​of the sequence to be decoded using the following formula 6:

[0101] ;(Formula 6)

[0102] in, It is expressed as the sum of the absolute values ​​of the sequence to be decoded.

[0103] Step 6: Figure 7 As shown, set the threshold value , performing reliability judgment based on the related sequence and the sequence to be decoded to obtain a corresponding reliability judgment result.

[0104] Specifically, calculate ;when When , the corresponding reliability judgment result is obtained, indicating that the decoding is successful; when When the corresponding reliability judgment result is not passed, it is obtained, indicating that the decoding fails.

[0105] In one embodiment, the method further includes: when the preliminary decoding sequence fails the pre-check or the cyclic redundancy check, performing Viterbi decoding on the decoding sequence again until the decoding with the maximum number of wraparound times is performed and a judgment is made as to whether the CRC check is correct or incorrect.

[0106] It should be noted that those skilled in the art can set the maximum number of wraparound times according to actual needs, and the present invention does not limit this.

[0107] Figure 8 is a schematic block diagram of a Viterbi decoding configuration device for reducing false detection probability provided by an embodiment of the present application. Figure 8 As shown, the device 8 comprises:

[0108] The decoding module 81 is used to perform Viterbi decoding on the sequence to be decoded observed by the receiving end to obtain a preliminary decoded sequence;

[0109] A pre-check module 82, used for pre-checking the preliminary decoding sequence;

[0110] A cyclic redundancy check module 83, configured to perform a cyclic redundancy check on the preliminary decoding sequence after the preliminary decoding sequence passes the pre-check;

[0111] The anti-false-check module 84 is used to perform an anti-false-check check on the preliminary decoding sequence when the preliminary decoding sequence passes the cyclic redundancy check, and output the decoding sequence that passes the anti-false-check check as the final decoding result.

[0112] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0113] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0114] In one embodiment, the specific process of performing Viterbi decoding on the sequence to be decoded observed by the receiving end includes: based on the sequence to be decoded, calculating the branch metric and path metric of the state transition, and obtaining the path information of the state transition; based on the node backtracking truncation rule, using the path metric and path information, according to the set backtracking length, performing multiple node backtracking truncation operations to obtain a preliminary decoding sequence.

[0115] In one embodiment, the node backtracking truncation rule includes: when the current node backtracking truncation operation is the first operation, according to the set backtracking length, using the path metric, determining the starting node of the current node backtracking truncation operation; starting from the determined starting node, using the path information to perform optimal path backtracking, and after the backtracking is completed, according to the set reliable decoding length, truncating the decoding sequence obtained after the backtracking is completed; when the current node backtracking truncation operation is not the first operation, according to the set backtracking length and the node position of the last operation truncation, using the path metric, determining the starting node of the current node backtracking truncation operation; starting from the determined starting node, using the path information to perform optimal path backtracking, and after the backtracking is completed, according to the set reliable decoding length, truncating the decoding sequence obtained after the backtracking is completed.

[0116] In one embodiment, the pre-check method includes: judging whether the first and last lengths of the preliminary decoding sequence are equal to the number of bits of the shift register; if they are judged to be the same, the preliminary decoding sequence passes the pre-check; if they are judged to be different, the preliminary decoding sequence fails the pre-check.

[0117] In one embodiment, the specific process of the anti-false detection verification includes: encoding the preliminary decoding sequence to obtain an encoded bit sequence; mapping the encoded bit sequence to obtain a mapped sequence; correlating the sequence to be decoded and the mapped sequence to obtain a correlated sequence; performing reliability judgment based on the correlated sequence and the sequence to be decoded to obtain a corresponding reliability judgment result; if the result of the reliability judgment is passed, the decoding sequence is output as the final decoding result; if the result of the reliability judgment is failed, the decoding fails.

[0118] In one embodiment, reliability judgment is performed based on the related sequence and the sequence to be decoded to obtain a corresponding reliability judgment result, including: calculating the sum of the related sequences and the sum of the absolute values ​​of the sequences to be decoded; based on the sum of the related sequences and the sum of the absolute values ​​of the sequences to be decoded, calculating the division result between the two; if the division result is greater than a set threshold value, obtaining a corresponding passed reliability judgment result; if the division result is less than the set threshold value, obtaining a corresponding failed reliability judgment result.

[0119] In one embodiment, the decoding module is further configured to, when the preliminary decoding sequence fails the pre-check or the cyclic redundancy check, perform Viterbi decoding on the decoding sequence again until a set maximum number of iterations is reached.

[0120] Fig. 9 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Fig. 9 As shown, the electronic terminal includes: at least one processor 901, a memory 902, at least one network interface 903 and a user interface 905. The various components in the device are coupled together through a bus system 904. It can be understood that the bus system 904 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 904 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Fig. 9 In the specification, various buses are labeled as bus systems.

[0121] The user interface 905 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0122] It is understood that the memory 902 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0123] The memory 902 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic terminal 900. Examples of these data include: any executable program for operating on the electronic terminal 900, such as an operating system 9021 and an application 9022; the operating system 9021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 9022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The Viterbi decoding method for reducing the false detection probability provided by the embodiment of the present invention can be included in the application 9022.

[0124] The method disclosed in the above embodiment of the present invention can be applied to the processor 901, or implemented by the processor 901. The processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 901 or the instruction in the form of software. The above processor 901 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 901 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 901 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0125] In an exemplary embodiment, the electronic terminal 900 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0126] According to the method provided in the embodiment of the present application, the present application also provides a computer program product, which includes: a computer program code, when the computer program code is run on a computer, the computer executes Figure 1The Viterbi decoding method for reducing the false detection probability in the illustrated embodiment.

[0127] According to the method provided in the embodiment of the present application, the present application also provides a computer-readable storage medium, which stores a program code, and when the program code is run on a computer, the computer executes Figure 1 The Viterbi decoding method for reducing the false detection probability in the illustrated embodiment.

[0128] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program and / or a computer running on a processor. By way of illustration, both applications and computing devices running on a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0129] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0130] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0131] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0132] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0133] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0134] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0135] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0136] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0137] In summary, the present application provides a Viterbi decoding method, device, terminal and medium for reducing the false detection probability, the method comprising: the soft bit sequence observed at the channel input end is subjected to Viterbi decoding of a surround structure to obtain a preliminary decoding sequence; the preliminary decoding sequence is pre-checked, and after the preliminary decoding sequence passes the pre-check, the preliminary decoding sequence is subjected to a cyclic redundancy check; when the preliminary decoding sequence passes the cyclic redundancy check, an anti-false detection check is performed on it, and the decoding sequence that passes the anti-false detection check is output as the final decoding result. The present application improves the decoding performance through surround Viterbi decoding, making it close to the maximum likelihood performance, and reduces the false detection probability through pre-checking and anti-false detection checking. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0138] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A Viterbi decoding method for reducing false detection probability, characterized in that: include: Performing a surround Viterbi decoding process on the obtained sequence to be decoded to obtain a preliminary decoding sequence; Performing a pre-check on the preliminary decoding sequence, and after the preliminary decoding sequence passes the pre-check, performing a cyclic redundancy check on the preliminary decoding sequence; The pre-verification methods include: Performing the same judgment on the bits whose head and tail lengths of the preliminary decoding sequence are equal to the number of shift registers; If they are judged to be the same, the preliminary decoding sequence passes the pre-check; If it is judged that they are not the same, the preliminary decoding sequence fails the pre-check; When the preliminary decoding sequence passes the cyclic redundancy check, an anti-false check check is performed on it, and the decoding sequence that passes the anti-false check check is output as the final decoding result; The specific process of the anti-false detection verification includes: Encoding the preliminary decoded sequence to obtain an encoded bit sequence; Performing mapping processing on the encoded bit sequence to obtain a mapped sequence; Performing correlation processing on the sequence to be decoded and the mapped sequence to obtain a correlation sequence; Performing reliability judgment based on the related sequence and the sequence to be decoded to obtain a corresponding reliability judgment result; If the result of the reliability judgment is passed, the decoding sequence is output as the final decoding result; If the result of the reliability judgment is not passed, the decoding fails; And wherein, performing reliability judgment based on the related sequence and the sequence to be decoded to obtain a corresponding reliability judgment result includes: Calculating the sum of the correlation sequences and calculating the sum of the absolute values ​​of the sequences to be decoded; Calculate a division result between the sum of the correlation sequences and the sum of the absolute values ​​of the sequences to be decoded based on the sum of the correlation sequences and the absolute values ​​of the sequences to be decoded; If the division result is greater than the set threshold value, a corresponding passed reliability judgment result is obtained; If the division result is less than the set threshold value, a corresponding failed reliability judgment result is obtained.

2. The Viterbi decoding method for reducing false detection probability according to claim 1, characterized in that: The specific process of performing surround Viterbi decoding on the sequence to be decoded observed by the receiving end includes: Based on the sequence to be decoded, a branch metric and a path metric of a state transition are calculated, and path information of the state transition is obtained; Based on the node backtracking truncation rule, using the path metric and path information, and according to the set backtracking length, multiple node backtracking truncation operations are performed to obtain a preliminary decoding sequence.

3. The Viterbi decoding method for reducing false detection probability according to claim 2, characterized in that: The node backtracking truncation rules include: When the current node backtracking and truncation operation is the first operation, the starting node of the current node backtracking and truncation operation is determined according to the set backtracking length and the path metric; starting from the determined starting node, the optimal path backtracking is performed using the path information, and after the backtracking is completed, the decoding sequence obtained after the backtracking is completed is truncated according to the set reliable decoding length; When the current node backtracking and truncation operation is not the first operation, the starting node of the current node backtracking and truncation operation is determined using the path metric according to the set backtracking length and the node position truncated in the last operation; starting from the determined starting node, the optimal path backtracking is performed using the path information, and after the backtracking is completed, the decoding sequence obtained after the backtracking is completed is truncated according to the set reliable decoding length.

4. The Viterbi decoding method for reducing false detection probability according to claim 1, characterized in that: The method further comprises: when the preliminary decoding sequence fails to pass the pre-check or the cyclic redundancy check, performing Viterbi decoding on the decoding sequence again until a set maximum number of iterations is reached.

5. A Viterbi decoding device for reducing false detection probability, characterized in that: include: A decoding module, used for performing Viterbi decoding on the sequence to be decoded observed by the receiving end to obtain a preliminary decoding sequence; A pre-check module, used for pre-checking the preliminary decoding sequence; The pre-verification methods include: Performing the same judgment on the bits whose head and tail lengths of the preliminary decoding sequence are equal to the number of shift registers; If they are judged to be the same, the preliminary decoding sequence passes the pre-check; If it is judged that they are not the same, the preliminary decoding sequence fails the pre-check; A cyclic redundancy check module, used for performing a cyclic redundancy check on the preliminary decoding sequence after the preliminary decoding sequence passes the pre-check; An anti-false check module is used to perform an anti-false check on the preliminary decoding sequence when the preliminary decoding sequence passes the cyclic redundancy check, and output the decoding sequence that passes the anti-false check as the final decoding result; The specific process of the anti-false detection verification includes: Encoding the preliminary decoded sequence to obtain an encoded bit sequence; Performing mapping processing on the encoded bit sequence to obtain a mapped sequence; Performing correlation processing on the sequence to be decoded and the mapped sequence to obtain a correlation sequence; Performing reliability judgment based on the related sequence and the sequence to be decoded to obtain a corresponding reliability judgment result; If the result of the reliability judgment is passed, the decoding sequence is output as the final decoding result; If the result of the reliability judgment is not passed, the decoding fails; And wherein, performing reliability judgment based on the related sequence and the sequence to be decoded to obtain a corresponding reliability judgment result includes: Calculating the sum of the correlation sequences and calculating the sum of the absolute values ​​of the sequences to be decoded; Calculate a division result between the sum of the correlation sequences and the sum of the absolute values ​​of the sequences to be decoded based on the sum of the correlation sequences and the absolute values ​​of the sequences to be decoded; If the division result is greater than the set threshold value, a corresponding passed reliability judgment result is obtained; If the division result is less than the set threshold value, a corresponding failed reliability judgment result is obtained.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

7. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method according to any one of claims 1 to 4.

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