Digital programmable power supply suitable for embedded integrated circuit testing and power supply testing method

Abstract

The present invention relates to a digital program-controlled power supply and a power supply test method suitable for embedded integrated circuit testing. It comprises: a reference voltage generating unit, which generates an adjustable test reference voltage by program control; a low voltage dropout voltage regulator LDO unit, which receives the test reference voltage loaded by the reference voltage generating unit, and provides a target test voltage to the connected circuit under test DUT based on the test reference voltage; an isolated sampling feedback unit, which is used to sample the target test voltage loaded to the power supply end of the circuit under test DUT, and negatively feed back the test sampling voltage generated by the sampling to the low voltage dropout voltage regulator LDO unit, so that the low voltage dropout voltage regulator LDO unit provides a stable target test voltage to the circuit under test DUT under the test sampling voltage, wherein when sampling the target test voltage, the target test voltage and the test sampling voltage are isolated from each other. The present invention can meet the test requirements of embedded integrated circuits, reduce test costs, and improve test accuracy and controllability.

Description

Technical Field

[0001] The invention relates to a digital program-controlled power supply and a power supply test method, in particular to a digital program-controlled power supply and a power supply test method suitable for embedded integrated circuit testing. Background Art

[0002] Power supply is one of the indispensable modules in integrated circuit testing. For the power supply in the integrated circuit, it is generally required to output a stable, accurate, and programmable output voltage, and also to be able to accurately test the current flowing through the device under test (DUT).

[0003] The above-mentioned test requirements can currently be achieved based on the device power supply (DPS) board in the integrated circuit automatic test equipment ATE, which can have excellent performance indicators, but the disadvantages are: the DPS board is generally integrated in the chassis of the integrated circuit automatic test equipment ATE, which is large in size and expensive. The board interface is customized and the protocol is not public. Therefore, the DPS board is not conducive to integration into embedded test systems, nor is it conducive to large-scale multi-site test production.

[0004] In the current integrated circuit test production, some mass-produced products are sensitive to test costs. Higher test costs will directly affect product profits. Customized test systems based on embedded systems such as MCU and FPGA are low-cost, easy to mass produce and use, and can greatly reduce test costs and improve test capacity. However, the power supply in general embedded customized test systems is relatively simple, and there are the following shortcomings:

[0005] 1) The power supply cannot be program-controlled. When multiple test voltages are required, LM1117 is generally used similar to the traditional voltage regulator circuit. The potentiometer is manually adjusted to set the multiple voltages. During the test, the required voltage for the test is switched through the relay. When the production line changes to test other products, the required test voltage is different. The maintenance personnel may forget to adjust the test voltage, causing the DUT to be over-voltage damaged, or the voltage range required for the test cannot be reached, resulting in defective products flowing out, and even causing serious quality accidents.

[0006] 2) The power supply output accuracy is poor. LM1117 is similar to the traditional voltage stabilization circuit. After a period of time when the potentiometer is manually adjusted to set multiple voltages, the contact position of the potentiometer will be slightly displaced due to vibration, collision, etc., or the adjustment terminal will be accidentally touched, which will cause the LM1117 output voltage to change. In addition, the temperature drift of the potentiometer is also large, which will also cause the output voltage to shift.

[0007] 3) LM1117 is similar to the traditional voltage regulator circuit and cannot test the current flowing through the DUT. It requires additional peripheral circuits to achieve this.

[0008] 4) LM1117 is similar to traditional voltage regulator circuits, which are very old and relatively backward in technology. Key performance indicators such as linear regulation rate (LNR), load regulation rate (LDR), power supply rejection ratio (PSRR), output noise and other key parameters are relatively poor. When the circuit under test is sensitive to noise and the power supply voltage accuracy requirements are high, using such traditional voltage regulator circuits to power the circuit will greatly affect the test yield of the circuit under test.

[0009] 5) LM1117 is similar to the traditional voltage regulator circuit and cannot monitor the output voltage. When the output voltage is abnormal, it cannot output the alarm information.

[0010] In summary, the current embedded test power supply cannot meet the needs of integrated circuit testing. Summary of the invention

[0011] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a digital programmable power supply and power supply testing method suitable for embedded integrated circuit testing, which can meet the testing requirements of embedded integrated circuits, reduce testing costs, and improve testing accuracy and controllability.

[0012] According to the technical solution provided by the present invention, a digital programmable power supply suitable for embedded integrated circuit testing comprises:

[0013] A reference voltage generating unit, which generates an adjustable test reference voltage by program control, and loads the generated test reference voltage to a low voltage dropout regulator LDO unit;

[0014] A low-dropout voltage regulator LDO unit is adaptively connected to the reference voltage generating unit and the circuit under test DUT, receives the test reference voltage loaded by the reference voltage generating unit, and provides a target test voltage to the connected circuit under test DUT based on the test reference voltage;

[0015] The isolated sampling feedback unit is adaptively connected to the circuit under test DUT and the low voltage difference voltage regulator LDO unit, and is used to sample the target test voltage loaded on the power supply end of the circuit under test DUT, and negatively feed back the test sampling voltage generated by the sampling to the low voltage difference voltage regulator LDO unit, so that the low voltage difference voltage regulator LDO unit provides a stable target test voltage to the circuit under test DUT under the test sampling voltage, wherein,

[0016] When sampling the target test voltage, the target test voltage and the test sampling voltage are isolated from each other.

[0017] When sampling the target test voltage, the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured to be in a near-end sampling connection state or a far-end sampling connection state, wherein:

[0018] When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as a remote sampling connection state, the isolated sampling feedback unit directly performs voltage sampling on the target test voltage at the power supply terminal of the circuit under test DUT;

[0019] When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as a near-end sampling connection state, the isolated sampling feedback unit samples the target test voltage at the power supply terminal of the circuit under test DUT at least through the voltage sampling resistor.

[0020] The isolated sampling feedback unit includes a unit gain isolation buffer and a voltage sampling connection unit adapted to be connected to the input end of the unit gain isolation buffer, wherein:

[0021] The input end of the unity gain isolation buffer is adaptively connected to the power supply end of the circuit under test DUT through the voltage sampling connection unit, so as to use the voltage sampling connection unit to perform voltage sampling on the target test voltage at the power supply end of the circuit under test DUT, and load the generated test sampling voltage to the unity gain isolation buffer;

[0022] The output end of the unit gain isolation buffer is adapted to be connected with the low voltage dropout voltage regulator LDO unit, and the test sampling voltage is fed back to the low voltage dropout voltage regulator LDO unit through the unit gain isolation buffer;

[0023] The voltage sampling connection unit includes a voltage sampling first connection branch and / or a voltage sampling second connection branch, wherein the voltage sampling resistor is located in the voltage sampling first connection branch;

[0024] When the connection state between the isolated sampling feedback unit and the power supply end of the circuit under test DUT is configured as a proximal sampling connection state, the voltage sampling first connection branch is configured to be connected to the power supply end of the circuit under test DUT, so that the power supply end of the circuit under test DUT is connected to the input end of the unity gain isolation buffer through the voltage sampling resistor;

[0025] When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as a remote sampling connection state, at least the second voltage sampling connection branch is configured to be connected to the power supply terminal of the circuit under test DUT, so that the power supply terminal of the circuit under test DUT is directly connected to the input terminal of the unity gain isolation buffer.

[0026] The low voltage dropout voltage regulator LDO unit includes a low voltage dropout voltage regulator LDO chip, wherein:

[0027] The low voltage dropout voltage regulator LDO chip is adaptively connected to the reference voltage generation unit and the isolation sampling feedback unit through a voltage regulation network;

[0028] The voltage regulating network comprises a first voltage regulating resistor and a second voltage regulating resistor, wherein a first end of the first voltage regulating resistor and a first end of the second voltage regulating resistor are both connected to the FB end of the low voltage dropout voltage regulator LDO chip;

[0029] The second end of the voltage regulating first resistor is connected to the output end of the isolation sampling feedback unit;

[0030] The second end of the voltage regulating second resistor and the GND end of the low voltage difference voltage stabilizing LDO chip are both connected to the output end of the reference voltage generating power supply, so as to load the test reference voltage to the GND end of the low voltage difference voltage stabilizing LDO chip, and load it to the FB end of the low voltage difference voltage stabilizing LDO chip through the second end of the voltage regulating second resistor;

[0031] The low voltage difference stabilizer LDO chip superimposes the terminal voltage of the GND terminal of the low voltage difference stabilizer LDO chip with the test reference voltage to generate a target test voltage, and loads the generated target test voltage to the power supply terminal of the circuit under test DUT.

[0032] The reference voltage generating unit includes a voltage output DAC unit, a voltage reference unit and an embedded unit, wherein:

[0033] The voltage reference unit provides a power supply reference voltage required for the voltage output type DAC unit to work;

[0034] The voltage reference unit includes a low-noise LDO chip, a common-phase amplifier unit, and a first-order filter circuit connected in sequence, wherein the common-phase amplifier amplifies the 2.5V voltage output by the low-noise LDO chip to 5V, uses the first-order filter circuit to filter the 5V voltage output by the common-phase amplifier, and loads the filtered 5V voltage to the voltage output DAC unit;

[0035] The embedded unit is adaptively connected to the voltage output DAC unit. The embedded unit sends a test reference voltage generation instruction to the voltage output DAC unit to configure the voltage output DAC unit to generate a corresponding test reference voltage based on the test reference voltage generation instruction, and loads the generated test reference voltage to the low dropout voltage regulator LDO unit.

[0036] The digital program-controlled power supply also includes a test current measurement unit for measuring the current flowing through the circuit under test DUT, wherein:

[0037] The current measurement unit includes a current sampling resistor network, a sampling resistor selection network and a test current processing unit.

[0038] The current sampling resistor network includes a plurality of current sampling resistors distributed in parallel, and a current sampling resistor is configured to be connected in series between the output end of the low voltage dropout voltage regulator LDO unit and the power supply end of the circuit under test DUT;

[0039] The sampling resistor selection network is adaptively connected to the current sampling resistor network and the test current processing unit, and the test current processing unit configures the corresponding current sampling resistors in the current sampling resistor network to form a current sampling target equivalent resistor through the sampling resistor selection network;

[0040] The test current flowing through the DUT is converted into a load voltage using the formed current sampling target equivalent resistance.

[0041] The test current processing unit performs amplification processing and ADC sampling processing on the load voltage in sequence to generate a load sampling voltage after the ADC sampling processing, and determines the test current flowing through the circuit under test DUT based on the load sampling voltage and the current sampling target equivalent resistance.

[0042] In the current sampling resistor network, the current sampling resistor connected in series between the output end of the low voltage dropout regulator LDO unit and the power supply end of the circuit under test DUT is configured as a normally connected current sampling resistor, and the remaining current sampling resistors are configured as optional current sampling resistors, where:

[0043] The corresponding resistance value of the normally connected current sampling resistor is greater than the corresponding resistance value of any optional current sampling resistor;

[0044] The sampling resistor selection network includes a plurality of relays and a relay driving circuit for driving the switching state of the relays, wherein:

[0045] An optional current sampling resistor is adaptively connected to a normally open contact of a relay. When the normally open contact of the corresponding relay is driven to close by the relay driving circuit, the optional current sampling resistor is selected, and the selected optional current sampling resistor is connected in parallel with the normally connected current sampling resistor to form a current sampling target equivalent resistor based on the normally connected current sampling resistor and the selected optional current sampling resistor.

[0046] The test current processing unit includes an instrument amplifier and an embedded unit adapted to be connected to the instrument amplifier, wherein:

[0047] The instrument amplifier is connected to the current sampling resistor network, and the load voltage is amplified and sampled by the ADC using the instrument amplifier, and the generated load sampling voltage is loaded into the embedded unit.

[0048] Based on the load sampling voltage and the current sampling target equivalent resistance, the embedded unit determines the test current flowing through the circuit under test DUT.

[0049] The instrument amplifier is also connected to the power supply terminal of the circuit under test DUT, wherein:

[0050] Setting a low voltage alarm threshold and / or a high voltage alarm threshold in the instrument amplifier;

[0051] The instrument amplifier compares the target test voltage at the power supply end of the circuit under test DUT with the low voltage alarm threshold and the high voltage alarm threshold. When the target test voltage at the power supply end of the circuit under test DUT matches the low voltage alarm threshold or the high voltage alarm threshold, the instrument amplifier outputs an alarm message.

[0052] The instrument amplifier is also adaptively connected to the output end of the circuit under test DUT and the low voltage dropout regulator LDO unit through an automatic shutdown circuit, wherein:

[0053] When the instrumentation amplifier outputs an alarm message, the automatic shutdown circuit is controlled to cut off the target test voltage provided by the output end of the low dropout voltage regulator LDO unit to the circuit under test DUT.

[0054] A power supply test method suitable for embedded integrated circuit testing, for any circuit under test DUT, using the above-mentioned digital programmable power supply to provide a target test voltage, so as to perform a current test on the circuit under test DUT at the target test voltage.

[0055] The advantages of the present invention are as follows: the target test voltage output by the low-dropout voltage regulator LDO unit is adjusted by program control using the voltage output DAC unit to adapt to the test requirements of different circuits under test DUT; the voltage adjustment is completed by software and is independent of hardware, thus solving the key problems in the test production process such as the need for manual adjustment, incorrect output voltage, and inaccurate output voltage.

[0056] The high-precision, low-noise voltage reference unit is composed of a low-noise LDO chip, a common-mode amplifier, and a first-order filter circuit connected in sequence. The voltage reference unit provides the power supply reference voltage of the voltage output DAC unit, so that the test reference voltage output by the digital programmable power supply can be accurately adjusted, with an output range of 1.5V-6.5V and 4096 voltage adjustment steps. The low-dropout voltage-stabilized LDO unit with high input voltage, high PSRR, low IQ, and high current output is adopted to optimize the fluctuation and noise of the target test voltage loaded on the power supply end of the circuit under test DUT, improve the stability and noise performance of the circuit under test DUT during testing, and improve the input voltage tolerance.

[0057] A unity-gain isolation buffer is constructed using a low input bias current and low offset operational amplifier, and can be configured to form a proximal sampling connection state or a remote sampling connection state. When in the remote sampling connection state, it can effectively compensate for the voltage error caused by the parasitic resistance on the power supply path, the corresponding on-resistance in the automatic shutdown circuit, and the current sampling resistor network; at the same time, it can also isolate the test current flowing through the device under test DUT and the current flowing through the voltage regulation network. In subsequent current measurements, the instrument amplifier can accurately measure the test current flowing through the device under test DUT.

[0058] The relay drive circuit can use 74HC595 chip, which has a serial-in parallel-out shift register with latch function. When driving multiple relays, the number of relay drive paths can be cascaded to expand, greatly saving the IO port resources of the embedded unit.

[0059] The instrument amplifier uses a chip with built-in ADC unit, which can accurately measure the test current flowing through the circuit under test DUT. The built-in ADC unit of the instrument amplifier can greatly improve the current measurement accuracy. The ADC unit in the instrument amplifier uses a serial SPI interface to communicate with the embedded unit, saving the hardware resources of the embedded unit. The instrument amplifier can realize high and low voltage threshold alarms, which is convenient for the embedded unit to monitor whether the target test voltage at the power supply end of the circuit under test DUT is normal; at the same time, through the ALERT alarm port of the instrument amplifier connected to the automatic shutdown circuit, it can automatically cut off the power supply to the circuit under test DUT when abnormal voltage is output. Combined with the embedded operation of reducing voltage and switching small current gears, dual protection of the power supply is achieved. Compared with the DPS power supply board in the commercial integrated circuit automatic test equipment ATE, the digital programmable power supply requires very few devices, occupies a small PCB area, and is easy to integrate into the embedded test system. In addition, compared with the DPS power supply board in the commercial integrated circuit automatic test equipment ATE, it is low-cost and easy to use in mass production.

[0060] In summary, the present invention solves the problems in embedded testing such as the inability to programmatically adjust the voltage, the inability to accurately set the output voltage, the lack of remote voltage compensation, and the inability to accurately measure the test current flowing through the circuit under test DUT, thereby improving the stability of the target test voltage and the accuracy of the test current measurement. At the same time, the present invention occupies a small PCB area and is easy to be integrated on an embedded test board, with low cost, which not only reduces the test cost, but also meets the requirements of accurate, stable, programmable, and measurable current for embedded test power supplies during mass test production. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 The present invention is a circuit block diagram of an embodiment of the present invention that uses a digital programmable power supply to perform a power supply test on a circuit under test (DUT).

[0062] Figure 2The figure is a structural block diagram of an embodiment of the instrument amplifier of the present invention.

[0063] Figure 3 A schematic diagram of an embodiment of the relay drive circuit principle and cascade expansion of the present invention.

[0064] Figure 4 A principle block diagram of an embodiment of a reference voltage unit of the present invention.

[0065] Description of reference numerals: 100-digital programmable power supply, 101-instrumentation amplifier, 102-relay drive circuit, 103-gear shift relay array, 104-first optional current sampling resistor, 105-second optional current sampling resistor, 106-third optional current sampling resistor, 107-normally connected current sampling resistor, 108-parasitic resistor, 109-voltage sampling resistor, 110-DUT unit, 111-remote compensation feedback line, 112-unit gain isolation buffer, 113-first voltage adjustment resistor, 114-second voltage adjustment resistor, 115-low dropout voltage regulator LDO unit, 116-low dropout voltage regulator LDO unit, 117-remote compensation feedback line, 118-unit gain isolation buffer, 119-remote compensation feedback line, 120-remote compensation feedback line, 121-remote compensation feedback line, 122-remote compensation feedback line, 123-remote compensation feedback line, 124-remote compensation feedback line, 125-remote compensation feedback line, 126-remote compensation feedback line, 127-remote compensation feedback line, 128-remote compensation feedback line, 129-remote compensation feedback line, 130-remote compensation feedback line, 131-remote compensation feedback line, 132-remote compensation feedback line, 133-remote compensation feedback line, 134-remote compensation feedback line, 135-remote compensation feedback line, 136-remote compensation feedback line, 137-remote compensation feedback line, 138-remote compensation feedback line, 139-remote compensation feedback line, 140-remote compensation feedback line, 141-remote compensation feedback line, 142-remote compensation feedback line, 143- 6-voltage output DAC unit, 117-voltage reference unit, 118-embedded unit, 119-shutdown circuit pull-up resistor, 120-shutdown circuit NMOS tube, 121-shutdown circuit PMOS tube, 122-automatic shutdown circuit, 201-ADC unit, 202-front-end analog signal multiplexer, 203-analog storage register, 204-instrumentation amplifier SPI interface, 205-ALERT alarm port, 206-alarm threshold comparator, 207-alarm threshold setting register, 301-serial communication interface group, 302-first 74HC595 chip, 303- QH' port, 304-second 74HC595 chip, 305-8BIT shift register, 306-8BIT latch, 307-8BIT three-state output unit, 308-parallel output drive pin group, 309-relay array, 401-low noise LDO chip, 402-built-in first voltage setting resistor, 403-built-in second voltage setting resistor, 404-built-in amplifier, 405-built-in reference voltage source, 406-first resistor of the same-phase amplifier, 407-second resistor of the same-phase amplifier, 408-same-phase amplifier, 409-first-order low-pass filter resistor, 410-first-order low-pass filter capacitor. DETAILED DESCRIPTION

[0066] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0067] In order to meet the testing requirements of embedded integrated circuits and reduce the testing costs, the present invention provides a digital programmable power supply 100 suitable for embedded integrated circuit testing. Specifically, the digital programmable power supply 100 includes:

[0068] A reference voltage generating unit, which generates an adjustable test reference voltage by program control, and loads the generated test reference voltage to the low dropout voltage regulator LDO unit 115;

[0069] The low-dropout voltage regulator LDO unit 115 is adaptively connected to the reference voltage generating unit and the circuit under test DUT, receives the test reference voltage loaded by the reference voltage generating unit, and provides a target test voltage to the connected circuit under test DUT based on the test reference voltage;

[0070] The isolated sampling feedback unit is adaptively connected to the circuit under test DUT and the low voltage difference voltage regulator LDO unit 115, and is used to sample the target test voltage loaded on the power supply end of the circuit under test DUT, and negatively feed back the test sampling voltage generated by the sampling to the low voltage difference voltage regulator LDO unit 115, so that the low voltage difference voltage regulator LDO unit 115 provides a stable target test voltage to the circuit under test DUT under the test sampling voltage, wherein,

[0071] When sampling the target test voltage, the target test voltage and the test sampling voltage are isolated from each other.

[0072] Figure 1 An embodiment of a digital programmable power supply 100 is shown in FIG. 1 . In the figure, the DUT unit 110 is the circuit under test DUT. The type of the circuit under test DUT can be selected according to actual needs, so as to meet the test requirements of the integrated circuit. It can be seen from the above description that when the circuit under test DUT performs an embedded integrated circuit test, the digital programmable power supply 100 should provide the voltage required for the test of the circuit under test DUT, that is, it should provide the target test voltage to the circuit under test DUT. It can be understood that the target test voltage should be related to the type of the circuit under test DUT and the test requirements of the circuit under test DUT, so as to meet the test requirements of the circuit under test DUT.

[0073] In order to provide the target test voltage to the DUT, Figure 1 In the embodiment, the digital programmable power supply 100 should at least include a reference voltage generating unit and a low-dropout regulator (LDO) unit 115, wherein the reference voltage generating unit can generate a test reference voltage, and the test reference voltage generated by the reference voltage generating unit is adjustable. The test reference voltage here is adjustable, which specifically means that test reference voltages of different sizes can be generated according to the test requirements of different circuits under test DUT, or different test requirements of the same circuit under test DUT, that is, the reference voltage generating unit has a programmable characteristic, thereby improving the adaptability of the digital programmable power supply 100 in embedded integrated circuits and reducing the test cost.

[0074] After the reference voltage generating unit generates the test reference voltage, the test reference voltage should be loaded onto the low voltage dropout regulated LDO unit 115. Thereafter, the low voltage dropout regulated LDO unit 115 can generate a target test voltage according to the test reference voltage, and can load the target test voltage onto the circuit under test DUT. Specifically, the low voltage dropout regulated LDO unit 115 loads the target test voltage onto the power supply terminal of the circuit under test DUT.

[0075] During the test of the circuit under test DUT, in order to ensure the stability of the target test voltage, the target test voltage can be sampled through the isolated sampling feedback unit, wherein after the voltage sampling, a test sampling voltage can be generated, and the isolated sampling feedback unit can feed back the test sampling voltage to the low voltage dropout voltage stabilizing LDO unit 115, that is, the isolated sampling feedback unit and the low voltage dropout voltage stabilizing LDO unit 115 form a closed loop of negative feedback, thereafter, the low voltage dropout voltage stabilizing LDO unit 115 can perform negative feedback adjustment on the target test voltage according to the test sampling voltage, so that the target test voltage can be kept stable, and the manner in which the low voltage dropout voltage stabilizing LDO unit 115 performs negative feedback adjustment on the target test voltage according to the test sampling voltage can be consistent with the prior art, so as to keep the target test voltage stable.

[0076] In one embodiment of the present invention, when sampling the target test voltage, the target test voltage and the test sampling voltage are isolated from each other; it can be understood that when the test sampling voltage and the target test voltage are isolated from each other, the test sampling voltage and the target test voltage do not affect each other, thereby improving the stability of the target test voltage and further improving the accuracy and reliability of the DUT test of the circuit under test.

[0077] In one embodiment of the present invention, when sampling the target test voltage, the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured to be in a near-end sampling connection state or a far-end sampling connection state, wherein:

[0078] When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as a remote sampling connection state, the isolated sampling feedback unit directly performs voltage sampling on the target test voltage at the power supply terminal of the circuit under test DUT;

[0079] When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as the near-end sampling connection state, the isolated sampling feedback unit samples the target test voltage at the power supply terminal of the circuit under test DUT at least through the voltage sampling resistor 109 .

[0080] In specific implementation, the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit DUT to be tested can be configured to be in a near-end sampling connection state or a far-end sampling connection state according to requirements such as the test accuracy of the circuit DUT to be tested. When in the near-end sampling connection state, the power supply terminal of the circuit DUT to be tested is connected through a voltage sampling resistor. At this time, the test sampling voltage generated by the voltage sampling will be affected by the parasitic resistance 108 and the on-resistance of the shutdown circuit PMOS tube 121 when it is turned on in the automatic shutdown circuit 122, and the accuracy of the test sampling voltage is low; when in the far-end sampling connection state, since the isolated sampling feedback unit directly samples the target test voltage, the parasitic resistance 108 and the on-resistance of the shutdown circuit PMOS tube 121 when it is turned on can be placed in the feedback loop. At this time, the test sampling voltage generated by the voltage sampling will not be affected by the parasitic resistance 108 and the on-resistance of the shutdown circuit PMOS tube 121 when it is turned on, so the accuracy of the test sampling voltage can be improved, and then the accuracy of providing the target test voltage can be improved.

[0081] It should be noted that the automatic shutdown circuit 122 and the shutdown circuit PMOS tube 121 can refer to the following corresponding description. It can be understood that when the digital programmable power supply 100 of the present invention does not have an automatic shutdown circuit 122, the corresponding description of the above-mentioned proximal sampling tube connection state and the distal sampling connection state should exclude the corresponding description of the automatic shutdown circuit 122.

[0082] Combine the following Figure 1 The specific situations of the near-end sampling connection status and the far-end sampling connection status are explained in detail.

[0083] In one embodiment of the present invention, the isolated sampling feedback unit includes a unit gain isolation buffer 112 and a voltage sampling connection unit adapted to be connected to an input end of the unit gain isolation buffer 112, wherein:

[0084] The input end of the unity gain isolation buffer 112 is adaptively connected to the power supply end of the circuit under test DUT through the voltage sampling connection unit, so as to use the voltage sampling connection unit to perform voltage sampling on the target test voltage at the power supply end of the circuit under test DUT, and load the generated test sampling voltage to the unity gain isolation buffer 112;

[0085] The output end of the unit gain isolation buffer 112 is adaptively connected to the low voltage dropout voltage regulator LDO unit 115, and the test sampling voltage is fed back to the low voltage dropout voltage regulator LDO unit 115 through the unit gain isolation buffer 112;

[0086] The voltage sampling connection unit includes a voltage sampling first connection branch and / or a voltage sampling second connection branch, wherein the voltage sampling resistor 109 is located in the voltage sampling first connection branch;

[0087] When the connection state between the isolated sampling feedback unit and the power supply end of the circuit under test DUT is configured as the near-end sampling connection state, the voltage sampling first connection branch is configured to be connected to the power supply end of the circuit under test DUT, so that the power supply end of the circuit under test DUT is connected to the input end of the unity gain isolation buffer 112 through the voltage sampling resistor 109;

[0088] When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as a remote sampling connection state, at least the second voltage sampling connection branch is configured to be connected to the power supply terminal of the circuit under test DUT, so that the power supply terminal of the circuit under test DUT is directly connected to the input terminal of the unity gain isolation buffer 112.

[0089] Figure 1 An embodiment of the isolated sampling feedback unit is shown in FIG. 1 . In the figure, the isolated sampling feedback unit includes a unit gain isolation buffer 112 and a voltage sampling connection unit. The unit gain isolation buffer 112 can be implemented by an operational amplifier, such as connecting the inverting end of the operational amplifier to the output end of the operational amplifier. Thereafter, the non-inverting end of the operational amplifier is used as the input end of the unit gain isolation buffer 112, and the end after the output end of the operational amplifier is connected to the inverting end is used as the output end of the unit gain isolation buffer 112. The input end of the unit gain isolation buffer 112 is connected to the power supply end of the circuit under test DUT through the voltage sampling connection unit, that is, the test sampling voltage generated by sampling can be loaded into the unit gain isolation buffer 112 through the voltage sampling connection unit, and finally fed back to the low dropout voltage regulator LDO unit 115; since the unit gain isolation buffer 112 adopts an operational amplifier, it can be known based on the characteristics of the operational amplifier that when sampling the target test voltage, isolation between the target test voltage and the test sampling voltage can be achieved.

[0090] In order to satisfy the configuration of the above-mentioned proximal sampling connection state or the remote sampling connection state, the voltage sampling connection unit may include a voltage sampling first connection branch and / or a voltage sampling second connection main path, and the voltage sampling resistor 109 is located in the voltage sampling first connection branch. Figure 1 FIG. 4 shows an embodiment in which the voltage sampling resistor 109 uses only one resistor R3. Figure 1 In the embodiment, the resistance value of the resistor R3 can be 10K ohms, one end of the resistor R3 is connected to the input end of the unity gain isolation buffer 112, the other end of the resistor R3 is connected to the drain end of the shutdown circuit PMOS tube 121 through the parasitic resistor 108, and the source end of the shutdown circuit PMOS tube 121 is connected to the power supply end of the circuit under test DUT. Figure 1 In the figure, RP is the parasitic resistor 108; DUT_VDD is the target test voltage, and the target test voltage can also be grounded through the capacitor C1.

[0091] The second voltage sampling connection branch generally includes only one connecting wire. Figure 1 An embodiment of the voltage sampling second connection branch using the remote compensation feedback line 111 is shown in FIG. When the voltage sampling second connection branch is connected to the input end of the unit gain isolation buffer 112 and the power supply end of the circuit under test DUT, the voltage sampling first connection branch can be short-circuited. When the voltage sampling connection unit includes both the voltage sampling first connection branch and the voltage sampling second connection branch, in order to select the near-end sampling connection state and the far-end sampling connection state, a branch switch can be set in the voltage sampling second connection branch. When the branch switch is closed, the configuration of the far-end sampling connection state is realized. Otherwise, the configuration of the near-end sampling connection state is realized. That is, only when the voltage sampling second connection branch is not selected, it can be configured in the near-end sampling connection state. Otherwise, as long as the voltage sampling second connection branch is selected, it is configured in the far-end sampling connection state. It should be understood that the second connection branch for voltage sampling can also adopt other forms, and the switching selection method between the first connection branch for voltage sampling and the second connection branch for voltage sampling can be selected according to needs, so as to meet the configuration requirements of the proximal sampling connection state and the distal sampling connection state.

[0092] In specific implementation, when in the near-end sampling connection state, Figure 1 The feedback loop should be: the output end of the low-dropout voltage regulator LDO unit 115 - the voltage sampling resistor 109 - the unit gain isolation buffer 112 - the feedback end of the low-dropout voltage regulator LDO unit 115. Since the on-resistance of the shutdown circuit PMOS tube 121 and the parasitic resistance 108 are outside the feedback loop, an additional voltage drop is generated. When the voltage reaches the power supply end of the circuit under test DUT, an error will be generated due to the voltage drop of the parasitic resistance 108 and the on-resistance of the shutdown circuit PMOS tube 121. When in the remote sampling connection state, since the resistance of the connecting wire approaches 0 ohms, which is less than the 10K ohm resistance of the voltage sampling resistor 109, the feedback loop at this time is mainly based on remote feedback, and the feedback loop becomes: the unit gain isolation buffer 112 at the power supply end of the circuit under test DUT - the feedback end of the low voltage drop regulator LDO unit 115. At this time, the feedback loop automatically compensates for the voltage drop error of the on-resistance of the turn-off circuit PMOS tube 121 generated by the parasitic resistance 108 and the current sampling resistor network, ensuring the target test voltage accuracy reaching the power supply end of the circuit under test DUT. The current sampling resistor network can be referred to Figure 1 and the corresponding instructions below.

[0093] It can be seen from the above description that, according to actual usage requirements, if the test current flowing through the circuit under test DUT is small, or the accuracy requirement of the target test voltage loaded to the power supply end of the circuit under test DUT is not high, the voltage drop on the parasitic resistor 108 and the on-resistance of the shutdown circuit PMOS tube 121 can be ignored. At this time, only the first connection branch for voltage sampling can be configured, that is, it can be configured as a proximal sampling connection state; when the test current flowing through the circuit under test DUT is large, or the voltage accuracy requirement is high, it should be configured in a remote sampling connection state, thereby improving the test accuracy of the circuit under test DUT.

[0094] In one embodiment of the present invention, the low voltage dropout LDO unit 115 includes a low voltage dropout LDO chip, wherein:

[0095] The low voltage dropout voltage regulator LDO chip is adaptively connected to the reference voltage generation unit and the isolation sampling feedback unit through a voltage regulation network;

[0096] The voltage regulating network includes a first voltage regulating resistor 113 and a second voltage regulating resistor 114, wherein the first end of the first voltage regulating resistor 113 and the first end of the second voltage regulating resistor 114 are both connected to the FB end of the low voltage dropout voltage regulator LDO chip;

[0097] The second end of the voltage regulating first resistor 113 is connected to the output end of the isolation sampling feedback unit;

[0098] The second end of the voltage regulating second resistor 114 and the GND end of the low voltage difference voltage stabilizing LDO chip are both connected to the output end of the reference voltage generating power supply, so as to load the test reference voltage to the GND end of the low voltage difference voltage stabilizing LDO chip, and load the test reference voltage to the FB end of the low voltage difference voltage stabilizing LDO chip through the second end of the voltage regulating second resistor 114;

[0099] The low voltage difference stabilizer LDO chip superimposes the terminal voltage of the GND terminal of the low voltage difference stabilizer LDO chip with the test reference voltage to generate a target test voltage, and loads the generated target test voltage to the power supply terminal of the circuit under test DUT.

[0100] Specifically, the low voltage difference voltage stabilizing LDO unit 115 can adopt the existing commonly used low voltage difference voltage stabilizing LDO chip, such as the low voltage difference voltage stabilizing LDO unit 115 can adopt a high voltage, high current and high performance LDO chip. Figure 1, an embodiment of a low voltage difference stabilized LDO unit 115 using a low voltage difference stabilized LDO chip is shown in the figure. In the figure, the low voltage difference stabilized LDO chip includes an IN terminal, an OUT terminal, a GND terminal and an FB terminal, wherein the IN terminal is connected to a voltage of +9V, the OUT terminal serves as the output terminal of the entire low voltage difference stabilized LDO unit 115, the FB terminal is the feedback terminal of the low voltage difference stabilized LDO chip, and the GND terminal is the ground terminal of the low voltage difference stabilized LDO chip.

[0101] Figure 1 FIG. 2 shows an embodiment in which the first voltage regulating resistor 113 uses a resistor R10 and the second voltage regulating resistor 114 uses a resistor R20. Figure 1 In the embodiment, the resistance value of the resistor R10 can be 15K ohms, and the resistance value of the resistor R20 can be 10K ohms. Of course, the resistors R10 and R20 can also adopt other resistance values ​​to satisfy the requirements of forming the required voltage regulation network.

[0102] In order to generate the target test voltage, the test reference voltage is loaded to the GND end of the low voltage difference voltage regulator LDO chip, and loaded to the FB end of the low voltage difference voltage regulator LDO chip through the resistor R20. At this time, it should be ensured that the static current (IQ) of the low voltage difference voltage regulator LDO chip does not exceed the output driving capability of the reference voltage generating unit (especially the voltage output type DAC unit 116). For the low voltage difference voltage regulator LDO chip, generally a switch tube MOSFET is included. Therefore, the current path of the large current output of the low voltage difference voltage regulator LDO chip is from the external input voltage to the switch tube MOSFET, and then to the OUT end of the switch tube MOSFET. The output current will not pass through the GND end of the low voltage difference voltage regulator LDO chip. Therefore, the reference voltage generating unit loads the test reference voltage to the GND end of the low voltage difference voltage regulator LDO chip. When it is sufficient to drive the GND end of the low voltage difference voltage regulator LDO chip, the test reference voltage can be superimposed on the GND short of the low voltage difference voltage regulator LDO chip, so that the output voltage of the low voltage difference voltage regulator LDO chip can be accurately controlled.

[0103] As the core component of the digital programmable power supply 100, the selection of the low voltage dropout voltage regulator LDO chip needs to be considered from three aspects: input voltage range, maximum output current and power supply rejection ratio PSRR. In specific implementation, the low voltage dropout voltage regulator LDO chip can be selected as the chip model ET5HAADJ. It can be seen that the maximum input voltage can be 20V, and the input voltage range is wider than the highest voltage in general embedded systems. It has sufficient voltage input redundancy, so that the digital programmable power supply 100 is not easily damaged by overvoltage. The maximum current in the test system generally does not exceed 1A. The low voltage dropout voltage regulator LDO chip can continuously output 1A current, which can meet the test current requirements of most circuits under test DUT. In addition, as the power supply of the circuit under test DUT, the power supply rejection ratio PSRR is crucial. A higher PSRR can suppress the fluctuation and noise interference at the input end of the digital programmable power supply, so that the power supply fluctuation and noise at the power supply end of the circuit under test DUT are optimized, and the stability and noise performance of the test of the circuit under test DUT are improved. When the chip model ET5HAADJ is used, the PSRR index is as high as 80dB@1kHz, which further ensures the output stability, accuracy and anti-interference performance of the digital programmable power supply 100. Furthermore, the IQ of the ET5HAADJ chip is only a maximum of 190μA, and the voltage output DAC unit 116 can sufficiently drive the GND end of this ET5HAADJ chip.

[0104] In one embodiment of the present invention, the reference voltage generating unit includes a voltage output DAC unit 116, a voltage reference unit 117 and an embedded unit 118, wherein:

[0105] The voltage reference unit 117 provides a power supply reference voltage required for the voltage output type DAC unit 116 to work;

[0106] The voltage reference unit 117 includes a low-noise LDO chip 401, a common-phase amplifier unit, and a first-order filter circuit connected in sequence, wherein the common-phase amplifier unit amplifies the 2.5V voltage output by the low-noise LDO chip 401 to 5V, filters the 5V voltage output by the common-phase amplifier unit using the first-order filter circuit, and loads the filtered 5V voltage to the voltage output DAC unit 116;

[0107] The embedded unit 118 is adaptively connected to the voltage output DAC unit 116. The embedded unit 118 sends a test reference voltage generation instruction to the voltage output DAC unit 116 to configure the voltage output DAC unit 116 to generate a corresponding test reference voltage based on the test reference voltage generation instruction, and load the generated test reference voltage to the low dropout regulator LDO unit 115.

[0108] In order to generate a programmable and adjustable test reference voltage, the reference voltage generating unit may include a voltage output DAC unit 116, a voltage reference unit 117 and an embedded unit 118. The voltage reference unit 117 may provide a power supply reference voltage for the voltage output DAC unit 116. For example, the 5V voltage reference unit 117 may be composed of a low-noise LDO chip 401, a common-mode amplifier 408 and a first-order filter circuit connected in sequence, that is, the voltage reference unit 117 may provide a 5V voltage. When the voltage reference unit 117 is used to provide the output voltage of the voltage output DAC unit 116, the output cost is low, the initial voltage accuracy is high, the temperature drift is small, and the output noise is low. The 5V reference voltage can be accurately and stably output, and when the power supply reference voltage of the voltage output DAC unit 116 is provided, the accuracy of the test reference voltage output by the voltage output DAC unit 116 can be improved.

[0109] Figure 4 , an embodiment of the voltage reference unit 117 is shown in FIG. 1 , specifically, the voltage reference unit 117 includes a low-noise LDO chip 401, a common-mode amplifier unit, and a first-order filter circuit connected in sequence, wherein the low-noise LDO chip 401 can generate a 2.5V voltage, and the low-noise LDO chip 401 can adopt an existing commonly used chip type that meets low noise and generates 2.5V. In the figure, an embodiment of a built-in first voltage setting resistor 402, a built-in second voltage setting resistor 403, a built-in amplifier 404, and a built-in reference voltage source 405 is provided in the low-noise LDO chip 401, the IN terminal of the low-noise LDO chip 401 is connected to the +5V voltage and the first end of the capacitor CIN, the EN terminal of the low-noise LDO chip 401 is connected to the first end of the capacitor CIN, and the second end of the capacitor CIN is connected.

[0110] Figure 4 An embodiment of a common-phase amplifier unit is also shown in the figure. In the figure, the common-phase amplifier unit includes a common-phase amplifier 408. The common-phase end of the common-phase amplifier 408 is connected to one end of the capacitor COUT and the OUT end of the low-noise LDO chip 401, and the other end of the capacitor COUT is grounded. The output end of the common-phase amplifier 408 is connected to one end of the second resistor 407 of the common-phase amplifier, and the other end of the second resistor 407 of the common-phase amplifier is connected to one end of the first resistor 406 of the common-phase amplifier and the inverting end of the common-phase amplifier 408. One end of the first resistor 406 of the common-phase amplifier and the GND end of the low-noise LDO chip 401 are both grounded.

[0111] Figure 4FIG. 2 shows an embodiment in which a second resistor 407 of a common-phase amplifier is formed by a resistor RF and a first resistor 406 of a common-phase amplifier is formed by a resistor RG. The resistance values ​​of the resistors RF and RG are both 1K ohms. At this time, the common-phase amplifier unit can achieve a 2-fold amplification, thereby amplifying the 2.5V voltage output by the low-noise LDO chip 401 to 5V.

[0112] Figure 4 , an embodiment of the first-order filter circuit is also shown, the first-order filter circuit includes a first-order low-pass filter resistor 409 and a first-order low-pass filter capacitor 410. In the figure, the resistor RISO is the first-order low-pass filter resistor 409, and C1 is the first-order low-pass filter capacitor 410. When working, the 5V voltage output by the common-phase amplifier unit can filter out high-frequency interference through the first-order filter circuit to obtain a low-noise, high-precision 5V reference voltage. In addition, the first-order low-pass filter resistor 409 in the first-order filter circuit can also isolate the output of the common-phase amplifier 408 and the first-order low-pass filter capacitor 410, which plays a role in stabilizing the common-phase amplifier 408.

[0113] It should be noted that the voltage reference unit 117 is usually directly composed of a commercial dedicated reference circuit, but its price is relatively expensive. In order to reduce the cost of mass use, in one embodiment of the present invention, a mass-produced low-noise LDO chip 401, a common-phase amplifier unit, and a first-order filter circuit are used to form the voltage reference unit 117. Specifically, the mass-produced low-noise LDO chip 401 is inexpensive, and its noise characteristics and commercial reference circuits are both at the μVrms level. Its output accuracy can be screened out by using a test fixture to select a circuit with an accuracy of 0.1%, so that its voltage output accuracy is close to the commercial reference circuit, which can also meet the high-precision test requirements of the circuit under test DUT.

[0114] Figure 1 In the embodiment, the power supply terminal of the voltage reference unit 117 is connected to a voltage of +9V, and outputs a 5V voltage required for the operation of the voltage output type DAC unit 116. The voltage output type DAC unit 116 has a programmable feature, such as the embedded unit 118 can load a test reference voltage generation instruction to the voltage output type DAC unit 116, and thereafter, the voltage output type DAC unit 116 can output a test reference voltage according to the reference voltage generation instruction. It can be seen that the test reference voltage generation instruction should be consistent with the test reference voltage to be output. The embedded unit 118 can adopt an existing commonly used form, such as the MCU, FPGA and other forms mentioned in the above background technology, which can be selected according to needs. The embedded unit 118 can generate a reference voltage generation instruction according to the working characteristics of the voltage output type DAC unit 116 and the test state of the circuit under test DUT, and load it into the voltage output type DAC unit 116.

[0115] In specific implementation, the voltage output DAC unit 116 can use a dual 12BIT high-precision rail-to-rail voltage output DAC chip, such as a DAC chip of model DAC122S085. At this time, compared with the current output DAC, it is no longer necessary to perform current-voltage IV conversion, saving the IV conversion circuit and reducing hardware overhead. The voltage output DAC unit 116 has an accuracy of 12BIT and can output 4096 levels of voltage. It is a voltage output DAC and the output is rail-to-rail output. When the reference voltage is 5V, it can output a test reference voltage of 0-5V; in addition, the output current of the voltage output DAC unit 116 is greater than 50mA, and its output is connected to the GND end of the low-dropout voltage regulator LDO chip, which is sufficient to drive the low-dropout voltage regulator LDO chip with an IQ lower than 1mA. The embedded unit 118 controls the test reference voltage output by the voltage output DAC unit 116 through a three-wire SPI communication port, which can save the IO port resources of the embedded unit 118 compared with the parallel port control.

[0116] The following is an example of the process of generating the target test voltage, specifically:

[0117] According to the output voltage requirement, the embedded unit 118 determines the test reference voltage value output by the voltage output DAC unit, generates a conversion instruction corresponding to the test reference voltage, and loads the reference voltage generation instruction to the voltage output DAC unit 116. Figure 1 In the embodiment, the embedded unit 118 writes the reference voltage generation instruction into the voltage output type DAC unit 116 through the SPI interface, wherein the reference voltage generation instruction may be hexadecimal data.

[0118] The voltage output DAC unit 116 generates a corresponding test reference voltage according to the reference voltage generation instruction, and loads the test reference voltage to the GND terminal of the low voltage dropout voltage regulator LDO chip and the second terminal of the voltage regulating second resistor 114. When the low voltage dropout voltage regulator LDO chip generates a target test voltage based on the voltage regulating network and the test reference voltage, the corresponding expression can be:

[0119] VOUT=(1+R1 / R2)*VREF_LDO+V DAC ,

[0120] Among them, VOUT is the target test voltage, V DAC The reference voltage is tested, VREF_LDO is the voltage at the FB terminal of the low voltage dropout regulator LDO chip, R1 is the resistance value of the first voltage regulating resistor 113 , and R2 is the resistance value of the second voltage regulating resistor 114 .

[0121] It can be seen from the above description that the resistance value of R1 can be 15K, and the resistance value of R2 can be 10K. The voltage VREF_LDO at the FB end of the low voltage dropout regulator LDO chip is 0.6V. Since the reference voltage of the voltage output DAC unit 116 is 5V, the range of the test reference voltage output by the voltage output DAC unit 116 is 0V-5V; when the test reference voltage is 0V, the target test voltage is calculated to be 1.5V; when the test reference voltage is 5V, the target test voltage is calculated to be 6.5V. Therefore, the ratio of the voltage adjustment first resistor 113 and the voltage adjustment second resistor 114 can be adjusted according to the specific test voltage requirements, and the voltage range of the target test voltage can be further adjusted.

[0122] In one embodiment of the present invention, the digital programmable power supply 100 further includes a test current measurement unit for measuring the current flowing through the circuit under test DUT, wherein:

[0123] The current measurement unit includes a current sampling resistor network, a sampling resistor selection network and a test current processing unit.

[0124] The current sampling resistor network includes a plurality of current sampling resistors distributed in parallel, and a current sampling resistor is configured to be connected in series between the output end of the low dropout voltage regulator LDO unit 115 and the power supply end of the circuit under test DUT;

[0125] The sampling resistor selection network is adaptively connected to the current sampling resistor network and the test current processing unit, and the test current processing unit configures the corresponding current sampling resistors in the current sampling resistor network to form a current sampling target equivalent resistor through the sampling resistor selection network;

[0126] The test current flowing through the DUT is converted into a load voltage using the formed current sampling target equivalent resistance.

[0127] The test current processing unit performs amplification processing and ADC sampling processing on the load voltage in sequence to generate a load sampling voltage after the ADC sampling processing, and determines the test current flowing through the circuit under test DUT based on the load sampling voltage and the current sampling target equivalent resistance.

[0128] Specifically, the digital programmable power supply 100 also includes a test current measurement unit, that is, the test current measurement unit can be used to measure the test current in the test of the circuit under test DUT. In order to meet the requirements for test current measurement, the current measurement unit includes a current sampling resistor network, a sampling resistor selection network and a test current processing unit, wherein the test current flowing through the circuit under test DUT can be converted into a load voltage by using the current sampling resistor network, and in order to adapt to different test currents, the current sampling resistor network should include a number of current sampling resistors, and the corresponding current sampling resistor is selected by the sampling resistor selection network, and the corresponding current sampling target equivalent resistance can be generated by the selected current sampling resistor. It can be understood that the current sampling target equivalent resistance should be adapted to the current test current of the circuit under test DUT, and the adaptation to the test current means that the test current can be effectively converted into the corresponding load voltage.

[0129] After the test current is converted into a load voltage through the current sampling target equivalent resistance, the load voltage is processed by the test current processing unit so that the test current currently flowing through the circuit under test DUT can be obtained after processing. The processing of the load voltage may include amplification processing and ADC sampling processing. The form of the test current processing unit and the method and process of processing can refer to the corresponding instructions below.

[0130] In one embodiment of the present invention, in the current sampling resistor network, the current sampling resistor connected in series between the output end of the low dropout voltage regulator LDO unit 115 and the power supply end of the circuit under test DUT is configured as the normally connected current sampling resistor 107, and the remaining current sampling resistors are configured as optional current sampling resistors, wherein,

[0131] The corresponding resistance value of the normally connected current sampling resistor 107 is greater than the corresponding resistance value of any optional current sampling resistor;

[0132] The sampling resistor selection network includes a plurality of relays and a relay driving circuit for driving the switching state of the relays, wherein:

[0133] An optional current sampling resistor is adaptively connected to a normally open contact of a relay. When the normally open contact of the corresponding relay is driven to close by the relay driving circuit, the optional current sampling resistor is selected, and the selected optional current sampling resistor is connected in parallel with the normally connected current sampling resistor to form a current sampling target equivalent resistor based on the normally connected current sampling resistor and the selected optional current sampling resistor.

[0134] It should be noted that, generally, multiple current sampling resistors may be provided in the current sampling resistor network, and the resistance values ​​of the multiple current sampling resistors may not be completely equal or completely unequal, and may be selected according to actual needs. The multiple current sampling resistors are connected in parallel.

[0135] In order to ensure the stability of the feedback loop of the digital programmable power supply 100 and avoid the abnormal high-voltage overshoot voltage in the power supply output when the power supply feedback loop is instantly switched from an open-loop state to a closed-loop state, thereby damaging the circuit under test DUT, the feedback loop of the power supply needs to work in a closed-loop state all the time. Therefore, in the current sampling resistor network, a current sampling resistor is used as a normally connected current sampling resistor 107, one end of the normally connected current sampling resistor 107 is connected to the OUT end of the low-voltage difference voltage regulator LDO chip, and the other end of the normally connected current sampling resistor 107 should be adaptively connected to the power supply end of the circuit under test DUT, that is, a state of being connected in series between the low-voltage side voltage regulator LDO chip and the power supply end of the circuit under test DUT is formed. Figure 1 FIG. 1 shows an embodiment of using resistor RS4 to form a normally connected current sampling resistor 107. Figure 1 In the embodiment, the resistance value of resistor RS4 can be 10K ohms.

[0136] Figure 1 In the embodiment, three optional current sampling resistors are also shown, that is, Figure 1 , an embodiment in which four current sampling resistors are provided in the current sampling resistor network is shown. At this time, after one current sampling resistor is configured as the normally connected current sampling resistor 107, the other three current sampling resistors respectively form corresponding optional current sampling resistors, wherein the three optional current sampling resistors are respectively a first optional current sampling resistor 104, a second optional current sampling resistor 105 and a third optional current sampling resistor 106. Figure 1 In the figure, an embodiment is shown in which a first optional current sampling resistor 104 is formed by a resistor RS1, a second optional current sampling resistor 105 is formed by a resistor RS2, and a third optional current sampling resistor 106 is formed by a resistor RS3; when the current sampling resistor network is other cases, please refer to the description here, which will not be repeated here.

[0137] Figure 1 In the figure, the resistance value of resistor RS1 can be 1K ohm, the resistance value of resistor RS2 can be 10 ohm, and the resistance value of resistor RS3 can be 0.1 ohm. It can be seen that the resistance values ​​of the optional current sampling resistors are all smaller than the resistance value of the normally connected current sampling resistor 107. At this time, it can be satisfied that within the current range from ampere to microampere, high-precision sampling of the test of the circuit under test DUT can be guaranteed.

[0138] It should be understood that for any optional current sampling resistor, specifically, the current current sampling resistor can be selected. After being selected, it forms a parallel connection with the normally connected current sampling resistor 107. Generally, one optional current sampling resistor can be selected each time, and after being connected in parallel with the normally connected current sampling resistor 107, the corresponding current sampling target equivalent resistance can be generated.

[0139] In order to realize the selection of the optional current sampling resistor, the sampling resistor selection network may include a plurality of relays and relay driving circuits, wherein one relay driving circuit may be used to drive all the relays. When the relays are driven, the energized state of the relay coils may be controlled, thereby controlling the switch state of the corresponding contacts of the relays. At this time, the gear switching relay array 103 may be formed by the relays.

[0140] In a specific implementation, an optional current sampling resistor is adaptively connected to a normally open contact of a relay. When the normally open contact of the corresponding relay is driven to close by the relay driving circuit, the optional current sampling resistor is selected. Figure 1 In the embodiment, the current sampling resistor RS1 cooperates with the normally open contact of the relay K1, the current sampling resistor RS2 cooperates with the normally open contact of the relay K2, and the current sampling resistor RS3 cooperates with the normally open contact of the relay K3. When the relay driving circuit energizes the coil of the relay K1, the normally open contact of the relay K1 is closed. At this time, the current sampling resistor RS is selected. For other situations in which the current sampling resistors are selected, please refer to the description here, and they will not be listed here one by one.

[0141] For the relay drive circuit 102, generally, discrete devices such as triode resistors or dedicated circuits, such as Darlington integrated circuits of model ULN2803, can be used to implement it. Since the digital program-controlled power supply 100 of the present invention has more than one channel in actual testing, when a multi-channel digital program-controlled power supply 100 is used, the input end of the relay drive circuit 102 needs an additional embedded IO port to control. When a multi-channel digital program-controlled power supply 100 is used, more IO port lines are required, while the IO port resources of the embedded unit 118 are limited. Therefore, in one embodiment of the present invention, the digital program-controlled power supply 100 can use a 74HC595 with serial input and parallel output to drive the relay, that is, the relay drive circuit 102 can use a chip of model 74HC595. Specifically, the current sinking driving capability of the 74HC595 chip is about 50mA, which is sufficient to drive a relay coil with a current of 10mA-20mA.

[0142] It should be noted that the 74HC595 chip is not a common relay driver chip in the prior art. Since the 74HC595 chip is a common circuit of a serial-input and parallel-output shift register with a latch function, in order to meet the embedded integrated circuit test requirements, the present invention cooperates the 74HC595 chip with the embedded unit 118 to effectively realize the driving of the relay. Specifically, the embedded unit 118 writes configuration data through the serial communication interface of the 74HC595 chip, such as OE, RCLK, SRCK, and SER ports, to set the output logic high and low of the 8 ports corresponding to the 74HC595 chip, such as QA-QH. QA-QH is connected to the negative end of the corresponding relay coil, so as to control the charged state of the relay coil, and then control the contact state of the relay. The state of the corresponding port of the 74HC595 chip can be latched and maintained. When the relay control data transmission is completed, the IO port controlling the OE, RCLK, SRCK, and SER ports can be used for other purposes.

[0143] In addition, multiple 74HC595 chips can be cascaded through QH' port 303, and only 4 embedded IO ports are needed to control more than a dozen relays, further expanding the number of relay control channels, meeting the gear control of multiple digital programmable power supplies 100, and greatly reducing the use of IO port resources of the embedded system. Figure 3 1 shows an embodiment of cascading. In the figure, when cascading, a first 74HC595 chip 302 and a second 74HC595 chip 304 are included. The serial communication interface group 301 (including OE port, RCLK port, SRCK port, SER port) of the first 74HC595 chip 302 is connected to the SPI interface of the embedded unit 118, and the serial communication interface group (OE, RCLK, SRCK) of the second 74HC595 chip 304 is connected to the serial communication interface group (OE, RCLK, SRCK) of the first 74HC595 chip 302. ) are connected in parallel, and then connected to the SPI interface of the embedded unit 118, the SER port in the serial communication interface of the second 74HC595 chip 304 is connected to the QH' of the first 74HC595 chip 302. When writing data, two 8BIT data are written through the serial communication interface (OE, RCLK, SRCK, SER) of the first 74HC595 chip 302, and then through the rising edge of the RCLK clock, the latching of the two 8BIT 16-way relay driving data can be completed, so that the control of 16-way relays can be completed only through the 4-wire serial interface.

[0144] Figure 3In the embodiment, the first 74HC595 chip 302 and the second 74HC595 chip 304 each include an 8BIT shift register 305, an 8BIT latch 306 and an 8BIT tri-state output unit 307. At this time, a parallel output drive pin group 308 can be obtained through two 8BIT tri-state output units 307. The parallel output drive pin group 308 can be used to drive a relay array 309. The relay array 309 may include the relays mentioned above and other correspondingly extended relays, which will not be described in detail here. For other cascade situations, please refer to Figure 3 As well as the cascade description here, no examples are given here one by one.

[0145] In one embodiment of the present invention, the test current processing unit includes an instrumentation amplifier 101 and an embedded unit 118 adapted to be connected to the instrumentation amplifier 101, wherein:

[0146] The instrument amplifier 101 is connected to the current sampling resistor network, and the load voltage is amplified and sampled by ADC by the instrument amplifier 101, and the generated load sampling voltage is loaded into the embedded unit.

[0147] Based on the load sampling voltage and the current sampling target equivalent resistance, the embedded unit 118 determines the test current flowing through the circuit under test DUT.

[0148] Figure 1 An embodiment of a test current processing unit is shown in the figure. In the figure, the test current processing unit may include an instrument amplifier 101 and an embedded unit 118. At this time, the embedded unit 118 is simultaneously connected to the voltage output DAC unit 116 and the instrument amplifier 101. The instrument amplifier 101 can adopt an existing commonly used form. The instrument amplifier 101 can be used to implement the above-mentioned amplification processing and ADC sampling processing.

[0149] It should be noted that multiple current sampling resistors are provided in the current sampling resistor network to match different test current gears. The current sampling resistors should be divided into current gears according to the full-scale input voltage range of the instrumentation amplifier 101 and the range of the current value to be sampled. Figure 1When the current sampling resistor network includes four current sampling resistors, four current gears can be formed. Specifically, the voltage drop on the current sampling resistor and the power dissipation should not be too large, and the input voltage index of the instrument amplifier 101 is referred to, and the sampling current gear and the sampling resistor value are set as follows: 1.6A gear, the full-scale input voltage range of the instrument amplifier 101 is 160mV, and the current sampling target equivalent resistance is 0.1Ω; 16mA gear, the full-scale input voltage range of the instrument amplifier 101 is 160mV, and the current sampling target equivalent resistance is 10Ω; 160μA gear, the full-scale input voltage range of the instrument amplifier 101 is 160mV, and the current sampling target equivalent resistance is 1KΩ; 16μA gear, the full-scale input voltage range of the instrument amplifier 101 is 160mV, and the current sampling target equivalent resistance is 10KΩ; in order to ensure the accuracy of current sampling, all current sampling resistors use high-precision resistors with an accuracy of 0.1% and a temperature drift of 10PPM.

[0150] It should be noted that, since the normally connected current sampling resistor 107 is set to be in a series state, the current sampling target equivalent resistance can be selected according to actual conditions. For example, when the current range is 16μA, the normally connected current sampling resistor 107 can provide a current sampling target equivalent resistance of 10KΩ. At this time, the remaining optional current sampling resistors are not selected; when the current range is 160μA, the current sampling target equivalent resistance should be formed by connecting a 10KΩ resistor in parallel with a 1KΩ resistor. At this time, the normally open contact of relay K1 should be closed, and the normally open contacts of relay K2 and relay K3 should remain in an open state. The current sampling target equivalent resistance should be 0.909KΩ. For other situations, please refer to the description here and will not be repeated here.

[0151] In the specific implementation, different current gear relays are selected. The current flowing through the 160μA and 16mA current measurement gears is not large, so a single-pole single-throw relay is used. For the 1.6A current gear, due to the large current, a double-pole double-throw relay is used for connection. The number of relay contacts is increased to reduce the current load of a single contact of the relay, ensuring that the relay contacts are not damaged during long-term high-current measurement while reducing the contact resistance of the relay, thereby improving the stability and accuracy of high-current gear measurement; Figure 1 FIG. 2 shows an embodiment in which the relay K3 is a double-pole double-throw relay.

[0152] It can be seen from the above description that when sampling the target test voltage, the connection between the circuit under test DUT and the voltage regulation network connected to the FB terminal of the low-dropout voltage regulator LDO chip can be isolated by the unit gain isolation buffer 112, so that the current flowing through the circuit under test DUT is separated from the current flowing through the voltage regulation network, and the instrument amplifier 101 can only sample the current flowing through the circuit under test DUT, so that the measurement of the test current flowing through the circuit under test DUT is more accurate.

[0153] It should be noted that the operational amplifier used in the unit gain isolation buffer 112 needs to be considered from three aspects: input bias current, input offset voltage, and input voltage range: in order to ensure the accuracy of the sampling current, especially the current at the μA level, the input bias current of the unit gain isolation buffer 112 cannot be too large, and an operational amplifier with an input bias current of ±5 pA level is preferably used. In order to ensure the accuracy of the feedback voltage, the offset voltage of the operational amplifier cannot be too large, and an operational amplifier with an offset voltage of ±5 µV is preferably used to ensure the accuracy of the feedback voltage. Since most embedded systems lack negative power rails, in order to process a sufficiently wide feedback voltage signal, an operational amplifier with both input and output rail-to-rail input and output (RRIO) is selected here to form the unit gain isolation buffer 112, and the power supply of the operational amplifier is set to +9V, which is sufficient to meet the voltage adjustment range of 1.5V-6.5V of the digital programmable power supply 100 of the present invention.

[0154] In specific implementation, the instrumentation amplifier 101 may adopt an existing commonly used form, such as an amplifier chip of model INA229. Figure 1 and Figure 2 1 shows an embodiment of an amplifier chip of model INA229 used in the instrument amplifier 101. As can be seen from the figure, the instrument amplifier 101 has an IN+ terminal and an IN- terminal, and the corresponding input bias current of the IN+ terminal and the IN- terminal is as low as a typical value of 0.1nA, and the input offset voltage VOS is only a typical value of ±0.3µV, which ensures the accuracy of the test current processing of the circuit under test DUT. The instrument amplifier 101 has a built-in 20BIT ADC unit 201, and the conversion accuracy of the ADC unit 201 is much higher than the 12BIT ADC in the embedded unit 118, which further improves the accuracy of sampling and processing the test current of the circuit under test DUT.

[0155] Figure 2In the embodiment, the IN+ and IN- terminals of the instrument amplifier 101 are connected to the front-end analog signal multiplexer 202 of the instrument amplifier 101, and the IN+ and IN- terminals constitute differential connection terminals. The IN+ and IN- terminals can be connected to the two corresponding ends of the current sampling target equivalent resistance. The differential signal is sampled and converted by the ADC unit 201 in the instrument amplifier 101, and the data is stored in the Voltage register of the analog storage register 203. The embedded unit 118 obtains the voltage value after conversion through the instrument amplifier SPI interface 204. Thereafter, the test current flowing through the circuit under test DUT is calculated in the embedded unit 118. If the current test current exceeds the current gear, the embedded unit 118 controls the relay drive circuit 102 to drive the corresponding relay through the SPI interface to select the appropriate current gear, thereby improving the accuracy and reliability of measuring the test current flowing through the circuit under test DUT.

[0156] In a specific implementation, when the embedded unit 118 calculates the test current flowing through the circuit under test DUT, a feasible calculation method is: I DUT =V DELTA / R S , where V DELTA is the load sampling voltage converted by the instrumentation amplifier 101, R S is the equivalent resistance value of the current sampling target.

[0157] In one embodiment of the present invention, the instrument amplifier 101 is also connected to the power supply terminal of the circuit under test DUT, wherein:

[0158] Setting a low voltage alarm threshold and / or a high voltage alarm threshold in the instrumentation amplifier 101;

[0159] The instrument amplifier 101 compares the target test voltage at the power supply end of the circuit under test DUT with the low voltage alarm threshold and the high voltage alarm threshold. When the target test voltage at the power supply end of the circuit under test DUT matches lower than the low voltage alarm threshold or higher than the high voltage alarm threshold, the instrument amplifier 101 outputs an alarm message.

[0160] It should be noted that when the instrument amplifier 101 adopts the above-mentioned form, the target test voltage of the circuit under test DUT can also be monitored. When the power supply of the circuit under test DUT is monitored, the VBUS terminal of the instrument amplifier 101 is connected to the power supply terminal of the circuit under test DUT. At this time, the power supply voltage of the circuit under test DUT is sent to the instrument amplifier 101 through the VBUS terminal, and the target test voltage is loaded into the front-end analog signal multiplexer 202 in the instrument amplifier 101 through the VBUS terminal. Thereafter, the ADC unit 201 is used for sampling and voltage conversion to store the converted voltage in the Voltage register of the analog storage register 203.

[0161] The embedded unit 118 reads the voltage value stored in the Voltage register through the instrument amplifier SPI interface 204. The embedded unit 118 can also write the low voltage alarm threshold and the high voltage alarm threshold into the alarm threshold setting register 207 of the instrument amplifier 101 through the instrument amplifier SPI interface 204. The low voltage alarm threshold and the high voltage alarm threshold can be set to + / - 5% of the set target test voltage. For example, the low voltage alarm threshold can be the target test voltage * 0.95, and the high voltage alarm threshold can be the target test voltage * 1.05. That is, for the circuit to be tested DUT, after determining the target test voltage, the corresponding high voltage alarm threshold and the low voltage alarm threshold can be determined.

[0162] Specifically, the alarm threshold comparator 206 in the instrument amplifier 101 can compare the low voltage alarm threshold and the high voltage alarm threshold in the alarm threshold setting register 207 with the voltage value of the Voltage register in the analog storage register 203. When the voltage value in the Voltage register of the analog storage register 203 matches the high voltage alarm threshold or the low voltage alarm threshold in the alarm threshold setting register 207, the ALERT alarm port 205 outputs a low level alarm message. The ALERT alarm port 205 of the instrument amplifier 101 is connected to the general input and output port GPIO of the embedded unit 118. After the general input and output port GPIO of the embedded unit 118 detects a low level, the embedded unit 118 enters the interrupt service program. The embedded unit 118 processes the abnormal voltage, such as reducing the target test voltage output by the above-mentioned low voltage difference regulator LDO chip, and / or reducing the current value of the current gear to prevent overvoltage and overcurrent from damaging the circuit under test DUT.

[0163] In the specific implementation, the target test voltage matches the low-voltage alarm threshold, which specifically means that after the target test voltage is compared with the low-voltage alarm threshold, the condition for outputting the alarm information is met, such as the target test voltage is lower than the low-voltage alarm threshold, or the difference between the two is within a preset numerical range; the case where the target test voltage matches the high-voltage alarm threshold can be referred to the description here, such as the target test voltage matches the high-voltage alarm threshold, which specifically means that after the target test voltage is compared with the high-voltage alarm, the target test voltage is greater than the high-voltage alarm threshold, or the difference between the two is higher than a preset numerical range. In addition, the level state of the alarm information output by the ALERT alarm port 205 can be selected according to actual conditions, such as it can also be a high level state.

[0164] In one embodiment of the present invention, the instrument amplifier 101 is also adaptively connected to the output end of the circuit under test DUT and the low dropout voltage regulator LDO unit through the automatic shutdown circuit 122, wherein:

[0165] When the instrumentation amplifier 101 outputs the alarm information, the automatic shutdown circuit 122 is controlled to cut off the target test voltage provided by the output terminal of the low dropout voltage regulator LDO unit to the circuit under test DUT.

[0166] As can be seen from the above description, when monitoring the target test voltage, the instrumentation amplifier 101 can output an alarm message. In order to ensure the reliability of the DUT test, the automatic shutdown circuit 122 can also be used to cut off the connection between the low-dropout voltage regulator LDO unit and the power supply terminal of the DUT, that is, to cut off the target test voltage loaded by the low-voltage side voltage regulator LDO unit to the power supply terminal of the DUT, and stop the test of the DUT.

[0167] When the ALERT alarm port 205 outputs a low level alarm message, Figure 1 An embodiment of the automatic shutdown circuit 122 is shown in the figure. In the figure, the automatic shutdown circuit 122 includes a shutdown circuit pull-up resistor 119, a shutdown circuit NMOS tube 120 and a shutdown circuit PMOS tube 121, wherein the ALERT alarm port 205 of the instrument amplifier 101 is connected to the gate end of the shutdown circuit NMOS tube 120, the source end of the shutdown circuit NMOS tube 120 is grounded, the drain end of the shutdown circuit NMOS tube 120 is connected to the shutdown circuit pull-up resistor 119 and the gate end of the shutdown circuit PMOS tube 121, the other end of the shutdown circuit pull-up resistor 119 is connected to the output end of the low voltage difference regulator LDO unit, the source end of the shutdown circuit PMOS tube 121 is connected to the power supply end of the circuit to be tested DUT, the drain end of the shutdown circuit PMOS tube 121 is connected to one end of the parasitic resistor 108, and the other end of the parasitic resistor 108 is connected to the current sampling resistor network.

[0168] Figure 1 In the illustrated embodiment, the shutdown circuit NMOS transistor 120 is an NMOS transistor M2 , the shutdown circuit PMOS transistor 121 is a PMOS transistor M1 , and the shutdown circuit pull-up resistor 119 is a resistor R4 .

[0169] When the ALERT alarm port 205 of the instrumentation amplifier 101 outputs a low-level alarm message, the shutdown circuit NMOS tube 120 is turned off, and the drain terminal of the shutdown circuit NMOS tube 120 is connected to the output of the low-voltage difference voltage regulator LDO unit through the shutdown circuit pull-up resistor 119. The drain terminal of the shutdown circuit NMOS tube 120 is at a high potential. Since the drain terminal of the shutdown circuit NMOS tube 120 is connected to the gate of the shutdown circuit PMOS tube 121, the gate terminal of the shutdown circuit PMOS tube 121 is also at a high potential. At this time, the shutdown circuit PMOS tube 121 is also turned off, cutting off the connection between the output terminal of the entire low-voltage difference voltage regulator LDO unit and the power supply terminal of the circuit under test DUT.

[0170] As can be seen from the above description, the automatic shutdown circuit 122 can realize double protection of the circuit under test DUT during the test. When the target test voltage output by the low voltage difference voltage regulator LDO unit meets the test of the circuit under test DUT, the ALERT alarm port 205 of the instrument amplifier 101 outputs a high level, at which time, the shutdown circuit NMOS tube 120 is turned on, and the drain terminal of the shutdown circuit NMOS tube 120 is at a low potential. Since the drain terminal of the shutdown circuit NMOS tube 120 is connected to the gate terminal of the shutdown circuit PMOS tube 121, the gate terminal of the shutdown circuit PMOS tube 121 is also at a low potential, so the shutdown circuit PMOS tube 121 is also turned on, and the target test voltage output by the low voltage difference voltage regulator LDO unit can be loaded to the power supply terminal of the circuit under test DUT.

[0171] It should be noted that the target test voltage meets the test requirements of the circuit under test (DUT), specifically, the target test voltage meets the high and low voltage alarm thresholds and is lower than the high voltage alarm threshold, that is, the target test voltage is consistent with the test voltage of the normal test of the circuit under test (DUT).

[0172] In summary, a power supply test method suitable for embedded integrated circuit testing can be obtained. In one embodiment of the present invention, for any circuit under test DUT, the digital programmable power supply 100 described above is used to provide a target test voltage to test the circuit under test DUT at the target test voltage.

[0173] Specifically, the method and process of using the digital programmable power supply 100 to test the DUT in the circuit under test can refer to the corresponding description above, which will not be repeated here.

[0174] It can be seen from the above description that the present invention uses the voltage output DAC unit 116 to programmatically adjust the target test voltage output by the low-dropout voltage regulator LDO unit 115 to adapt to the test requirements of different circuits under test DUT. The voltage adjustment is completed by software and is independent of hardware, which solves the key problems in the test production process, such as the need for manual adjustment, incorrect output voltage, and inaccurate output voltage.

[0175] The use of a high-precision, low-noise voltage reference unit 117 and a voltage output DAC unit 116 allows the test reference voltage output by the digital programmable power supply 100 to be accurately adjusted, with an output range of 1.5V-6.5V and 4096 voltage adjustment steps. The use of a low-dropout voltage regulator LDO unit 115 with high input voltage, high PSRR, low IQ, and high current output optimizes the fluctuation and noise of the target test voltage loaded to the power supply end of the circuit under test DUT, improves the stability and noise performance of the circuit under test DUT during testing, and improves the input voltage tolerance.

[0176] A unit gain isolation buffer 112 is constructed using a low input bias current and low offset operational amplifier, and can be configured to form a near-end sampling connection state or a far-end sampling connection state. When in the far-end sampling connection state, it can effectively compensate for the voltage error caused by the parasitic resistance 108 on the power supply path and the current sampling resistor network; at the same time, it can also isolate the test current flowing through the device under test DUT and the current flowing through the voltage regulation network. In subsequent current measurements, the instrument amplifier 101 can accurately measure the test current flowing through the device under test DUT.

[0177] The relay driving circuit 102 may use a 74HC595 chip, which has a serial-in parallel-out shift register with a latching function. When driving multiple relays, the number of relay driving paths can be cascaded to expand, greatly saving IO port resources of the embedded unit 118 .

[0178] The instrument amplifier 101 uses a chip with a built-in 20BIT ADC unit 201, which can accurately measure the test current flowing through the circuit under test DUT. The built-in 20BIT ADC unit 201 of the instrument amplifier 101 can greatly improve the current measurement accuracy. The ADC unit 201 in the instrument amplifier 101 uses a serial SPI interface to communicate with the embedded unit 118, saving the hardware resources of the embedded unit 118. The instrument amplifier 101 can realize high and low voltage threshold alarms, which facilitates the embedded unit 118 to monitor whether the target test voltage at the power supply end of the circuit under test DUT is normal. At the same time, the ALERT alarm port 205 of the instrument amplifier 101 is connected to the automatic shutdown circuit 122, which can automatically cut off the power supply to the circuit under test DUT when an abnormal voltage is output. Combined with the embedded operation of reducing the voltage and switching the small current gear, dual protection of the power supply is achieved. Compared with the DPS power supply board in the commercial integrated circuit automatic test equipment ATE, the digital program-controlled power supply 100 of the present invention requires very few devices, occupies a small PCB area, and is easy to be integrated into an embedded test system. In addition, compared with the DPS power supply board in commercial integrated circuit automatic test equipment ATE, the implementation cost is low and it is easy to use in mass production.

[0179] In summary, the present invention solves the problems in embedded testing such as the inability to programmatically adjust the voltage, the inability to accurately set the output voltage, the lack of remote voltage compensation, and the inability to accurately measure the test current flowing through the circuit under test DUT, thereby improving the voltage and current accuracy and stability of the test. At the same time, the PCB area occupied is small and easy to be integrated on the embedded test board, and the cost is low, which not only reduces the test cost, but also meets the requirements of accurate, stable, programmable, and measurable current of the embedded test power supply during mass test production.

Claims

1. A digital programmable power supply suitable for embedded integrated circuit testing, characterized in that: The digital program-controlled power supply comprises: A reference voltage generating unit, which generates an adjustable test reference voltage by program control, and loads the generated test reference voltage to a low dropout voltage regulator LDO unit; A low-dropout voltage regulator LDO unit is adaptively connected to the reference voltage generating unit and the circuit under test DUT, receives the test reference voltage loaded by the reference voltage generating unit, and provides a target test voltage to the connected circuit under test DUT based on the test reference voltage; The isolated sampling feedback unit is adaptively connected to the circuit under test DUT and the low voltage difference voltage regulator LDO unit, and is used to sample the target test voltage loaded on the power supply end of the circuit under test DUT, and negatively feed back the test sampling voltage generated by the sampling to the low voltage difference voltage regulator LDO unit, so that the low voltage difference voltage regulator LDO unit provides a stable target test voltage to the circuit under test DUT under the test sampling voltage, wherein, When sampling the target test voltage, the target test voltage and the test sampling voltage are isolated from each other; The reference voltage generating unit includes a voltage output DAC unit, a voltage reference unit and an embedded unit, wherein: The voltage reference unit provides a power supply reference voltage required for the voltage output type DAC unit to work; The voltage reference unit includes a low-noise LDO chip, a common-phase amplifier unit, and a first-order filter circuit connected in sequence, wherein the common-phase amplifier amplifies the 2.5V voltage output by the low-noise LDO chip to 5V, uses the first-order filter circuit to filter the 5V voltage output by the common-phase amplifier, and loads the filtered 5V voltage to the voltage output DAC unit; The embedded unit is adaptively connected to the voltage output DAC unit, and the embedded unit sends a test reference voltage generation instruction to the voltage output DAC unit to configure the voltage output DAC unit to generate a corresponding test reference voltage based on the test reference voltage generation instruction, and load the generated test reference voltage to the low dropout voltage regulator LDO unit; The low voltage dropout voltage regulator LDO unit includes a low voltage dropout voltage regulator LDO chip, wherein: The low voltage dropout voltage regulator LDO chip is adaptively connected to the reference voltage generation unit and the isolation sampling feedback unit through a voltage regulation network; The voltage regulating network comprises a first voltage regulating resistor and a second voltage regulating resistor, wherein a first end of the first voltage regulating resistor and a first end of the second voltage regulating resistor are both connected to the FB end of the low voltage dropout voltage regulator LDO chip; The second end of the voltage regulating first resistor is connected to the output end of the isolation sampling feedback unit; The second end of the voltage regulating second resistor and the GND end of the low voltage difference voltage stabilizing LDO chip are both connected to the output end of the reference voltage generating power supply, so as to load the test reference voltage to the GND end of the low voltage difference voltage stabilizing LDO chip, and load it to the FB end of the low voltage difference voltage stabilizing LDO chip through the second end of the voltage regulating second resistor; The low voltage difference stabilizer LDO chip superimposes the terminal voltage of the GND terminal of the low voltage difference stabilizer LDO chip with the test reference voltage to generate a target test voltage, and loads the generated target test voltage to the power supply terminal of the circuit under test DUT.

2. The digital programmable power supply suitable for embedded integrated circuit testing according to claim 1 is characterized in that: When sampling the target test voltage, the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured to be in a near-end sampling connection state or a far-end sampling connection state, wherein: When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as a remote sampling connection state, the isolated sampling feedback unit directly performs voltage sampling on the target test voltage at the power supply terminal of the circuit under test DUT; When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as a near-end sampling connection state, the isolated sampling feedback unit samples the target test voltage at the power supply terminal of the circuit under test DUT at least through the voltage sampling resistor.

3. The digital programmable power supply suitable for embedded integrated circuit testing according to claim 2 is characterized in that: The isolated sampling feedback unit includes a unit gain isolation buffer and a voltage sampling connection unit adapted to be connected to the input end of the unit gain isolation buffer, wherein: The input end of the unity gain isolation buffer is adaptively connected to the power supply end of the circuit under test DUT through the voltage sampling connection unit, so as to use the voltage sampling connection unit to perform voltage sampling on the target test voltage at the power supply end of the circuit under test DUT, and load the generated test sampling voltage to the unity gain isolation buffer; The output end of the unit gain isolation buffer is adapted to be connected with the low voltage dropout voltage regulator LDO unit, and the test sampling voltage is fed back to the low voltage dropout voltage regulator LDO unit through the unit gain isolation buffer; The voltage sampling connection unit includes a voltage sampling first connection branch and / or a voltage sampling second connection branch, wherein the voltage sampling resistor is located in the voltage sampling first connection branch; When the connection state between the isolated sampling feedback unit and the power supply end of the circuit under test DUT is configured as a proximal sampling connection state, the voltage sampling first connection branch is configured to be connected to the power supply end of the circuit under test DUT, so that the power supply end of the circuit under test DUT is connected to the input end of the unity gain isolation buffer through the voltage sampling resistor; When the connection state between the isolated sampling feedback unit and the power supply terminal of the circuit under test DUT is configured as a remote sampling connection state, at least the second voltage sampling connection branch is configured to be connected to the power supply terminal of the circuit under test DUT, so that the power supply terminal of the circuit under test DUT is directly connected to the input terminal of the unity gain isolation buffer.

4. The digital programmable power supply suitable for embedded integrated circuit testing according to any one of claims 1 to 3, characterized in that: The digital program-controlled power supply also includes a test current measurement unit for measuring the current flowing through the circuit under test DUT, wherein: The current measurement unit includes a current sampling resistor network, a sampling resistor selection network and a test current processing unit. The current sampling resistor network includes a plurality of current sampling resistors distributed in parallel, and a current sampling resistor is configured to be connected in series between the output end of the low voltage dropout voltage regulator LDO unit and the power supply end of the circuit under test DUT; The sampling resistor selection network is adaptively connected to the current sampling resistor network and the test current processing unit, and the test current processing unit configures the corresponding current sampling resistors in the current sampling resistor network to form a current sampling target equivalent resistor through the sampling resistor selection network; The test current flowing through the DUT is converted into a load voltage using the formed current sampling target equivalent resistance. The test current processing unit performs amplification processing and ADC sampling processing on the load voltage in sequence to generate a load sampling voltage after the ADC sampling processing, and determines the test current flowing through the circuit under test DUT based on the load sampling voltage and the current sampling target equivalent resistance.

5. The digital programmable power supply suitable for embedded integrated circuit testing according to claim 4 is characterized in that: In the current sampling resistor network, the current sampling resistor connected in series between the output end of the low voltage dropout regulator LDO unit and the power supply end of the circuit under test DUT is configured as a normally connected current sampling resistor, and the remaining current sampling resistors are configured as optional current sampling resistors, where: The corresponding resistance value of the normally connected current sampling resistor is greater than the corresponding resistance value of any optional current sampling resistor; The sampling resistor selection network includes a plurality of relays and a relay driving circuit for driving the switching state of the relays, wherein: An optional current sampling resistor is adaptively connected to a normally open contact of a relay. When the normally open contact of the corresponding relay is driven to close by the relay driving circuit, the optional current sampling resistor is selected, and the selected optional current sampling resistor is connected in parallel with the normally connected current sampling resistor to form a current sampling target equivalent resistor based on the normally connected current sampling resistor and the selected optional current sampling resistor.

6. The digital programmable power supply suitable for embedded integrated circuit testing according to claim 4, characterized in that: The test current processing unit includes an instrument amplifier and an embedded unit adapted to be connected to the instrument amplifier, wherein: The instrument amplifier is connected to the current sampling resistor network, and the load voltage is amplified and sampled by the ADC using the instrument amplifier, and the generated load sampling voltage is loaded into the embedded unit. Based on the load sampling voltage and the current sampling target equivalent resistance, the embedded unit determines the test current flowing through the circuit under test DUT.

7. The digital programmable power supply suitable for embedded integrated circuit testing according to claim 6 is characterized in that: The instrument amplifier is also connected to the power supply terminal of the circuit under test DUT, wherein: Setting a low voltage alarm threshold and / or a high voltage alarm threshold in the instrument amplifier; The instrument amplifier compares the target test voltage at the power supply end of the circuit under test DUT with the low voltage alarm threshold and the high voltage alarm threshold. When the target test voltage at the power supply end of the circuit under test DUT matches the low voltage alarm threshold or the high voltage alarm threshold, the instrument amplifier outputs an alarm message.

8. The digital programmable power supply suitable for embedded integrated circuit testing according to claim 7, characterized in that: The instrument amplifier is also adaptively connected to the output end of the circuit under test DUT and the low voltage dropout regulator LDO unit through an automatic shutdown circuit, wherein: When the instrumentation amplifier outputs an alarm message, the automatic shutdown circuit is controlled to cut off the target test voltage provided by the output end of the low dropout voltage regulator LDO unit to the circuit under test DUT.

9. A power supply test method suitable for embedded integrated circuit testing, characterized in that: For any circuit under test DUT, the digital programmable power supply according to any one of claims 1 to 8 is used to provide a target test voltage, so as to perform a current test on the circuit under test DUT at the target test voltage.

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