Prefetching control device and method, processor and electronic equipment

Abstract

The embodiment of the invention discloses a prefetching control device and method, a processor and electronic equipment, relates to the technical field of computers, and can effectively reduce data prefetching power consumption and reduce or avoid cache pollution in richer application scenes. The device comprises an obtaining module which is used for being coupled with a prefetch input filter and is configured to obtain target memory access information from the prefetch input filter and send the target memory access information to a searching module; the searching module is coupled with the obtaining module and is configured to search whether a first filtering entry corresponding to the target memory access information exists in a preset filtering lookup table, and the filtering lookup table is related to the address rule information in the first prefetcher; one end of the indicating module is coupled with the searching module, the other end of the indicating module is used for being coupled with the prefetching input filter, and the indicating module is configured to indicate the prefetching input filter to send the target memory access information to the first prefetching device and not to send the target memory access information to the second prefetching device under the condition that the searching module finds the first filtering entry.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a pre-fetch control device, method, processor and electronic equipment. Background Art

[0002] Most modern high-performance CPUs (central processing units) use a multi-level cache architecture. This is because program instructions and data are stored in DRAM (Dynamic Random Access Memory), and the CPU core runs at a much higher frequency than DRAM. Without a multi-level cache architecture, the CPU core would read program instructions and data from DRAM, which would consume hundreds of CPU core clocks each time, often causing the CPU core to idle and performance to degrade. In a multi-level cache, the L1 cache has the smallest capacity and the fastest response speed; the LLC (last level cache) (usually the L3 cache) has the largest capacity and the slowest response speed; the L2 cache has a capacity and response speed somewhere in between.

[0003] The data prefetcher is a device that predicts the data addresses to be used in the future based on the historical rules of cache access, and transfers the data from the memory or higher-level cache (such as L3) to the lower-level cache (such as L1) before the data is needed based on the prediction results. If the prediction is accurate, it can effectively improve the program running speed.

[0004] Data prefetchers can be implemented by different algorithms, and modern high-performance CPU cores usually support more than one prefetch algorithm. On the one hand, the prefetchers of these different algorithms can cover different footprint histories, thereby giving different predictions for the data addresses to be used in the future. On the other hand, the structural complexity of prefetchers of different algorithms is also different, so the time it takes to get the prediction results is also different. Taking the stream prefetch algorithm and the stride prefetch algorithm as examples, the time it takes for the stream prefetch algorithm to get the prediction results is less than that for the stride prefetch algorithm. Therefore, under the same conditions, the stream prefetch algorithm will get the prediction results faster than the stride prefetch algorithm.

[0005] In order to reduce power consumption and reduce cache contamination by unnecessary data, in the related art, for the prefetcher that obtains the prediction result faster, if the credibility of its prediction result is higher, it will send a control signal to the prefetcher that obtains the prediction result slower, so that the prefetcher that obtains the prediction result slower will terminate the address prediction operation in advance. But on the other hand, for the prefetcher that obtains the prediction result slower, if the credibility of its prediction result is higher, it cannot terminate the prefetcher that obtains the prediction result faster, because the prefetcher that obtains the prediction result faster has already executed all of its pipelines and prefetched the data into the cache. Therefore, in this case, power consumption cannot be effectively reduced, and cache contamination cannot be reduced. Summary of the invention

[0006] In view of this, embodiments of the present invention provide a pre-fetch control device, method, processor and electronic device, which can effectively reduce data pre-fetch power consumption in richer application scenarios and reduce or avoid cache contamination by unnecessary data.

[0007] In a first aspect, an embodiment of the present invention provides a prefetch control device, comprising: an acquisition module, coupled to a prefetch input filter, configured to acquire target memory access information from the prefetch input filter and send the target memory access information to a search module; the search module, coupled to the acquisition module, configured to receive the target memory access information and search a preset filter search table for a first filter entry corresponding to the target memory access information, wherein the filter search table is related to address regularity information in a first prefetcher; an indication module, one end of which is coupled to the search module and the other end of which is coupled to the prefetch input filter, configured to indicate the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher when the search module finds the first filter entry; wherein a first time required for the first prefetcher to obtain a first prediction result based on its own address regularity information is longer than a second time required for the second prefetcher to obtain a second prediction result based on its own address regularity information under the same conditions; the first prediction result is used for the first prefetcher to perform a data prefetch operation, and the second prediction result is used for the second prefetcher to perform a data prefetch operation.

[0008] In one embodiment, the filter lookup table includes at least one filter entry, each of which includes an address feature information; the target memory access information includes a memory address corresponding to a cache line accessed by a target memory access instruction; the search module is configured to: determine the target feature information corresponding to the target memory access information according to a preset algorithm and the memory address, and compare the target feature information with each address feature information in the filter lookup table; when the target feature information is the same as any of the address feature information, determine the filter entry corresponding to any of the address feature information as the first filter entry; when the target feature information is different from all the address feature information in the filter lookup table, determine that the first filter entry does not exist in the filter lookup table.

[0009] In one embodiment, the first prefetcher includes an address pattern statistics table, which includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address pattern statistics table, and the amount of data in the address pattern statistics table is greater than the amount of data in the filter lookup table.

[0010] In one embodiment, each of the filter entries also includes entry evaluation information; the prefetch control device also includes an update module, which is used to couple with the first prefetcher and is configured to, after the indication module instructs the prefetch input filter to send the target memory access information to the first prefetcher instead of the second prefetcher: in response to the first prefetcher feedback that the target memory access information hits the first prediction entry in the address regularity statistics table and the credibility corresponding to the first prediction entry is greater than or equal to a preset credibility threshold, increase the evaluation value of the entry evaluation information corresponding to the first filter entry by a preset step length; wherein the first prediction entry is the prediction entry in the address regularity statistics table corresponding to the first filter entry, and the data volume of the first filter entry is less than the data volume of the first prediction entry; or, in response to the first prefetcher feedback that the target memory access information hits the first prediction entry in the address regularity statistics table but the credibility corresponding to the first prediction entry is less than the credibility threshold, or, in response to the first prefetcher feedback that the target memory access information does not hit any of the prediction entries in the address regularity statistics table, mark the first filter entry as an illegal filter entry.

[0011] In one embodiment, the first prefetcher includes an address pattern statistics table, which includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address pattern statistics table, and the data volume of the address pattern statistics table is greater than the data volume of the filter lookup table; the indication module is also configured to, when the lookup module fails to find the first filter entry, instruct the prefetch input filter to send the target memory access information to the first prefetcher and the second prefetcher respectively; the device also includes an insertion module, which is used to couple with the first prefetcher, and the insertion module is also configured to: in response to the lookup module failing to find the first filter entry and the first prefetcher feedbacking that the target memory access information hits the first prediction entry, insert part of the content of the first prediction entry into the filter lookup table.

[0012] In one embodiment, the insertion module is configured to: detect whether there is an illegal filter entry in the filter lookup table, wherein the illegal filter entry exists in the filter lookup table, and the predicted entry corresponding to the illegal filter entry does not exist in the address regularity statistics table; in the case where the illegal filter entry exists in the filter lookup table, replace the corresponding content of the illegal filter entry with part of the content of the first predicted entry.

[0013] In one embodiment, each of the filter entries also includes entry evaluation information; the insertion module is configured to: in the case where the illegal filter entry does not exist in the filter lookup table, detect whether there is a second filter entry in the filter lookup table, wherein the evaluation value of the entry evaluation information corresponding to the second filter entry is a preset value; in the case where the second filter entry exists in the filter lookup table, replace the corresponding content of the second filter entry with part of the content of the first prediction entry.

[0014] In one implementation, the insertion module is configured to: when the second filter entry does not exist in the filter lookup table, reduce the evaluation value of the item evaluation information corresponding to each filter entry in the filter lookup table by a preset step length.

[0015] In one embodiment, the indication module is further configured to: when the search module finds the first filter entry, instruct the prefetch input filter to lock the target memory access information so that other prefetchers except the first prefetcher cannot perform data prefetch operations based on the target memory access information.

[0016] In a second aspect, an embodiment of the present invention further provides a prefetch control method, comprising: obtaining target memory access information from a prefetch input filter; searching in a preset filter lookup table whether there is a first filter entry corresponding to the target memory access information, wherein the filter lookup table is related to the address regularity information in the first prefetcher; when the first filter entry is found, instructing the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher; wherein a first time required for the first prefetcher to obtain a first prediction result based on its own address regularity information is greater than a second time required for the second prefetcher to obtain a second prediction result based on its own address regularity information under the same conditions; the first prediction result is used for the first prefetcher to perform data prefetch operations, and the second prediction result is used for the second prefetcher to perform data prefetch operations.

[0017] In one embodiment, the filter lookup table includes at least one filter entry, each of which includes an address feature information; the target memory access information includes a memory address corresponding to a cache line accessed by a target memory access instruction; the searching in a preset filter lookup table for whether there is a first filter entry corresponding to the target memory access information includes: determining the target feature information corresponding to the target memory access information according to a preset algorithm and the memory address, and comparing the target feature information with each piece of address feature information in the filter lookup table; when the target feature information is the same as any of the address feature information, determining the filter entry corresponding to any of the address feature information as the first filter entry; when the target feature information is different from all the address feature information in the filter lookup table, determining that the first filter entry does not exist in the filter lookup table.

[0018] In one embodiment, the first prefetcher includes an address pattern statistics table, which includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address pattern statistics table, and the amount of data in the address pattern statistics table is greater than the amount of data in the filter lookup table.

[0019] In one embodiment, each of the filter entries also includes entry evaluation information; after instructing the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher, the method also includes: in response to the first prefetcher feedback that the target memory access information hits the first prediction entry in the address regularity statistics table and the credibility corresponding to the first prediction entry is greater than or equal to a preset credibility threshold, increasing the evaluation value of the entry evaluation information corresponding to the first filter entry by a preset step size; wherein the first prediction entry is the prediction entry in the address regularity statistics table corresponding to the first filter entry, and the data volume of the first filter entry is smaller than the data volume of the first prediction entry; or, in response to the first prefetcher feedback that the target memory access information hits the first prediction entry in the address regularity statistics table but the credibility corresponding to the first prediction entry is smaller than the credibility threshold, or, in response to the first prefetcher feedback that the target memory access information does not hit any of the prediction entries in the address regularity statistics table, marking the first filter entry as an illegal filter entry.

[0020] In one embodiment, the first prefetcher includes an address pattern statistics table, which includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address pattern statistics table, and the data volume of the address pattern statistics table is greater than the data volume of the filter lookup table; the method also includes: when the first filter entry is not found, instructing the prefetch input filter to send the target memory access information to the first prefetcher and the second prefetcher respectively; in response to not finding the first filter entry and the first prefetcher feedback that the target memory access information hits the first prediction entry, inserting part of the content of the first prediction entry into the filter lookup table.

[0021] In one embodiment, the method also includes: detecting whether there is an illegal filter entry in the filter lookup table, wherein the illegal filter entry exists in the filter lookup table, and the predicted entry corresponding to the illegal filter entry does not exist in the address regularity statistics table; in the case that the illegal filter entry exists in the filter lookup table, replacing the corresponding content of the illegal filter entry with part of the content of the first predicted entry.

[0022] In one embodiment, each of the filter entries also includes entry evaluation information; the method also includes: in a case where the illegal filter entry does not exist in the filter lookup table, detecting whether there is a second filter entry in the filter lookup table, wherein the evaluation value of the entry evaluation information corresponding to the second filter entry is a preset value; in a case where the second filter entry exists in the filter lookup table, replacing the corresponding content of the second filter entry with part of the content of the first prediction entry.

[0023] In one embodiment, the method further includes: when the second filter entry does not exist in the filter lookup table, reducing the evaluation value of the item evaluation information corresponding to each filter entry in the filter lookup table by a preset step length.

[0024] In one embodiment, after searching in a preset filter lookup table whether there is a first filter entry corresponding to the target memory access information, the method further includes: when the first filter entry is found, instructing the prefetch input filter to lock the target memory access information so that other prefetchers except the first prefetcher cannot perform data prefetch operations based on the target memory access information.

[0025] In the third aspect, an embodiment of the present invention further provides a processor, comprising: a prefetch input filter, a prefetch control device, and a prefetcher, wherein the prefetch control device is any one of the prefetch control devices provided by the embodiments of the present invention; one end of the prefetch input filter is coupled to the prefetch control device, and the other end is coupled to each of the prefetchers, and is configured to sample memory access behavior to obtain target memory access information; the prefetch control device is coupled to the prefetch input filter; the prefetcher includes the first prefetcher and the second prefetcher.

[0026] In a fourth aspect, an embodiment of the present invention further provides an electronic device, comprising a circuit board, a processor and a memory, wherein the processor and the memory are respectively arranged on the circuit board, and the processor is electrically connected to the memory for performing a read operation or a write operation on the memory, wherein the processor is any one of the processors provided in the embodiments of the present invention.

[0027] The prefetch control device, method, processor and electronic device provided by the embodiment of the present invention, the acquisition module of the device is used to couple with the prefetch input filter, can obtain the target memory access information from the prefetch input filter and send the target memory access information to the search module; the search module is coupled with the acquisition module, can receive the target memory access information, and search whether there is a first filter entry corresponding to the target memory access information in the preset filter search table; the indication module, one end of which is coupled with the search module, and the other end is used to couple with the prefetch input filter, and is configured to indicate the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher when the search module finds the first filter entry. Since the filter search table is related to the address regularity information in the first prefetcher, in this way, the search module first searches whether there is a first filter entry corresponding to the target memory access information in the preset filter search table, so that before performing the data prefetch operation, it can be known in advance whether the first prefetcher has a greater possibility of obtaining an accurate prediction result. In the case where the first prefetcher has a greater possibility of obtaining an accurate prediction result, the target memory access information can be sent only to the first prefetcher instead of to the second prefetcher. In this way, even if the first time required for the first prefetcher to obtain the first prediction result based on its own address regularity information is longer than the second time required for the second prefetcher to obtain the second prediction result based on its own address regularity information under the same conditions, the second prefetcher can still be prevented from performing data prefetching operations on the target memory access information in time according to the search result of the filter lookup table, thereby effectively reducing the power consumption of data prefetching in richer application scenarios and avoiding or reducing the cache from being polluted by unnecessary data. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic diagram of the structure of a pre-fetch control device provided by an embodiment of the present invention; Figure 2 A schematic diagram of an application scenario of the pre-fetch control device provided by an embodiment of the present invention; Figure 3 A schematic diagram of a corresponding relationship between a filter lookup table and an address rule statistics table in an embodiment of the present invention; Figure 4 Another structural schematic diagram of a pre-fetch control device provided by an embodiment of the present invention; Figure 5A schematic diagram of marking whether a filtering entry is valid in an embodiment of the present invention; Figure 6 A flow chart of updating a filter lookup table in an embodiment of the present invention; Figure 7 A flow chart of a pre-fetch control method provided by an embodiment of the present invention; Figure 8 A schematic diagram of the structure of a processor provided by an embodiment of the present invention; Fig. 9 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In a first aspect, an embodiment of the present invention provides a pre-fetch control device, which can effectively reduce the power consumption of data pre-fetching in a wider range of application scenarios, and reduce or avoid the pollution of the cache by unnecessary data.

[0033] like Figure 1 As shown, the pre-fetch control device 1 provided in the embodiment of the present invention may include: An acquisition module 11, coupled to the pre-fetch input filter 2, configured to acquire target memory access information from the pre-fetch input filter 2 and send the target memory access information to the search module 12; A search module 12, coupled to the acquisition module 11, is configured to receive the target memory access information and search a preset filter lookup table for a first filter entry corresponding to the target memory access information, wherein the filter lookup table is related to the address regularity information in the first prefetcher 31; The indication module 13 is coupled with the search module 12 at one end and is used to couple with the prefetch input filter 2 at the other end. The indication module 13 is configured to indicate the prefetch input filter 2 to send the target memory access information to the first prefetcher 31 and not to send it to the second prefetcher 32 when the search module 12 finds the first filter entry; wherein the first time required for the first prefetcher 31 to obtain the first prediction result based on its own address regularity information is greater than the second time required for the second prefetcher 32 to obtain the second prediction result based on its own address regularity information under the same conditions; the first prediction result is used for the first prefetcher 31 to perform data prefetching operations, and the second prediction result is used for the second prefetcher 32 to perform data prefetching operations.

[0034] The prefetch control device provided by the embodiment of the present invention has an acquisition module 11 for coupling with the prefetch input filter 2, and can acquire target memory access information from the prefetch input filter 2 and send the target memory access information to the search module 12; the search module 12 is coupled with the acquisition module 11, and can receive the target memory access information, and search whether there is a first filter entry corresponding to the target memory access information in a preset filter search table; the indication module 13 is coupled with the search module 12 at one end, and is coupled with the prefetch input filter 2 at the other end, and is configured to indicate the prefetch input filter 2 to send the target memory access information to the first prefetcher 31 and not to the second prefetcher 32 when the search module 12 finds the first filter entry. Since the filter search table is related to the address regularity information in the first prefetcher 31, the search module 12 first searches whether there is a first filter entry corresponding to the target memory access information in the preset filter search table, so that before performing the data prefetch operation, it can be known in advance whether the first prefetcher 31 has a greater possibility of obtaining an accurate prediction result. In the case where the first prefetcher has a greater possibility of obtaining an accurate prediction result, the target memory access information can be sent only to the first prefetcher instead of to the second prefetcher. In this way, even if the first time required for the first prefetcher 31 to obtain the first prediction result based on its own address regularity information is longer than the second time required for the second prefetcher 32 to obtain the second prediction result based on its own address regularity information under the same conditions, the second prefetcher can still be timely prevented from performing data prefetch operations on the target memory access information based on the search result of the filter lookup table, thereby effectively reducing data prefetching power consumption in richer application scenarios and avoiding or reducing the cache from being polluted by unnecessary data.

[0035] Specifically, in an embodiment of the present invention, the target memory access information may include one or more information related to memory access or cache access in the target memory access instruction (i.e., the instruction in the program counter PC), for example, which instruction is the memory access or cache access, which level of cache is accessed, what is the memory address of the cache line accessed, whether the memory access hits, etc.

[0036] The prefetch input filter (Prefetch Input Filter) 2 can sample the footprint of the memory access address or the footprint of the cache miss address and send it to the prefetcher. The prefetcher can use these address footprints for training to form address regularity information, and then use the address regularity information to predict the address of the data required in the future (i.e., the future data address) to obtain the prediction result, so as to implement data prefetching according to the prediction result. Among them, the so-called address regularity information is the information indicating the relationship between the future memory access address and the current memory access address, so the future memory access address can be predicted based on this. Of course, in some cases, it may not be possible to use the address regularity information to predict the address of the data required in the future, that is, it is impossible to obtain the prediction result, then the corresponding data prefetching can be omitted.

[0037] In order to improve the accuracy of data prefetching, multiple prefetchers can be set, and each prefetcher can be implemented based on a different algorithm, so as to cover more data prefetching scenarios. Among them, various algorithms may include, for example, stream algorithms, stride algorithms, etc. Different algorithms may have different complexities, resulting in different times for each algorithm to obtain prediction results. For example, the number of pipeline (i.e., register) levels required by different algorithms may be different. Then, the time taken by the algorithm with more pipeline levels to obtain the prediction result will be longer than the time taken by the algorithm with fewer pipeline levels under the same conditions. Therefore, the algorithm with more pipeline levels will obtain the prediction result relatively slower and later. Exemplarily, in one example, the stream algorithm can obtain the prediction result in the first stage of the pipeline, while the stride algorithm can obtain the prediction result in the second stage of the pipeline. Therefore, the stride algorithm obtains the prediction result later than the stream algorithm. In one example, the coordination and constraint relationship between the stream prefetcher and the stride prefetcher can be as follows: Figure 2 shown.

[0038] In an embodiment of the present invention, the basis for the search module 12 to perform a search operation is a filter lookup table, and the filter lookup table can be set in the prefetch control device in a hardware manner. In one example, the filter lookup table may include one or more filter entries, each of which may include an address feature information. Depending on the algorithm on which the prefetcher is based, the specific content of the address feature information may also vary. For example, in some examples, the address feature information may be the data address information of a historical memory access instruction, or part of the address bit information in the data address information. In other examples, the address feature information may also be information obtained by performing calculations based on the data address information and other information. For example, in one example, the address feature information may be information obtained by performing a hash operation on a part of the content of the data address information of a historical memory access instruction and the historical memory access instruction. Exemplarily, a schematic diagram of a filter lookup table can be shown in Table 1.

[0039]

[0040] In order to facilitate the search of the filter lookup table according to the target memory access information, in one embodiment, the target memory access information may include the memory address corresponding to the cache line accessed by the target memory access instruction; based on this, the search module 12 can be configured to: determine the target feature information corresponding to the target memory access information according to a preset algorithm and the memory address, and compare the target feature information with each address feature information in the filter lookup table; when the target feature information is the same as any address feature information, determine the filter entry corresponding to any address feature information as the first filter entry; when the target feature information is different from all the address feature information in the filter lookup table, determine that the first filter entry does not exist in the filter lookup table.

[0041] The preset algorithm for determining the target characteristic information may be the same as the algorithm for determining the address characteristic information. For example, if the address characteristic information is obtained by applying algorithm A to the upper 9-bit address information in the data address information of the historical memory access instruction, then correspondingly, the target characteristic information is obtained by applying algorithm A to the upper 9-bit address information of the memory address corresponding to the cache line accessed by the target memory access instruction.

[0042] Since the target feature information corresponding to the target memory access instruction has the same algorithm as the address feature information in the filter lookup table, and the filter lookup table is related to the address regularity information in the first prefetcher 31, if the target feature information of the target memory access instruction is the same as the address feature information of a certain filter entry in the filter lookup table, it means that the target feature information is also related to the address regularity information in the first prefetcher 31, so the first prefetcher can be used to make a more accurate prediction of the data address required for the target memory access instruction, and accordingly, the filter entry can be determined as the first filter entry. On the contrary, if the target feature information of the target memory access instruction is different from the address feature information of all filter entries in the filter lookup table, it means that the correlation between the target feature information and the address regularity information in the first prefetcher 31 cannot be determined, and the first prefetcher 31 cannot be used to make a more accurate prediction of the data address required for the target memory access instruction, and accordingly, it can be determined that the first filter entry does not exist in the filter lookup table.

[0043] In one embodiment of the present invention, the first prefetcher 31 may include an address regularity statistics table, which may include one or more prediction entries; each prediction entry may include corresponding address feature information; each filter entry in the filter lookup table has a corresponding prediction entry in the address regularity statistics table, and the amount of data in the address regularity statistics table is greater than the amount of data in the filter lookup table. Here, the address feature information between the filter entry and its corresponding prediction entry is the same. For example, the relationship between the filter lookup table and the address regularity statistics table can be seen in Figure 3 .like Figure 3 As shown, the address feature information of the filter entry E1 is tag1, the address feature information of the filter entry E2 is tag2, the address feature information of the prediction entry F4 is tag1, and the address feature information of the prediction entry F3 is tag2. Based on the corresponding filter entries and prediction entries, the address feature information corresponds to the same judgment principle, and it can be known that the filter entry E1 corresponds to the prediction entry F4, and the filter entry E2 corresponds to the prediction entry F3. Here, the data volume of the address regularity statistics table is larger than the data volume of the filter lookup table, which can include the case where the number of prediction entries contained in the address regularity statistics table is larger than the number of filter entries contained in the filter lookup table (for example, the address regularity statistics table contains 20 prediction entries, and the filter lookup table contains 10 filter entries), and can also include the case where the data volume of each prediction entry is larger than the data volume of each filter entry (for example, each prediction entry can include 6 items of information, and each filter entry can include 2 or 3 of the 6 items of information, etc.), and can also include both cases, which are not limited in the embodiments of the present invention. In this way, since the data volume of the filtering lookup table is smaller than the data volume of the address regularity statistical table, the filtering lookup table does not need to consume too much storage resources, and the search is also very convenient and fast.

[0044] In addition to the address feature information, each prediction entry may include address regularity information corresponding to the address feature information. In one embodiment of the present invention, if the search module 12 finds the first filter entry in the filter search table, the indication module 13 may indicate the prefetch input filter 2 to send the target memory access information to the first prefetcher 31, but not to the second prefetcher 32. After receiving the target memory access information, the first prefetcher 31 may predict the data address required in the future based on the target memory access information and its own address regularity information, that is, obtain the prediction result. Specifically, in one example, the first prefetcher 31 may detect whether the target memory access information hits the first prediction entry in the address regularity statistics table, and the credibility corresponding to the first prediction entry is greater than or equal to the preset credibility threshold. If the detection result is yes, it means that the first prefetcher 31 can predict the data address required in the future based on the first prediction entry and obtain the prediction result. Among them, the first prediction entry is the prediction entry corresponding to the first filter entry in the address regularity statistics table.

[0045] Furthermore, in one embodiment of the present invention, the indication module 13 is also configured to: when the search module 12 finds the first filter entry, instruct the prefetch input filter 2 to lock the target memory access information so that other prefetchers except the first prefetcher 31 cannot perform data prefetch operations according to the target memory access information. For example, the indication module 13 can instruct the prefetch input filter 2 to send a locking signal, such as a lock=1 signal, when sending the target memory access information to the first prefetcher 31. In this way, in the subsequent pipeline, when other prefetchers except the first prefetcher 31 find lock=1, they will not use the target memory access information for data prefetching or data prefetching training.

[0046] The above embodiments describe in detail how to apply the filter lookup table to perform prefetch control, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the filter lookup table may be updated as instructions are executed.

[0047] Specifically, in addition to the address feature information, in one embodiment of the present invention, each filter entry in the filter lookup table may also include entry evaluation information. The entry evaluation information may be used to evaluate the application value of the filter entry. The higher the application value of the filter entry, the more the filter entry should be retained in the filter lookup table to facilitate application. The lower the application value of the filter entry, the more the filter entry should be deleted from the filter lookup table to avoid wasting resources. The application of the entry evaluation information is described in detail below.

[0048] Specifically, if Figure 4As shown, in one embodiment of the present invention, the prefetch control device may further include an update module 14, which may be used to couple with the first prefetcher 31. In one example, the update module 14 may be configured to, after the indication module 13 indicates that the prefetch input filter 2 sends the target memory access information to the first prefetcher 31 instead of to the second prefetcher 32: in response to the first prefetcher 31 feedback that the target memory access information hits the first prediction entry in the address regularity statistics table and the credibility corresponding to the first prediction entry is greater than or equal to the preset credibility threshold, increase the evaluation value of the entry evaluation information corresponding to the first filter entry by a preset step length; wherein the first prediction entry is the prediction entry corresponding to the first filter entry in the address regularity statistics table, and the data volume of the first filter entry is less than the data volume of the first prediction entry; or, in response to the first prefetcher 31 feedback that the target memory access information hits the first prediction entry in the address regularity statistics table but the credibility corresponding to the first prediction entry is less than the credibility threshold, or, in response to the first prefetcher 31 feedback that the target memory access information does not hit any of the prediction entries in the address regularity statistics table, mark the first filter entry as an illegal filter entry. For example, Figure 5 As shown, in one example, an illegal filter entry can be marked in the filter lookup table by valid. Valid is a flag indicating whether it is an illegal filter entry, wherein if valid is equal to 0, the filter entry is an illegal entry, and if valid is equal to 1, the filter entry is a legal entry.

[0049] That is to say, in this embodiment, the filter lookup table will be updated according to whether the target memory access information in the first prefetcher 31 can hit the first prediction entry in the address regularity statistics table, and the size of the credibility corresponding to the first prediction entry. The update can include updating the evaluation value of the entry evaluation information (for example, increasing the evaluation value by a preset step length), and can also include updating to add other marks to the filter entry (for example, adding an illegal mark to the first filter entry), and can also include other updates, which are not limited by the embodiment of the present invention. Specifically, if the target memory access information can hit the first prediction entry in the address regularity statistics table, and the credibility corresponding to the first prediction entry is high, it means that the first prefetcher predicts the target memory access information more successfully. In this way, within a certain range of hit times, each time the first prediction entry is successfully hit, the application value of the first filter entry corresponding to the first prediction entry is confirmed once, so the evaluation value of the entry evaluation information of the first filter entry can be increased by a preset step length. For example, in one example, the entry evaluation information can be implemented by a counter, and within a certain range of hit times (for example, 4 times), each time the first prediction entry is successfully hit, the evaluation value of the entry evaluation information of the first filter entry can be increased by 1. For example, in one example, the counter is implemented by three binary bits, and the initial evaluation value of the item evaluation information of the first filter item can be 100, and when the evaluation value increases to 111, it no longer increases. Of course, in other embodiments of the present invention, the number of bits, the initial value, and the maximum value of the counter can be set and adjusted as needed, and the embodiments of the present invention are not limited to this.

[0050] The above embodiment describes in detail the case where the search module 12 finds the first filter entry corresponding to the target memory access information in the filter lookup table, but the embodiments of the present invention are not limited to this. In other embodiments of the present invention, the search module 12 may not find the first filter entry corresponding to the target memory access information in the filter lookup table. In this case, the indication module 13 can also be configured to instruct the prefetch input filter 2 to send the target memory access information to the first prefetcher 31 and the second prefetcher 32 respectively when the search module 12 fails to find the first filter entry. That is to say, in this case, the first prefetcher 31 and the second prefetcher 32 will both try to use the target memory access information to perform data prefetch operations. Based on this, refer again to Figure 4In one embodiment of the present invention, the prefetch control device 1 provided by the embodiment of the present invention may further include an insertion module 15. The insertion module 15 may be used to couple with the first prefetcher 31. The insertion module 15 may be configured to: in response to the search module 12 failing to find the first filter entry, and the first prefetcher 31 feeding back the target memory access information that hits the first prediction entry, insert a portion of the content of the first prediction entry into the filter lookup table. Optionally, when inserting a portion of the content of the first prediction entry into the filter lookup table, partial information may be selected from the first prediction entry and inserted into the filter lookup table according to the specific structure of the filter lookup table. For example, in one example, the address feature information in the first prediction entry may be inserted into the filter lookup table.

[0051] Specifically, the insertion module 15 may have multiple insertion schemes when inserting part of the information in the first prediction entry into the filter lookup table. For example, in one embodiment of the present invention, the insertion module 15 may also be configured to: detect whether there is an illegal filter entry in the filter lookup table, wherein the illegal filter entry exists in the filter lookup table, and the prediction entry corresponding to the illegal filter entry does not exist in the address regularity statistics table of the first prefetcher 31; in the case where there is an illegal filter entry in the filter lookup table, replace the corresponding content of the illegal filter entry with part of the content of the first prediction entry. Since the illegal filter entry exists in the filter lookup table, and the corresponding prediction entry does not exist in the filter entry in the address regularity statistics table of the first prefetcher 31, that is to say, according to the guidance given by the illegal filter entry, the first prefetcher 31 cannot obtain a more accurate prediction result, therefore, the corresponding content of the illegal filter entry may be replaced with part of the content of the first prediction entry, thereby replacing the illegal filter entry with a new filter entry. After the replacement is completed, the original illegal mark will no longer exist, or become a legal mark. In one example, after the original illegal filtering entry is replaced with a new filtering entry, an initial evaluation value may be set for the entry evaluation information of the new filtering entry, for example, set to a binary number 100.

[0052] In another embodiment of the present invention, the insertion module 15 can also be configured as follows: when there is no illegal filter entry in the filter lookup table, detect whether there is a second filter entry in the filter lookup table, wherein the evaluation value of the item evaluation information corresponding to the second filter entry is a preset value; when there is a second filter entry in the filter lookup table, replace the corresponding content of the second filter entry with part of the content of the first prediction item. That is to say, if there is no illegal filter entry in the filter lookup table, part of the content of the first prediction item can be inserted into the filter entry whose item evaluation information has an evaluation value of a preset value. The preset value can be a value less than the initial value. For example, in one example, the preset value can be 0. In this way, the filter entry with a lower evaluation value can be replaced, so that the item evaluation information of each filter entry in the filter lookup table has a higher evaluation value.

[0053] Furthermore, in another embodiment of the present invention, the insertion module 15 can also be configured to: when there is no second filter entry in the filter lookup table, the evaluation values ​​of the item evaluation information corresponding to each filter item in the filter lookup table are reduced by a preset step length. In this way, this round of updating the filter lookup table only updates the evaluation values ​​of the item evaluation information, and does not insert the first predicted item into the filter lookup table. Since the evaluation values ​​of the item evaluation information are reduced by a preset step length, when the filter lookup table is updated in the next round, it can be detected whether the reduced evaluation values ​​are equal to the preset values. If so, the first predicted item can be inserted into the filter item with the preset evaluation value.

[0054] Exemplarily, the updating process of the filter lookup table by the insertion module 15 can be as follows: Figure 6 As shown. Wherein, valid is a flag indicating whether it is an illegal filter entry, wherein if valid is equal to 0, the filter entry is an illegal entry, and if valid is equal to 1, the filter entry is a legal entry. cnt is the evaluation value of the entry evaluation information of the filter entry.

[0055] In a second aspect, an embodiment of an embodiment of the present invention provides a prefetch control method, which can effectively reduce data prefetch power consumption in richer application scenarios and reduce or avoid cache contamination by unnecessary data.

[0056] like Figure 7 As shown, the pre-fetch control method provided by the embodiment of the present invention may include: S41, obtaining target memory access information from a prefetch input filter; S42, searching in a preset filter lookup table whether there is a first filter entry corresponding to the target memory access information, wherein the filter lookup table is related to the address regularity information in the first prefetcher; S43. When the first filter entry is found, instruct the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher; wherein the first time duration required for the first prefetcher to obtain the first prediction result based on its own address regularity information is greater than the second time duration required for the second prefetcher to obtain the second prediction result based on its own address regularity information under the same conditions; the first prediction result is used for the first prefetcher to perform data prefetch operations, and the second prediction result is used for the second prefetcher to perform data prefetch operations.

[0057] The prefetch control method provided by the embodiment of the present invention can obtain the target memory access information from the prefetch input filter, and search whether there is a first filter entry corresponding to the target memory access information in the preset filter lookup table, and when the first filter entry is found, instruct the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher. Since the filter lookup table is related to the address regularity information in the first prefetcher, by first searching whether there is a first filter entry corresponding to the target memory access information in the preset filter lookup table, it is possible to know in advance whether the first prefetcher is more likely to obtain an accurate prediction result before performing the data prefetch operation. In the case where the first prefetcher has a greater possibility of obtaining an accurate prediction result, the target memory access information can be sent only to the first prefetcher instead of to the second prefetcher. In this way, even if the first time required for the first prefetcher to obtain the first prediction result based on its own address regularity information is longer than the second time required for the second prefetcher to obtain the second prediction result based on its own address regularity information under the same conditions, the second prefetcher can still be prevented from performing data prefetching operations on the target memory access information in time according to the search result of the filter lookup table, thereby effectively reducing the power consumption of data prefetching in richer application scenarios and avoiding or reducing the cache from being polluted by unnecessary data.

[0058] In one embodiment, the filter lookup table includes at least one filter entry, each of which includes an address feature information; the target memory access information includes a memory address corresponding to a cache line accessed by a target memory access instruction; step S42 searches a preset filter lookup table for a first filter entry corresponding to the target memory access information, which may include: determining the target feature information corresponding to the target memory access information according to a preset algorithm and the memory address, and comparing the target feature information with each piece of address feature information in the filter lookup table; when the target feature information is the same as any of the address feature information, determining the filter entry corresponding to any of the address feature information as the first filter entry; when the target feature information is different from all the address feature information in the filter lookup table, determining that the first filter entry does not exist in the filter lookup table.

[0059] In one embodiment, the first prefetcher includes an address pattern statistics table, which includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address pattern statistics table, and the amount of data in the address pattern statistics table is greater than the amount of data in the filter lookup table.

[0060] In one implementation, each of the filter entries further includes entry evaluation information; after instructing the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher, the prefetch control method provided by the embodiment of the present invention may further include: In response to the first prefetcher feeding back that the target memory access information hits a first prediction entry in the address regularity statistics table and the credibility corresponding to the first prediction entry is greater than or equal to a preset credibility threshold, increasing the evaluation value of the entry evaluation information corresponding to the first filtering entry by a preset step length; wherein the first prediction entry is a prediction entry in the address regularity statistics table corresponding to the first filtering entry, and the data volume of the first filtering entry is less than the data volume of the first prediction entry; or, In response to the first prefetcher feedback that the target memory access information hits the first prediction entry in the address regularity statistics table but the credibility corresponding to the first prediction entry is less than the credibility threshold, or in response to the first prefetcher feedback that the target memory access information does not hit any of the prediction entries in the address regularity statistics table, the first filter entry is marked as an illegal filter entry.

[0061] In one implementation, the first prefetcher includes an address regularity statistics table, the address regularity statistics table includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address regularity statistics table, and the data volume of the address regularity statistics table is greater than the data volume of the filter lookup table; the prefetch control method provided by the embodiment of the present invention may further include: In the case where the first filter entry is not found, the prefetch input filter is instructed to send the target memory access information to the first prefetcher and the second prefetcher respectively; in response to the first filter entry not being found and the first prefetcher feedbacks that the target memory access information hits the first prediction entry, a portion of the content of the first prediction entry is inserted into the filter lookup table.

[0062] In one embodiment, the prefetch control method provided by an embodiment of the present invention may also include: detecting whether there is an illegal filter entry in the filter lookup table, wherein the illegal filter entry exists in the filter lookup table, and the predicted entry corresponding to the illegal filter entry does not exist in the address regularity statistics table; in the case that the illegal filter entry exists in the filter lookup table, replacing the corresponding content of the illegal filter entry with part of the content of the first predicted entry.

[0063] In one embodiment, each of the filter entries also includes entry evaluation information; the pre-fetch control method provided by an embodiment of the present invention may also include: in a case where the illegal filter entry does not exist in the filter lookup table, detecting whether there is a second filter entry in the filter lookup table, wherein the evaluation value of the entry evaluation information corresponding to the second filter entry is a preset value; in a case where the second filter entry exists in the filter lookup table, replacing the corresponding content of the second filter entry with part of the content of the first prediction entry.

[0064] In one implementation, the pre-fetch control method provided by an embodiment of the present invention may further include: when the second filter entry does not exist in the filter lookup table, reducing the evaluation value of the entry evaluation information corresponding to each filter entry in the filter lookup table by a preset step length.

[0065] In one embodiment, after searching in a preset filter lookup table whether there is a first filter entry corresponding to the target memory access information, the prefetch control method provided by an embodiment of the present invention may also include: when the first filter entry is found, instructing the prefetch input filter to lock the target memory access information so that other prefetchers except the first prefetcher cannot perform data prefetch operations based on the target memory access information.

[0066] Thirdly, Figure 8 As shown, an embodiment of the present invention further provides a processor, comprising: a prefetch input filter 2, a prefetch control device 1, and a prefetcher 3, wherein the prefetch control device 1 is any one of the prefetch control devices provided in the aforementioned embodiments; one end of the prefetch input filter 2 is coupled to the prefetch control device 1, and the other end is coupled to each prefetcher 3, and is configured to sample memory access behavior to obtain target memory access information; the prefetch control device 1 is coupled to the prefetch input filter 2; the prefetcher 3 includes a first prefetcher 31 and a second prefetcher 32.

[0067] The processor provided by the embodiment of the present invention includes any one of the pre-fetch control devices 1 provided by the aforementioned embodiments, and thus can also achieve corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0068] Fourthly, Fig. 9 As shown, an embodiment of the present invention further provides an electronic device 6, which includes a circuit board 61, a processor 62 and a memory 63. The processor 62 and the memory 63 are respectively arranged on the circuit board 61, and the processor 62 is electrically connected to the memory 63 for performing a read operation or a write operation on the memory 63. The processor 62 is any processor provided in the aforementioned embodiments, and therefore can also achieve corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0069] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0070] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0071] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0072] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0073] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0074] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A pre-fetch control device, characterized in that: include: an acquisition module, coupled to the pre-fetch input filter, configured to acquire target memory access information from the pre-fetch input filter and send the target memory access information to the search module; The search module is coupled to the acquisition module and is configured to receive the target memory access information and search a preset filter lookup table for a first filter entry corresponding to the target memory access information, wherein the filter lookup table is related to the address regularity information in the first prefetcher; An indication module, one end of which is coupled to the search module and the other end of which is used to couple to the prefetch input filter, is configured to indicate the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher when the search module finds the first filter entry; wherein the first time required for the first prefetcher to obtain the first prediction result based on its own address regularity information is longer than the second time required for the second prefetcher to obtain the second prediction result based on its own address regularity information under the same conditions; the first prediction result is used for the first prefetcher to perform data prefetch operations, and the second prediction result is used for the second prefetcher to perform data prefetch operations.

2. The pre-fetch control device according to claim 1, characterized in that: The filter lookup table includes at least one filter entry, each of which includes a piece of address feature information; The target memory access information includes a memory address corresponding to a cache line accessed by the target memory access instruction; The search module is configured as follows: Determine the target feature information corresponding to the target memory access information according to a preset algorithm and the memory address, and compare the target feature information with each piece of address feature information in the filter lookup table; In a case where the target characteristic information is the same as any of the address characteristic information, determining a filter entry corresponding to any of the address characteristic information as the first filter entry; When the target characteristic information is different from all address characteristic information in the filter lookup table, it is determined that the first filter entry does not exist in the filter lookup table.

3. The pre-fetch control device according to claim 2, characterized in that: The first prefetcher includes an address pattern statistics table, which includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address pattern statistics table, and the amount of data in the address pattern statistics table is greater than the amount of data in the filter lookup table.

4. The pre-fetch control device according to claim 3, characterized in that: Each of the filtering items also includes item evaluation information; The prefetch control device further includes an update module, the update module being used to be coupled to the first prefetcher, and the update module being configured to, after the indication module instructs the prefetch input filter to send the target memory access information to the first prefetcher instead of to the second prefetcher: In response to the first prefetcher feeding back that the target memory access information hits a first prediction entry in the address regularity statistics table and the credibility corresponding to the first prediction entry is greater than or equal to a preset credibility threshold, increasing the evaluation value of the entry evaluation information corresponding to the first filtering entry by a preset step length; wherein the first prediction entry is a prediction entry in the address regularity statistics table corresponding to the first filtering entry, and the data volume of the first filtering entry is less than the data volume of the first prediction entry; or, In response to the first prefetcher feedback that the target memory access information hits the first prediction entry in the address regularity statistics table but the credibility corresponding to the first prediction entry is less than the credibility threshold, or in response to the first prefetcher feedback that the target memory access information does not hit any of the prediction entries in the address regularity statistics table, the first filter entry is marked as an illegal filter entry.

5. The pre-fetch control device according to any one of claims 1 to 4, characterized in that: The first prefetcher includes an address regularity statistics table, the address regularity statistics table includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address regularity statistics table, and the data volume of the address regularity statistics table is greater than the data volume of the filter lookup table; The instructing module is further configured to instruct the prefetching input filter to send the target memory access information to the first prefetcher and the second prefetcher respectively if the searching module fails to find the first filtering entry; The device also includes an insertion module, which is used to couple with the first prefetcher. The insertion module is configured to: in response to the search module failing to find the first filter entry and the first prefetcher feeding back that the target memory access information hits the first prediction entry, insert part of the content of the first prediction entry into the filter lookup table.

6. The pre-fetch control device according to claim 5, characterized in that: The plug-in module is configured to: Detecting whether there is an illegal filter entry in the filter lookup table, wherein the illegal filter entry exists in the filter lookup table, and a prediction entry corresponding to the illegal filter entry does not exist in the address regularity statistics table; In the case that the illegal filter entry exists in the filter lookup table, the corresponding content of the illegal filter entry is replaced with part of the content of the first prediction entry.

7. The pre-fetch control device according to claim 6, characterized in that: Each of the filtering items also includes item evaluation information; The plug-in module is configured to: In the case that the illegal filtering entry does not exist in the filtering lookup table, detecting whether there is a second filtering entry in the filtering lookup table, wherein the evaluation value of the entry evaluation information corresponding to the second filtering entry is a preset value; In the case that the second filter entry exists in the filter lookup table, corresponding content of the second filter entry is replaced with part of the content of the first prediction entry.

8. The pre-fetch control device according to claim 7, characterized in that: The plug-in module is configured to: In the case that the second filter entry does not exist in the filter lookup table, the evaluation values ​​of the entry evaluation information corresponding to each filter entry in the filter lookup table are reduced by a preset step length.

9. The pre-fetch control device according to any one of claims 1 to 4, characterized in that: The indication module is further configured to: when the search module finds the first filter entry, instruct the prefetch input filter to lock the target memory access information so that other prefetchers except the first prefetcher cannot perform data prefetch operations according to the target memory access information.

10. A pre-fetch control method, characterized in that: include: Get target access information from prefetch input filter; Searching in a preset filter lookup table whether there is a first filter entry corresponding to the target memory access information, wherein the filter lookup table is related to the address regularity information in the first prefetcher; When the first filter entry is found, the prefetch input filter is instructed to send the target memory access information to the first prefetcher and not to the second prefetcher; wherein the first time duration required for the first prefetcher to obtain the first prediction result based on its own address regularity information is greater than the second time duration required for the second prefetcher to obtain the second prediction result based on its own address regularity information under the same conditions; the first prediction result is used for the first prefetcher to perform data prefetch operations, and the second prediction result is used for the second prefetcher to perform data prefetch operations.

11. The prefetch control method according to claim 10, characterized in that: The filter lookup table includes at least one filter entry, each of which includes a piece of address feature information; The target memory access information includes a memory address corresponding to a cache line accessed by the target memory access instruction; The searching in a preset filter lookup table whether there is a first filter entry corresponding to the target memory access information includes: Determine the target feature information corresponding to the target memory access information according to a preset algorithm and the memory address, and compare the target feature information with each piece of address feature information in the filter lookup table; In a case where the target characteristic information is the same as any of the address characteristic information, determining a filter entry corresponding to any of the address characteristic information as the first filter entry; When the target characteristic information is different from all address characteristic information in the filter lookup table, it is determined that the first filter entry does not exist in the filter lookup table.

12. The prefetch control method according to claim 11, characterized in that: The first prefetcher includes an address pattern statistics table, which includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address pattern statistics table, and the amount of data in the address pattern statistics table is greater than the amount of data in the filter lookup table.

13. The prefetch control method according to claim 12, characterized in that: Each of the filtering items also includes item evaluation information; After instructing the prefetch input filter to send the target memory access information to the first prefetcher and not to the second prefetcher, the method further includes: In response to the first prefetcher feeding back that the target memory access information hits a first prediction entry in the address regularity statistics table and the credibility corresponding to the first prediction entry is greater than or equal to a preset credibility threshold, increasing the evaluation value of the entry evaluation information corresponding to the first filtering entry by a preset step length; wherein the first prediction entry is a prediction entry in the address regularity statistics table corresponding to the first filtering entry, and the data volume of the first filtering entry is less than the data volume of the first prediction entry; or, In response to the first prefetcher feedback that the target memory access information hits the first prediction entry in the address regularity statistics table but the credibility corresponding to the first prediction entry is less than the credibility threshold, or in response to the first prefetcher feedback that the target memory access information does not hit any of the prediction entries in the address regularity statistics table, the first filter entry is marked as an illegal filter entry.

14. The prefetch control method according to claim 13, characterized in that: The first prefetcher includes an address regularity statistics table, the address regularity statistics table includes at least one prediction entry; each filter entry in the filter lookup table has a corresponding prediction entry in the address regularity statistics table, and the data volume of the address regularity statistics table is greater than the data volume of the filter lookup table; The method further comprises: In case the first filter entry is not found, instructing the prefetch input filter to send the target memory access information to the first prefetcher and the second prefetcher respectively; In response to not finding the first filter entry and the first prefetcher feeding back that the target memory access information hits a first prediction entry, a portion of the content of the first prediction entry is inserted into the filter lookup table.

15. The pre-fetch control method according to claim 14, characterized in that: The method further comprises: Detecting whether there is an illegal filter entry in the filter lookup table, wherein the illegal filter entry exists in the filter lookup table, and a prediction entry corresponding to the illegal filter entry does not exist in the address regularity statistics table; In the case that the illegal filter entry exists in the filter lookup table, the corresponding content of the illegal filter entry is replaced with part of the content of the first prediction entry.

16. The pre-fetch control method according to claim 15, characterized in that: Each of the filtering items also includes item evaluation information; The method further comprises: In the case that the illegal filtering entry does not exist in the filtering lookup table, detecting whether there is a second filtering entry in the filtering lookup table, wherein the evaluation value of the entry evaluation information corresponding to the second filtering entry is a preset value; In the case that the second filter entry exists in the filter lookup table, corresponding content of the second filter entry is replaced with part of the content of the first prediction entry.

17. The prefetch control method according to claim 16, characterized in that: The method further comprises: In the case that the second filter entry does not exist in the filter lookup table, the evaluation values ​​of the entry evaluation information corresponding to each filter entry in the filter lookup table are reduced by a preset step length.

18. The pre-fetch control method according to any one of claims 10 to 13, characterized in that: After searching in a preset filter lookup table whether there is a first filter entry corresponding to the target memory access information, the method further includes: when the first filter entry is found, instructing the prefetch input filter to lock the target memory access information so that other prefetchers except the first prefetcher cannot perform data prefetch operations based on the target memory access information.

19. A processor, characterized in that: The processor comprises: a prefetch input filter, a prefetch control device, and a prefetcher, wherein the prefetch control device is the prefetch control device according to any one of claims 1 to 9; One end of the pre-fetch input filter is coupled to the pre-fetch control device, and the other end is coupled to each of the pre-fetchers, and is configured to sample the memory access behavior to obtain target memory access information; The pre-fetch control device is coupled to the pre-fetch input filter; The prefetcher includes the first prefetcher and the second prefetcher.

20. An electronic device, characterized in that: The electronic device includes a circuit board, a processor and a memory, wherein the processor and the memory are respectively arranged on the circuit board, and the processor is electrically connected to the memory for performing a read operation or a write operation on the memory, wherein the processor is the processor described in claim 19.

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