An in-chip memory repair system and method

Abstract

The application provides a chip-in-memory repair system and method, which comprises a chip-in-BIST logic and a BIST controller, a chip-in-BISR logic and a BISR controller, a chip-in-TAP controller and a chip-in-memory recovery controller, further comprises an external nonvolatile storage medium, the external nonvolatile storage medium has an access interface C17 with the chip-in-memory recovery controller, and the access interface C17 is used for recording memory repair information stored in the chip-in-memory recovery controller into the external nonvolatile storage medium or loading the memory repair information in the external nonvolatile storage medium into the chip-in-memory recovery controller. The technical scheme of the application guarantees that the memory repair can be performed at the board level, saves the efuse programming time of the test and repair memory on the ATE, and saves the efuse resources in the chip.

Description

Technical Field

[0001] This application belongs to the field of semiconductor storage technology, and specifically relates to an in-chip memory repair system and method. Background Technology

[0002] With the continuous development of chip technology and the increasing complexity of chips, the probability of chip defects or malfunctions also increases. Among these, memory, which occupies the largest area of ​​the chip, including RAM and ROM, is particularly vulnerable to defects or malfunctions that significantly impact chip operation. Since some memory defects are unavoidable during chip manufacturing, how to utilize these defective chips and maximize chip yield is a pressing issue that needs to be addressed.

[0003] The existing methods for repairing in-chip memory primarily rely on BIST logic testing within the chip to identify memory defects and then designing redundant BISR repair logic for fixes. However, this method has several drawbacks: firstly, it consumes significant ATE testing time; secondly, the method of recording repair information using efuse is one-time and irreversible, thus lacking flexibility when multiple modifications or repairs are required; and thirdly, it cannot be used in actual system applications.

[0004] Therefore, there is a need to provide a more efficient and flexible memory repair system and method to adapt to the actual usage requirements of the chip in the system. Summary of the Invention

[0005] The purpose of this application is to provide an in-chip memory repair system and method, which aims to ensure that memory repair can be performed at the board level, thereby saving the testing and repair time of memory efuse programming on the ATE and saving efuse resources within the chip.

[0006] The first aspect of this application proposes an on-chip memory repair system, including an on-chip TAP (Test Access Port) controller, on-chip BIST logic, on-chip BISR logic and BISR controller, and an on-chip memory recovery controller. It includes an external non-volatile storage medium, wherein the external non-volatile storage medium and the on-chip memory recovery controller have an access interface C17. The access interface C17 is used to record memory repair information stored in the on-chip memory recovery controller to the external non-volatile storage medium or to load memory repair information from the external non-volatile storage medium into the on-chip memory recovery controller.

[0007] In an optional implementation, an external non-volatile storage medium update tool is further included, the external non-volatile storage medium update tool having an access interface C23 for updating the external non-volatile storage medium.

[0008] In an optional implementation, the TAP controller is logically connected to the BIST via the BIST control interface C3, and a first MUX (Multiplexer) is provided between the TAP controller and the on-chip memory recovery controller. The TAP controller is connected to the first MUX via the repair information transmission interface C13.1.

[0009] In an optional implementation, the BISR controller is connected to a single BISR logic via the BISR configuration interface C21. The single BISR logic is connected to different ROM entities C11.1, C11.2, ..., C11.m within the chip via access buses C9.1, C9.2, ..., C9.m, and to different RAM entities C12.1, C12.2, ..., C12.n within the chip via access buses C10.1, C10.2, ..., C10.n.

[0010] In an optional implementation, the BISR controller is connected to multiple BISR logics via a BISR configuration interface, and the multiple BISR logics are respectively connected to an on-chip ROM entity or a RAM entity.

[0011] In an optional implementation, the BIST logic has one or more second MUXs between it and one or more BISR logics, the one or more second MUXs being connected to the BIST logic via a memory test access interface C5.0, and the second MUXs being connected to one or more BISR logics via a memory access interface C7.

[0012] In an optional implementation, the in-chip memory recovery controller is connected to the BISR controller via a repair information transmission interface C19.

[0013] In an optional implementation, the second-MUX has a main function access interface C5.1 for memory.

[0014] In an optional implementation, the BIST logic is connected to the on-chip memory recovery controller via the repair information transmission interface C13.0.

[0015] In an optional implementation, the TAP controller has a test interface C1, which provides test control and comparison information of ROM contents.

[0016] The second aspect of this application proposes a method for repairing in-chip memory, comprising the following steps:

[0017] The startup test is performed by providing test control and ROM content comparison information to the memory through the test interface of the TAP controller, and testing the memory through BIST logic.

[0018] If a memory defect is found during testing, the memory repair information is transmitted to the on-chip memory recovery controller, which then records the repair information to an external non-volatile medium; or,

[0019] Without performing a boot test, the external non-volatile storage medium is directly updated using the external non-volatile storage medium update tool;

[0020] When the chip starts up, the on-chip memory recovery controller loads the repair information of the memory in the external non-volatile medium and repairs the specified location on the memory through the BISR repair logic.

[0021] In an optional implementation, the BISR repair logic controls or repairs all ROM or RAM entities of the memory.

[0022] In an optional implementation, the BISR repair logic controls or repairs each ROM or RAM entity of the memory individually.

[0023] Compared with related technologies, the technical solution of this application has at least the following advantages:

[0024] 1. This application utilizes a chip board-level platform and custom and redundant designs within the chip to perform memory repair within the chip. The board-level design is compatible with previous designs, keeping the BOM cost (Bill of Materials, the cost of various raw materials, components, tools and labor required in the product manufacturing process, mainly referring to the cost of board-level raw materials) unchanged.

[0025] 2. This application changes the method of memory testing and repair updates from the ATE testing process to the board-level SLT (System Level Test) process or the board-level mass production flashing process, saving expensive ATE testing time;

[0026] 3. This application saves the efuse overhead required for recording memory repair information within the chip;

[0027] 4. Since the repair information is recorded in an external non-volatile storage medium, and this part of the repair information is dynamically configured for the BISR repair logic within the chip, this application can be modified and updated multiple times.

[0028] 5. The repair information can be repeatedly updated in different or the same locations. In particular, the modification of ROM content is not limited to repair. When it is found that the ROM content (such as some important parameters are placed in the ROM) needs to be updated, the same or different locations of the ROM can be modified multiple times as needed and reused repeatedly to improve chip utilization and yield.

[0029] 6. This application provides multiple repairs throughout the chip's entire lifecycle, provided that redundancy allows;

[0030] 7. In the event of redundancy exhaustion, this application can adjust the priority and repair strategy according to the importance of different locations of different memories that need to be repaired, so as to maximize the use of memory in the chip and ensure that the most important functions in the chip can operate normally through differentiated repair strategies.

[0031] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures and processes shown in the description and the accompanying drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a centrally controlled memory repair system according to an exemplary embodiment of this application.

[0034] Figure 2 This is a schematic diagram of a memory repair system with separate control according to an exemplary embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] With the continuous development of chip technology and the increasing complexity of chips, the probability of chip defects or malfunctions also increases. Among these defects, memory occupies the largest area of ​​the chip. Chip memory generally includes RAM (Random Access Memory) and ROM (Read Only Memory). Since the program or data used by the chip during operation comes from its internal memory, memory defects or malfunctions have a significant impact on chip operation. Moreover, as an unavoidable process in chip manufacturing, some memory defects introduced during production are inevitable. To address this, redundancy design is generally considered from the initial design stage, allowing for memory repair during manufacturing and use. In fact, memory repair has become an indispensable technical means in chip development and manufacturing.

[0037] Currently, relevant methods for in-chip memory repair mainly rely on BIST (Build-in Self-Test) logic designed within the chip to detect memory defects, and then design redundant BISR (Build-in Self-Repair) logic for repair. After the memory defect is detected by the in-chip BIST logic, the repair information is actively recorded in the in-chip efuse (Electronic Fuse) controller. Finally, when the chip starts up, the BISR repair logic repairs the memory based on the repair information recorded in the efuse. Once the efuse in the chip is programmed, the corresponding repair information cannot be changed again. This approach has gained the support of many EDA (Electronic Design Automation) vendors and has become a typical design method and technology in the DFT (Design for Test) toolchain for chip design.

[0038] However, this method has some shortcomings: First, the design concept mainly considers the recording of test and repair information on the ATE (Automatic Test Equipment, an automated test machine for chip testing), thus consuming expensive ATE testing time; second, the method of recording repair information using efuse is one-time and irreversible, so it lacks flexibility when multiple modifications or repairs are needed; third, it cannot be repaired in actual system use, because memory repair may need to be addressed throughout the entire life cycle of the chip, and the method of using efuse and factory one-time repair cannot solve the problems faced by the chip in actual system use to the greatest extent.

[0039] Based on the above analysis, an exemplary implementation of a centralized memory repair system provided in this application is as follows: Figure 1 As shown. The centralized memory repair system includes an on-chip TAP controller C2, an on-chip BIST logic C4, an on-chip BISR logic C8 and a BISR controller C20, an on-chip save and restore controller (used for data storage and recovery within the chip) C16, an external non-volatile storage medium C18, and an external non-volatile storage medium update tool C22. A first MUX C14 is located between the on-chip TAP controller C2 and the on-chip save and restore controller C16, and a second MUX C6 is located between the on-chip BISR logic C8 and the on-chip BIST logic C4.

[0040] For example, the TAP controller C2 described above has a test interface C1, which is used to provide comparison information of test control and ROM content. The test interface C1 is usually a JTAG interface (Joint Test Action Group, which is a common name for the IEEE standard 1149.1 for standard test access ports and boundary scan structures), but is not limited to the JTAG interface. Considering the need to accelerate the process of testing and repair information recording at the system level, a custom interface can also be used.

[0041] For example, the TAP controller C2 provides BIST test control and ROM content comparison information through an external test interface C1, or directly starts and configures the in-chip storage and repair controller C16 to record memory repair information after being selected by the logic of the first MUX C14. The first MUX C14 implements the switching control of the repair information transmission interface C13.1, and has a corresponding repair information transmission interface C15 after the selection switch. The repair information transmitted by the BIST logic C4 or the TAP controller C2 is finally transmitted to the in-chip storage and repair controller C16 through this interface. The TAP controller C2 is connected to the first MUX through the repair information transmission interface C13.1. Similarly, considering the need to accelerate the testing and repair information recording process at the system level, the TAP controller C2 can be developed and designed according to a custom test interface.

[0042] For example, the TAP controller C2 is connected to the on-chip BIST logic C4 via the BIST control interface C3. The on-chip BIST logic C4 is an embedded self-test logic. When a memory defect is found during testing, it can transmit the memory repair information to the on-chip storage and repair controller C16. The on-chip BIST logic is connected to the on-chip storage and recovery controller C16 via the repair information transmission interface C13.0, and the on-chip storage and repair controller C16 records the memory repair information to the external non-volatile storage medium C18.

[0043] Furthermore, the aforementioned BISR controller C20 is connected to the BISR logic C8 via the BISR configuration interface C21. The BISR logic C8 is an embedded redundant memory repair logic (Build-in SelfRepair). Through the configured memory repair information, it can repair a specified location on a specified memory. Different configurations can achieve repair on different locations on different memories; that is, changing the BISR configuration means changing the repair location and repair strategy for different memories. The aforementioned in-chip memory recovery controller C16 is connected to the aforementioned BISR controller C20 via the repair information transmission interface C19.

[0044] For example, the BISR logic C8 is connected to different ROM entities C11.1, C11.2, ..., C11.m within the chip via access buses C9.1, C9.2, ..., C9.m, and is connected to different RAM entities C12.1, C12.2, ..., C12.n within the chip via access buses C10.1, C10.2, ..., C10.m.

[0045] The aforementioned BIST logic C4 and BISR logic C8 are connected by a second MUXC6. The second MUXC6 is connected to the BIST logic C4 via a memory test access interface C5.0, and to the BISR logic C8 via a memory access interface C7. After passing through the BISR logic C8, the memory access interface C7 can replace the repaired memory with redundant repair logic provided within the BISR, thus realizing the memory repair function. The second MUXC6 has a main memory access interface C5.1.

[0046] The external non-volatile storage medium C18 and the on-chip memory recovery controller C16 share an access interface C17. This access interface C17 is used to record memory repair information stored in the on-chip memory recovery controller C16 to the external non-volatile storage medium C18 or to load memory repair information from the external non-volatile storage medium C18 into the on-chip memory recovery controller C16. The external non-volatile storage medium update tool C22 has an access interface C23 for updating the external non-volatile storage medium C18.

[0047] In another implementation, the BISR repair logic and repair information can be distributed across the ROM or RAM entities corresponding to each memory, thus achieving a separately controlled memory repair system, such as... Figure 2 As shown in the diagram. The BISR controller connects to multiple BISR logic units via a BISR configuration interface. These BISR logic units are connected to either an on-chip ROM entity or a RAM entity. Each of these BISR logic units is connected to the BIST logic unit via multiple MUXs.

[0048] A second aspect of this application exemplarily provides a method for on-chip memory repair using the aforementioned on-chip memory repair system, comprising the following steps:

[0049] The startup test is performed by providing test control and ROM content comparison information to the memory through the test interface of the TAP controller, and testing the memory through BIST logic.

[0050] If a memory defect is found during testing, the memory repair information is transmitted to the on-chip memory recovery controller, which then records the memory repair information into an external non-volatile medium.

[0051] Alternatively, without performing a boot test, the external non-volatile storage medium can be updated directly using the external non-volatile storage medium update tool;

[0052] When the chip starts up, the on-chip memory recovery controller loads the repair information of the memory in the external non-volatile medium and repairs the specified location on the memory through the BISR repair logic.

[0053] For example, the above BISR repair logic can control or repair all ROM or RAM entities of the memory, or it can control or repair each ROM or RAM entity of the memory individually.

[0054] As can be seen, the on-chip memory repair system and method proposed in this application have the following advantages compared with related technologies:

[0055] This application's in-chip memory repair system maintains the existing BIST and BISR designs within the chip to the greatest extent possible, but introduces the memory repair method from within the chip to the board-level system. A new workflow and mechanism are defined on a system compatible with previous board-level designs, and in conjunction with the unique design within the chip, memory repair information is recorded in an external non-volatile storage medium. During chip startup, the repair information is loaded from the external non-volatile storage medium for repair, ensuring that memory repair can be performed at the board level. This not only saves time on ATE testing and memory repair efuse programming but also conserves efuse resources within the chip. Furthermore, since the repair information on the external non-volatile storage medium can be easily modified and adjusted, and this repair information is dynamically configured for the BISR repair logic within the chip, multiple repeated updates are possible. Especially for ROM content modifications, it is not limited to repair; when the ROM content (e.g., important parameters stored in the ROM) needs adjustment, the same location in the ROM can be modified multiple times as needed for repeated use.

[0056] It is understood that the circuit structures, names, and parameters described in the above embodiments are merely examples. Those skilled in the art can also make readily conceived combinations and adjustments to the structural features of the above embodiments according to their needs, and the concept of this application should not be limited to the specific details of the above examples.

[0057] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An on-chip memory repair system, comprising an on-chip TAP controller, on-chip BIST logic, on-chip BISR logic and BISR controller, and an on-chip memory recovery controller, characterized in that, Includes an external non-volatile storage medium, wherein the external non-volatile storage medium and the on-chip memory recovery controller have an access interface C17, wherein the access interface C17 is used to record memory repair information stored in the on-chip memory recovery controller to the external non-volatile storage medium or to load memory repair information in the external non-volatile storage medium into the on-chip memory recovery controller; The BISR controller is connected to a single BISR logic via the BISR configuration interface C21. The single BISR logic is connected to different ROM entities C11.1, C11.2, ..., C11.m within the chip via access buses C9.1, C9.2...C9.m, and to different RAM entities C12.1, C12.2...C12.n within the chip via access buses C10.1, C10.2...C10.n. The BIST logic and the individual BISR logic are connected by a second MUX, which is connected to the BIST logic via a memory test access interface C5.0 and to the individual BISR logic via a memory access interface C7.

2. The in-chip memory repair system according to claim 1, characterized in that, It further includes an external non-volatile storage medium update tool, which has an access interface C23 for updating the external non-volatile storage medium.

3. The in-chip memory repair system according to claim 1, characterized in that, The TAP controller is logically connected to the BIST via the BIST control interface C3. The TAP controller and the on-chip memory recovery controller have a first MUX. The TAP controller is connected to the first MUX via the repair information transmission interface C13.

1.

4. The in-chip memory repair system according to claim 1, characterized in that, The second MUX has the main function access interface C5.1 for memory.

5. The in-chip memory repair system according to claim 1, characterized in that, The in-chip memory recovery controller is connected to the BISR controller via the repair information transmission interface C19.

6. The in-chip memory repair system according to claim 1, characterized in that, The BIST logic is connected to the first MUX C14 within the chip via the repair information transmission interface C13.

0.

7. The in-chip memory repair system according to claim 1, characterized in that, The TAP controller has a test interface C1, which is used to provide test control and comparison information of ROM content.

8. An on-chip memory repair system, comprising an on-chip TAP controller, on-chip BIST logic, on-chip BISR logic and BISR controller, and an on-chip memory recovery controller, characterized in that, Includes an external non-volatile storage medium, which has an access interface with the on-chip memory recovery controller. The access interface is used to record memory repair information stored in the on-chip memory recovery controller to the external non-volatile storage medium or to load memory repair information in the external non-volatile storage medium into the on-chip memory recovery controller. The BISR controller is connected to multiple BISR logics through a BISR configuration interface, and the multiple BISR logics are respectively connected to the ROM entity or RAM entity in each chip. The BIST logic and multiple BISR logics have multiple second MUXs. The multiple second MUXs are connected to the BIST logic through a memory test access interface, and the second MUXs are connected to the multiple BISR logics through a memory access interface.

9. The in-chip memory repair system according to claim 8, characterized in that, The second MUX has a main function access interface for memory.

10. A method for repairing in-chip memory, characterized in that, The repair method is performed using the on-chip memory repair system as described in any one of claims 1-9, and includes the following steps: The startup test is performed by providing test control and ROM content comparison information to the memory through the test interface of the TAP controller, and testing the memory through BIST logic. If a memory defect is found during testing, the memory repair information is transmitted to the on-chip memory recovery controller, which then records the memory repair information into an external non-volatile medium. or, Without performing a boot test, the external non-volatile storage medium is directly updated using the external non-volatile storage medium update tool; When the chip starts up, the on-chip memory recovery controller loads the repair information of the memory in the external non-volatile medium and repairs the specified location on the memory through the BISR repair logic.

11. The on-chip memory repair method according to claim 10, characterized in that, The BISR repair logic controls or repairs all ROM or RAM entities of the memory; or, the BISR repair logic controls or repairs each ROM or RAM entity of the memory individually.

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