Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a hard mask structure on a portion of the substrate surface, the hard mask structure including a hard mask layer and a protective layer located on the hard mask layer, the protective layer and the hard mask layer being made of different materials; using the hard mask structure as a mask, etching the substrate using a first etching process to form trenches within the substrate, wherein after forming the trenches, the protective layer is still retained and the hard mask layer is not exposed; forming an isolation material layer within the trenches and on the surface of the protective layer, the top surface of the isolation material layer being higher than the top surface of the protective layer, and the material of the isolation material layer being different from the material of the hard mask layer; planarizing the isolation material layer and the protective layer until the hard mask layer is exposed, thereby forming an isolation layer with the isolation material layer; after the planarization process, removing the hard mask layer, which helps to reduce the probability of substrate exposure on the sidewalls of the trenches, helps to reduce the linewidth roughness of the isolation layer, improves the performance of the finally formed device, and reduces the probability of leakage current abnormalities.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] Shallow Trench Isolation (STI) technology plays a crucial role in the isolation between devices and in preventing leakage current.

[0003] Shallow trench isolation typically involves first depositing a silicon nitride (Si3N4) layer on a semiconductor substrate, then patterning the silicon nitride layer to form a hard mask. Next, shallow trenches are etched into the isolation region of the substrate, followed by the deposition of an oxide layer (SiO2). The substrate is then planarized using a chemical mechanical polishing (CMP) process to remove excess oxide. Finally, the silicon nitride layer is removed using an acid pickling process.

[0004] However, the existing shallow trench isolation process needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a hard mask structure on a portion of the substrate surface, the hard mask structure including a hard mask layer and a protective layer located on the hard mask layer, the protective layer and the hard mask layer being made of different materials; using the hard mask structure as a mask, etching the substrate using a first etching process to form trenches within the substrate, wherein after forming the trenches, the protective layer remains and the hard mask layer is not exposed; forming an isolation material layer within the trenches and on the surface of the protective layer, the top surface of the isolation material layer being higher than the top surface of the protective layer, and the material of the isolation material layer being different from the material of the hard mask layer; planarizing the isolation material layer and the protective layer until the hard mask layer is exposed, thereby forming an isolation layer with the isolation material layer; and removing the hard mask layer after the planarization process.

[0007] Optionally, the method for forming the hard mask structure includes: forming a hard mask material layer and a protective material layer on the substrate; patterning the protective material layer and the hard mask material layer, forming the protective layer with the patterned protective material layer, and forming the hard mask layer with the patterned hard mask material layer.

[0008] Optionally, the hard mask layer includes a buffer layer and an etch barrier layer located on the buffer layer; the hard mask material layer includes a buffer material layer and an etch barrier material layer located on the surface of the buffer material layer; the method of forming the hard mask layer further includes: forming the buffer layer with the buffer material layer and forming the etch barrier layer with the etch barrier material layer.

[0009] Optionally, the buffer layer is made of silicon oxide; the etching barrier layer is made of silicon nitride.

[0010] Optionally, the method for patterning the protective material layer and the hard mask material layer includes: forming a photoresist material layer on the surface of the protective material layer; patterning the photoresist material layer to form a photoresist layer; and using the photoresist layer as a mask to etch the protective material layer and the hard mask material layer.

[0011] Optionally, the thickness range of the photoresist material layer is [missing information]. to

[0012] Optionally, before forming the photoresist material layer, the method further includes: forming a bottom anti-reflective layer on the surface of the protective material layer, wherein the photoresist material layer is located on the surface of the bottom anti-reflective layer.

[0013] Optionally, before etching the protective material layer and the hard mask material layer, the method further includes: using the photoresist layer as a mask to etch the bottom anti-reflection layer.

[0014] Optionally, the thickness range of the bottom anti-reflective layer is [missing information]. to

[0015] Optionally, before forming the protective material layer, the method further includes: determining the thickness of the protective material layer according to the first etching process.

[0016] Optionally, the substrate includes a central region and an edge region surrounding the central region; the first etching process has a first etching rate on the protective layer on the edge region and a second etching rate on the protective layer on the central region, the first etching rate and the second etching rate being different; the first etching rate is greater than the second etching rate.

[0017] Optionally, the etching selectivity ratio of the first etching process for the protective layer and the substrate ranges from 1:3 to 1:8.

[0018] Optionally, the thickness range of the hard mask layer is: to

[0019] Optionally, the thickness range of the protective layer is: to

[0020] Optionally, the material of the protective layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0021] Optionally, the material of the hard mask layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0023] In the semiconductor structure formation method provided by the present invention, a hard mask structure is used as a mask, and a first etching process is used to etch the substrate to form trenches in the substrate. After the trenches are formed, the protective layer is still retained, and the hard mask layer is not exposed. Since the hard mask layer is protected by the protective layer, the etching damage to the hard mask layer caused by the first etching process and the uneven thickness problem of the hard mask layer introduced by the first etching process are reduced. This facilitates precise control of the thickness of the hard mask layer, thereby facilitating control of the step height formed between the top surface of the isolation layer and the substrate surface and the uniformity of the step height. This, in turn, helps to reduce the probability of substrate exposure on the trench sidewalls, reduces the linewidth roughness of the isolation layer, improves the performance of the finally formed device, and reduces the probability of leakage current abnormalities. Attached Figure Description

[0024] Figures 1 to 4 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0025] Figure 5 This is a flowchart of the steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0026] Figures 6 to 12 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0027] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0028] As described in the background section, existing shallow trench isolation processes require further improvement. The following analysis will illustrate this with reference to the formation process of a semiconductor structure.

[0029] Figures 1 to 4This is a cross-sectional schematic diagram of the formation process of a semiconductor structure.

[0030] Please refer to Figure 1 A substrate 100 is provided; a hard mask layer is formed on a portion of the surface of the substrate 100, the hard mask layer including an oxide layer 101 and a silicon nitride layer 102 located on the surface of the oxide layer 101; the substrate 100 is etched using the hard mask layer as a mask to form a trench 103 in the substrate 100.

[0031] Please refer to Figure 2 An isolation material layer 104 is formed in the trench 103 and on the surface of the hard mask layer, and the isolation material layer 104 is higher than the hard mask layer.

[0032] Please refer to Figure 3 The isolation material layer 104 is planarized until the hard mask layer is exposed.

[0033] Please refer to Figure 4 Remove the hard mask layer and form an isolation structure 105 with the isolation material layer 104.

[0034] The above method is used in shallow trench isolation processes, where the substrate 100 between adjacent isolation structures 105 is an active region. After the planarization process, a dishing defect (e.g., ...) will occur on the surface of the isolation material layer 104. Figure 3 As shown by the dashed line in the middle, during the removal of the hard mask layer, the isolation material layer 104 is also etched. The edges of the butterfly-shaped defect are more easily etched than the center, causing a protrusion to form on the top surface of the isolation structure 105 (as shown by the dashed line in the middle). Figure 4 As shown in region A), a step is formed between the top surface of the isolation structure 105 and the substrate surface. When the height h of this step is small, it easily leads to the exposure of the active region sidewall, resulting in a groove (e.g., at the interface between the active region and the isolation structure 105) at the adjacent interface. Figure 5 As shown in region B, the groove B is easily filled with metal silicide material in the subsequent Salicide process, which leads to device leakage problems.

[0035] The height h of the step is achieved by controlling the thickness of the hard mask layer. However, in the etching process of forming the trench 103, due to the etching edge effect where the gas concentration on the wafer surface increases from the center to the edge, after the trench 103 is formed, the thickness of the hard mask layer at the wafer edge is lower than that at the wafer center. This makes it difficult to control the uniformity of the step height h across the entire wafer, affecting the performance of the final device.

[0036] To address the aforementioned issues, this invention provides a method for forming a semiconductor structure. A hard mask structure is used as the mask, and a first etching process is employed to etch the substrate, forming trenches within the substrate. After the trenches are formed, the protective layer remains, and the hard mask layer is not exposed. Because the hard mask layer is protected by the protective layer, the etching damage caused by the first etching process to the hard mask layer is reduced, as is the thickness unevenness of the hard mask layer introduced by the first etching process. This facilitates precise control of the hard mask layer thickness, thereby enabling control of the step height and uniformity between the top surface of the isolation layer and the substrate surface. Consequently, it reduces the probability of substrate exposure on the trench sidewalls, lowers the linewidth roughness of the isolation layer, improves the performance of the final formed device, and reduces the probability of leakage current abnormalities.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figure 5 This is a flowchart of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] In this embodiment, the method for forming the semiconductor structure includes the following steps:

[0040] Step S201: Provide a substrate.

[0041] Step S202: A hard mask structure is formed on a portion of the substrate surface. The hard mask structure includes a hard mask layer and a protective layer located on the hard mask layer. The protective layer and the hard mask layer are made of different materials.

[0042] Step S203: Using the hard mask structure as a mask, the substrate is etched using a first etching process to form trenches in the substrate. After the trenches are formed, the protective layer is still retained and the hard mask layer is not exposed.

[0043] Step S204: An isolation material layer is formed in the trench and on the surface of the protective layer, the top surface of the isolation material layer is higher than the top surface of the protective layer, and the material of the isolation material layer is different from the material of the hard mask layer;

[0044] Step S205: Planarize the isolation material layer and the protective layer until the hard mask layer is exposed, thereby forming an isolation layer with the isolation material layer;

[0045] Step S206: After the planarization process, the hard mask layer is removed.

[0046] The following will be described in detail with reference to the accompanying drawings.

[0047] Figures 6 to 12 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0048] Please refer to Figure 6 Substrate 300 is provided.

[0049] In this embodiment, the substrate 300 is made of silicon.

[0050] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0051] In this embodiment, the substrate 300 includes a central region (not shown in the figure) and an edge region surrounding the central region (not shown in the figure).

[0052] Subsequently, a hard mask structure is formed on a portion of the surface of the substrate 300. The hard mask structure includes a hard mask layer and a protective layer located on the hard mask layer. The protective layer and the hard mask layer are made of different materials.

[0053] In this embodiment, the method for forming the hard mask structure is described in reference [reference needed]. Figures 6 to 8 .

[0054] Please continue to refer to this. Figure 6 A hard mask material layer 301 and a protective material layer 302 located on the surface of the hard mask material layer 301 are formed on the substrate 300.

[0055] In this embodiment, before forming the protective material layer 302, the method further includes: determining the thickness of the protective material layer 302 according to a subsequent first etching process. The protective material layer 302 is used to form a protective layer, and an appropriate thickness of the protective material layer 302 is selected to ensure that the protective layer is still retained after the first etching process.

[0056] In this embodiment, the thickness range of the protective material layer 302 is [missing information]. to

[0057] The material of the protective material layer 302 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0058] In this embodiment, the material of the protective material layer 302 is silicon oxide.

[0059] In this embodiment, the thickness range of the hard mask material layer 301 is [missing information]. to

[0060] In this embodiment, the hard mask material layer 301 is a double-layer material layer. Specifically, the hard mask material layer includes a buffer material layer 301a and an etching barrier material layer 301b located on the surface of the buffer material layer 301a. In another embodiment, the hard mask material layer can be a single-layer or multi-layer material layer.

[0061] Specifically, the thickness range of the etching barrier material layer 301b is [missing information]. to The thickness range of the etching barrier material layer 301b is: to

[0062] The hard mask material layer 301 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbide. The hard mask material layer 301 is used to form a hard mask layer.

[0063] In this embodiment, the buffer material layer 301a is made of silicon oxide; the etching barrier material layer 301b is made of silicon nitride. The buffer material layer 301a is used to reduce the stress between the etching barrier material layer 301b and the substrate 300.

[0064] Subsequently, the protective material layer 302 and the hard mask material layer 301 are patterned, with the patterned protective material layer 302 forming the protective layer and the patterned hard mask material layer forming the hard mask layer.

[0065] In this embodiment, the method for graphically representing the protective material layer 302 and the hard mask material layer 301 is described in reference [reference needed]. Figures 7 to 8 .

[0066] Please refer to Figure 7 A photoresist material layer (not shown in the figure) is formed on the surface of the protective material layer 302; the photoresist material layer is patterned to form a photoresist layer 304.

[0067] In this embodiment, the thickness range of the photoresist material layer is: to Here, the thickness of the photoresist material layer is determined based on the thickness of the protective material layer 302 to avoid the photoresist layer 304 being consumed before the etching is completed during the subsequent etching of the protective material layer 302.

[0068] In this embodiment, before forming the photoresist material layer, a bottom anti-reflection layer 303 is also formed on the surface of the protective material layer, and the photoresist material layer is located on the surface of the bottom anti-reflection layer 303.

[0069] In this embodiment, the thickness range of the bottom anti-reflective layer 303 is [missing information]. to Here, the thickness of the bottom anti-reflective layer is determined based on the thickness of the photoresist material layer.

[0070] Please refer to Figure 8 Using the photoresist layer 304 as a mask, the protective material layer 302 and the hard mask material layer 301 are etched to form the protective layer 305 and the hard mask layer 306.

[0071] In this embodiment, the thickness range of the hard mask layer 306 is [missing information]. to

[0072] In this embodiment, the thickness range of the protective layer 305 is [missing information]. to

[0073] In this embodiment, the hard mask layer 306 includes a buffer layer 306a and an etch barrier layer 306b located on the buffer layer 306a.

[0074] In this embodiment, the method for forming the hard mask layer 306 further includes: forming the buffer layer 306a with the buffer material layer 301a, and forming the etch barrier layer 306b with the etch barrier material layer 301b.

[0075] In this embodiment, before etching the protective material layer 302 and the hard mask material layer 301, the bottom anti-reflection layer 303 is etched using the photoresist layer 304 as a mask.

[0076] In this embodiment, after forming the hard mask layer 306, the photoresist layer 304 and the bottom anti-reflection layer 303 are also removed.

[0077] Please refer to Figure 9 Using the hard mask structure as a mask, the substrate 300 is etched using a first etching process to form a trench 307 in the substrate 300. After the trench 307 is formed, the protective layer 305 is still retained and the hard mask layer 306 is not exposed.

[0078] In the first etching process, the protective layer 305 protects the hard mask layer 306, which helps to control the thickness uniformity of the hard mask layer 306 on the entire substrate 300.

[0079] The first etching process has a first etching rate for the protective layer 305 on the edge region and a second etching rate for the protective layer 305 on the center region, wherein the first etching rate and the second etching rate are different.

[0080] In this embodiment, the first etching rate is greater than the second etching rate. Here, the difference between the first and second etching rates is due to the etching edge effect. In another embodiment, the first etching rate is less than the second etching rate.

[0081] In this embodiment, the first etching process includes a dry etching process.

[0082] In this embodiment, the etching selectivity ratio of the first etching process for the protective layer 305 and the substrate 300 ranges from 1:3 to 1:8.

[0083] It should be noted that an appropriate thickness of the protective layer 305 (protective material layer 302) needs to be selected to ensure that the protective layer 305 is still retained after the first etching process.

[0084] Specifically, the first etching rate, the second etching rate, the etching selectivity ratio of the first etching process for the protective layer and the substrate, and the depth range of the trench can be provided in advance; the thickness of the protective material layer 302 can be determined based on the first etching rate, the second etching rate, the etching selectivity ratio, and the depth range of the trench; or a suitable first etching process can be selected subsequently based on the set thickness of the protective layer 305.

[0085] Please refer to Figure 10 An isolation material layer 308 is formed in the trench 307 and on the surface of the protective layer 305. The top surface of the isolation material layer 308 is higher than the top surface of the protective layer 305, and the material of the isolation material layer 308 is different from the material of the hard mask layer 306.

[0086] The material of the insulating material layer 308 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0087] In this embodiment, the material of the isolation material layer 308 is silicon oxide.

[0088] The process for forming the isolation material layer 308 includes chemical vapor deposition (CVD).

[0089] In this embodiment, the isolation material layer 308 is formed by high-density plasma deposition (HDP).

[0090] Please refer to Figure 11 The isolation material layer 308 and the protective layer 305 are planarized until the hard mask layer 306 is exposed, and the isolation material layer 308 forms the isolation layer 309.

[0091] The planarization process includes a mechanical chemical polishing (CMP) process.

[0092] In the planarization process, the hard mask layer 306 acts as an etching stop. As mentioned above, the protective layer 305 improves the thickness uniformity of the hard mask layer 306 across the entire substrate 300. Therefore, the hard mask layer 306 (the hard mask material layer 301) can be set to a thinner thickness, which helps to reduce the planarization process time and, consequently, the depth of the dishing defect D on the surface of the isolation layer 309.

[0093] In this embodiment, the planarization process has a first grinding rate on the isolation material layer 308 and a second grinding rate on the hard mask layer 306. The ratio of the first grinding rate to the second grinding rate is in the range of 10:1 to 100:1.

[0094] Please refer to Figure 12 After the planarization process, the hard mask layer 306 is removed.

[0095] Thus, because the hard mask layer is protected by the protective layer, the etching damage to the hard mask layer caused by the first etching process is reduced, as is the thickness unevenness of the hard mask layer introduced by the first etching process. This facilitates precise control of the thickness of the hard mask layer, thereby facilitating control of the step height H formed between the top surface of the isolation layer 309 and the surface of the substrate 300, and the uniformity of the step height H. Consequently, it helps to reduce the exposure of the substrate 300 on the sidewalls of the trench 307. Figure 12 The probability (shown by the dashed line) helps to reduce the line width roughness of the isolation layer 309, improve the performance of the final device, and reduce the probability of leakage current abnormality.

[0096] It should be noted that the substrate 300 between the trenches 307 is used to form the active region of the device.

[0097] The process for removing the hard mask layer 306 is a second etching process, which includes one or both of dry etching and wet etching. In this embodiment, the second etching process is a wet etching process.

[0098] The etching selectivity ratio of the second etching process for the etching barrier layer 306b and the isolation material layer 308 ranges from 10:1 to 200:1.

[0099] In this embodiment, during the second etching process, since both the buffer layer 306a and the isolation layer 308 are made of silicon oxide, the isolation layer 309 is also etched while the buffer layer 306a is being removed. Because the depth of the butterfly-shaped defect D on the surface of the isolation layer 309 is small, the surface of the formed isolation layer 309 is relatively flat, reducing the exposure of the substrate 300 on the sidewalls of the trench 307. Figure 12 The probability (shown by the dashed line in the middle) is beneficial to improving the performance of the formed device.

[0100] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a central region and an edge region surrounding the central region; A hard mask material layer and a protective material layer located on the surface of the hard mask material layer are formed on the substrate; A photoresist material layer is formed on the surface of the protective material layer; The photoresist material layer is patterned to form a photoresist layer; Using the photoresist layer as a mask, the protective material layer and the hard mask material layer are etched, and the protective material layer and the hard mask material layer are patterned. The patterned protective material layer forms a protective layer, and the patterned hard mask material layer forms a hard mask layer, thereby forming a hard mask structure on a portion of the substrate surface. The hard mask structure includes the hard mask layer and the protective layer located on the hard mask layer. The protective layer and the hard mask layer are made of different materials. After forming the hard mask layer, the photoresist layer is removed; Using the hard mask structure as a mask, the substrate is etched using a first etching process to form trenches in the substrate. After the trenches are formed, the protective layer is still retained and the hard mask layer is not exposed. The first etching process has a first etching rate for the protective layer on the edge region and a second etching rate for the protective layer on the center region. The first etching rate and the second etching rate are different. An isolation material layer is formed within the trench and on the surface of the protective layer, the top surface of the isolation material layer being higher than the top surface of the protective layer, and the material of the isolation material layer being different from the material of the hard mask layer; Planarize the isolation material layer and the protective layer until the hard mask layer is exposed, thereby forming an isolation layer with the isolation material layer; After the planarization process, the hard mask layer is removed.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The hard mask layer includes a buffer layer and an etch barrier layer located on the buffer layer; the hard mask material layer includes a buffer material layer and an etch barrier material layer located on the surface of the buffer material layer; the method of forming the hard mask layer further includes: forming the buffer layer with the buffer material layer and forming the etch barrier layer with the etch barrier material layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The buffer layer is made of silicon oxide; the etching barrier layer is made of silicon nitride.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the photoresist material layer ranges from 1800 Å to 2500 Å.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the photoresist material layer, the method further includes: forming a bottom anti-reflective layer on the surface of the protective material layer, wherein the photoresist material layer is located on the surface of the bottom anti-reflective layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, Before etching the protective material layer and the hard mask material layer, the method further includes: using the photoresist layer as a mask to etch the bottom anti-reflection layer.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The thickness of the bottom anti-reflective layer ranges from 500 Å to 1200 Å.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the protective material layer, the method further includes: determining the thickness of the protective material layer according to the first etching process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that... The first etching rate is greater than the second etching rate.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The etching ratio of the first etching process for the protective layer and the substrate ranges from 1:3 to 1:

8.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the hard mask layer ranges from 500 Å to 1500 Å.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the protective layer ranges from 100 Å to 500 Å.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the hard mask layer includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

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