A package structure and a semiconductor structure

Abstract

The present disclosure provides a packaging structure and a semiconductor structure, including a packaging substrate, a surface of the packaging substrate is provided with a signal pin array; the signal pin array includes a plurality of clock pins for carrying a clock signal and a plurality of command address pins for carrying a command address signal, the plurality of clock pins are arranged along a first direction, and each clock pin is adjacent to one command address pin along a second direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a packaging structure and a semiconductor structure. BACKGROUND

[0002] One important purpose of microelectronic device (e.g., chip) packaging is to connect the device to a higher level package of an electronic system. One aspect of packaging is to convert signals from the relatively small features (e.g., bond pads or re-routed bond pads) of a die to the larger and more widely spaced connection sites of the next higher level package (e.g., a circuit board). In particular, the various input / output signals involved with a chip are packaged as an array of signal pins, the pattern and pitch of which is generally dictated by industry-wide (i.e., JEDEC) standards. However, the update cycle of various types of chips is becoming smaller and smaller, and thus there is a need to provide a packaging structure that meets the requirements of a new generation of memory chips. SUMMARY

[0003] The present disclosure provides a packaging structure and a semiconductor structure.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, the present disclosure provides a packaging structure, comprising a packaging substrate, a surface of the packaging substrate is provided with a signal pin array; the signal pin array comprises a plurality of clock pins for carrying clock signals and a plurality of command address pins for carrying command address signals, the plurality of clock pins are arranged along a first direction, and each clock pin is adjacent to one command address pin along a second direction; wherein the first direction is a column extension direction of the signal pin array, and the second direction is a row extension direction of the signal pin array.

[0006] In some embodiments, the signal pin array further comprises a plurality of chip select pins for carrying chip select signals; the plurality of chip select pins are arranged along the first direction; each chip select pin is adjacent to one command address pin along the second direction.

[0007] In some embodiments, the signal pin array further comprises a plurality of chip select pins for carrying chip select signals and a plurality of data pins for carrying data signals; one chip select pin is further adjacent to one data pin along the first direction; one clock pin is further adjacent to another command address pin along the first direction.

[0008] In some embodiments, the signal pin array further comprises a plurality of chip select pins for carrying chip select signals and a plurality of data pins for carrying data signals; the signal pin array is sequentially divided into a first edge row, a data transmission region, a control transmission region and a second edge row along a first direction; the plurality of data pins are located in the data transmission region, and any two data pins are not linearly adjacent; the plurality of command address pins, the plurality of clock pins and the plurality of chip select pins are located in the control transmission region; and, in the first direction, at most 3 of the command address pins are allowed to be arranged continuously; in the second direction, at most 2 of the command address signals are allowed to be arranged continuously.

[0009] In some embodiments, the signal pin array is sequentially divided into a first longitudinal region, a center column and a second longitudinal region along a second direction, the number of signal pins in the first longitudinal region and the number of signal pins in the second longitudinal region are the same, and the pins in the center column are removed; the plurality of data pins are located in the non-edge columns of the first longitudinal region and the non-edge columns of the second longitudinal region, and the data pins in the first longitudinal region are symmetric about the center column with the data pins in the second longitudinal region; the plurality of command address pins are located in the part of the first longitudinal region close to the center column and the part of the second longitudinal region close to the center column, and the command address pins in the first longitudinal region are symmetric about the center column with the command address pins in the second longitudinal region.

[0010] In some embodiments, the plurality of chip select pins are located in the first longitudinal region, and the chip select pins are located on the side of the adjacent command address pins away from the center column; the plurality of clock signal pins are located in the second longitudinal region and adjacent to the center column.

[0011] In some embodiments, the data transmission region is divided into a first transmission region and a second transmission region along the first direction, the total number of pins in the first transmission region is greater than the total number of pins in the first transmission region, and the number of data pins in the first transmission region is the same as the number of data pins in the second transmission region; the data pins in the first transmission region are used to transmit high-bit data signals, and the data pins in the second transmission region are used to transmit low-bit data signals; or, the data pins in the first transmission region are used to transmit low-bit data signals, and the data pins in the second transmission region are used to transmit high-bit data signals.

[0012] In some embodiments, the signal pin array further comprises two pairs of data strobe pins carrying data strobe signals, the first pair of data strobe pins is located in the first transmission region, the second pair of data strobe pins is located in the second transmission region, and the data strobe pins are adjacent to the center column; the two pins of each pair of data strobe pins are adjacent in the first direction, and the first pair of data strobe pins and the second pair of data strobe pins are not adjacent in the first direction; wherein the first pin of each pair of data strobe pins is linearly adjacent to at least one data pin, and the second pin of each pair of data strobe pins is not linearly adjacent to any data pin.

[0013] In some embodiments, the data transmission region is further distributed with two pairs of first auxiliary control pins, the first pair of first auxiliary control pins is symmetric about the center column with the first pair of data strobe pins, and the second pair of first auxiliary control pins is symmetric about the center column with the second pair of data strobe pins; the other pins in the data transmission region are power pins or ground pins.

[0014] In some embodiments, one of the pins of each pair of first auxiliary control pins is used to carry a mask control signal or a terminal data strobe signal, and the other pin of each pair of first auxiliary control pins is used to transmit a ground signal or as a reserved signal pin.

[0015] In some embodiments, the control transmission region is further distributed with a plurality of second auxiliary control pins, a plurality of third auxiliary control pins, a plurality of fourth auxiliary control pins, a fifth auxiliary control pin and a sixth auxiliary control pin, the plurality of second auxiliary control pins and the plurality of chip select pins are symmetric about the center column; the plurality of third auxiliary control pins and the plurality of fourth auxiliary control pins are symmetric about the center column, one third auxiliary control pin, one chip select pin and one command address pin are arranged continuously in the second direction, one command address pin, one second auxiliary control pin and one fourth auxiliary control pin are arranged continuously in the second direction; the fifth auxiliary control pin and the sixth auxiliary control pin are symmetric about the center column, the fifth auxiliary control pin is in the same column as the third auxiliary control pin, and the fifth auxiliary control pin is not adjacent to the third auxiliary control pin; the sixth auxiliary control pin is in the same column as the fourth auxiliary control pin, and the sixth auxiliary control pin is not adjacent to the fourth auxiliary control pin; the other pins in the control transmission region are power pins or ground pins.

[0016] In some embodiments, the first edge row is distributed with local data pins carrying local data signals and local data strobe pins carrying local data strobe signals, and the local data pins and the local data strobe pins are symmetric about the center column, the local data pins are adjacent to one data pin in the first direction, and the local data strobe pins are adjacent to one data pin in the first direction; the first edge row is further distributed with a seventh auxiliary control pin, the seventh auxiliary control pin is adjacent to the center column, and the seventh auxiliary control pin is adjacent to a data pin in the first direction; the other pins in the first edge row and the second edge row are all power pins or ground pins.

[0017] In some embodiments, at least one second auxiliary control pin is used to carry a test mode enable signal, and at least one second auxiliary control pin is used as a reserved signal pin; at least one third auxiliary control pin is used to carry a mirror mode enable signal, and at least one third auxiliary control pin is used to carry a check error signal; at least one fourth auxiliary control pin is used to carry a first protocol signal, and at least one fourth auxiliary control pin is used to carry a second protocol signal; a fifth auxiliary control pin is used to carry a termination signal, and a sixth auxiliary control pin is used to carry a reset signal; a seventh auxiliary control pin is used to carry a calibration pin of an impedance calibration signal.

[0018] In some embodiments, the signal pin array has 14 rows, the first longitudinal area has 4 columns, and the second longitudinal area has 4 columns; the package form of each pin of the signal pin array is a ball grid, in the first direction, the distance between the center points of two adjacent ball grids is a first value, in the first direction, the distance between the center points of two adjacent ball grids is a second value, and the first value is less than the second value.

[0019] In a second aspect, the embodiments of the present disclosure provide a semiconductor structure, including the package structure of the first aspect and a chip; wherein the data bit width of the chip is 4 bits, 8 bits or 16 bits.

[0020] The embodiments of the present disclosure provide a package structure and a semiconductor structure, which can be compatible with chips of different specifications, have strong adaptability, and have a small overall area. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A schematic diagram of a package structure provided by the embodiments of the present disclosure is shown;

[0022] Figure 2 A schematic diagram of another package structure provided by the embodiments of the present disclosure is shown;

[0023] Figure 3 A schematic diagram of a signal pin array provided by the embodiments of the present disclosure is shown; Figure 1 ;

[0024] Figure 4 A schematic diagram of a signal pin array provided by the embodiments of the present disclosure is shown; Figure 2 ;

[0025] Figure 5 A schematic diagram of a signal pin array provided by the embodiments of the present disclosure is shown; Figure 3 ;

[0026] Figure 6 A schematic diagram of a signal pin array provided by the embodiments of the present disclosure is shown; Figure 4 ;

[0027] Figure 7 A schematic diagram of a signal pin array is shown;

[0028] Figure 8 Another schematic diagram of a signal pin array provided by an embodiment of the present disclosure is provided.

[0029] Figure 9 A structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms “first”, “second”, “third” involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that “first”, “second”, “third” can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described.

[0031] Static Random-Access Memory (SRAM);

[0032] Dynamic Random Access Memory (DRAM);

[0033] Synchronous Dynamic Random Access Memory (SDRAM);

[0034] Double Data Rate SDRAM (DDR);

[0035] Fifth-generation DDR (DDR5);

[0036] Sixth-generation DDR (DDR6);

[0037] Two-wire bidirectional serial bus protocol (I3C);

[0038] printed circuit board (PCB).

[0039] Before introducing the embodiments of the present disclosure, the following three directions for describing the three-dimensional structure that the plane may use are defined. Taking the Cartesian coordinate system as an example, the three directions can include the X-axis, Y-axis and Z-axis directions (not involved in the embodiments of the present disclosure). The packaging structure can include a top surface at the front face and a bottom surface at the back face opposite to the front face; in the case of ignoring the flatness of the top surface and the bottom surface, the direction intersecting (for example, perpendicular to) the top surface and the bottom surface of the packaging structure is defined as the third direction. In the direction of the top surface and the bottom surface of the packaging structure (i.e. the plane where the packaging structure is located), two directions intersecting with each other are defined, for example, the column extension direction of the signal pin array can be defined as the first direction, and the row extension direction of the signal pin array can be defined as the second direction, and the plane direction of the packaging structure can be determined based on the first direction and the second direction. In the embodiments of the present disclosure, the first direction and the second direction can be perpendicular to each other, and in other embodiments, the first direction and the second direction can also be not perpendicular.

[0040] In addition, the term "linearly adjacent" used in this paper in connection with the signal pin array means and includes the pins directly above, directly below, directly left and directly right of a given pin when the signal pin array is parallel to the drawing plane; the term "diagonally arranged" used in this paper in connection with the signal pin array means and includes the pins right above, right below, left above and left below of a given pin when the signal pin array is parallel to the drawing plane; the term "surrounding pins" used in this paper in connection with the signal pin array means and includes the pins directly above, directly below, directly left, directly right, right above, right below, left above and left below of a given pin when the signal pin array is parallel to the drawing plane. The term "pin A is adjacent to pin B in the first direction" used in this paper in connection with the signal pin array only includes that pin A and pin B are adjacent when the signal pin array is parallel to the drawing plane, and pin A is directly above or directly below pin B. The term "pin A is adjacent to pin B in the second direction" used in this paper in connection with the signal pin array only includes that pin A and pin B are adjacent when the signal pin array is parallel to the drawing plane, and pin A is directly left or directly right of pin B.

[0041] In particular, the illustrations presented in the present disclosure are not meant to be actual views of any particular microelectronic device package, signal pin array, or component thereof, but are merely idealized representations used to describe the illustrative embodiments. Thus the drawings are not necessarily to scale.

[0042] Since the 4-bit data width (X4), 8-bit data width (X8), 16-bit data width (X16) DDR6 chips are involved in the subsequent description of the embodiments of the present disclosure, Table 1 is provided to illustrate the relevant signals and the number of signals involved in the packaging of the above-mentioned chips.

[0043] Table 1

[0044]

[0045]

[0046]

[0047] Specifically, for the X8 chip, the terminal data strobe signals tdqs_c and tdqs_t are required. The X4 and X16 chips do not require these signals, but they do require the mask inversion control signals dmu_n and dml_n. Specifically, for the same design specification, the terminal data strobe signals can share a single pin with the mask inversion control signals; that is, tdqs_c and dmu_n share a single pin, and tdqs_t and dml_n share a single pin.

[0048] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0049] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of a packaging structure 10 provided in an embodiment of the present disclosure. For example... Figure 1 As shown, the packaging structure 10 includes a packaging substrate 11, and a signal pin array 20 (or ball pin array) is disposed on the surface of the packaging substrate 11.

[0050] It should be noted that the packaging structure 10 provided in this embodiment is applicable to at least DDR5 or DDR6, and can simultaneously support DDR5 or DDR6 chips with data bit widths of 4 bits, 8 bits, and 16 bits. Specifically, the DDR chip includes a device substrate, which includes semiconductor material and bonding pads coupled to the active surface of the device substrate. The packaging substrate is fixed to the device substrate, and the aforementioned packaging substrate 11 is configured to route signals to / from the bonding pads. Simultaneously, the signal pin array 20 is supported on and electrically connected to the packaging substrate 11. In particular, the distribution position of the signal pin array 20 on the packaging substrate 11 is merely illustrative and does not constitute a limitation. In reality, the surface of the packaging substrate 11 is not necessarily a perfectly regular rectangle, and the signal pin array 20 can be distributed in any area of ​​the surface of the packaging substrate 11.

[0051] In the following description, the first direction is the column extension direction of the signal pin array 20, and the second direction is the row extension direction of the signal pin array 20.

[0052] like Figure 1 As shown, the signal pin array 20 includes multiple clock pins (201, 202) for carrying clock signals and multiple command address pins for carrying command address signals. Figure 1Only part, i.e. 211, 212), a plurality of clock pins (201, 202) are arranged along a first direction, and each clock pin is adjacent to a command address pin along a second direction, for example, clock pin 201 is adjacent to command address pin 211 along the second direction, and clock pin 202 is adjacent to command address pin 212 along the second direction.

[0053] That is, a plurality of clock pins are located in the same column and adjacent to each other, and one clock pin and one command address pin are located in the same row and adjacent to each other.

[0054] It should be noted that, Figure 1 Two clock pins are shown, but there can be more or less in actual scenarios. For example, Figure 1 Clock pin 201 is specifically used to transmit clock signal ck_t in Table 1, and clock pin 202 is specifically used to transmit clock signal ck_c in Table 1, and clock signal ck_t and clock signal ck_c are a pair of differential signals.

[0055] In this way, in the embodiments of the present disclosure, the clock pin is allowed to be adjacent to the command address pin along the second direction, which can reduce the size of the signal pin array 20 and save the substrate area. At the same time, since the clock pin is adjacent to the command address pin along the second direction, the clock and address time delay can be better matched, the overall transmission path is closer, the signal integrity is improved, and the overall product competitiveness is improved.

[0056] In some embodiments, as Figure 2 shown, the signal pin array 20 further includes a plurality of chip select pins (231, 232) for carrying chip select signals, and the plurality of chip select pins (231, 232) are arranged along the first direction; each chip select pin is adjacent to a command address pin along the second direction, for example, chip select pin 231 is adjacent to command address pin 213 along the second direction.

[0057] That is, a plurality of chip select pins are located in the same column and adjacent to each other, and one chip select pin and one command address pin are located in the same row and adjacent to each other.

[0058] It should be noted that, Figure 2 Two chip select pins are shown, but there can be more or less in actual scenarios. For example, Figure 2 Chip select pin 231 is specifically used to transmit chip select signal cs_n[0] in Table 1, and chip select pin 232 is specifically used to transmit chip select signal cs_n[1] in Table 1, and at most only one of chip select signal cs_n[0] and chip select signal cs_n[1] is valid.

[0059] Thus, in this embodiment of the disclosure, allowing the chip select pin and the command address pin to be adjacent along the second direction can compress the number of rows occupied by the address signals in the signal pin array 20, further saving space, and at the same time, can better match the timing between the clock and address signals.

[0060] In some embodiments, such as Figure 2 As shown, the signal pin array 20 also includes multiple data pins that carry data signals. Figure 2 Only one is shown, namely 241); one of the chip select pins 232 is also adjacent to one data pin 241 along the first direction; one of the clock pins 202 is also adjacent to another command address pin 215 along the first direction.

[0061] Thus, in this embodiment of the disclosure, the chip select pin and the command address pin are allowed to be adjacent along the second direction, and the chip select pin and the data pin are allowed to be adjacent along the first direction; at the same time, the clock pin and the command address pin are allowed to be adjacent in both the first and second directions, so that the signal distribution is concentrated under the premise that the signal quality meets the requirements.

[0062] For ease of explanation, please refer to Figure 3 This is a schematic diagram of the signal pin array 20 for the specific application scenario of DDR6 chips. Figure 3 In the signal pin array 20, there are 14 rows (rows numbered a to p) × 11 columns (columns numbered 1 to 11), including 16 data pins DQ, 14 command address pins CA, 2 clock pins (CK_T and CK_C), and 2 chip select pins (CS_N[0] and CS_N[1]). It should be understood that Figure 3 This is only one specific embodiment of the present disclosure. Without departing from the following description, the size of the signal pin array 20, the number of different types of signals, and the detailed arrangement of each signal can be adaptively adjusted.

[0063] In some embodiments, such as Figure 3 As shown, the signal pin array 20 is divided into a first edge row, a data transmission area, a control transmission area and a second edge row along the first direction; multiple data pins DQ are located in the data transmission area, and any two data pins DQ are not adjacent in a straight line; multiple command address pins CA, multiple clock pins (CK_T and CK_C) and multiple chip select pins (CS_N[0] and CS_N[1]) are located in the control transmission area.

[0064] It should be noted that for one data pin DQ, its upper, lower, left and right are not allowed to distribute another data pin DQ; but its upper left, lower left, upper right and lower right are allowed to distribute another data pin DQ. That is, two data pins DQ can be arranged along the diagonal, but not linearly adjacent, in order to improve the signal distortion problem caused by magnetic field superposition.

[0065] It should be noted that, Figure 3 The signal pin array 20 includes a total of 16 data pins DQ, which can support 4-bit, 8-bit and 16-bit data bit width chips. In simple terms, if the packaging structure 10 is applied to a 4-bit data bit width (X4) chip, only 4 data pins are enabled, and the remaining 12 data pins are not connected; if the packaging structure 10 is applied to an 8-bit data bit width (X8) chip, only 8 data pins are enabled, and the remaining 8 data pins are not connected; if the packaging structure 10 is applied to a 16-bit data bit width (X16) chip, all data pins are enabled.

[0066] In some embodiments, as shown in Figure 3 The signal pin array 20 is sequentially divided into a first longitudinal region, a center column and a second longitudinal region along the second direction, and the number of signal pins in the first longitudinal region and the number of signal pins in the second longitudinal region are the same.

[0067] It should be noted that the pins in the center column are removed. That is, after the signal pin array 20 is completed, the pins in the center column need to be removed to facilitate PCB wiring. Figure 3 The center column in the above contains 3 columns, but this does not constitute a relevant limitation, and the number of columns contained in the center column can be more or less. In particular, in the above Figure 3 In the above, the length of each column (i.e. the 5th / 6th / 7th column) in the center column along the second direction is short, but this is only to save page space, and in fact the length of each column of the signal pin array 20 along the second direction is basically the same.

[0068] Please refer to Figure 3 , a plurality of data pins DQ are located in the non-edge columns of the first longitudinal region and the non-edge columns in the second longitudinal region, and the data pins DQ in the first longitudinal region and the data pins DQ in the second longitudinal region are symmetric about the center column. In this way, the data pins DQ in the first longitudinal region and the second longitudinal region are mirror images of each other, so that the via holes can be shared when the PCB is designed for positive and negative pasting; in addition, the 1st column and the last column (i.e. the edge column) do not set data pins DQ, thereby shortening the length of the data pins DQ along the second direction.

[0069] Exemplarily, as shown in Figure 3As shown, even-numbered data pins DQ are distributed in columns 2, 3, 4, and odd-numbered data pins DQ are distributed in columns 8, 9, 10. Alternatively, even-numbered data pins DQ are distributed in columns 8, 9, 10, and odd-numbered data pins DQ are distributed in columns 2, 3, 4.

[0070] As shown in FIG. 1, the data pins DQ are distributed in columns 2, 3, 4, and the command address pins CA are distributed in columns 9, 10. Figure 3 As shown in FIG. 1, the data pins DQ are distributed in columns 2, 3, 4, and the command address pins CA are distributed in columns 9, 10.

[0071] As shown in FIG. 1, the data pins DQ are distributed in columns 2, 3, 4, and the command address pins CA are distributed in columns 9, 10. Figure 3 As shown, even-numbered command address pins CA are distributed in columns 3, 4, and odd-numbered command address pins CA are distributed in columns 9, 10. Alternatively, even-numbered command address pins CA are distributed in columns 9, 10, and odd-numbered command address pins CA are distributed in columns 3, 4.

[0072] It should be noted that, in the first direction, at most 3 command address pins CA are allowed to be arranged in succession; in the second direction, at most 2 command address pins CA are allowed to be arranged in succession.

[0073] In this way, the data pins DQ are not arranged in a straight line in either the first direction or the second direction, avoiding the strength and degree of overlap in the magnetic field generated by the data signals carried thereby, so that the signals have higher quality and fidelity. In addition, the command address pins CA are more compactly distributed, thereby reducing the area occupied by the overall signal pin array.

[0074] In some embodiments, the chip select pins (CS_N[0] and CS_N[1]) are located in the first longitudinal region, and the chip select pins are located on the side of the adjacent command address pins CA away from the center column; the clock signal pins are located in the second longitudinal region and adjacent to the center column.

[0075] In this way, the clock signal pins (CK_T and CK_C) are all adjacent to the center column, which can be located in column 4 or column 8, and the rows of the clock signal pins are adjacent, facilitating PCB or substrate wiring.

[0076] In some embodiments, as shown in FIG. 1, the chip select pins (CS_N[0] and CS_N[1]) are located in the first longitudinal region, and the chip select pins are located on the side of the adjacent command address pins CA away from the center column; the clock signal pins are located in the second longitudinal region and adjacent to the center column. Figure 3The data transmission area is divided into a first transmission area and a second transmission area along a first direction. The total number of pins in the first transmission area is greater than the total number of pins in the second transmission area, and the number of data pins (DQ) in the first transmission area is the same as the number of data pins (DQ) in the second transmission area.

[0077] In the first possibility, the data pins DQ in the first transmission area are used to transmit the high-order data signal (i.e., dqu[7:0] in Table 1), and the data pins DQ in the second transmission area are used to transmit the low-order data signal (i.e., dql[7:0] in Table 1). In this case, for DDR6 with a 4-bit data width, only 4 data pins in the second transmission area are enabled; for DDR6 with an 8-bit data width, only 8 data pins are enabled; and for DDR6 with a 16-bit data width, all data pins are enabled.

[0078] In the second possibility, the data pins DQ in the first transmission area are used to transmit the low-order data signals (i.e., dql[7:0] in Table 1), and the data pins DQ in the second transmission area are used to transmit the high-order data signals (i.e., dqu[7:0] in Table 1). In this case, for DDR6 with a 4-bit data width, only the four data pins in the first transmission area are enabled; for DDR6 with an 8-bit data width, only eight of the data pins are enabled; and for DDR6 with a 16-bit data width, all data pins are enabled.

[0079] Thus, in this embodiment of the disclosure, the transmission areas of high-order data signals and low-order data signals are independent of each other, resulting in a more reasonable layout.

[0080] In some embodiments, such as Figure 3 As shown, the signal pin array 20 also includes two pairs of data strobe pins carrying data strobe signals; the first pair of data strobe pins is labeled DQS0_T and DQS0_C, which transmit a pair of differential signals; the second pair of data strobe pins is labeled DQS1_T and DQS1_C, which also transmit a pair of differential signals. That is, one pair of data strobe pins is used to transmit dqsl_t and dqsl_c in Table 1, and the other pair of data strobe pins is used to transmit dqsu_t and dqsu_c in Table 1.

[0081] The first pair of data strobe pins (DQS0_T, DQS0_C) are located in the first transmission region, the second pair of data strobe pins (DQS1_T, DQS1_C) are located in the second transmission region, and all the data strobe pins (DQS0_T, DQS0_C, DQS1_T, DQS1_C) are adjacent to the center column; the two pins of each pair of data strobe pins are adjacent in the first direction, that is, the data strobe pin DQS0_T and the data strobe pin DQS0_C are adjacent in the first direction, and the data strobe pin DQS1_T and the data strobe pin DQS1_C are adjacent in the first direction. The first pair of data strobe pins and the second pair of data strobe pins are not adjacent in the first direction; here, not adjacent means that there is at least one pin between the "first pair of data strobe pins" and the "second pair of data strobe pins". For example, in Figure 3 , the data strobe pin DQS0_C and the data strobe pin DQS1_T are separated by one power pin VDDQ.

[0082] In this way, each pair of data strobe pins can be located in the fourth column or the eighth column, and the two pins of each pair of data strobe pins are located in adjacent rows, thereby facilitating PCB or substrate wiring.

[0083] It should be noted that the first pin of each pair of data strobe pins is linearly adjacent to at least one data pin DQ, that is, the data strobe pin DQS0_T is distributed with one data pin DQ above and to the left, and the data strobe pin DQS1_C is distributed with one data pin DQ to the left. At the same time, the second pin of each pair of data strobe pins is not linearly adjacent to any data pin DQ; here, "not linearly adjacent" means that the upper, lower, left, and right of the "second pin of each pair of data strobe pins" are not allowed to be distributed with data pins DQ.

[0084] It should also be noted that in Figure 4 , all the data strobe pins are in the same column. In other embodiments, please refer to Figure 3 , the first pair of data strobe pins (DQS0_T, DQS0_C) is located in the first longitudinal region close to one column of the center column, and the second pair of data strobe pins (DQS0_T, DQS0_C) is located in the second longitudinal region close to one column of the center column. In still other embodiments, the first pair of data strobe pins (DQS0_T, DQS0_C) is located in the second longitudinal region close to one column of the center column, and the second pair of data strobe pins (DQS0_T, DQS0_C) is located in the first longitudinal region close to one column of the center column.

[0085] In some embodiments, please refer to Figure 4 or Figure 3The data transmission area also has two pairs of first auxiliary control pins (301-304). The first pair of first auxiliary control pins (301, 302) and the first pair of data strobe pins (DQS0_T, DQS0_C) are symmetrical about the center column. The second pair of first auxiliary control pins (301, 302) and the second pair of data strobe pins (DQS1_T, DQS1_C) are symmetrical about the center column. The other pins in the data transmission area are power supply pins or ground pins VSS.

[0086] It should be noted that, depending on the function and / or voltage value, the power supply pins are labeled VDD, VDDQ, and VPP. In particular, each data pin DQ is surrounded by at least one ground pin and one power supply pin. Here, "surrounding the data pin DQ" includes the pins directly above, below, to the left, to the right, to the upper left, to the lower left, to the upper right, and to the lower right of the data pin DQ. This not only provides isolation but also facilitates the generation of data signals.

[0087] In some embodiments, such as Figure 4 or Figure 3 As shown, the control transmission area also has multiple second auxiliary control pins (305, 306), multiple third auxiliary control pins (307, 308), multiple fourth auxiliary control pins (309, 310), a fifth auxiliary control pin 311, and a sixth auxiliary control pin 312.

[0088] First, multiple secondary auxiliary control pins (305, 306) and multiple chip select pins (CS_N[0] and CS_N[1]) are symmetrical about the center column.

[0089] Secondly, multiple third auxiliary control pins (307, 308) and multiple fourth auxiliary control pins (309, 310) are symmetrical about the center column. A third auxiliary control pin, a chip select pin, and a command address pin CA are arranged continuously along the second direction, as are a command address pin CA, a second auxiliary control pin, and a fourth auxiliary control pin; for example... Figure 5 As shown, the third auxiliary control pin 307, the chip select pin CS_N[0] and one command address pin CA are arranged continuously along the second direction; the third auxiliary control pin 308, the chip select pin CS_N[1] and one command address pin CA are arranged continuously along the second direction; at the same time, one command address pin CA, the second auxiliary control pin 305 and the fourth auxiliary control pin 309 are arranged continuously along the second direction; and one command address pin CA, the second auxiliary control pin 306 and the fourth auxiliary control pin 310 are arranged continuously along the second direction.

[0090] Finally, the fifth auxiliary control pin 311 and the sixth auxiliary control pin 312 are symmetrical about the center column, the fifth auxiliary control pin 311 is in the same column as the third auxiliary control pin (307 and 308), and the fifth auxiliary control pin 311 is not adjacent to the third auxiliary control pin (307 and 308); the sixth auxiliary control pin 312 is in the same column as the fourth auxiliary control pin (309 and 310), and the sixth auxiliary control pin 312 is not adjacent to the fourth auxiliary control pin (309 and 310);

[0091] The other pins in the control transmission region are power pins or ground pins, that is, the other pins in the control transmission region are either power pins or ground pins.

[0092] In some embodiments, referring to Figure 5 , the first edge row is also distributed with a local data pin LBDQ carrying a local data signal lbdq and a local data strobe pin LBDQS carrying a local data strobe signal lbdqs, and the local data pin LBDQ and the local data strobe pin LBDQS are symmetrical about the center column, the local data pin LBDQ is adjacent to one data pin DQ in the first direction, and the local data strobe pin LBDQS is adjacent to one data pin DQ in the first direction;

[0093] The first edge row is also distributed with a seventh auxiliary control pin 313, the seventh auxiliary control pin 313 is adjacent to the center column, and the seventh auxiliary control pin 313 is adjacent to a data pin DQ in the first direction; the other pins in the first edge row and the second edge row are power pins or ground pins, in particular, the power pin VPP is overlapped with another power pin VPP after rotating 180 degrees about the center of the signal array.

[0094] It should be noted that, in Figure 5 , the seventh auxiliary control pin 313 is located on the same side of the center column as the local data strobe pin LBDQS; in other embodiments, the seventh auxiliary control pin 313 can also be located on the same side of the center column as the local data pin LBDQ, at which time the position of the power pin VPP needs to be adjusted accordingly.

[0095] For the above-mentioned 13 auxiliary control pins, the relatively flexible ones are used to transmit the following signals: mask control signals (dml, dmu) or terminal data strobe signals (tdqs_t, tdqs_c), test mode enable signal ten (for controlling the chip to enter / not enter the test mode), reserved signal rfu (which can be customized by each manufacturer), mirror mode enable signal mir (for controlling the chip to enter / not enter the mirror mode), check error signal (for prompting the error checked in the cyclic redundancy check operation) alert_n, first protocol signal msda (I3C related signal), second protocol signal mscl (I3C related signal), termination signal ca_odt, reset signal reset, impedance calibration signal zq.

[0096] It should be noted that the above signals can be transmitted by any auxiliary control pin relatively flexibly, which mainly depends on the structure of the internal circuit and the wiring demand, and the following only provides an illustration and does not constitute a specific limitation.

[0097] In this way, the signal pin array 20 can support the transmission of all the signals in Table 1, thereby being compatible with X4, X8 and X16 chips.

[0098] In a specific embodiment, referring to Figure 6 one pin DM of each pair of first auxiliary control pins is used to carry mask control signals (dml, dmu) or terminal data strobe signals (tdqs_t, tdqs_c), and the other pin (VSS, RFU) of each pair of first auxiliary control pins is used to transmit ground signal vss or as a reserved signal pin; at least one second auxiliary control pin TEN is used to carry a test mode enable signal ten, and at least one second auxiliary control pin RFU is used as a reserved signal pin; at least one third auxiliary control pin MIR is used to carry a mirror mode enable signal mir, and at least one third auxiliary control pin ALERT_n is used to carry a check error signal alert_n; at least one fourth auxiliary control pin MSDA is used to carry a first protocol signal msda, and at least one fourth auxiliary control pin MSCL is used to carry a second protocol signal mscl; a fifth auxiliary control pin CA_ODT is used to carry a termination signal ca_odt, a sixth auxiliary control pin Reset is used to carry a reset signal reset, and a seventh auxiliary control pin ZQ is used to carry an impedance calibration signal zq.

[0099] In this way, some length-insensitive signals can be preferentially transmitted through the auxiliary control signals in the edge row or the edge column, and the layout is reasonable.

[0100] In another embodiment, as Figures 3-6As shown, one pin DM of each pair of first auxiliary control pins is used to carry mask control signals (dml, dmu) or terminal data strobe signals (tdqs_t, tdqs_c), and the other pin (VSS, RFU) of each pair of first auxiliary control pins is used to transmit ground signals or as a reserved signal pin; at least one second auxiliary control pin TEN carries the mirror mode enable signal MIR, and at least one second auxiliary control pin RFU is used as a reserved signal pin; at least one third auxiliary control pin MSDA carries the first protocol signal msda, and at least one third auxiliary control pin MSCL carries the second protocol signal mscl; at least one fourth auxiliary control pin ALERT_n carries the check error signal alert_n, and at least one fourth auxiliary control pin TEN carries the test mode enable signal ten; the fifth auxiliary control pin ZQ carries the impedance calibration signal zq, the sixth auxiliary control pin CA_ODT carries the termination signal ca_odt, and the seventh auxiliary control pin RESET carries the reset signal reset.

[0101] In addition, in this embodiment of the disclosure, the ground pin VSS and the power supply pins (VDD / VDDQ) need to be staggered and evenly distributed. In particular, the ground pin VSS is not adjacent in the first direction, and the power supply pins (VDD / VDDQ) are not adjacent in the first direction.

[0102] In some embodiments, the signal pin array 20 has 14 rows, a first vertical region has 4 columns, and a second vertical region has 4 columns; each pin of the signal pin array 20 is packaged as a ball grid, and in a first direction, the distance between the center points of two adjacent ball grids is a first value, and in the first direction, the distance between the center points of two adjacent ball grids is a second value, wherein the first value is less than the second value.

[0103] like Figure 7 As shown, the center column has 3 columns, so the signal pin array 20 has a size of 14 rows × 11 columns. That is, it has more pins in the first direction and fewer pins in the second direction. Therefore, the distance between the center points of two adjacent ball grids in the first direction can be reduced, thereby reducing the overall size of the signal pin array 20.

[0104] In one specific embodiment, the first value is 750 micrometers and the second value is 800 micrometers, so that the overall signal pin array 20 has a size of 10 mm × 11 mm and provides a total of 14 × 8 = 112 pins.

[0105] See Figure 7 Image (a) shows a schematic diagram of a package structure for a chip with a 4-bit / 8-bit data width. See also... Figure 7(b) shows a schematic diagram of a package structure for a 16-bit data width chip. Because the number of signal pins differs between X4 / X8 and X16 chips, therefore, as... Figure 7 As shown in (a), for the X4 / X8 chip, the chip has a total of 13×6 signal pins, and four corner pins with no signal connection (used only for support), with an overall size of 10 mm × 11 mm; Figure 7 As shown in (b), the X16 chip has a total of 17 × 6 signal pins, with four non-signal pins at its four corners (used only for support), and an overall size of 10 mm × 14 mm. In other words, compared to the X4 / X8 chips, the X16 chip is larger, requiring more substrate area and making it incompatible with Dual-Inline-Memory-Modules (DIMMs) of the same specifications.

[0106] As can be seen from the above, by using the packaging structure 10 provided in this disclosure, X4, X8, and X16 can share a common substrate, and the substrate size can be made close to that of... Figure 7 The size of (a) allows for the cutting of more chip units from a single substrate, reducing costs. It also shortens the design cycle, eliminating the need to design different substrates for chips with different bit widths. Furthermore, testing has shown that compared to… Figure 8 In (a), the signal pin array 20 provided in this disclosure has a longer solder joint life, less plastic strain, and a longer fatigue life.

[0107] In another embodiment of this disclosure, a signal pin array 30 is disposed on the surface of the packaging substrate 11. See also Figure 8 This illustrates a schematic diagram of a signal pin array 30 provided in an embodiment of this disclosure. Figure 8 As shown, the signal pin array 30 includes a plurality of data pins DQ, and the data pins DQ are used to transmit data signals; in the second direction, at most two data pins DQ are allowed to be arranged adjacent to each other.

[0108] It should be noted that, in the first direction, at most one data pin DQ is allowed to be arranged adjacently; and, in two adjacent rows, at most one row has data pin DQ distributed, or in other words, at most one data pin DQ is located around each data pin DQ (top, bottom, left, right, top left, top right, bottom left, bottom right), thereby improving the signal distortion problem while ensuring transmission quality.

[0109] In particular, the signal pin array 30 provided in this disclosure can also support X4, X8, and X16 chips.

[0110] In some embodiments, seeFigure 8 For the first part of the data pins DQ, which are located in the edge row of the signal pin array, and any data pin DQ of the first part is not adjacent to other data pins DQ; for the second part of the data pins DQ, which are located in the non-edge row and non-edge column of the signal pin array 30, every 2 data pins DQ of the second part are adjacent in the second direction; wherein, in the first direction, the data pins DQ of different rows are spaced by one row of pins.

[0111] In some embodiments, referring to Figure 8 , the signal pin array 30 further comprises a plurality of command address pins CA, which are used to transmit command address signals; for the first part of the command address pins CA, which are located in the edge row of the signal pin array 30, and any command address pin CA of the first part is not adjacent to other command address pins CA; for the second part of the command address pins CA, which are located in the non-edge row and non-edge column of the signal pin array 30, and at most 2 command address pins CA of the second part are allowed to be arranged continuously in the second direction, and at most 3 command address pins CA of the second part are allowed to be arranged continuously in the first direction, the first direction refers to the column extension direction of the signal pin array 30.

[0112] In this way, the signal pin array 30 allows the data pins DQ to be located in the edge row, and allows 2 data pins DQ to be arranged continuously adjacent, and allows the command address pins CA to be located in the edge row, which can reduce the area of the signal pin array and reduce the cost of the chip.

[0113] In some embodiments, referring to Figure 8 , the signal pin array 30 has N rows, the first part of the data pins DQ are located in the 1st row, the second part of the data pins DQ are all located in the 2nd to A rows, the second part of the command address pins CA are all located in the B to (N-1) rows, and the first part of the command address pins CA are located in the Nth row; A, B and N are all positive integers, A is less than B, and B is less than N-1.

[0114] In particular, Figure 8 Only N=13, A=7, B=9 are taken as examples.

[0115] In some embodiments, referring to Figure 8 , the data pins DQ located in the 1st to (C-1)th rows are used to transmit high-bit data signals; the data pins DQ located in the (C+1)th to A rows are used to transmit low-bit data signals; wherein, C=(A+1) / 2; or, the data pins DQ located in the 1st to C rows are used to transmit low-bit data signals; the data pins DQ located in the C+1th to A rows are used to transmit high-bit data signals; the pins located in the Cth row are all ground pins or power pins, and the ground pins are used to transmit ground signals and the power pins are used to transmit power signals.

[0116] In some embodiments, referring to Figure 8 , in the second direction, the signal pin array 30 is divided into a first array, a center array and a second array, the first array, the center array and the second array are distributed along the second direction, the number of pins in the first array and the number of pins in the second array are the same, and all pins of the center array are removed;

[0117] Wherein the data pins DQ located in the first array are symmetrical about the center array with the data pins DQ located in the second array, and the command address pins CA located in the first array are symmetrical about the center array with the command address pins CA located in the second array.

[0118] In some embodiments, referring to Figure 8 , the signal pin array 30 further includes 4 data strobe pins (DQS_T, DQS_C), which are used to transmit data strobe signals; in the second direction, each data strobe pin is adjacent to the center array, and part of the data strobe pins are adjacent to the data pins DQ;

[0119] In the first direction, 1 data pin DQ, the 1st data strobe pin, the 2nd data strobe pin, 1 ground pin or power pin, the 3rd data strobe pin, and the 4th data strobe pin are continuously arranged adjacent to each other along the first direction.

[0120] In some embodiments, referring to Figure 8 , the signal pin array 30 further includes 2 first auxiliary control pins DM, which are used to transmit mask flip control signals or transmit terminal data strobe signals; 1 first auxiliary control pin is symmetrical about the center array with 1 data strobe pin.

[0121] In some embodiments, the signal pin array 30 further includes 1 local data strobe pin LBDQS, 1 local data pin LBDQ and a ZQ seventh auxiliary control pin;

[0122] The local data strobe pin LBDQS is located in the edge column, and the local data strobe pin LBDQS is adjacent to 1 data pin DQ along the second direction;

[0123] The local data strobe pin LBDQS is symmetrical about the center array with the local data pin LBDQ;

[0124] The seventh auxiliary control pin ZQ is adjacent to the local data strobe pin LBDQS along the first direction;

[0125] Wherein the local data pin LBDQ is used to transmit a local data signal, the local data strobe pin LBDQS is used to transmit a local data strobe signal, and the seventh auxiliary control pin ZQ is used to transmit an impedance calibration signal zq.

[0126] In some embodiments, referring to Figure 8 , the signal pin array 30 further includes 2 chip select pins (CS_N[0], CS_N[1]) adjacent along the first direction, the chip select pins being configured to transmit chip select signals; a first chip select pin is adjacent to a data pin DQ along the first direction; a second chip select pin is adjacent to a command address pin CA along the second direction and is adjacent to another command address pin CA along the first direction.

[0127] In some embodiments, referring to , the signal pin array 30 further includes 2 clock pins (CK_C, CK_T) adjacent along the first direction, the clock pins being configured to transmit clock signals; a first clock pin is not adjacent to any command address pin CA; a second clock pin is adjacent to a command address pin CA along the second direction and is adjacent to another command address pin CA along the first direction.

[0128] Figure 8 In some embodiments, referring to , the 2 chip select pins are located in the first array and are adjacent to the edge column of the signal pin array 30; the 2 clock pins are located in the second array and are adjacent to the center array; a first chip select pin is located in the same row as a first clock pin, and a second chip select pin is located in the same row as a second clock pin.

[0129] Figure 8 In some embodiments, referring to , the signal pin array 30 further includes 2 third auxiliary control pins (MIR, ALERT_n), and both of the 2 third auxiliary control pins are located in the edge column of the signal pin array 30; a first third auxiliary control pin MIR is adjacent to a first chip select pin along the second direction; a second third auxiliary control pin ALERT_n is adjacent to a second chip select pin along the second direction;

[0130] wherein the first third auxiliary control pin MIR is configured to transmit at least a mirror mode enable signal, and the second third auxiliary control pin ALERT_n is configured to transmit a check error indication signal.

[0131] Figure 9 In some embodiments, referring to , the signal pin array 30 further includes 2 reserved pins RFU, a second auxiliary control pin TEN configured to transmit a test mode enable signal, and 2 fourth auxiliary control pins (MSCL, MSDA) configured to transmit protocol control signals.

[0132] The 2 reserved pins are symmetric to the 2 chip select pins about the center array; the 2nd fourth auxiliary control pin MSCL is symmetric to one of the 3rd auxiliary control pins MIR about the center array, the 2nd auxiliary control pin TEN is symmetric to another of the 3rd auxiliary control pins ALERT_n about the center array, and the 1st fourth auxiliary control pin MSDA, the 2nd fourth auxiliary control pin MSCL and the 2nd auxiliary control pin TEN are arranged continuously along the 1st direction.

[0133] In some embodiments, referring to Figure 9 , the signal pin array 30 further comprises a 5th auxiliary control pin CA_ODT and a 6th auxiliary control pin RESET, the 5th auxiliary control pin CA_ODT and the 6th auxiliary control pin RESET are located in the edge column of the signal pin array 30; the 5th auxiliary control pin CA_ODT and the 6th auxiliary control pin RESET are symmetric about the center array; the straight-line adjacent pins of the 5th auxiliary control pin CA_ODT are all ground pins and / or power pins, and the straight-line adjacent pins of the 6th auxiliary control pin are all ground pins and / or power pins; the 5th auxiliary control pin CA_ODT is in the same row as at least one command address pin CA, and the 6th auxiliary control pin RESET is in the same row as at least one command address pin CA; wherein the 5th auxiliary control pin CA_ODT is used to transmit a termination signal, and the 6th auxiliary control pin RESET is used to transmit a reset signal.

[0134] It should be noted that the signals transmitted by the above auxiliary control pins are only an example and do not constitute a corresponding limitation. That is, for the above-mentioned auxiliary control pins, they are relatively flexible for transmitting the following signals: mask control signals (dml, dmu) or terminal data selection signals (tdqs_t, tdqs_c), test mode enable signal ten (for controlling the chip to enter / not enter the test mode), mirror mode enable signal mir (for controlling the chip to enter / not enter the mirror mode), check error signal (for prompting that an error is detected in the cyclic redundancy check operation) alert_n, first protocol signal msda (I3C related signal), second protocol signal mscl (I3C related signal), termination signal ca_odt, reset signal reset, impedance calibration signal zq. Meanwhile, the positions of the reserved pins can also be exchanged with the positions of the auxiliary control pins.

[0135] In some embodiments, referring to ​ , the signal pin array 30 has 13 rows, the 1st array has 4 columns, and the 2nd array has 4 columns, providing a total of 104 signal pins; A = 7, B = 9.

[0136] In yet another embodiment of the present disclosure, referring to ​ , which shows a schematic diagram of the composition structure of a semiconductor structure 60 provided by an embodiment of the present disclosure. As ​As shown, the semiconductor structure 60 at least includes the aforementioned packaging structure 10 and a chip, and the chip has a data bit width of 4 bits, 8 bits or 16 bits.

[0137] Here, the chip can be placed on the packaging structure 10, and the chip can be electrically connected with the signal pin array on the packaging substrate, so that various signals involved by the chip are output / input through the packaging structure 10.

[0138] In summary, the packaging structure 10 provided by the embodiments of the present disclosure can be compatible with chips of X4, X8 and X16 specifications, so that chips of different bit widths can share the same substrate; moreover, the substrate size is smaller, so that the cost is controlled, and the overall performance is better.

[0139] The above merely provides preferred embodiments of the present disclosure, but is not intended to limit the protection scope of the present disclosure. It should be noted that, in the present disclosure, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive containing, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element. The above sequence number of the embodiments of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method or device embodiments. The above merely provides specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A package structure, characterized by, The package substrate has a surface provided with a signal pin array; The signal pin array includes a plurality of clock pins for carrying clock signals and a plurality of command address pins for carrying command address signals, the plurality of clock pins are arranged adjacent to each other along a first direction, and the plurality of command address pins are arranged adjacent to each other along the first direction, each clock pin is adjacent to one command address pin along a second direction; The first direction is a column extension direction of the signal pin array, and the second direction is a row extension direction of the signal pin array; The signal pin array further includes a plurality of chip select pins for carrying chip select signals and a plurality of data pins for carrying data signals; the plurality of chip select pins are arranged adjacent to each other along the first direction; each chip select pin is adjacent to one command address pin along the second direction; One of the chip select pins is also adjacent to one of the data pins along the first direction; One of the clock pins is also adjacent to another command address pin along the first direction.

2. The package structure of claim 1, wherein The signal pin array is sequentially divided into a first edge row, a data transmission region, a control transmission region, and a second edge row along the first direction; The plurality of data pins are all located in the data transmission region, and any two data pins are not linearly adjacent; The plurality of command address pins, the plurality of clock pins, and the plurality of chip select pins are all located in the control transmission region; and, in the first direction, at most three command address pins are allowed to be arranged continuously; and, in the second direction, at most two command address signals are allowed to be arranged continuously.

3. The package structure of claim 2, wherein, The signal pin array is sequentially divided into a first longitudinal region, a center column, and a second longitudinal region along the second direction, the number of signal pins in the first longitudinal region is the same as the number of signal pins in the second longitudinal region, and the pins in the center column are removed; The plurality of data pins are located in the non-edge columns of the first longitudinal region and the non-edge columns of the second longitudinal region, and the data pins in the first longitudinal region are symmetric about the center column with the data pins in the second longitudinal region; The plurality of command address pins are located in the portions of the first longitudinal region close to the center column and the portions of the second longitudinal region close to the center column, and the command address pins in the first longitudinal region are symmetric about the center column with the command address pins in the second longitudinal region.

4. The package structure of claim 3, wherein The plurality of chip select pins are located in the first longitudinal region, and the chip select pins are located on the side of the adjacent command address pins away from the center column; The plurality of clock signal pins are located in the second longitudinal region and adjacent to the center column.

5. The package structure of claim 3 or 4, wherein, The data transmission region is divided into a first transmission region and a second transmission region along a first direction, the total number of pins in the first transmission region is greater than the total number of pins in the first transmission region, and the number of data pins in the first transmission region is the same as the number of data pins in the second transmission region; The data pins in the first transmission region are used to transmit high-bit data signals, and the data pins in the second transmission region are used to transmit low-bit data signals; or the data pins in the first transmission region are used to transmit low-bit data signals, and the data pins in the second transmission region are used to transmit high-bit data signals.

6. The package structure of claim 5, wherein, The array of signal pins further includes 2 pairs of data strobe pins carrying data strobe signals, the first pair of data strobe pins is located in the first transmission region, and the second pair of data strobe pins is located in the second transmission region, and the data strobe pins are adjacent to the center column; The two pins of each pair of data strobe pins are adjacent along a first direction, and the first pair of data strobe pins and the second pair of data strobe pins are not adjacent along the first direction; Wherein, the first pin of each pair of data strobe pins is linearly adjacent to at least one data pin, and the second pin of each pair of data strobe pins is not linearly adjacent to any data pin.

7. The packaging structure of claim 6, wherein The data transmission region is further distributed with 2 pairs of first auxiliary control pins, the first pair of first auxiliary control pins is symmetric about the center column with the first pair of data strobe pins, and the second pair of first auxiliary control pins is symmetric about the center column with the second pair of data strobe pins; The other pins in the data transmission region are power pins or ground pins.

8. The packaging structure of claim 7, wherein One pin of each pair of first auxiliary control pins is used to carry a mask control signal or a terminal data strobe signal, and the other pin of each pair of first auxiliary control pins is used to transmit a ground signal or as a reserved signal pin.

9. The package structure of any one of claims 3-8, wherein, The control transmission region is further distributed with a plurality of second auxiliary control pins, a plurality of third auxiliary control pins, a plurality of fourth auxiliary control pins, a fifth auxiliary control pin and a sixth auxiliary control pin, The plurality of second auxiliary control pins and the plurality of chip select pins are symmetric about the center column; The plurality of third auxiliary control pins and the plurality of fourth auxiliary control pins are symmetric about the center column, one third auxiliary control pin, one chip select pin and one command address pin are arranged continuously along a second direction, and one command address pin, one second auxiliary control pin and one fourth auxiliary control pin are arranged continuously along the second direction; The fifth auxiliary control pin and the sixth auxiliary control pin are symmetric about the center column, the fifth auxiliary control pin is located in the same column as the third auxiliary control pin, and the fifth auxiliary control pin is not adjacent to the third auxiliary control pin; the sixth auxiliary control pin is located in the same column as the fourth auxiliary control pin, and the sixth auxiliary control pin is not adjacent to the fourth auxiliary control pin; The other pins in the control transmission region are power pins or ground pins.

10. The package structure of claim 9, wherein, the first edge row has local data pins carrying local data signals and local data strobe pins carrying local data strobe signals, and the local data pins and the local strobe data pins are symmetric about the center column, the local data pins being adjacent to one of the data pins in the first direction, and the local data strobe pins being adjacent to one of the data pins in the first direction; the first edge row also has a seventh auxiliary control pin, the seventh auxiliary control pin being adjacent to the center column, and the seventh auxiliary control pin being adjacent to the data pins in the first direction; the other pins in the first edge row and the second edge row are power pins or ground pins.

11. The package structure of claim 10, wherein, at least one of the second auxiliary control pins is used to carry a test mode enable signal, and at least one of the second auxiliary control pins is used as a reserved signal pin; at least one of the third auxiliary control pins carries a mirror mode enable signal, and at least one of the third auxiliary control pins is used to carry a check error signal; at least one of the fourth auxiliary control pins is used to carry a first protocol signal, and at least one of the fourth auxiliary control pins is used to carry a second protocol signal; the fifth auxiliary control pin is used to carry a termination signal, and the sixth auxiliary control pin is used to carry a reset signal; the seventh auxiliary control pin is used to carry a calibration pin of an impedance calibration signal.

12. The package structure of any one of claims 3-11, wherein, the signal pin array has 14 rows, the first longitudinal region has 4 columns, and the second longitudinal region has 4 columns; each pin of the signal pin array is in the form of a ball grid, in the first direction, a distance between center points of two adjacent ball grids is a first value, in the second direction, a distance between center points of two adjacent ball grids is a second value, and the first value is less than the second value.

13. A semiconductor structure, characterized by a chip including the package structure of any one of claims 1-12, and wherein the chip has a data bit width of 4 bits, 8 bits, or 16 bits.

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