Data transmission method, system and device, communication device and storage medium

Abstract

The embodiment of the application provides a data transmission method, system, device, communication equipment and storage medium, the method comprises the following steps: a first bit width adaptation module adjusts the bit width of first data in a first downlink processor based on the user side interface bit width of a first serial transceiver, obtains adjusted first data, and sends the adjusted first data to the first serial transceiver; the adjusted first data is sent to a second serial transceiver through the first serial transceiver; the adjusted first data is sent to a second bit width adaptation module through the second serial transceiver; the adjusted first data is demapped through the second bit width adaptation module, the first data before adjustment is obtained, and the first data before adjustment is sent to a second uplink processor. In the application, the bit width adaptation module adjusts the data bit width based on the interface bit width of the serial transceiver, and solves the problems of large FPGA resource consumption and high power consumption caused by the instantiation of multiple serial transceivers.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip communication, and in particular to a data transmission method, system, device, communication equipment and storage medium. BACKGROUND

[0002] FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) as a highly flexible integrated circuit, is widely used in various digital signal processing and communication systems. However, the bit width of the SerDes (Serializer / Deserializer, Serializer / Deserializer) user side interface inside the FPGA is usually fixed, while the bit width of the data in the internal module of the FPGA may have multiple modes. This difference requires the designer to take measures to ensure that the internal module can be correctly connected with the SerDes to realize efficient data transmission.

[0003] In the existing data transmission method, in order to adapt to the different bit widths of the data in the module, the designer may instantiate multiple SerDes to realize the normal transmission of the data in the internal module of the FPGA through multiple SerDes. For example, the bit width of the data in the internal module is 40 bits, and the bit width of the user side interface of the SerDes is 8 bits. The designer usually instantiates 5 SerDes, so that the data in the internal module is transmitted through the 5 SerDes.

[0004] However, the use of multiple SerDes in the existing data transmission method will excessively consume the internal resources of the FPGA. At the same time, the use of multiple SerDes will also cause the power consumption of the FPGA to increase significantly, which is not conducive to the energy efficiency ratio of the overall system. Therefore, the existing data transmission method has the problems of large FPGA resource consumption and high power consumption. SUMMARY

[0005] Therefore, the present application aims to provide a data transmission method, system, device, communication equipment and storage medium to solve the problems of large FPGA resource consumption and high power consumption caused by instantiating multiple SerDes in the FPGA.

[0006] According to a first aspect of the present application, a data transmission method is provided, which is applied to a data transmission system including a first programmable logic device and a second programmable logic device, wherein the first programmable logic device includes a first bit width adaptation module, a first downlink processor and a first serial transceiver, the first bit width adaptation module is communicatively connected with the first downlink processor and the first serial transceiver respectively, the second programmable logic device includes a second bit width adaptation module, a second uplink processor and a second serial transceiver, the second bit width adaptation module is communicatively connected with the second uplink processor and the second serial transceiver respectively, and the method includes:

[0007] The first bit width adaptation module adjusts a bit width of first data in the first downlink processor based on a user side interface bit width of the first serial transceiver, to obtain adjusted first data, wherein the user side interface is an interface for connecting the serial transceiver with other logic modules in the programmable logic device, and the bit width of the adjusted first data is the same as the user side interface bit width of the first serial transceiver;

[0008] The first bit width adaptation module sends the adjusted first data to the first serial transceiver;

[0009] The first serial transceiver sends the adjusted first data to the second serial transceiver;

[0010] The second serial transceiver sends the adjusted first data to the second bit width adaptation module;

[0011] In a case where the second bit width adaptation module receives the adjusted first data, the second bit width adaptation module demaps the adjusted first data to obtain first data before adjustment;

[0012] The second bit width adaptation module sends the first data before adjustment to the second uplink processor.

[0013] Optionally, before the step of adjusting the bit width of the first data in the first downlink processor based on the user side interface bit width of the first serial transceiver to obtain the adjusted first data, the method includes:

[0014] Obtaining a maximum interface bit width of the first downlink processor;

[0015] Setting the user side interface bit width of the first serial transceiver according to the maximum interface bit width of the first downlink processor.

[0016] Optionally, the first bit width adaptation module adjusts a bit width of the first data in the first downlink processor based on a user side interface bit width of the first serial transceiver, and the first data before adjustment comprises:

[0017] The first bit width adaptation module acquires the bit width of the first data in the first downlink processor and the user side interface bit width of the first serial transceiver;

[0018] According to the bit width of the first data in the first downlink processor and the user side interface bit width of the first serial transceiver, a numerical relationship between the bit width of the first data in the first downlink processor and the user side interface bit width of the first serial transceiver is determined.

[0019] If the numerical relationship is that the bit width of the first data in the first downlink processor is less than the user side interface bit width of the first serial transceiver, each bit of the first data in the first downlink processor is duplicated to obtain adjusted first data.

[0020] Optionally, after the step of determining the numerical relationship between the bit width of the first data in the first downlink processor and the user side interface bit width of the first serial transceiver, the method comprises:

[0021] If the numerical relationship is that the bit width of the first data in the first downlink processor is equal to the user side interface bit width of the first serial transceiver, the first data in the first downlink processor is sent to the first serial transceiver.

[0022] Optionally, the de-mapping of the adjusted first data to obtain the first data before adjustment comprises:

[0023] The adjusted first data is subjected to data division to obtain a plurality of groups of preset numerical bits;

[0024] For any one group of preset numerical bits, the numerical value of the preset numerical bits is acquired;

[0025] The numerical value of the preset numerical bits is weighted to obtain a weighted bit value;

[0026] The weighted bit value is compared with a preset threshold value;

[0027] If the weighted bit value is greater than or equal to the preset threshold value, the preset numerical bits are de-mapped into a first numerical value;

[0028] If the weighted bit value is less than the preset threshold value, the preset numerical bits are de-mapped into a second numerical value.

[0029] Optionally, the first programmable logic device comprises a first uplink processor, the first uplink processor being communicatively connected with the first bit width adaptation module, the second programmable logic device comprises a second downlink processor, the second downlink processor being communicatively connected with the second bit width adaptation module, after the step of transmitting the first data before adjustment to the second uplink processor through the second bit width adaptation module, the method comprises:

[0030] The second bit width adaptation module adjusts a bit width of the second data in the second downlink processor based on a user side interface bit width of the second serial transceiver, to obtain second data after adjustment, wherein the bit width of the second data after adjustment is the same as the user side interface bit width of the second serial transceiver;

[0031] The second data after adjustment is transmitted to the second serial transceiver through the second bit width adaptation module;

[0032] The second data after adjustment is transmitted to the first serial transceiver through the second serial transceiver;

[0033] The second data after adjustment is transmitted to the first bit width adaptation module through the first serial transceiver;

[0034] In the case that the first bit width adaptation module receives the second data after adjustment, the second data after adjustment is de-mapped to obtain second data before adjustment;

[0035] The second data before adjustment is transmitted to the second uplink processor through the first bit width adaptation module.

[0036] According to the second aspect of the present application, a data transmission system is provided, characterized in that the data transmission system comprises a first programmable logic device and a second programmable logic device, wherein the first programmable logic device comprises a first bit width adaptation module, a first downlink processor and a first serial transceiver, the first bit width adaptation module is communicatively connected with the first downlink processor and the first serial transceiver respectively, the second programmable logic device comprises a second bit width adaptation module, a second uplink processor and a second serial transceiver, the second bit width adaptation module is communicatively connected with the second uplink processor and the second serial transceiver respectively;

[0037] The first bit width adaptation module is used to adjust the bit width of the first data in the first downlink processor based on the bit width of the user-side interface of the first serial transceiver, to obtain the adjusted first data, and to send the adjusted first data to the first serial transceiver. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device, and the bit width of the adjusted first data is the same as the bit width of the user-side interface of the first serial transceiver.

[0038] The first serial transceiver is used to send the adjusted first data to the second serial transceiver;

[0039] The second serial transceiver is used to send the adjusted first data to the second bit-width adapter module;

[0040] The second bit-width adaptation module is used to demap the adjusted first data upon receiving the adjusted first data to obtain the first data before adjustment, and then send the first data before adjustment to the second uplink processor.

[0041] According to a third aspect of the present invention, a data transmission apparatus is provided, the data transmission apparatus comprising:

[0042] The first bit width adaptation module is used to adjust the bit width of the first data in the first downlink processor based on the bit width of the user-side interface of the first serial transceiver to obtain the adjusted first data. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device, and the bit width of the adjusted first data is the same as the bit width of the user-side interface of the first serial transceiver.

[0043] The first data transmission module is used to send the adjusted first data to the first serial transceiver through the first bit width adaptation module.

[0044] The first serial transceiver processing module is used to send the adjusted first data to the second serial transceiver through the first serial transceiver.

[0045] The second serial transceiver processing module is used to send the adjusted first data to the second bit-width adapter module through the second serial transceiver.

[0046] The first data demapping module is used to demapping the adjusted first data when the second bit-width adaptation module receives the adjusted first data to obtain the first data before adjustment.

[0047] The second data transmission module is used to send the first data before adjustment to the second uplink processor through the second bit-width adaptation module.

[0048] Optionally, the device includes:

[0049] The first maximum interface bit width acquisition module is used to acquire the maximum interface bit width of the first downlink processor;

[0050] The first interface bit width setting module is used to set the user-side interface bit width of the first serial transceiver according to the maximum interface bit width of the first downlink processor.

[0051] Optionally, the first bit-width adaptation module includes:

[0052] The bit width acquisition submodule is used to acquire the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver through the first bit width adaptation module.

[0053] The bit width numerical relationship determination submodule is used to determine the numerical relationship between the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver based on the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver.

[0054] The data bit width adjustment submodule is used to copy each bit of the first data in the first downlink processor to obtain the adjusted first data if the numerical relationship is that the bit width of the first data in the first downlink processor is less than the user-side interface bit width of the first serial transceiver.

[0055] Optionally, the first bit-width adaptation module includes:

[0056] The data transmission submodule is configured to transmit the first data in the first downlink processor to the first serial transceiver if the numerical relationship is such that the bit width of the first data in the first downlink processor is equal to the bit width of the user-side interface of the first serial transceiver.

[0057] Optionally, the first data demapping module includes:

[0058] The data partitioning submodule is used to partition the adjusted first data to obtain several sets of preset numerical bits.

[0059] The bit value acquisition submodule is used to acquire the value of any set of preset bit values.

[0060] The data weighting submodule is used to weight the values ​​of the preset numerical bits to obtain the weighted bit values;

[0061] The data comparison submodule is used to compare the weighted bit value with a preset threshold.

[0062] The first data demapping submodule is used to demap the preset value bit to a first value if the weighted bit value is greater than or equal to the preset threshold.

[0063] The second data demapping submodule is used to demap the preset value bit to a second value if the weighted bit value is less than the preset decision threshold.

[0064] Optionally, the device includes:

[0065] The second bit width adaptation module is used to adjust the bit width of the second data in the second downlink processor based on the bit width of the user-side interface of the second serial transceiver to obtain the adjusted second data, wherein the bit width of the adjusted second data is the same as the bit width of the user-side interface of the second serial transceiver.

[0066] The third data transmission module is used to send the adjusted second data to the second serial transceiver through the second bit width adaptation module;

[0067] The third serial transceiver processing module is used to send the adjusted second data to the first serial transceiver through the second serial transceiver.

[0068] The fourth serial transceiver processing module is used to send the adjusted second data to the first bit-width adapter module through the first serial transceiver.

[0069] The second data demapping module is used to demapping the adjusted second data when the first width adaptation module receives the adjusted second data to obtain the second data before adjustment.

[0070] The fourth data transmission module is used to send the second data before adjustment to the second uplink processor through the first bit-width adaptation module.

[0071] According to another aspect of the present invention, an electronic device is also provided, comprising:

[0072] processor;

[0073] Memory used to store the processor's executable instructions;

[0074] The processor is configured to execute the instructions to implement the data transfer method described above.

[0075] According to another aspect of the present invention, a readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the data transmission method described above.

[0076] The data transmission method provided in this embodiment of the invention is applied to a data transmission system. The data transmission system includes a first programmable logic device and a second programmable logic device. The first programmable logic device includes a first bit-width adapter module, a first downlink processor, and a first serial transceiver. The first bit-width adapter module establishes communication connections with both the first downlink processor and the first serial transceiver. The second programmable logic device includes a second bit-width adapter module, a second uplink processor, and a second serial transceiver. The second bit-width adapter module establishes communication connections with both the second uplink processor and the second serial transceiver. The first bit-width adapter module adjusts the bit width of the first data in the first downlink processor based on the user-side interface bit width of the first serial transceiver. The process involves adjusting the data to obtain the adjusted first data. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device. The bit width of the adjusted first data is the same as the bit width of the user-side interface of the first serial transceiver. The adjusted first data is then sent to the first serial transceiver via the first bit width adapter module. The adjusted first data is then sent to the second serial transceiver via the first serial transceiver. The adjusted first data is then sent to the second bit width adapter module via the second serial transceiver. Upon receiving the adjusted first data, the second bit width adapter module demaps the adjusted first data to obtain the first data before adjustment. Finally, the first data before adjustment is sent to the second uplink processor via the second bit width adapter module. This invention adds a bit-width adaptation module, which enables the bit-width adaptation module to adjust the bit-width of the first data in the first downlink processor based on the bit-width of the user-side interface of the first serial transceiver. Regardless of the bit-width mode of the first data in the first downlink processor, it can ensure that the first data in the first downlink processor can be transmitted normally to the first serial transceiver. Moreover, only one first serial transceiver is needed to achieve this, without the need to instantiate multiple first serial transceivers. This significantly reduces the consumption of internal FPGA resources and the power consumption of the FPGA, thereby solving the problem of high FPGA resource consumption and high power consumption caused by instantiating multiple SerDes in the FPGA.

[0077] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0078] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0079] Figure 1 This is one of the flowcharts of a data transmission method provided in an embodiment of the present invention;

[0080] Figure 2 This is a schematic diagram of a data transmission system provided in an embodiment of the present invention;

[0081] Figure 3 This is the second step flowchart of a data transmission method provided in an embodiment of the present invention;

[0082] Figure 4 This is the third step in a flowchart of a data transmission method provided in an embodiment of the present invention;

[0083] Figure 5 This is the fourth step in a flowchart of a data transmission method provided in an embodiment of the present invention;

[0084] Figure 6 This is a device block diagram of a data transmission apparatus provided in an embodiment of the present invention;

[0085] Figure 7 This is a schematic diagram of a communication device provided in an embodiment of the present invention. Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of the present invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0087] Reference Figure 1 This diagram illustrates one of the steps of a data transmission method provided in an embodiment of the present invention, applied to a data transmission system. The method may include:

[0088] Step 101: The first width adaptation module adjusts the bit width of the first data in the first downlink processor based on the bit width of the user-side interface of the first serial transceiver to obtain the adjusted first data. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device. The bit width of the adjusted first data is the same as the bit width of the user-side interface of the first serial transceiver.

[0089] It should be noted that, in the embodiments of the present invention, as... Figure 2 As shown, the data transmission system includes a first programmable logic device and a second programmable logic device. The first programmable logic device includes a first bit-width adapter module, a first downlink processor, and a first serial transceiver. The first bit-width adapter module establishes communication connections with both the first downlink processor and the first serial transceiver. The second programmable logic device includes a second bit-width adapter module, a second uplink processor, and a second serial transceiver. The second bit-width adapter module establishes communication connections with both the second uplink processor and the second serial transceiver. It should be noted that the programmable logic device can be an FPGA (Field-Programmable Gate Array), and the serial transceiver can be a SerDes (Serializer / Deserializer).

[0090] The first width adaptation module adjusts the bit width of the first data in the first downlink processor based on the user-side interface bit width of the first serial transceiver, obtaining adjusted first data. This adjusted first data ensures that its bit width matches the user-side interface bit width of the first serial transceiver, guaranteeing that the first data in the first downlink processor can be transmitted normally to the first serial transceiver. It should be noted that the user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device besides the serial transceiver itself.

[0091] Step 102: The adjusted first data is sent to the first serial transceiver through the first wide adapter module.

[0092] Step 103: The adjusted first data is sent to the second serial transceiver via the first serial transceiver.

[0093] It should be noted that, in this embodiment of the invention, when the first width adapter module receives the adjusted first data, it sends the adjusted first data to the first serial transceiver. Since the adjusted first data is in parallel format, upon receiving the adjusted first data from the first width adapter module, the first serial transceiver converts the data format of the adjusted first data from parallel data to serial data. After completing the data format conversion of the adjusted first data, the first serial transceiver sends the adjusted first data to the second serial transceiver in the second programmable logic device.

[0094] Step 104: The adjusted first data is sent to the second bit-width adapter module via the second serial transceiver.

[0095] Step 105: When the second bit-width adaptation module receives the adjusted first data, it demaps the adjusted first data to obtain the first data before adjustment.

[0096] Step 106: The first data before adjustment is sent to the second uplink processor through the second bit-width adaptation module.

[0097] It should be noted that, in this embodiment of the invention, when the second serial transceiver receives the adjusted first data sent by the first serial transceiver, the second serial transceiver will convert the data format of the adjusted first data from serial data to parallel data. After completing the conversion of the data format of the adjusted first data, the second serial transceiver will send the adjusted first data to the second bit-width adaptation module.

[0098] When the second bit-width adapter module receives the adjusted first data sent by the second serial transceiver, the second bit-width adapter module demaps the adjusted first data to obtain the first data before adjustment.

[0099] After the second bit-width adapter module receives the first data before adjustment, it sends the first data before adjustment to the second uplink processor. Thus, the first programmable logic device and the second programmable logic device complete one round of data interaction.

[0100] In the process of transmitting data from the first programmable logic device to the second programmable logic device, this invention adds a first width adaptation module. This module can adjust the bit width of the first data in the first downlink processor based on the user-side interface bit width of the first serial transceiver. Regardless of the bit width mode of the first data in the first downlink processor, it can ensure that the first data in the first downlink processor can be transmitted normally to the first serial transceiver. Moreover, only one first serial transceiver is needed, eliminating the need to instantiate multiple first serial transceivers. This significantly reduces the consumption of internal resources and power consumption of the first programmable logic device, thereby solving the problem of high resource consumption and high power consumption of the first programmable logic device caused by instantiating multiple SerDes in the first programmable logic device.

[0101] Furthermore, such as Figure 3 The diagram illustrates a second flowchart of the data transmission method provided in an embodiment of the present invention. In this embodiment, the following steps may be included before step 101:

[0102] Step 301: Obtain the maximum interface bit width of the first downlink processor.

[0103] Step 302: Set the user-side interface width of the first serial transceiver according to the maximum interface width of the first downlink processor.

[0104] It should be noted that, in this embodiment of the invention, when instantiating the first serial transceiver, the model or specification of the first downlink processor used can be determined first, and the technical documentation or datasheet of the downlink processor can be consulted to find the technical specifications regarding the interface bit width. Typically, this information will clearly indicate the maximum interface bit width supported by the downlink processor.

[0105] After determining the maximum interface width of the first downlink processor, the user-side interface width of the first serial transceiver is configured to be the maximum interface width of the first downlink processor.

[0106] This invention configures the user-side interface width of the first serial transceiver to the maximum interface width of the first downlink processor, making the design of the first programmable logic device more flexible and adaptable to data transmission requirements with different bit widths. This provides convenience for future upgrades and expansions of the data transmission system, and makes it easier for designers to adjust and optimize the configuration of the data transmission system.

[0107] Furthermore, such as Figure 4 The diagram illustrates a third step of the data transmission method provided in this embodiment of the invention. In this embodiment, step 101 may further include the following steps:

[0108] Step 401: Obtain the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver through the first bit width adapter module.

[0109] Step 402: Determine the numerical relationship between the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver based on the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver.

[0110] It should be noted that, in this embodiment of the invention, the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver are obtained through the first bit width adaptation module. The first bit width adaptation module compares the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver to determine the numerical relationship between the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver.

[0111] Step 403: If the numerical relationship is that the bit width of the first data in the first downlink processor is less than the bit width of the user-side interface of the first serial transceiver, then each bit of the first data in the first downlink processor is copied to obtain the adjusted first data.

[0112] It should be noted that, in this embodiment of the invention, if the numerical relationship between the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver is such that the bit width of the first data in the first downlink processor is less than the bit width of the user-side interface of the first serial transceiver, then each bit of the first data in the first downlink processor is copied to obtain the adjusted first data.

[0113] For example, when the bit width of the first data in the first downlink processor is 8 bits and the bit width of the user-side interface of the first serial transceiver is 40 bits, if the first data in the first downlink processor is 01010101, then each bit of the first data "0", "1", "0", "1", "0", "1", "0", "1" is copied 5 times, and the adjusted first data is 0000011111000001111100000111110000011111000001111110000011111.

[0114] This invention ensures that the bit width of the first data in the first downlink processor is the same as the bit width of the user-side interface of the first serial transceiver when the bit width of the first data in the first downlink processor is smaller than the bit width of the user-side interface of the first serial transceiver, thereby realizing normal data transmission between the first downlink processor and the first serial transceiver.

[0115] Furthermore, in this embodiment of the invention, the following steps may be included after step 402:

[0116] If the numerical relationship is such that the bit width of the first data in the first downlink processor is equal to the bit width of the user-side interface of the first serial transceiver, then the first data in the first downlink processor is sent to the first serial transceiver.

[0117] It should be noted that, in this embodiment of the invention, if the numerical relationship between the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver is such that the bit width of the first data in the first downlink processor is equal to the bit width of the user-side interface of the first serial transceiver, then the first data in the first downlink processor is directly sent to the first serial transceiver through the first bit width adaptation module.

[0118] For example, when the bit width of the first data in the first downlink processor is 40 bits and the bit width of the user-side interface of the first serial transceiver is 40 bits, the first bit width adapter module does not need to adjust the bit width of the first data in the first downlink processor and can directly send the first data in the first downlink processor to the first serial transceiver.

[0119] This invention, by not adjusting the bit width of the first data in the first downlink processor when the bit width of the first data in the first downlink processor is equal to the bit width of the user-side interface of the first serial transceiver, directly sends the first data in the first downlink processor to the first serial transceiver, avoiding any additional data processing or copying operations, thereby reducing the consumption of FPGA internal resources and maximizing the utilization of FPGA resources, thus improving resource utilization efficiency.

[0120] Furthermore, such as Figure 5 The diagram illustrates a fourth step of the data transmission method provided in this embodiment of the invention. In this embodiment, step 105 may further include the following steps:

[0121] Step 501: Divide the adjusted first data into several sets of preset numerical bits.

[0122] Step 502: For any set of preset value bits, obtain the value of the preset value bits.

[0123] Step 503: Weight the preset numerical bit values ​​to obtain the weighted bit values.

[0124] Step 504: Compare the weighted bit value with the preset threshold.

[0125] Step 505: If the weighted bit value is greater than or equal to a preset threshold, then the preset bit value is demapped to the first bit value.

[0126] Step 506: If the weighted bit value is less than the preset decision threshold, then the preset bit value is demapped to the second bit value.

[0127] It should be noted that in this embodiment of the invention, during data transmission, interference may occur due to frequency offset or other factors, causing some bits to be transmitted incorrectly. Therefore, the data after mapping 1 bit to multiple bits needs to be judged based on the value of the multiple bits to demap out the data before adjustment.

[0128] Therefore, when the second bit-width adapter module receives the data from the second serial transceiver, it divides the data to obtain several sets of preset numerical bits.

[0129] For example: The first bit-width adapter module copies each bit of the first data in the first downlink processor by 5 times to obtain the adjusted first data. Then, the adjusted first data is sent to the second bit-width adapter module through the first serial transceiver and the second serial transceiver. If the adjusted first data received by the second bit-width adapter module is 00001000001111111111011100000110000011111, the adjusted first data is divided into 5 groups of preset value bits, namely "00001", "00000", "111111", "11110", "11100", "00011", "00000", and "11111".

[0130] For any set of preset value bits, obtain the value of the preset value bits. Weight the values ​​of the preset value bits to obtain a weighted bit value. Compare the weighted bit value with a preset threshold. If the weighted bit value is greater than or equal to the preset threshold, demap the preset value bits to a first value. If the weighted bit value is less than the preset decision threshold, demap the preset value bits to a second value. It should be noted that the preset threshold can be 3, the first value can be 1, and the second value can be 0. The specific value of the preset threshold can be adjusted as the scheme is optimized.

[0131] For example: the value of bit[4:0] is 11111. The weighted value of these 5 bits is 5. Since 5 is greater than the preset threshold of 3, 11111 is demapped to 1 and 1 is used as bit[0] of the first data before adjustment; the value of bit[9:5] is 00000. The weighted value of these 5 bits is 0. Since 0 is less than the preset threshold of 3, 00000 is demapped to 0 and 0 is used as bit[1] of the first data before adjustment. The value of bit[14:10] is 00011. The weighted value of these 5 bits is 2. Since 2 is less than the preset threshold 3, 00011 is demapped to 0 and 0 is used as the first data bit before adjustment [2]. The value of bit[19:15] is 11100. The weighted value of these 5 bits is 3. Since 3 is equal to the preset threshold 3, 11100 is demapped to 1 and 1 is used as the first data bit before adjustment [3]. The value of bit[24:20] is 11110. The 5-bit value is weighted and the resulting weighted bit value is 4. Since 4 is greater than the preset threshold 3, 11110 is demapped to 1 and 1 is used as the first data bit before adjustment [4]. The value of bit[29:25] is 11111. The 5-bit value is weighted and the resulting weighted bit value is 5. Since 5 is greater than the preset threshold 3, 11111 is demapped to 1 and 1 is used as the first data bit before adjustment [5]. The value of bits [34:30] is 00000. Weighting these 5 bits yields a weighted bit value of 0. Since 0 is less than the preset threshold of 3, 00000 is demapped to 0, and 0 is used as the first bit of the data before adjustment [6]. The value of bits [39:35] is 00001. Weighting these 5 bits yields a weighted bit value of 1. Since 1 is less than the preset threshold of 3, 00000 is demapped to 0, and 0 is used as the first bit of the data before adjustment [7]. Therefore, the first data before adjustment can be demapped to 00111001.

[0132] This invention obtains the original first data by demapping the adjusted first data, which can effectively detect and correct data transmission errors, improve the reliability of data transmission, and thus ensure the reliability of communication between FPGAs. Furthermore, it improves the overall performance of communication between FPGAs.

[0133] Furthermore, in this embodiment of the invention, the method may further include the following steps:

[0134] The second bit-width adaptation module adjusts the bit width of the second data in the second downlink processor based on the bit width of the user-side interface of the second serial transceiver to obtain the adjusted second data, wherein the bit width of the adjusted second data is the same as the bit width of the user-side interface of the second serial transceiver.

[0135] The adjusted second data is sent to the second serial transceiver via the second bit-width adapter module.

[0136] The adjusted second data is sent to the first serial transceiver via the second serial transceiver.

[0137] The adjusted second data is sent to the first wide adapter module via the first serial transceiver.

[0138] When the first wide-adapter module receives the adjusted second data, it demaps the adjusted second data to obtain the original second data.

[0139] The first wide-adapter module sends the second data before adjustment to the second uplink processor.

[0140] It should be noted that, in the embodiments of the present invention, as... Figure 2 As shown, the first programmable logic device includes a first uplink processor, which establishes a communication connection with the first bit-width adapter module. The second programmable logic device includes a second downlink processor, which establishes a communication connection with the second bit-width adapter module.

[0141] After setting the user-side interface bit width of the second serial transceiver, the second bit width adaptation module adjusts the bit width of the second data in the second downlink processor based on the user-side interface bit width of the second serial transceiver, obtaining the adjusted second data. This adjusted second data ensures that its bit width matches the user-side interface bit width of the second serial transceiver, guaranteeing that the second data in the second downlink processor can be transmitted normally to the second serial transceiver. It should be noted that the user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device besides the serial transceiver itself.

[0142] Upon receiving the adjusted second data, the second bit-width adapter module sends the adjusted second data to the second serial transceiver. Since the adjusted second data is in parallel format, upon receiving the adjusted second data from the second bit-width adapter module, the second serial transceiver converts the adjusted second data from parallel to serial format. After completing the format conversion, the second serial transceiver sends the adjusted second data to the first serial transceiver in the first programmable logic device.

[0143] When the first serial transceiver receives the adjusted second data sent by the second serial transceiver, the first serial transceiver converts the data format of the adjusted second data from serial data to parallel data. After completing the data format conversion of the adjusted second data, the first serial transceiver sends the adjusted second data to the first wide adapter module.

[0144] When the first wide adapter module receives the adjusted second data sent by the first serial transceiver, the first wide adapter module demaps the adjusted second data to obtain the second data before adjustment.

[0145] Once the first wide-adapter module receives the second data before adjustment, it sends the second data before adjustment to the first uplink processor. At this point, the second programmable logic device and the first programmable logic device complete one round of data interaction.

[0146] In the process of the second programmable logic device feeding back data to the first programmable logic device, this invention adds a second bit-width adaptation module. This module can adjust the bit width of the second data in the second downlink processor based on the bit width of the user-side interface of the second serial transceiver. Regardless of the bit width mode of the second data in the second downlink processor, it can ensure that the second data in the second downlink processor can be transmitted normally to the second serial transceiver. Moreover, only one second serial transceiver is needed, eliminating the need to instantiate multiple second serial transceivers. This significantly reduces the consumption of internal resources and power consumption of the second programmable logic device, thereby solving the problem of high resource consumption and high power consumption of the second programmable logic device caused by instantiating multiple SerDes in the second programmable logic device.

[0147] Furthermore, in this embodiment of the invention, the following steps may be included before the step of "the second bit-width adaptation module adjusts the bit width of the second data in the second downlink processor based on the user-side interface bit width of the second serial transceiver to obtain the adjusted second data":

[0148] Upon receiving the first data before adjustment, the second uplink processor obtains the maximum interface width of the second downlink processor.

[0149] The user-side interface width of the second serial transceiver is set according to the maximum interface width of the second downlink processor.

[0150] It should be noted that, in this embodiment of the invention, the second serial transceiver is instantiated after the second uplink processor receives the first data before adjustment. When instantiating the second serial transceiver, the model or specification of the second downlink processor can be determined first, and its technical documentation or datasheet can be consulted to find the technical specifications regarding the interface width. Typically, this information will clearly indicate the maximum interface width supported by the downlink processor.

[0151] After determining the maximum interface width of the second downlink processor, the user-side interface width of the second serial transceiver is configured to be the maximum interface width of the second downlink processor.

[0152] This invention configures the user-side interface width of the second serial transceiver to the maximum interface width of the second downlink processor, making the design of the second programmable logic device more flexible and adaptable to data transmission requirements with different bit widths. This provides convenience for future upgrades and expansions of the data transmission system, and makes it easier for designers to adjust and optimize the configuration of the data transmission system.

[0153] According to embodiments of the present invention, a data transmission system is also provided, such as... Figure 2 As shown, the data transmission system includes a first programmable logic device and a second programmable logic device. The first programmable logic device includes a first bit-width adapter module, a first downlink processor, and a first serial transceiver. The first bit-width adapter module establishes communication connections with the first downlink processor and the first serial transceiver, respectively. The second programmable logic device includes a second bit-width adapter module, a second uplink processor, and a second serial transceiver. The second bit-width adapter module establishes communication connections with the second uplink processor and the second serial transceiver, respectively.

[0154] The first width adapter module is used to adjust the width of the first data in the first downlink processor based on the width of the user-side interface of the first serial transceiver to obtain the adjusted first data, and send the adjusted first data to the first serial transceiver. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device, and the width of the adjusted first data is the same as the width of the user-side interface of the first serial transceiver.

[0155] The first serial transceiver is used to send the adjusted first data to the second serial transceiver;

[0156] The second serial transceiver is used to send the adjusted first data to the second bit-width adapter module.

[0157] The second bit-width adaptation module is used to demap the adjusted first data upon receiving it, obtain the first data before adjustment, and send the first data before adjustment to the second uplink processor.

[0158] It should be noted that, in this embodiment of the invention, the first width adaptation module adjusts the width of the first data in the first downlink processor based on the user-side interface width of the first serial transceiver to obtain adjusted first data. This adjusted first data ensures that its width matches the user-side interface width of the first serial transceiver, thereby guaranteeing that the first data in the first downlink processor can be transmitted normally to the first serial transceiver. It should also be noted that the user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device besides the serial transceiver.

[0159] Upon receiving the adjusted first data, the first wide-adapter module sends the adjusted first data to the first serial transceiver. Since the adjusted first data is in parallel format, upon receiving the adjusted first data from the first wide-adapter module, the first serial transceiver converts the data format of the adjusted first data from parallel to serial data. After completing the data format conversion, the first serial transceiver sends the adjusted first data to the second serial transceiver in the second programmable logic device.

[0160] When the second serial transceiver receives the adjusted first data sent by the first serial transceiver, the second serial transceiver converts the data format of the adjusted first data from serial data to parallel data. After completing the data format conversion of the adjusted first data, the second serial transceiver sends the adjusted first data to the second bit-width adapter module.

[0161] When the second bit-width adapter module receives the adjusted first data sent by the second serial transceiver, the second bit-width adapter module demaps the adjusted first data to obtain the first data before adjustment.

[0162] After the second bit-width adapter module receives the first data before adjustment, it sends the first data before adjustment to the second uplink processor. Thus, the first programmable logic device and the second programmable logic device complete one round of data interaction.

[0163] In the process of transmitting data from the first programmable logic device to the second programmable logic device, this invention adds a first bit width adaptation module. This module can adjust the bit width of the first data in the first downlink processor based on the user-side interface bit width of the first serial transceiver. Regardless of the bit width mode of the first data in the first downlink processor, it can ensure that the first data in the first downlink processor can be transmitted normally to the first serial transceiver. Moreover, only one first serial transceiver is needed, eliminating the need to instantiate multiple first serial transceivers. This significantly reduces the consumption of internal resources and power consumption of the first programmable logic device, thereby solving the problem of high resource consumption and high power consumption of the first programmable logic device caused by instantiating multiple SerDes in the first programmable logic device.

[0164] Reference Figure 6 , Figure 6 This is a block diagram of a data transmission device provided in an embodiment of the present invention. The data transmission device includes:

[0165] The first bit width adaptation module 601 is used to adjust the bit width of the first data in the first downlink processor based on the bit width of the user-side interface of the first serial transceiver to obtain the adjusted first data. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device, and the bit width of the adjusted first data is the same as the bit width of the user-side interface of the first serial transceiver.

[0166] The first data transmission module 602 is used to send the adjusted first data to the first serial transceiver through the first bit width adaptation module.

[0167] The first serial transceiver processing module 603 is used to send the adjusted first data to the second serial transceiver through the first serial transceiver.

[0168] The second serial transceiver processing module 604 is used to send the adjusted first data to the second bit width adapter module through the second serial transceiver.

[0169] The first data demapping module 605 is used to demapping the adjusted first data when the second bit-width adaptation module receives the adjusted first data to obtain the first data before adjustment.

[0170] The second data transmission module 606 is used to send the first data before adjustment to the second uplink processor through the second bit width adaptation module.

[0171] Optionally, the device includes:

[0172] The first maximum interface bit width acquisition module is used to acquire the maximum interface bit width of the first downlink processor;

[0173] The first interface bit width setting module is used to set the user-side interface bit width of the first serial transceiver according to the maximum interface bit width of the first downlink processor.

[0174] Optionally, the first wide adapter module includes:

[0175] The bit width acquisition submodule is used to acquire the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver through the first bit width adaptation module.

[0176] The bit width numerical relationship determination submodule is used to determine the numerical relationship between the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver based on the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver.

[0177] The data bit width adjustment submodule is used to copy each bit of the first data in the first downlink processor to obtain the adjusted first data if the numerical relationship is that the bit width of the first data in the first downlink processor is less than the user-side interface bit width of the first serial transceiver.

[0178] Optionally, the first wide adapter module includes:

[0179] The data transmission submodule is configured to transmit the first data in the first downlink processor to the first serial transceiver if the numerical relationship is such that the bit width of the first data in the first downlink processor is equal to the bit width of the user-side interface of the first serial transceiver.

[0180] Optionally, the first data demapping module includes:

[0181] The data partitioning submodule is used to partition the adjusted first data to obtain several sets of preset numerical bits.

[0182] The bit value acquisition submodule is used to acquire the value of any set of preset bit values.

[0183] The data weighting submodule is used to weight the values ​​of the preset numerical bits to obtain the weighted bit values;

[0184] The data comparison submodule is used to compare the weighted bit value with a preset threshold.

[0185] The first data demapping submodule is used to demap the preset value bit to a first value if the weighted bit value is greater than or equal to the preset threshold.

[0186] The second data demapping submodule is used to demap the preset value bit to a second value if the weighted bit value is less than the preset decision threshold.

[0187] Optionally, the device includes:

[0188] The second bit width adaptation module is used to adjust the bit width of the second data in the second downlink processor based on the bit width of the user-side interface of the second serial transceiver to obtain the adjusted second data, wherein the bit width of the adjusted second data is the same as the bit width of the user-side interface of the second serial transceiver.

[0189] The third data transmission module is used to send the adjusted second data to the second serial transceiver through the second bit width adaptation module;

[0190] The third serial transceiver processing module is used to send the adjusted second data to the first serial transceiver through the second serial transceiver.

[0191] The fourth serial transceiver processing module is used to send the adjusted second data to the first bit-width adapter module through the first serial transceiver.

[0192] The second data demapping module is used to demapping the adjusted second data when the first width adaptation module receives the adjusted second data to obtain the second data before adjustment.

[0193] The fourth data transmission module is used to send the second data before adjustment to the second uplink processor through the first bit-width adaptation module.

[0194] This invention also provides an electronic device, such as... Figure 7 As shown, it includes a processor 701, a communication interface 702, a memory 703, and a communication bus 704, wherein the processor 701, the communication interface 702, and the memory 703 communicate with each other through the communication bus 704.

[0195] Memory 703 is used to store computer programs;

[0196] When processor 701 executes a program stored in memory 703, it performs the following steps:

[0197] The first width adapter module adjusts the width of the first data in the first downlink processor based on the user-side interface width of the first serial transceiver to obtain the adjusted first data. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device. The width of the adjusted first data is the same as the user-side interface width of the first serial transceiver.

[0198] The adjusted first data is sent to the first serial transceiver via the first wide adapter module.

[0199] The adjusted first data is sent to the second serial transceiver via the first serial transceiver;

[0200] The adjusted first data is sent to the second bit-width adapter module via the second serial transceiver.

[0201] When the second bit-width adapter module receives the adjusted first data, it demaps the adjusted first data to obtain the first data before adjustment.

[0202] The first data before adjustment is sent to the second uplink processor through the second bit-width adaptation module.

[0203] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0204] The communication interface is used for communication between the aforementioned terminal and other devices.

[0205] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0206] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0207] In another embodiment of the present invention, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform any of the data transmission methods described in the above embodiments.

[0208] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state drive, or SSD).

[0209] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0210] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0211] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A data transmission method, characterized in that, An application is made in a data transmission system, the data transmission system comprising a first programmable logic device and a second programmable logic device, wherein the first programmable logic device includes a first bit-width adapter module, a first downlink processor, and a first serial transceiver, the first bit-width adapter module establishing communication connections with the first downlink processor and the first serial transceiver respectively; the second programmable logic device includes a second bit-width adapter module, a second uplink processor, and a second serial transceiver, the second bit-width adapter module establishing communication connections with the second uplink processor and the second serial transceiver respectively; the method includes: The first bit width adaptation module adjusts the bit width of the first data in the first downlink processor based on the bit width of the user-side interface of the first serial transceiver to obtain the adjusted first data. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device. The bit width of the adjusted first data is the same as the bit width of the user-side interface of the first serial transceiver. The bit width of the user-side interface of the first serial transceiver is configured as the maximum interface bit width of the first downlink processor. The adjusted first data is sent to the first serial transceiver through the first bit-width adaptation module. The adjusted first data is sent to the second serial transceiver via the first serial transceiver. The adjusted first data is sent to the second bit-width adaptation module via the second serial transceiver. When the second bit-width adaptation module receives the adjusted first data, it demaps the adjusted first data to obtain the first data before adjustment. The first data before adjustment is sent to the second uplink processor through the second bit-width adaptation module.

2. The method according to claim 1, characterized in that, Before the step of adjusting the bit width of the first data in the first downlink processor based on the user-side interface bit width of the first serial transceiver to obtain the adjusted first data, the method includes: Obtain the maximum interface bit width of the first downlink processor; The user-side interface width of the first serial transceiver is set according to the maximum interface width of the first downlink processor.

3. The method according to claim 1, characterized in that, The first bit-width adaptation module adjusts the bit width of the first data in the first downlink processor based on the user-side interface bit width of the first serial transceiver, resulting in the adjusted first data including: The first bit width adaptation module obtains the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver. Based on the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver, determine the numerical relationship between the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver. If the numerical relationship is such that the bit width of the first data in the first downlink processor is less than the bit width of the user-side interface of the first serial transceiver, then each bit of the first data in the first downlink processor is copied to obtain the adjusted first data.

4. The method according to claim 3, characterized in that, After the step of determining the numerical relationship between the bit width of the first data in the first downlink processor and the bit width of the user-side interface of the first serial transceiver, the method includes: If the numerical relationship is such that the bit width of the first data in the first downlink processor is equal to the bit width of the user-side interface of the first serial transceiver, then the first data in the first downlink processor is sent to the first serial transceiver.

5. The method according to claim 1, characterized in that, The step of demapping the adjusted first data to obtain the unadjusted first data includes: The adjusted first data is divided into several sets of preset numerical bits; For any set of preset value bits, obtain the value of the preset value bits; The preset numerical bit values ​​are weighted to obtain weighted bit values; The weighted bit value is compared with a preset threshold. If the weighted bit value is greater than or equal to the preset threshold, then the preset bit value is demapped to the first bit value; If the weighted bit value is less than the preset threshold, then the preset bit value is demapped to a second bit value.

6. The method according to claim 1, characterized in that, The first programmable logic device includes a first uplink processor, which establishes a communication connection with the first bit-width adaptation module. The second programmable logic device includes a second downlink processor. The link processor establishes a communication connection with the second bit-width adaptation module. After the step of sending the first data before adjustment to the second uplink processor through the second bit-width adaptation module, the method includes: The second bit width adaptation module adjusts the bit width of the second data in the second downlink processor based on the bit width of the user-side interface of the second serial transceiver to obtain the adjusted second data, wherein the bit width of the adjusted second data is the same as the bit width of the user-side interface of the second serial transceiver. The adjusted second data is sent to the second serial transceiver via the second bit-width adaptation module. The adjusted second data is sent to the first serial transceiver via the second serial transceiver; The adjusted second data is sent to the first bit-width adaptation module via the first serial transceiver. When the first wide-adapter module receives the adjusted second data, it demaps the adjusted second data to obtain the second data before adjustment. The first bit-width adaptation module sends the second data before adjustment to the second uplink processor.

7. A data transmission system, characterized in that, The data transmission system includes a first programmable logic device and a second programmable logic device. The first programmable logic device includes a first bit-width adapter module, a first downlink processor, and a first serial transceiver. The first bit-width adapter module establishes communication connections with the first downlink processor and the first serial transceiver, respectively. The second programmable logic device includes a second bit-width adapter module, a second uplink processor, and a second serial transceiver. The second bit-width adapter module establishes communication connections with the second uplink processor and the second serial transceiver, respectively. The first bit-width adaptation module is used to adjust the bit width of the first data in the first downlink processor based on the bit width of the user-side interface of the first serial transceiver, to obtain the adjusted first data, and to send the adjusted first data to the first serial transceiver. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device. The bit width of the adjusted first data is the same as the bit width of the user-side interface of the first serial transceiver. The bit width of the user-side interface of the first serial transceiver is configured as the maximum interface bit width of the first downlink processor. The first serial transceiver is used to send the adjusted first data to the second serial transceiver; The second serial transceiver is used to send the adjusted first data to the second bit-width adapter module; The second bit-width adaptation module is used to demap the adjusted first data upon receiving the adjusted first data to obtain the first data before adjustment, and then send the first data before adjustment to the second uplink processor.

8. A data transmission device, characterized in that, The data transmission device includes: The first bit width adaptation module is used to adjust the bit width of the first data in the first downlink processor based on the bit width of the user-side interface of the first serial transceiver to obtain the adjusted first data. The user-side interface is the interface connecting the serial transceiver to other logic modules in the programmable logic device. The bit width of the adjusted first data is the same as the bit width of the user-side interface of the first serial transceiver. The bit width of the user-side interface of the first serial transceiver is configured as the maximum interface bit width of the first downlink processor. The first data transmission module is used to send the adjusted first data to the first serial transceiver through the first bit width adaptation module. The first serial transceiver processing module is used to send the adjusted first data to the second serial transceiver through the first serial transceiver. The second serial transceiver processing module is used to send the adjusted first data to the second bit-width adapter module through the second serial transceiver. The first data demapping module is used to demapping the adjusted first data when the second bit-width adaptation module receives the adjusted first data to obtain the first data before adjustment. The second data transmission module is used to send the first data before adjustment to the second uplink processor through the second bit-width adaptation module.

9. An electronic device, characterized in that, include: Memory used to store processor-executable instructions; The processor is configured to execute the instructions to implement the data transmission method as described in any one of claims 1 to 6.

10. A readable storage medium, characterized in that, A computer program is stored on the readable storage medium, which, when executed by a processor, implements the data transmission method as described in any one of claims 1 to 6.

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