Low-dropout linear regulator circuit, power supply, and electronic device

Abstract

The application discloses a low-dropout linear voltage regulator circuit, a power supply and an electronic device, and belongs to the technical field of electronic devices. The LDO circuit comprises a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit. In the case that the LDO circuit jumps downward, the current sampling circuit can collect an increased sampling current, so that the error amplifier generates an increased error amplification voltage, the output voltage of the output power tube is rapidly reduced, the overshoot voltage of the LDO circuit is reduced, and the state recovery time length of the output voltage of the LDO circuit is reduced. In the case that the LDO circuit jumps upward, the current sampling circuit collects a reduced sampling current, so that the error amplifier generates a reduced error amplification voltage, the output voltage of the output power tube is rapidly increased, the undershoot voltage of the LDO circuit is reduced, the state recovery time length of the output voltage of the LDO circuit is reduced, and the load transient response capability is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic equipment, and particularly relates to a low-dropout linear regulator circuit, a power supply and an electronic device. BACKGROUND

[0002] A low-dropout linear regulator (LDO) is a kind of linear DC voltage regulator, which is used to provide a stable DC voltage power supply. The LDO circuit has a relatively good power supply rejection ratio (PSRR) and a simple structure, and is thus widely used in various power supply systems.

[0003] In the actual use process of the LDO circuit, if the load current jumps, the output voltage of the LDO circuit will also change. The process of the output voltage of the LDO circuit from the initial change state to the stable state under the action of the load transient jump is the load transient response process. The load transient response capability is an important performance of the LDO circuit, and the current power supply system also has a relatively high requirement on the load transient response capability. For example, in the one time program (OTP) burning scene, the OTP burning has the characteristics of short burning period and large burning current jump. Therefore, the OTP burning system has a relatively high requirement on the load transient response capability of the power supply, so as to meet the requirements of small overshoot and fast state recovery of the power supply.

[0004] However, the bandwidth of the current LDO circuit is usually small. The load transient response capability is limited by the bandwidth of the LDO circuit, which makes the load transient response capability of the current LDO circuit poor, resulting in the problems of large overshoot voltage, large undershoot voltage and long stable state recovery time under the action of the load transient jump. SUMMARY

[0005] The LDO circuit, the power supply and the electronic device provided by the embodiments of the application can solve the problem of poor load transient response capability of the current LDO circuit to some extent.

[0006] In a first aspect, an LDO circuit is provided, and the LDO circuit comprises: a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit.

[0007] The voltage sampling circuit is connected with a voltage output end of the LDO circuit and the error amplifier, and is configured to transmit a feedback voltage corresponding to the voltage output end to the error amplifier.

[0008] The current sampling circuit is connected with the error amplifier and the voltage output end, and is configured to convert an output voltage of the voltage output end into a sampling current and transmit the sampling current to the error amplifier.

[0009] The error amplifier is connected with the output power tube, and is configured to generate an error amplification voltage by forward adjusting the error between the feedback voltage and the reference voltage according to the sampling current, and transmit the error amplification voltage to the output power tube.

[0010] The output power tube is connected with the voltage output end, and is configured to convert an input voltage into an output voltage under the control of the error amplification voltage, and transmit the output voltage to the voltage output end.

[0011] In a second aspect, a power supply is provided, and the power supply comprises the LDO circuit according to any one of the first aspect.

[0012] In a third aspect, an electronic device is provided, and the electronic device comprises the LDO circuit according to any one of the first aspect or the power supply according to the second aspect.

[0013] In the LDO circuit, the power supply and the electronic device provided by the embodiments of the present application, the LDO circuit comprises a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit. The voltage sampling circuit is configured to transmit a feedback voltage corresponding to a voltage output end of the LDO circuit to the error amplifier. The error amplifier is configured to generate an error amplification voltage according to a reference voltage and the feedback voltage, and transmit the error amplification voltage to the output power tube. The output power tube is configured to convert an input voltage of the LDO circuit into an output voltage under the control of the error amplification voltage, and transmit the output voltage to the voltage output end. The current sampling circuit is configured to convert the output voltage into a sampling current, and transmit the sampling current to the error amplifier. The error amplifier is further configured to forward adjust the error amplification voltage according to the sampling current.

[0014] In the technical solution, the current sampling circuit can convert the size change of the output voltage into the size change of the sampling current, so that the error amplifier generates an error amplification voltage that changes in a positive direction with the current. In this way, when the load of the LDO circuit jumps downward and an overshoot of the output voltage occurs, the current sampling circuit can collect an increased sampling current, so that the error amplifier generates an increased error amplification voltage, controls the on-resistance of the output power transistor to be increased, rapidly reduces the output voltage transmitted by the output power transistor to the voltage output terminal, reduces the overshoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. Similarly, when the load of the LDO circuit jumps upward and an undershoot of the output voltage occurs, the current sampling circuit can collect a decreased sampling current, so that the error amplifier generates a decreased error amplification voltage, controls the on-resistance of the output power transistor to be decreased, rapidly increases the output voltage transmitted by the output power transistor to the voltage output terminal, reduces the undershoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a structural schematic diagram of an LDO circuit provided by the related art;

[0016] Figure 2 is a structural schematic diagram of another LDO circuit provided by the related art;

[0017] Figure 3 is a structural schematic diagram of an LDO circuit provided by an embodiment of the present application;

[0018] Figure 4 is a structural schematic diagram of another LDO circuit provided by an embodiment of the present application;

[0019] Figure 5 is a structural schematic diagram of another LDO circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0021] An LDO is a low-dropout linear regulator, which is used to provide a stable DC voltage power supply. The LDO circuit has a relatively good PSRR and a simple structure, and is thus widely applied to various power supply systems.

[0022] For example, refer to Figure 1 which shows a structural diagram of an LDO circuit provided by the related art. As shown in Figure 1 , the LDO circuit 10 includes an error amplifier EA, an output power tube M10, a third resistor Rfb1, a fourth resistor Rfb2, an equivalent series resistance (ESR) ESR, and a load capacitor Cload. The output power tube M10 can be a P-channel Metal Oxide Semiconductor (PMOS) tube. The equivalent series resistance ESR is the equivalent series resistance of the load capacitor Cload.

[0023] The inverse input end of the error amplifier EA is connected with the reference voltage end VREF, for receiving the reference voltage Vref provided by the reference voltage end VREF. The forward input end of the error amplifier EA is connected with the third resistor Rfb1 and the fourth resistor Rfb2 respectively. The output end of the error amplifier EA is also connected with the gate of the output power tube M10. The source of the output power tube M10 is connected with the voltage input end VIN, for receiving the input voltage Vin provided by the voltage input end VIN. The drain of the output power tube M10 is grounded through the third resistor Rfb1 and the fourth resistor Rfb2 in series. The drain of the output power tube M10 is also connected with the voltage output end VOUT of the LDO circuit 10. One end of the equivalent series resistance ESR is connected with the voltage output end VOUT, and the other end of the equivalent series resistance ESR is grounded through the load capacitor Cload.

[0024] In the LDO circuit 10, the third resistor Rfb1 and the fourth resistor Rfb2 are used to collect the output voltage Vout of the voltage output end VOUT, and convert the output voltage Vout into the feedback voltage Vfb in proportion according to the resistance values of the third resistor Rfb1 and the fourth resistor Rfb2, and transmit the feedback voltage Vfb to the error amplifier EA. The error amplifier EA is used to amplify the error between the feedback voltage Vfb and the reference voltage Vref, generate an error amplification voltage, and transmit the error amplification voltage to the output power tube M10, for adjusting the on-resistance of the output power tube M10. The output power tube M10 is used to convert the input voltage Vin into the output voltage Vout according to the on-resistance, and transmit the output voltage Vout to the voltage output end VOUT.

[0025] The LDO circuit 10 can perform error amplification on the reference voltage Vref through negative feedback to output a stable output voltage Vout in proportion to the resistance value of the feedback resistors (i.e., the third resistor Rfb1 and the fourth resistor Rfb2). The output voltage Vout satisfies the formula: Vout = (1 + R11 / R12) x Vref. In the formula, R11 represents the resistance value of the third resistor Rfb1. R12 represents the resistance value of the fourth resistor Rfb2. Vref represents the reference voltage. The LDO circuit 10 is generally applicable to low-voltage power supplies and has the advantages of low noise, small quiescent current, and low cost.

[0026] For another example, the device structure of the error amplifier included in the LDO circuit can be a fold-cascode structure. The error amplifier with the fold-cascode structure can be a fold amplifier. The LDO circuit including the error amplifier with the fold-cascode structure is a fold-cascode structure LDO circuit. Please refer to Figure 2 which shows the structure diagram of another LDO circuit provided by the related art. As Figure 2 shown, the LDO circuit 10 includes a compensation capacitor Cc, an error amplifier 101, an output power tube M10, a third resistor Rfb1, a fourth resistor Rfb2, an equivalent series resistance ESR, and a load capacitor Cload. The output power tube M10 is a PMOS tube M10.

[0027] The error amplifier 101 includes a first power tube M1, a second power tube M2, a third power tube M3, a fourth power tube M4, a fifth power tube M5, a sixth power tube M6, a seventh power tube M7, an eighth power tube M8, and a ninth power tube (i.e., a tail current source tube) M9.

[0028] The gate of the first power tube M1 is connected with the feedback voltage node VFB. The drain of the first power tube M1 is connected with the source of the sixth power tube M6 and the drain of the fourth power tube M4. The source of the first power tube M1 is connected with the source of the second power tube M2 and the drain of the ninth power tube M9.

[0029] The gate of the second power tube M2 is connected with the reference voltage terminal VREF for receiving the reference voltage Vref provided by the reference voltage terminal VREF. The drain of the second power tube M2 is connected with the source of the fifth power tube M5 and the drain of the third power tube M3. The source of the third power tube M3 and the source of the fourth power tube M4 are grounded. The gate of the third power tube M3 is connected with the gate of the fourth power tube M4 and the second bias voltage terminal.

[0030] The drain of the fifth power tube M5 is connected with the drain of the seventh power tube M7 and the gate of the output power tube M10. The gate of the fifth power tube M5 is connected with the gate of the sixth power tube M6 and the third bias voltage terminal.

[0031] The drain of the sixth power transistor M6 is connected to the drain of the eighth power transistor M8, the gate of the eighth power transistor M8 and the gate of the seventh power transistor M7, respectively. The source of the seventh power transistor M7 and the source of the eighth power transistor M8 are connected to the voltage input terminal VIN of the LDO circuit 10. The source of the ninth power transistor M9 is connected to the voltage input terminal VIN. The gate of the ninth power transistor M9 is connected to the fourth bias voltage terminal.

[0032] The fourth bias voltage terminal is configured to provide a bias voltage Vb4 of the ninth power transistor M9, which is used to adjust the on-resistance of the ninth power transistor M9 and control the on or off of the ninth power transistor M9. The second bias voltage terminal is configured to provide a bias voltage Vb2 of the third power transistor M3 and the fourth power transistor M4, which is used to adjust the on-resistance of the third power transistor M3 and the fourth power transistor M4 and control the on or off of the third power transistor M3 and the fourth power transistor M4. The third bias voltage terminal is configured to provide a bias voltage Vb3 of the fifth power transistor M5 and the sixth power transistor M6, which is used to adjust the on-resistance of the fifth power transistor M5 and the sixth power transistor M6 and control the on or off of the fifth power transistor M5 and the sixth power transistor M6. The voltage input terminal VIN is configured to provide an input voltage Vin of the LDO circuit 10. In addition, the first power transistor M1, the second power transistor M2, the seventh power transistor M7, the eighth power transistor M8 and the ninth power transistor M9 are PMOS transistors. The third power transistor M3, the fourth power transistor M4, the fifth power transistor M5 and the sixth power transistor M6 are NMOS transistors.

[0033] The source of the output power transistor M10 is connected to the voltage input terminal VIN. The drain of the output power transistor M10 is connected to the voltage output terminal VOUT. One end of the third resistor Rfb1 is connected to the voltage output terminal VOUT, and the other end of the third resistor Rfb1 is connected to ground through the fourth resistor Rfb2. The feedback node VFB is located on the path between the third resistor Rfb1 and the fourth resistor Rfb2. One end of the equivalent series resistance ESR is connected to the voltage output terminal VOUT, and the other end of the equivalent series resistance ESR is connected to ground through the load capacitor Cload. One end of the compensation capacitor Cc is connected to the voltage output terminal VOUT, and the other end of the compensation capacitor Cc is connected to the source of the fifth power transistor M5 and the drain of the third power transistor M3, respectively. The compensation capacitor Cc is used to compensate the stability of the circuit.

[0034] In the LDO circuit 10, the third resistor Rfb1 and the fourth resistor Rfb2 serve as feedback voltage divider resistors. They are used to acquire the output voltage Vout at the voltage output terminal VOUT and convert it into a feedback voltage Vfb proportionally to the resistance values ​​of Rfb1 and Rfb2. This feedback voltage Vfb is then transmitted to the first power transistor M1 of the error amplifier 101. The error amplifier 101 amplifies the error between the feedback voltage Vfb and the reference voltage Vref to generate an error amplification voltage. This error amplification voltage is transmitted to the gate of the output power transistor M10 to adjust its on-resistance. The output power transistor M10 converts the input voltage Vin into the output voltage Vout based on its on-resistance and transmits it to the voltage output terminal VOUT.

[0035] Compared to Figure 1 The LDO circuit shown is Figure 2 The LDO circuit shown effectively reduces input noise by using PMOS transistors as the input differential pair. Furthermore, the error amplifier 101 employs a folded cascode structure, resulting in higher open-loop gain and improved output voltage accuracy. Additionally, the output power transistor M10 uses a PMOS transistor, which offers lower dropout voltage compared to NMOS transistors. Cascode compensation using capacitor Cc effectively isolates the feedforward path, eliminates the right-half-plane zero (RHZ) of the LDO circuit, and optimizes the PSRR. Moreover, cascode compensation saves on the compensation series resistor and reduces circuit area compared to Miller compensation.

[0036] However, the bandwidth of current LDO circuits is typically small. Since the quality of load transient response is limited by the bandwidth of the LDO circuit, current LDO circuits have poor load transient response capabilities. They cannot respond instantaneously when the load current of the LDO circuit changes, resulting in problems such as large overshoot voltage, large undershoot voltage, and long recovery time under the action of load transient changes.

[0037] However, the current power supply system also has a high requirement on the load transient response capability. For example, in the OTP burning scene, the OTP burning has the characteristics of short burning period and large burning current jump. The OTP burning system will extract current of tens of milliamperes to twenty milliamperes from its power supply, and requires the power supply to reach the steady state to maintain the target output voltage within 10% of the burning time. Otherwise, it is easy to cause the fuse to burn continuously due to insufficient burning current, which affects the OTP burning. Therefore, the OTP burning system has a high requirement on the load transient response capability of the power supply, and needs to meet the requirements of small overshoot and fast state recovery of the power supply.

[0038] Please refer to Figure 3 which shows a structure diagram of an LDO circuit provided by an embodiment of the present application. The LDO circuit can improve the load transient response capability to a certain extent. As shown in Figure 3 , the LDO circuit 10 includes an error amplifier 101, an output power tube 102, a current sampling circuit 103 and a voltage sampling circuit 104.

[0039] Among them, the voltage sampling circuit 104 is connected with the voltage output end VOUT of the LDO circuit 10 and the error amplifier 101. The voltage sampling circuit 104 is used to transmit the feedback voltage Vfb corresponding to the voltage output end VOUT to the error amplifier 101. Specifically, the voltage sampling circuit 104 is used to convert the output voltage Vout of the voltage output end VOUT into the feedback voltage Vfb, and transmit the feedback voltage Vfb to the error amplifier 101.

[0040] The current sampling circuit 103 is connected with the error amplifier 101 and the voltage output end VOUT of the LDO circuit 10. The current sampling circuit 103 is used to convert the output voltage Vout of the voltage output end VOUT into the sampling current I, and transmit the sampling current I to the error amplifier 101.

[0041] The error amplifier 101 is connected with the output power transistor 102. The error amplifier 101 is configured to generate an error amplified voltage Vc according to the reference voltage Vref and the feedback voltage Vfb, and transmit the error amplified voltage Vc to the output power transistor 102. In addition, the error amplifier 101 is configured to adjust the error amplified voltage Vc according to the sampling current I. That is, the error amplifier 101 is configured to increase the error amplified voltage Vc when the sampling current I increases, and decrease the error amplified voltage Vc when the sampling current I decreases. Optionally, the error amplifier 101 has a negative input terminal connected with the reference voltage terminal VREF, and configured to receive the reference voltage Vref provided by the reference voltage terminal VREF. The error amplifier 101 has a positive input terminal connected with the voltage sampling circuit 104, and configured to receive the feedback voltage Vfb transmitted by the voltage sampling circuit 104. The error amplifier 101 has an output terminal connected with a control terminal of the output power transistor 102, and configured to transmit the error amplified voltage Vc to the output power transistor 102.

[0042] The output power transistor 102 is connected with the voltage output terminal VOUT. The output power transistor 102 is configured to convert the input voltage into the output voltage Vout under the control of the error amplified voltage Vc, and transmit the output voltage Vout to the voltage output terminal VOUT. Specifically, the error amplified voltage Vc is configured to adjust the on-resistance of the output power transistor 102. The output power transistor 102 is configured to convert the input voltage into the output voltage Vout according to the on-resistance, and transmit the output voltage Vout to the voltage output terminal VOUT. Optionally, the output power transistor 102 has a power supply terminal connected with the voltage input terminal VIN of the LDO circuit 10, and configured to receive the input voltage provided by the voltage input terminal VIN. The output power transistor 102 is connected with the error amplifier 101. The output power transistor 102 has an output terminal connected with the voltage output terminal VOUT of the LDO circuit 10. For example, the output power transistor 102 can be a PMOS transistor. The output power transistor 102 has a gate connected with the error amplifier 101, a source connected with the voltage input terminal VIN, and a drain connected with the voltage output terminal VOUT.

[0043] In the embodiment of the present application, when the load current of the LDO circuit 10 jumps downward, for example, from 15 mA to 500 uA, the output voltage Vout of the LDO circuit 10 will be temporarily raised, an overshoot phenomenon occurs, and an overshoot voltage is generated. The current sampling circuit 103 can convert the increased output voltage Vout into an increased sampling current I and transmit it to the error amplifier 101. The error amplifier 101 positively adjusts the error amplification voltage Vc according to the sampling current I to increase the error amplification voltage Vc, controls the output power tube 102 to be turned off, so that the on-resistance of the output power tube 102 increases. The output power tube 102 stops providing the output voltage Vout to the voltage output terminal VOUT, so that the output voltage Vout of the LDO circuit 10 rapidly decreases, the overshoot voltage rapidly decreases, and the influence of the output voltage overshoot is weakened.

[0044] With the gradual decrease of the output voltage Vout of the LDO circuit 10, the sampling current I collected by the current sampling circuit 103 gradually decreases. The error amplifier 101 adjusts the error amplification voltage Vc according to the sampling current I to decrease, and the output power tube 102 is turned on. After the output voltage Vout of the LDO circuit 10 is in a stable state, the sampling current I collected by the current sampling circuit 103 is in a stable state. The error amplifier 101 weakens the adjustment ability of the error amplification voltage Vc by the sampling current I, and the error amplification voltage Vc output by the error amplifier 101 is in a stable state.

[0045] Similarly, when the load current of the LDO circuit 10 jumps upward, for example, from 500 uA to 15 mA, the output voltage Vout of the LDO circuit 10 will be temporarily pulled down, an undershoot phenomenon occurs, and an undershoot voltage is generated. The current sampling circuit 103 can convert the reduced output voltage Vout into a reduced sampling current I and transmit it to the error amplifier 101. The error amplifier 101 positively adjusts the error amplification voltage Vc according to the sampling current I to decrease the error amplification voltage Vc, controls the on-resistance of the output power tube 102 to decrease. The output power tube 102 provides an increased output voltage Vout to the voltage output terminal VOUT, so that the output voltage Vout of the LDO circuit 10 rapidly increases, the undershoot voltage rapidly decreases, the influence of the output voltage undershoot is weakened, and the load transient response capability is improved.

[0046] In the embodiment of the present application, the LDO circuit comprises: a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit. The voltage sampling circuit is configured to transmit a feedback voltage corresponding to a voltage output end of the LDO circuit to the error amplifier. The error amplifier is configured to generate an error amplification voltage according to the reference voltage and the feedback voltage, and transmit the error amplification voltage to the output power tube. The output power tube is configured to convert an input voltage of the LDO circuit into an output voltage under the control of the error amplification voltage, and transmit the output voltage to the voltage output end. The current sampling circuit is configured to convert the output voltage into a sampling current, and transmit the sampling current to the error amplifier. The error amplifier is further configured to adjust the error amplification voltage in a positive direction according to the sampling current.

[0047] In the technical solution, the current sampling circuit can convert the size change of the output voltage into the size change of the sampling current, so that the error amplifier generates the error amplification voltage that changes in a positive direction with the current. In this way, when the load of the LDO circuit jumps downward and the output voltage overshoots, the current sampling circuit can collect the increased sampling current, so that the error amplifier generates the increased error amplification voltage to control the increased on-resistance of the output power tube, quickly reduces the output voltage transmitted by the output power tube to the voltage output end, reduces the overshoot voltage of the LDO circuit, reduces the state recovery time length of the output voltage of the LDO circuit, and improves the load transient response capability. Similarly, when the load of the LDO circuit jumps upward and the output voltage undershoots, the current sampling circuit can collect the decreased sampling current, so that the error amplifier generates the decreased error amplification voltage to control the decreased on-resistance of the output power tube, quickly increases the output voltage transmitted by the output power tube to the voltage output end, reduces the undershoot voltage of the LDO circuit, reduces the state recovery time length of the output voltage of the LDO circuit, and improves the load transient response capability.

[0048] Optionally, as shown in Figure 4 The current sampling circuit 103 comprises: a current conversion module 1031 and a current amplification module 1032. The current conversion module 1031 is connected with the voltage output end VOUT of the LDO circuit 10 and the current amplification module 1032. The current conversion module 1031 is configured to convert the output voltage Vout into a sampling current I, and transmit the sampling current I to the current amplification module 1032.

[0049] The current amplification module 1032 is connected with the error amplifier 101. The current amplification module 1032 is configured to amplify the sampling current I and transmit the amplified sampling current I to the error amplifier 101. In this way, the sampling current is amplified by the current amplification module 1032, so that the change of the sampling current can more accurately reflect the change of the output voltage of the LDO circuit. Then, the error amplifier 101 can more accurately control the on-resistance of the output power tube 102 according to the error amplified voltage adjusted by the sampling current, effectively reduce the state recovery time of the output voltage of the LDO circuit, and improve the load transient response capability.

[0050] Further optionally, the device structure of the error amplifier 101 is a folded common-source common-gate structure. The error amplifier 101 includes a common-source common-gate tube module. As shown in Figure 5 The current amplification module 1032 includes a first current amplifier Q1 and a second current amplifier Q2.

[0051] The first current amplifier Q1 is connected with the current conversion module 1031 and a first input end IN1 of the common-source common-gate tube module of the error amplifier 101. The first current amplifier Q1 is configured to amplify the sampling current I and transmit the amplified sampling current I to the first input end IN1.

[0052] The second current amplifier Q2 is connected with a second input end IN2 of the common-source common-gate tube module. The second current amplifier Q2 is configured to provide a matching current between the second input end IN2 and the first input end IN1. Optionally, the matching current can be equal to the amplified sampling current I output by the first current amplifier Q1 in the case that the voltage output end VOUT of the LDO circuit 10 is in a stable state. In this way, the currents transmitted by the current amplification module 1032 to the first input end IN1 and the second input end IN2 of the common-source common-gate tube module are equal in the case that the voltage output end VOUT of the LDO circuit 10 is in a stable state, so as to avoid the occurrence of a misadjustment current and affect the circuit performance.

[0053] In an optional implementation manner, as shown in Figure 5 The first current amplifier Q1 is a first transistor Q1, and the second current amplifier Q2 is a second transistor Q2. Optionally, the first transistor Q1 and the second transistor Q2 are both NPN transistors.

[0054] The base of the first transistor Q1 is connected with the current conversion module 1031. The base of the first transistor Q1 is also configured to receive a bias voltage of the first transistor Q1. The emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected with the first input end IN1. The base of the second transistor Q2 is configured to receive a bias voltage of the second transistor Q2. The emitter of the second transistor Q2 is grounded. The collector of the second transistor Q2 is connected with the second input end IN2.

[0055] The first transistor Q1 is configured to amplify the sampling current I transmitted by the current conversion module 1031 to obtain an amplified sampling current I. In addition, the amplified sampling current I is output from the collector of the first transistor Q1. Therefore, the amplified sampling current I can also be represented as Ic. The amplified sampling current I satisfies the formula: I = β × Ib. In the formula, I represents the amplified sampling current I. β is the current amplification factor of the first transistor Q1. Ib represents the sampling current I output by the current conversion module 1031, i.e., the sampling current before amplification. The second transistor Q2 is configured to amplify the bias voltage corresponding current to obtain a matching current, and transmit the matching current to the second input IN2 of the common-source common-gate tube module.

[0056] Further optionally, the current amplification module 1032 further includes a first resistor R1 and a second resistor R2. The base of the first transistor Q1 is connected with the current conversion module 1031. The base of the first transistor Q1 is also connected with the first bias voltage terminal VB1 through the first resistor R1. The emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected with the first input IN1 of the common-source common-gate tube module. The base of the second transistor Q2 is connected with the first bias voltage terminal VB1 through the second resistor R2. The emitter of the second transistor Q2 is grounded. The collector of the second transistor Q2 is connected with the second input IN2 of the common-source common-gate tube module.

[0057] The first bias voltage terminal VB1 is configured to provide the bias voltage Vb1 of the first transistor Q1 and the second transistor Q2. The first resistor R1 and the second resistor R2 are configured as current limiting resistors to limit the current flowing into the second transistor Q2. In this way, the sampling current I transmitted by the current conversion module 1031 is blocked by the first resistor R1 and the second resistor R2, and mainly flows to the base of the first transistor Q1, so that the collector of the first transistor Q1 outputs the amplified sampling current I. The second transistor Q2 does not receive additional sampling current I, so that the current at the base of the second transistor Q2 is almost unchanged, and the output current at the collector of the second transistor Q2 is also almost unchanged.

[0058] In the embodiment of the present application, the voltage sampling circuit 104 is configured to transmit the feedback voltage Vfb corresponding to the voltage output VOUT to the error amplifier 101. Optionally, as shown in FIG. 1, the voltage sampling circuit 104 includes a voltage sampling resistor R3. The voltage sampling resistor R3 is connected between the voltage output VOUT and the error amplifier 101. The voltage sampling resistor R3 is configured to sample the voltage output VOUT to obtain the feedback voltage Vfb, and transmit the feedback voltage Vfb to the error amplifier 101. Figure 5As shown, the voltage sampling circuit 104 includes a third resistor Rfb1 and a fourth resistor Rfb2. One end of the third resistor Rfb1 is connected to the voltage output terminal VOUT, and the other end of the third resistor Rfb1 is grounded through the fourth resistor Rfb2. The third resistor Rfb1 and the fourth resistor Rfb2 are used to collect the output voltage Vout of the voltage output terminal VOUT, and are proportionally converted into the feedback voltage Vfb according to the resistance values of the third resistor Rfb1 and the fourth resistor Rfb2, and transmit the feedback voltage Vfb to the error amplifier 101.

[0059] In an alternative case, the error amplifier 101 further includes a differential input tube module, a tail current source tube, a power input tube module, and a load tube module.

[0060] The differential input tube module is connected to the voltage sampling module 104, the tail current source tube, the power input tube module, and the first input terminal IN1 and the second input terminal IN2 of the common-source common-gate tube module. The tail current source tube is connected to the voltage input terminal VIN of the LDO circuit 10. The power input tube module is connected to the first input terminal IN1 and the second input terminal IN2 of the common-source common-gate tube module, and the power input tube module is grounded. The common-source common-gate tube module is further connected to the load tube module and the control terminal of the output power tube 102. The load tube module is further connected to the voltage input terminal VIN.

[0061] The voltage output node of the error amplifier 101 is located between the common-source common-gate tube module and the load tube module. The common-source common-gate tube module is used to extract the amplified sampling current I output by the current amplification module 1032, and transmit the sampling current I to the load tube module, so that the load tube module positively regulates the error amplification voltage Vc.

[0062] Further alternatively, as shown, Figure 5 The differential input tube module includes a first power tube M1 and a second power tube M2. The power input tube module includes a third power tube M3 and a fourth power tube M4. The common-source common-gate tube module includes a fifth power tube M5 and a sixth power tube M6. The load tube module includes a seventh power tube M7 and an eighth power tube M8. That is, the error amplifier 101 includes the first power tube M1 to the eighth power tube M8 and the tail current source tube (the ninth power tube) M9.

[0063] The gate of the first power transistor M1 is connected to the voltage sampling circuit 104. The drain of the first power transistor M1 is connected to the source of the sixth power transistor M6 and the drain of the fourth power transistor M4. The source of the first power transistor M1 is connected to the source of the second power transistor M2 and the drain of the tail current source transistor M9. The gate of the second power transistor M2 is used to receive the reference voltage Vref of the error amplifier 101. The drain of the second power transistor M2 is connected to the source of the fifth power transistor M5 and the drain of the third power transistor M3. The source of the third power transistor M3 and the source of the fourth power transistor M4 are grounded. The gate of the third power transistor M3 is connected to the gate of the fourth power transistor M4 and the second bias voltage terminal VB2. The drain of the fifth power transistor M5 is connected to the drain of the seventh power transistor M7 and the control terminal of the output power transistor 102. The gate of the fifth power transistor M5 is connected to the gate of the sixth power transistor M6 and the third bias voltage terminal VB3. The drain of the sixth power transistor M6 is connected to the drain of the eighth power transistor M8, the gate of the eighth power transistor M8, and the gate of the seventh power transistor M7, respectively. The sources of the seventh power transistor M7 and the eighth power transistor M8 are connected to the voltage input terminal VIN of the LDO circuit 10. The source of the tail current source transistor M9 is connected to the voltage input terminal VIN. The gate of the tail current source transistor M9 is connected to the fourth bias voltage terminal VB4.

[0064] In this configuration, the first input terminal IN1 of the cascode module is the source of the sixth transistor M6. The second input terminal IN2 of the cascode module is the source of the fifth transistor M5. The second bias voltage terminal VB2 provides the bias voltage Vb2 for the third power transistor M3 and the fourth power transistor M4. The third bias power supply terminal VB3 provides the bias voltage Vb3 for the fifth power transistor M5 and the sixth power transistor M6. The fourth bias voltage terminal VB4 provides the bias voltage Vb4 for the tail current source transistor M9. Optionally, the first power transistor M1, the second power transistor M2, the seventh power transistor M7, the eighth power transistor M8, and the ninth power transistor M9 are PMOS transistors. The third power transistor M3, the fourth power transistor M4, the fifth power transistor M5, and the sixth power transistor M6 are NMOS transistors. For example, the gate of the first power transistor M1 is connected to the feedback node VFB of the voltage sampling circuit 104. The feedback node VFB is located in the path between the third resistor Rfb1 and the fourth resistor Rfb2 of the voltage sampling circuit 104.

[0065] Optionally, such as Figure 5 As shown, the current conversion module 1031 may include a sampling capacitor C. The sampling capacitor C is used to convert the output voltage Vout of the voltage output terminal VOUT into a sampling current I, which is then transmitted to the error amplifier 101. The sampling current I satisfies the formula: I = C × dV / dt. In this formula, C represents the capacitance value of the sampling capacitor C, dV represents the change in output voltage Vout, and dt represents the time of change of output voltage Vout.

[0066] Optionally, as shown in Figure 5 The LDO circuit 10 further comprises a compensation capacitor Cc. One end of the compensation capacitor Cc is connected with the second input end IN2 of the cascode module, and the other end of the compensation capacitor Cc is connected with the voltage output end VOUT. The compensation capacitor Cc is used for leading compensation of the cascode module, so as to cut off the feedforward path of the error amplifier 101 and maintain the stability of the circuit.

[0067] Optionally, please continue to refer to Figure 5 The LDO circuit 10 further comprises a load capacitor Cload and an equivalent series resistance ESR. One end of the equivalent series resistance ESR is connected with the voltage output end VOUT. The other end of the equivalent series resistance ESR is grounded through the load capacitor Cload.

[0068] For example, taking the LDO circuit shown in Figure 5 as an example, the working principle of the LDO circuit provided by the embodiment of the present application can be described again.

[0069] In the case that the load current of the LDO circuit 10 jumps down, for example, from 15 mA to 500 uA, the output voltage of the LDO circuit 10 will be temporarily raised, and an overshoot phenomenon will occur, generating an overshoot voltage. The sampling capacitor C converts the overshoot voltage into an increased sampling current I, which is an alternating current.

[0070] Due to the current limiting effect of the first resistor R1 and the second resistor R2, the sampling current I transmitted by the sampling capacitor C mainly flows to the base of the first transistor Q1, so that the collector of the first transistor Q1 outputs the amplified sampling current I to the source of the sixth power transistor M6. The current at the base of the second transistor Q2 is almost unchanged, and the output current at the collector of the second transistor Q2 is almost unchanged, so that the matching current of the second input end IN2 and the first input end IN1 of the output cascode module is maintained.

[0071] The sampling current I flows into the source of the sixth power transistor M6 (i.e. the folding point of the Fold-cascode structure LDO circuit), and is transmitted to the gate and drain of the eighth power transistor M8 through the drain of the sixth power transistor M6, so that the drain of the eighth transistor M8 increases the sampling current I on the basis of the input voltage.

[0072] The drain of the eighth transistor M8 is connected to the gate of the eighth transistor M8 and the gate of the seventh transistor M7. At this time, the voltage of the gate of the eighth power transistor M8 will instantaneously increase by a target value. The target value is I / Cg. Where Cg represents the parasitic capacitance of the gate of the eighth power transistor M8. I represents the amplified sampling current transmitted by the first transistor Q1. That is, the gate-source voltage Vgs of the seventh power transistor M7 and the eighth power transistor M8 will instantaneously increase by a target voltage dVgs. The target voltage dVg satisfies: dVgs≈[2I / (μ×Cox×W / L)]1 / 2+Vthp. Where I represents the amplified sampling current transmitted by the first transistor Q1. μ represents the mobility of the seventh power transistor M7 and the eighth power transistor M8. Cox represents the unit capacitance of the gate oxide layer of the seventh power transistor M7 and the eighth power transistor M8. W / L represents the width-length ratio of the seventh power transistor M7 and the eighth power transistor M8. Vthp is the threshold voltage of the seventh power transistor M7 and the eighth power transistor M8.

[0073] The sampling current I causes the gate-source voltage of the seventh power transistor M7 to increase, the on-resistance of the seventh power transistor M7 to decrease, and the voltage of the drain of the seventh power transistor M7 to instantaneously increase, that is, the error amplification voltage Vc transmitted to the output power transistor M10 instantaneously increases, and the output power transistor M10 turns off. The output power transistor 102 stops providing the output voltage to the voltage output end VOUT, so that the output voltage of the LDO circuit 10 rapidly decreases, the overshoot rapidly decreases, and the influence of the output voltage overshoot is weakened.

[0074] As the output voltage of the LDO circuit 10 gradually decreases, the sampling current I collected by the capacitor C gradually decreases. The sampling current I transmitted by the first transistor Q1 to the sixth power transistor M6 decreases. The gate-source voltage of the seventh power transistor M7 decreases, the on-resistance of the seventh power transistor M7 increases, and the voltage of the drain of the seventh power transistor M7 decreases. That is, the error amplification voltage Vc transmitted to the output power transistor M10 decreases, the output power transistor M10 turns on, and the output power transistor 102 provides the output voltage to the voltage output end Vout.

[0075] After the output voltage of the LDO circuit 10 is in a stable state, the sampling current I collected by the sampling capacitor C is in a stable state, and the sampling current I transmitted by the first transistor Q1 to the sixth power transistor M6 is in a stable state. The gate-source voltage of the seventh power transistor M7 is stable, the on-resistance of the seventh power transistor M7 is stable, and the voltage of the drain of the seventh power transistor M7 is stable. That is, the error amplification voltage Vc transmitted to the output power transistor M10 is stable, and the output power transistor 102 provides a stable output voltage to the voltage output end Vout.

[0076] Similarly, in the case of a load current jump up, for example, from 500uA to 15mA, the output voltage of the LDO circuit 10 will be pulled down momentarily, and a undershoot voltage will be generated. The sampling capacitor C converts the undershoot voltage into a reduced sampling current I.

[0077] The first transistor Q1 amplifies the sampling current I received by its base, and outputs the amplified sampling current I to the source of the sixth power transistor M6 through the collector. The sampling current I flows into the source of the sixth power transistor M6, and is transmitted to the gate and drain of the eighth power transistor M8 through the drain of the sixth power transistor M6, so that the voltage of the drain of the eighth transistor M8 is reduced compared to the stable state of the LDO circuit 10.

[0078] The drain of the eighth transistor M8 is connected to the gate of the eighth transistor M8 and the gate of the seventh transistor M7. The sampling current I reduces the gate-source voltage of the seventh power transistor M7, increases the on-resistance of the seventh power transistor M7, and reduces the voltage of the drain of the seventh power transistor M7, that is, the error amplification voltage Vc transmitted to the output power transistor M10 is reduced, and the on-resistance of the power adjustment transistor M10 is reduced. The output power transistor 102 provides an increased output voltage to the voltage output end Vout, so that the output voltage of the LDO circuit 10 increases rapidly, the undershoot decreases rapidly, the impact of the output voltage undershoot is weakened, and the load transient response capability is improved.

[0079] As the output voltage of the LDO circuit 10 gradually increases, the sampling current I collected by the capacitor C gradually increases. The sampling current I transmitted to the sixth power transistor M6 by the first transistor Q1 increases. The gate-source voltage of the seventh power transistor M7 increases, the on-resistance of the seventh power transistor M7 decreases, and the voltage of the drain of the seventh power transistor M7 increases. That is, the error amplification voltage Vc transmitted to the output power transistor M10 increases, the on-resistance of the power adjustment transistor M10 increases, the output power transistor 102 provides a reduced output voltage to the voltage output end Vout, and the output voltage of the LDO circuit 10 is stable.

[0080] In summary, the LDO circuit provided by the embodiment of the present application comprises: a voltage sampling circuit, an output power transistor, an error amplifier, and a current sampling circuit. The voltage sampling circuit is configured to transmit a feedback voltage corresponding to a voltage output end of the LDO circuit to the error amplifier. The error amplifier is configured to generate an error amplification voltage according to a reference voltage and the feedback voltage, and transmit the error amplification voltage to the output power transistor. The output power transistor is configured to convert an input voltage of the LDO circuit into an output voltage under the control of the error amplification voltage, and transmit the output voltage to the voltage output end. The current sampling circuit is configured to convert the output voltage into a sampling current, and transmit the sampling current to the error amplifier. The error amplifier is further configured to positively adjust the error amplification voltage according to the sampling current.

[0081] In the technical solution, the current sampling circuit can convert the size change of the output voltage into the size change of the sampling current, so that the error amplifier generates the error amplification voltage that changes in the positive direction with the current. In this way, when the load of the LDO circuit jumps downward and the output voltage overshoots, the current sampling circuit can collect the increased sampling current, so that the error amplifier generates the increased error amplification voltage, controls the on-resistance of the output power transistor to be increased, rapidly reduces the output voltage transmitted by the output power transistor to the voltage output terminal, reduces the overshoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. Similarly, when the load of the LDO circuit jumps upward and the output voltage undershoots, the current sampling circuit can collect the decreased sampling current, so that the error amplifier generates the decreased error amplification voltage, controls the on-resistance of the output power transistor to be decreased, rapidly increases the output voltage transmitted by the output power transistor to the voltage output terminal, reduces the undershoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. In addition, the LDO circuit provided by the embodiment of the present application also has the characteristics of easy implementation, good robustness, small circuit area, and the like.

[0082] The embodiment of the present application also provides a power supply. The power supply can include the LDO circuit provided by the embodiment of the present application. Alternatively, the power supply can include the LDO circuit shown in Figure 3 , Figure 4 or Figure 5 . The power supply includes the LDO circuit described above, and thus has the same technical effects as the LDO circuit described above. To avoid repetition, details are not described here.

[0083] The embodiment of the present application also provides an electronic device. The electronic device includes the LDO circuit provided by the embodiment of the present application, or includes the power supply provided by the embodiment of the present application. The electronic device includes the LDO circuit described above, and thus has the same technical effects as the LDO circuit described above. To avoid repetition, details are not described here.

[0084] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the specific embodiments described above, which are only illustrative rather than limiting. Those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the protection scope of the claims, which all belong to the protection scope of the present application.

Claims

1. A low-dropout linear regulator (LDO) circuit, comprising: The LDO circuit comprises a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit; The voltage sampling circuit is connected with a voltage output end of the LDO circuit and the error amplifier, and is configured to transmit a feedback voltage corresponding to the voltage output end to the error amplifier; The current sampling circuit is connected with the error amplifier and the voltage output end, and is configured to convert an output voltage of the voltage output end into a sampling current and transmit the sampling current to the error amplifier; The error amplifier is connected with the output power tube, and is configured to adjust an error amplification voltage of the feedback voltage and a reference voltage in a positive direction according to the sampling current and transmit the error amplification voltage to the output power tube; The output power tube is connected with the voltage output end, and is configured to convert an input voltage into the output voltage under control of the error amplification voltage and transmit the output voltage to the voltage output end, The current sampling circuit comprises a current conversion module and a current amplification module; The current conversion module is connected with the voltage output end and the current amplification module, and is configured to convert the output voltage into the sampling current and transmit the sampling current to the current amplification module; The current amplification module is connected with the error amplifier, and is configured to amplify the sampling current and transmit the amplified sampling current to the error amplifier, The error amplifier has a folded common-source common-gate structure; and the current amplification module comprises a first current amplifier and a second current amplifier; The first current amplifier is connected with the current conversion module and a first input end of a common-source common-gate tube module of the error amplifier, and is configured to amplify the sampling current and transmit the amplified sampling current to the first input end; The second current amplifier is connected with a second input end of the common-source common-gate tube module, and is configured to provide a matching current between the second input end and the first input end.

2. The LDO circuit of claim 1, wherein, The current conversion module comprises a sampling capacitor, which is configured to convert the output voltage into the sampling current and transmit the sampling current to the error amplifier.

3. The LDO circuit of claim 1, wherein, The first current amplifier is a first transistor, and the second current amplifier is a second transistor; A base of the first transistor is connected with the current conversion module, the base of the first transistor is also configured to receive a bias voltage of the first transistor, an emitter of the first transistor is grounded, and a collector of the first transistor is connected with the first input end; A base of the second transistor is configured to receive a bias voltage of the second transistor, an emitter of the second transistor is grounded, and a collector of the second transistor is connected with the second input end.

4. The LDO circuit of claim 3, wherein, The current amplification module further comprises a first resistor and a second resistor; The base of the first transistor is further connected with a first bias voltage end through the first resistor, the base of the second transistor is connected with the first bias voltage end through the second resistor, and the first bias voltage end is configured to provide the bias voltage of the first transistor and the second transistor.

5. The LDO circuit of claim 1, wherein, The error amplifier further comprises a differential input tube module, a tail current source tube, a power input tube module and a load tube module; The differential input tube module is connected with the voltage sampling module, the tail current source tube, the power input tube module and the first input end and the second input end of the common source common gate tube module, the tail current source tube is connected with the voltage input end of the LDO circuit, the power input tube module is connected with the first input end and the second input end of the common source common gate tube module, and the power input tube module is grounded, the common source common gate tube module is further connected with the load tube module and the control end of the output power tube, the load tube module is further connected with the voltage input end, and the voltage input end is used for providing the input voltage.

6. The LDO circuit of claim 5, wherein, The differential input tube module comprises a first power tube and a second power tube, the power input tube module comprises a third power tube and a fourth power tube, the common source common gate tube module comprises a fifth power tube and a sixth power tube, and the load tube module comprises a seventh power tube and an eighth power tube, The gate of the first power tube is connected with the voltage sampling circuit, the drain of the first power tube is connected with the source of the sixth power tube and the drain of the fourth power tube, and the source of the first power tube is connected with the source of the second power tube and the drain of the tail current source tube; the gate of the second power tube is used for receiving the reference voltage of the error amplifier, and the drain of the second power tube is connected with the source of the fifth power tube and the drain of the third power tube; The source of the third power tube and the source of the fourth power tube are grounded, the gate of the third power tube is connected with the gate of the fourth power tube and a second bias voltage end, the drain of the fifth power tube is connected with the drain of the seventh power tube and the control end of the output power tube, the gate of the fifth power tube is connected with the gate of the sixth power tube and a third bias voltage end, the drain of the sixth power tube is connected with the drain, the gate of the eighth power tube and the gate of the seventh power tube respectively, the source of the seventh power tube and the source of the eighth power tube are connected with the voltage input end, the source of the tail current source tube is connected with the voltage input end, and the gate of the tail current source tube is connected with a fourth bias voltage end; The first input end of the common source common gate tube module is the source of the sixth power tube, and the second input end is the source of the fifth power tube.

7. A power supply, characterized by The power supply comprises the low dropout linear regulator (LDO) circuit of any one of claims 1 to 6.

8. An electronic device, comprising: The electronic device comprises the low dropout linear regulator (LDO) circuit of any one of claims 1 to 6, or the power supply of claim 7.

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