Memory unloading transaction acceleration device, system and method and storage medium

Abstract

The embodiment of the invention provides a memory unloading transaction acceleration device, system and method and a storage medium, and belongs to the technical field of data processing, the device comprises an acceleration unit used for receiving a write transaction sent by a processor core, and the acceleration unit is provided with a cache interface and a non-cache interface; the acceleration interconnection component adopts a target shared access mode, and the acceleration interconnection component processes one write transaction every time in the target shared access mode; when the acceleration interconnection component currently processes the write transaction of the cache data sent by the cache interface, the write transaction operation of the cache data is initiated to the cache consistency control component so as to write the cache data into the cache; and when the acceleration interconnection component currently processes the write transaction of the non-cache data sent by the non-cache interface, initiating the write transaction operation of the cache data to the controller memory interconnection component so as to write the non-cache data into the memory. The embodiment of the invention aims at avoiding the deadlock problem occurring in the memory transaction processing process.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of data processing, and in particular, to an offload memory transaction acceleration device, system, method, and storage medium. Background Art

[0002] With the development of data processing technology, the demand for data storage is gradually increasing. Currently, a multi-core architecture is used to increase the concurrent processing capability of the system, such as using multiple central processing units (CPUs) to improve the energy utilization of the storage system. When the CPU performs memory operations on the memory, if traditional direct memory read or write operations are used, it will cause large blockages and delays, thereby reducing the CPU's computing power. At present, there is a way to use hardware acceleration units to offload memory read and write transaction operations, which can reduce the CPU's waiting time and burden, and accelerate the data processing and transmission process.

[0003] In order to solve the problem of maintaining cache consistency in multi-core processing applications, ARM launched the AXI4 bus protocol and ACE bus protocol and components such as corresponding cache consistency controllers to achieve cache consistency. However, when the hardware acceleration unit is applied at the same time, the cache consistency controller and the hardware acceleration unit may use the AXI bus components to access memory resources at the same time, causing conflicts between the operations of the two and prone to deadlock problems. Summary of the invention

[0004] Embodiments of the present application provide an offload memory transaction acceleration device, system, method, and storage medium, which are intended to avoid deadlock problems that occur during memory transaction processing.

[0005] In a first aspect, an embodiment of the present application provides an offload memory transaction acceleration device, which is applied to a system on chip, wherein the system on chip includes a processor core, a cache coherence control component, and a controller memory interconnect component, and the device includes an acceleration unit and an acceleration interconnect component, wherein:

[0006] The acceleration unit is used to receive write transactions sent by the processor core. The acceleration unit is provided with a cache interface and a non-cache interface. The cache interface is used to receive write transactions of cached data sent by the processor core, and the non-cache interface is used to receive write transactions of non-cache data sent by the processor core.

[0007] The acceleration interconnect component adopts a target shared access mode, in which the acceleration interconnect component processes one write transaction at a time;

[0008] When the acceleration interconnect component is currently processing a write transaction of cache data sent by the cache interface, initiating a write transaction operation of the cache data to the cache consistency control component to write the cache data into the cache;

[0009] When the acceleration interconnect component currently processes a write transaction of non-cached data sent by the non-cached interface, a write transaction operation of cached data is initiated to the controller memory interconnect component to write the non-cached data into the memory.

[0010] Optionally, when the acceleration interconnect component initiates a write transaction operation of cache data to the cache consistency control component, if the cache is full, the cache consistency control component initiates a memory consistency operation and sends a pause message to the acceleration interconnect component;

[0011] The acceleration interconnect component is used to suspend processing of any write transaction in response to the suspension information;

[0012] Wherein, when executing the memory consistency operation, the cache consistency control component is used to send the eliminated data in the cache to the controller memory interconnect component and write the eliminated data into the memory.

[0013] Optionally, a cache data queue and a non-cache data queue are provided in the acceleration interconnect component, and both the cache data queue and the non-cache data queue are first-in-first-out queues. The cache data queue is used to store write transactions of cache data sent by the cache interface, and the non-cache data queue is used to store write transactions of non-cache data sent by the non-cache interface.

[0014] The acceleration interconnect component is used to select a write transaction in the cache data queue or the non-cache data queue for processing each time.

[0015] Optionally, the acceleration interconnect component is used to poll the cache data queue or the non-cache data queue to select a write transaction for processing each time.

[0016] Optionally, different priorities are set for the cache data queue or the non-cached data queue, and the acceleration interconnect component is used to obtain a write transaction from the queue with a high priority for processing each time until the queue with a high priority does not contain any write transactions, and then obtain a write transaction from the queue with a low priority for processing.

[0017] Optionally, any write transaction of cached data or non-cached data includes a write address transaction and a write data transaction;

[0018] The acceleration interconnect component includes a write address transaction processor and a write data transaction processor;

[0019] When the write address transaction processor and the write data transaction processor determine that the currently processed transaction is a write transaction of non-cached data, the acceleration interconnect component is used to send the address information and data information of the non-cached data to the controller memory interconnect component, and the controller memory interconnect component is used to write the data information of the non-cached data into the location corresponding to the address of the non-cached data in the memory;

[0020] When the write address transaction processor and the write data transaction processor determine that the currently processed transaction is a write transaction of cache data, the acceleration interconnect component is used to send the address information and data information of the cache data to the cache consistency control component;

[0021] If the target cache in the multi-level cache corresponding to the address information of the cache data is not full, the cache controller in the cache coherence control component is used to write the data information of the cache data into the position corresponding to the address information of the cache data;

[0022] If the target cache in the multi-level cache corresponding to the address information of the cache data is full, the cache controller in the cache consistency control component is used to determine the eliminated data in the target cache, send the eliminated data to the controller memory interconnect component, write the eliminated data into the memory, and send a pause message to the acceleration interconnect component;

[0023] The acceleration interconnect component is used for suspending processing of any write transaction in response to the suspension information.

[0024] Optionally, when the acceleration interconnect component suspends processing of any write transaction, if the acceleration interconnect component receives continue processing information sent by the cache consistency control component, the acceleration interconnect component is used to respond to the continue processing information and continue processing any write transaction.

[0025] In a second aspect, an embodiment of the present application provides a system on chip, which includes a processor core, a cache consistency control component and a controller memory interconnect component, and the system on chip also includes the offload memory transaction acceleration device described in the first aspect of the embodiment.

[0026] In a third aspect, an embodiment of the present application provides a memory transaction processing method, which is applied to the system on chip described in the second aspect of the embodiment, and the method further includes:

[0027] In response to a write transaction processing instruction of any processor, determining to send the write transaction to a cache interface or a non-cache interface of an acceleration unit according to a data type corresponding to the write transaction;

[0028] The acceleration interconnect component determines a write transaction currently being processed, and when the write transaction currently being processed is a write transaction of cached data, initiates a write transaction operation of cached data to the cache consistency control component; when the write transaction currently being processed is a write transaction of non-cached data, initiates a write transaction operation of cached data to the controller memory interconnect component, so as to write the non-cached data into the memory;

[0029] When the cache of the system on chip is full, the cache coherence control component initiates a memory coherence operation and sends a pause message to the acceleration interconnect component;

[0030] The acceleration interconnect component suspends processing of any write transaction in response to the suspension information.

[0031] In a fourth aspect, an embodiment of the present application provides a non-volatile readable storage medium, wherein the non-volatile readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the memory transaction processing method described in the third aspect of the embodiment is executed.

[0032] Beneficial effects:

[0033] The offload memory transaction acceleration device provided in this embodiment is applied to a system on chip, wherein the system on chip includes a processor core, a cache consistency control component, and a controller memory interconnect component, and the device includes an acceleration unit and an acceleration interconnect component.

[0034] The acceleration unit includes a cache interface and a non-cache interface, the cache interface is used to receive write transactions of cached data sent by the processor core, and the non-cache interface is used to receive write transactions of non-cache data sent by the processor core; the acceleration interconnect component adopts a target shared access mode, in which the acceleration interconnect component processes one write transaction at a time.

[0035] When the acceleration interconnect component is currently processing a write transaction of cache data sent by the cache interface, a write transaction operation of cache data is initiated to the cache consistency control component to write the cache data into the cache; when the acceleration interconnect component is currently processing a write transaction of non-cached data sent by the non-cache interface, a write transaction operation of cache data is initiated to the controller memory interconnect component to write the non-cached data into the memory.

[0036] Then, the data that needs to be written into the cache or does not need to be written into the cache is classified and the write transaction is processed. In the target shared access mode, the acceleration interconnect component can only process one unfinished write transaction at a time. Therefore, there will be no conflict in the write transaction processing of cached data and non-cached data, avoiding deadlock problems in the memory transaction processing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art.

[0038] Figure 1 A functional module diagram of an offload memory transaction acceleration device provided in an embodiment of the present application is shown;

[0039] Figure 2 A schematic diagram of the architecture of a system on a chip provided by an embodiment of the present application is shown;

[0040] Figure 3 A flowchart showing the steps of the memory transaction processing method provided by an embodiment of the present application is shown;

[0041] Figure 4 A schematic diagram of a non-volatile readable storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0043] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in each embodiment of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not constitute any limitation, and the various embodiments can be combined with each other and referenced to each other without contradiction.

[0044] SSD: Solid State Disk, solid state drive;

[0045] CPU: Central Processing Unit, central processing unit;

[0046] SOC: System on Chip, system on chip;

[0047] AXI: Advanced Xtensible Interface, an advanced extensible on-chip bus for high performance, high bandwidth, and low latency;

[0048] ACE: AXI Coherency Extensions, AXI consistency extension;

[0049] CCI: Cache Coherent Interconnect, cache consistency control component

[0050] CMUIC: Controller Memory Unit Interconnect Controller, controller memory interconnect component;

[0051] DDR / SRAM: Double Data Rate, Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory;

[0052] ME: MoveEngine, acceleration unit;

[0053] ACC: Acceleration Module, uninstall memory transaction acceleration device.

[0054] With the development of data processing technology, the demand for data storage is gradually increasing. Currently, multi-core architecture is used to increase the concurrent processing capability of the system, such as using multiple CPUs to improve the energy utilization of the storage system. When the CPU performs memory operations on the memory, if traditional direct memory read or write operations are used, large blocking and delays will occur, thereby reducing the CPU's computing power. The use of hardware acceleration units to offload memory read and write transaction operations can reduce the CPU's waiting time and burden, and accelerate the data processing and transmission process.

[0055] The hardware acceleration unit can perform memory consistency (coherent) and memory non-coherent (non-coherent) operations on the memory at the same time. When the hardware acceleration unit performs memory consistency operations, it will pass through the cache. The cache is managed and maintained by the cache controller. When the data in the cache is full, the cache will simultaneously perform data invalidation operations, refresh part of the cache data to the memory, and complete the action of deleting the part of the data in the cache.

[0056] At present, in order to solve the problem of maintaining cache consistency in multi-core processing scenarios of system-on-chip applications, ARM has launched the AXI4 bus protocol and ACE bus protocol as well as methods to achieve cache consistency based on corresponding components such as cache consistency controllers. However, if hardware acceleration units continue to be used in scenarios where cache consistency is achieved based on components such as cache consistency controllers, the cache consistency controller and the hardware acceleration unit may use components of the AXI bus to access the memory at the same time, and the operations of the two may conflict with each other, which may easily lead to deadlock problems.

[0057] Therefore, in order to avoid the deadlock problem that occurs during the memory transaction processing, an embodiment of the present application provides an offload memory transaction acceleration device.

[0058] Reference Figure 1 , showing a functional module diagram of an offload memory transaction acceleration device provided in an embodiment of the present application, the device includes an acceleration unit and an acceleration interconnection component, the acceleration unit is denoted as ME, the acceleration unit is used to receive write transactions sent by the processor core, the acceleration unit is provided with a cache interface and a non-cache interface, the cache interface is used to receive write transactions of cached data sent by the processor core, and the non-cache interface is used to receive write transactions of non-cache data sent by the processor core.

[0059] In a feasible implementation, the acceleration interconnect component may be an ACE-Lite interconnect component based on the ACE-Lite protocol. The target shared access mode adopted by the ACE-Lite interconnect component may be an N-to-M shared access mode. In the N-to-M shared access mode, the acceleration interconnect component, i.e., the ACE-Lite interconnect component, processes one write transaction at a time.

[0060] The offload memory transaction acceleration device described in this embodiment is applied to a system on chip (SOC), which includes multiple processor cores, a cache consistency control component, a controller memory interconnect component, and a memory DDR.

[0061] Reference Figure 2 , showing a schematic diagram of the architecture of the system on chip provided by an embodiment of the present application, the SOC includes multiple processor cores, such as CPU-0...CPU-x, CPU-N, and multiple CPU cores can improve the concurrent processing capability of the system on chip; the ARM system of the SOC includes a cache and a cache consistency control component, the cache consistency control component is used to connect the CPU core, ME and memory DDR to ensure cache consistency across different components, the cache consistency control component also includes a cache controller, the cache controller is used to read and write data and invalidate the cache; the controller memory interconnect component is used to write data sent by the cache controller and non-cached data sent by the acceleration interconnect component into the memory, and the controller memory interconnect component includes an AXI connection component.

[0062] AXI is an advanced scalable on-chip bus defined by ARM for high performance, high bandwidth and low latency. AXI defines five independent channels between the host and the slave: write address channel, write data channel, write response channel, read address channel and read data channel. The address channel is used to send address and control information when performing basic handshake between the host and the slave; the data channel is used for the host to write data to the slave and for the slave to read data from the host; the write response information has a dedicated channel so that the host can verify whether the write transaction has been completed; each data exchange is called a transaction, which includes address and control information, sent data, and any response information.

[0063] The device sets two API interfaces in the acceleration unit: non-cached interface API1 and cached interface API2, and uses the two API interfaces as AXI master devices. When receiving a write transaction of data sent by any CPU core, it sends the data to the corresponding API interface according to whether the data is cached data that needs to be written to the cache or non-cached data that is directly written to the memory; the non-cached interface API1 and the cached interface API2 send the write transaction of the data to the acceleration interconnection component.

[0064] In this embodiment, the acceleration interconnect component is an ACE-Lite interconnect component based on the N-to-M shared access mode. In the N-to-M shared access mode, the ACE-Lite interconnect component processes one write transaction at a time. For each connected master device (non-cache interface AP1 and cache interface API2), the arbitrator of the ACE-Lite interconnect component selects a write transaction from the requesting master device for processing. After the data transmission is completed, arbitration for the next request will be performed, and then the next write transaction will be executed.

[0065] In a feasible implementation, in order to store write transactions sent by the two interfaces of the acceleration unit, a cache data queue and a non-cache data queue are provided in the acceleration interconnect component, and both the cache data queue and the non-cache data queue are first-in-first-out queues. The cache data queue is used to store write transactions of cache data sent by the cache interface, and the non-cache data queue is used to store write transactions of non-cache data sent by the non-cache interface; the acceleration interconnect component is used to select a write transaction from the cache data queue or the non-cache data queue for processing each time.

[0066] For example, the acceleration interconnect component can poll the cache data queue or the non-cache data queue to select a write transaction for processing each time, that is, obtain a write transaction in the cache data queue for processing, and then obtain a write transaction in the non-cache data queue for processing, and process the write transactions of the two data types in a cycle.

[0067] In actual implementation, different priorities can also be set for the cache data queue or the non-cached data queue, and the acceleration interconnect component is used to obtain a write transaction from the high-priority queue for processing each time until the high-priority queue does not contain any write transactions, and then obtain a write transaction from the low-priority queue for processing.

[0068] For example, the data in the cache is data that is processed more frequently, so the write transactions entering the cache can be processed first, and the priority of the cache data queue can be set to a high priority. Writing data to the memory can be slightly delayed compared to writing data to the cache, so the priority of the non-cache data queue can be set to a low priority.

[0069] When there are pending write transactions in the cache data queue, the acceleration interconnect component prioritizes processing the pending write transactions in the cache data queue one by one until the cache data queue contains no write transactions. The acceleration interconnect component obtains pending write transactions from the non-cache data queue and processes them one by one. When a new write transaction is detected in the cache data queue, the acceleration interconnect component can jump to execute the new write transaction added to the cache data queue.

[0070] In another feasible implementation, a continuous processing times threshold may be set. When the number of times the acceleration interconnect component continuously processes write transactions in the cache data queue is greater than the first continuous processing times threshold, the write transactions in the non-cache data queue may be processed. When the number of times the acceleration interconnect component continuously processes write transactions in the non-cache data queue is greater than the second continuous processing times threshold, the write transactions in the cache data queue continue to be processed, thereby avoiding the problem of a long waiting time for write transactions in any data queue.

[0071] In actual application, the arbitration method for the acceleration interconnect component to obtain write transactions in the cache data queue or the non-cached data queue for processing can also be customized according to the needs of the actual application.

[0072] When the acceleration interconnect component currently processes a write transaction of cache data sent by the cache interface, a write transaction operation of cache data is initiated to the cache consistency control component to write the cache data into the cache.

[0073] When the acceleration interconnect component currently processes a write transaction of non-cached data sent by the non-cached interface, a write transaction operation of cached data is initiated to the controller memory interconnect component to write the non-cached data into the memory.

[0074] Specifically, any write transaction of cached data or non-cached data includes a write address transaction (Write Address) and a write data transaction (Write Data); the acceleration interconnect component includes a write address transaction processor and a write data transaction processor.

[0075] When the acceleration interconnect component obtains a write transaction from any data queue for processing, it includes obtaining the write address transaction Write Address and the write data transaction Write Data of the write transaction, and then determining the slave device corresponding to the write transaction through the address transaction processor and the write data transaction processor.

[0076] When the write address transaction processor and the write data transaction processor determine that the transaction currently being processed is a write transaction for non-cached data, the ACE-AXI component is used as a slave device, and the address information and data information of the non-cached data are converted by the ACE-AXI component and then sent to the AXI connection component in the controller memory interconnect component through the AXI interface. The controller memory interconnect component is used to write the data information of the non-cached data into the position corresponding to the address of the non-cached data in the memory.

[0077] When the write address transaction processor and the write data transaction processor determine that the currently processed transaction is a write transaction of cache data, the ACE-LS interface of the ARM system is used as a slave device to send the address information and data information of the cache data to the cache consistency control component to write the cache data into the cache.

[0078] When the acceleration interconnect component initiates a write transaction operation of cache data to the cache consistency control component, if the cache is full, the cache needs to remove some eliminated data from itself to free up space to store data information of the write transaction sent by the acceleration interconnect component. The way in which the cache determines the eliminated data can be customized according to the needs of the actual application, such as using the data with the least access frequency as the eliminated data.

[0079] After determining the eliminated data, the cache consistency control component needs to initiate a memory consistency operation, that is, to flush the eliminated data to the memory. At this time, the cache controller in the cache consistency control component occupies the interface of the controller memory interconnection component through AXI-M, and writes the eliminated data into the memory. After the writing is completed, the data information of the cache data sent by the acceleration interconnection component is stored in the position corresponding to the address information of the cache data in the cache.

[0080] Because the cache controller is occupying the interface of the controller memory interconnect component during the process of writing the eliminated data into the memory, a pause message can be sent to the acceleration interconnect component at this time; the acceleration interconnect component is used to respond to the pause message and pause processing of any write transaction to further avoid deadlock problems.

[0081] In a feasible implementation, the cache may also be a multi-level cache, such as a first-level cache L1, a second-level cache L2, and a third-level cache L3. If the target cache in the multi-level cache corresponding to the address information of the cache data is not full, the cache controller in the cache consistency control component is used to write the data information of the cache data to the location corresponding to the address information of the cache data.

[0082] If the target cache in the multi-level cache corresponding to the address information of the cache data is full, the cache controller in the cache consistency control component is used to determine the eliminated data in the target cache, send the eliminated data to the controller memory interconnect component, write the eliminated data into the memory, and send a pause message to the acceleration interconnect component; the acceleration interconnect component is used to respond to the pause message and suspend processing of any write transaction.

[0083] When the acceleration interconnect component suspends processing of any write transaction, if the acceleration interconnect component receives the continue processing information sent by the cache consistency control component, the acceleration interconnect component is used to respond to the continue processing information and continue processing any write transaction.

[0084] An example is given to illustrate the deadlock problem that occurs in the existing cache consistency controller and hardware acceleration unit. Specifically, in the existing acceleration unit, there is only one master device to execute write transactions of cache data and non-cache data, that is, the acceleration unit of one master device performs write transactions of cache data and non-cache data at the same time.

[0085] Assume that at this time, the write transaction processing in the first-in-first-out queue should be write transaction 1 (Write Address1 and Write Data1), write transaction 2 (Write Address2 and Write Data2), and write transaction 3 (Write Address3 and Write Data3), and write transaction 1 and write transaction 3 are for cached data, and write transaction 3 is for non-cached data.

[0086] At this time, when the acceleration unit first initiates write transaction 1 and write transaction 2 of the cached data, Write Address 1 and Write Address 2 are first written to the full cache. Since the speed of writing non-cached data to the memory is faster than the speed of writing eliminated data in the cache to the memory, the acceleration unit initiates write transaction 3 of the non-cached data, that is, the address of WriteAddress 3 has been written to the AXI connection component, and only needs to wait for the Write Data 3 corresponding to write transaction 3.

[0087] The cache needs to perform a data invalidation operation. After writing the eliminated data to the memory, this process needs to occupy the interface of the AXI connection component in the controller memory interconnect component that writes to the memory. However, since the address of Write Address 3 has been written to the AXI connection component at this time, it is waiting for the Write Data 3 corresponding to write transaction 3. That is, because the write transaction 3 acceleration unit has been occupying the AXI interconnect, the eliminated data cannot occupy the interface of the AXI connection component to complete the memory write process.

[0088] As for Write Data3 of write transaction 3, due to the first-in-first-out queue, the data transmission process of sending Write Data3 to the AXI connection component can be carried out only after the data of write transactions 1 and 2, namely Write Data1 and Write Data2, are written into the cache; however, the premise for Write Data1 and Write Data2 to write into the cache is that the eliminated data in the cache is written into the memory, and because the AXI connection component is occupied by the ongoing write transaction 3, the eliminated data cannot complete the operation of writing into the memory, and then Write Data1 and Write Data2 cannot complete the write cache. When Write Data1 and Write Data2 cannot complete the write cache, Write Data3 cannot be processed, thus forming a deadlock.

[0089] In this device, a cache interface and a non-cache interface are set in the acceleration unit as two master devices of AXI, and the acceleration interconnection component adopts N-to-M shared access mode. When two write transactions, writing to cache and writing to memory, are initiated at the same time, the arbitrator of the acceleration interconnection component will select the cache interface or the non-cache interface as the master device, and enable the transaction transfer operation to the target slave device, and there is only one memory transaction request each time. When the write transaction being processed is completed, the next write transaction can be processed, that is, the next write transaction will be executed only after the Write Address and Write Data of any write transaction are completed. Therefore, there will be no deadlock problem like the above-mentioned acceleration unit with only one master device.

[0090] When the non-cached interface is arbitrated as the current master device, the write transaction of the non-cached data is sent to the target slave device ACE-AXI conversion component, and then sent to the controller memory interconnect controller to complete the process of writing the non-cached data into the memory.

[0091] When the cache interface is arbitrated as the current master device, the write transaction of the cache data is sent to the ACE-LS interface of the target slave device ARM system, and then the write transaction of the cache data is sent to the cache consistency control component to write the cache data into the cache.

[0092] Furthermore, when the cache is full, in order to avoid conflicts between the process of writing non-cached data into the memory and the process of writing eliminated data in the cache into the memory, the controller memory interconnect component sends a pause message to the acceleration interconnect component, so that the acceleration interconnect component responds to the pause message and suspends processing any write transaction, and thus will not continue to write cache data into the full cache, nor will it execute non-cached data writes into the memory, thereby further avoiding the problem of deadlock.

[0093] Reference Figure 3 , shows a flow chart of the steps of a memory transaction processing method provided in an embodiment of the present application, which is applied to the system on chip described in this embodiment, and the method includes the following steps:

[0094] S101: In response to a write transaction processing instruction of any processor, determine whether to send the write transaction to a cache interface or a non-cache interface of an acceleration unit according to a data type corresponding to the write transaction.

[0095] The cache interface stores the write transaction corresponding to the received cache data in the cache data queue; the non-cache interface stores the write transaction corresponding to the received non-cache data in the cache data queue.

[0096] S102: The acceleration interconnect component determines a write transaction currently being processed, and when the write transaction currently being processed is a write transaction of cached data, initiates a write transaction operation of cached data to the cache consistency control component; when the write transaction currently being processed is a write transaction of non-cached data, initiates a write transaction operation of cached data to the controller memory interconnect component to write the non-cached data into the memory.

[0097] The acceleration interconnect component uses the interface currently used as the master device, obtains the currently processed write transaction from the corresponding queue, and sends the write transaction to the corresponding target slave device according to the data type.

[0098] S103: When the cache of the system on chip is full, the cache consistency control component initiates a memory consistency operation and sends a pause message to the acceleration interconnect component.

[0099] S104: The acceleration interconnect component suspends processing of any write transaction in response to the suspension information.

[0100] When the cache is full, the eliminated data in the cache needs to be written to the memory. Therefore, a pause message can be sent to the acceleration interconnect component at this time, which can prevent the acceleration interconnect component from continuing to write cache data to the full cache, and can also prevent the acceleration interconnect component from processing non-cached data and writing them to the memory, further avoiding deadlock.

[0101] Reference Figure 4 , shows a schematic diagram of a non-volatile readable storage medium provided in an embodiment of the present application, wherein the non-volatile readable storage medium 400 stores a computer program 401, wherein the computer program, when executed by a processor, executes the memory transaction processing method described in this embodiment.

[0102] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0103] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0104] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0105] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0106] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0107] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0108] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0109] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An offload memory transaction acceleration device, characterized in that: Applied to a system on chip, the system on chip includes a processor core, a cache consistency control component and a controller memory interconnect component, the device includes an acceleration unit and an acceleration interconnect component, wherein: The acceleration unit is used to receive write transactions sent by the processor core. The acceleration unit is provided with a cache interface and a non-cache interface. The cache interface is used to receive write transactions of cached data sent by the processor core, and the non-cache interface is used to receive write transactions of non-cache data sent by the processor core. The acceleration interconnect component adopts a target shared access mode, in which the acceleration interconnect component processes one write transaction at a time; When the acceleration interconnect component is currently processing a write transaction of cache data sent by the cache interface, initiating a write transaction operation of the cache data to the cache consistency control component to write the cache data into the cache; When the acceleration interconnect component currently processes a write transaction of non-cached data sent by the non-cached interface, a write transaction operation of cached data is initiated to the controller memory interconnect component to write the non-cached data into the memory.

2. The device according to claim 1, characterized in that When the acceleration interconnect component initiates a write transaction operation of cache data to the cache consistency control component, if the cache is full, the cache consistency control component initiates a memory consistency operation and sends a pause message to the acceleration interconnect component; The acceleration interconnect component is used to suspend processing of any write transaction in response to the suspension information; Wherein, when executing the memory consistency operation, the cache consistency control component is used to send the eliminated data in the cache to the controller memory interconnect component and write the eliminated data into the memory.

3. The device according to claim 1, characterized in that The acceleration interconnect component is provided with a cache data queue and a non-cache data queue, both of which are first-in-first-out queues, the cache data queue is used to store write transactions of cache data sent by the cache interface, and the non-cache data queue is used to store write transactions of non-cache data sent by the non-cache interface; The acceleration interconnect component is used to select a write transaction in the cache data queue or the non-cache data queue for processing each time.

4. The device according to claim 3, characterized in that The acceleration interconnect component is used to poll and select a write transaction for processing in the cache data queue or the non-cache data queue each time.

5. The device according to claim 3, characterized in that Different priorities are set for the cache data queue or the non-cached data queue, and the acceleration interconnect component is used to obtain a write transaction from the queue with a high priority for processing each time until the queue with a high priority does not contain any write transactions, and then obtain a write transaction from the queue with a low priority for processing.

6. The device according to claim 1, characterized in that Any write transaction of cached data or non-cached data includes a write address transaction and a write data transaction; The acceleration interconnect component includes a write address transaction processor and a write data transaction processor; When the write address transaction processor and the write data transaction processor determine that the currently processed transaction is a write transaction of non-cached data, the acceleration interconnect component is used to send the address information and data information of the non-cached data to the controller memory interconnect component, and the controller memory interconnect component is used to write the data information of the non-cached data into the location corresponding to the address of the non-cached data in the memory; When the write address transaction processor and the write data transaction processor determine that the currently processed transaction is a write transaction of cache data, the acceleration interconnect component is used to send the address information and data information of the cache data to the cache consistency control component; If the target cache in the multi-level cache corresponding to the address information of the cache data is not full, the cache controller in the cache coherence control component is used to write the data information of the cache data into the position corresponding to the address information of the cache data; If the target cache in the multi-level cache corresponding to the address information of the cache data is full, the cache controller in the cache consistency control component is used to determine the eliminated data in the target cache, send the eliminated data to the controller memory interconnect component, write the eliminated data into the memory, and send a pause message to the acceleration interconnect component; The acceleration interconnect component is used for suspending processing of any write transaction in response to the suspension information.

7. The device according to claim 6, characterized in that When the acceleration interconnect component suspends processing of any write transaction, if the acceleration interconnect component receives the continue processing information sent by the cache consistency control component, the acceleration interconnect component is used to respond to the continue processing information and continue processing any write transaction.

8. A system on chip, characterized in that: The system on chip includes a processor core, a cache consistency control component and a controller memory interconnect component, and the system on chip also includes the offload memory transaction acceleration device according to any one of claims 1-7.

9. A memory transaction processing method, characterized in that: Applied to the system on chip of claim 8, the method further comprises: In response to a write transaction processing instruction of any processor, determining to send the write transaction to a cache interface or a non-cache interface of an acceleration unit according to a data type corresponding to the write transaction; The acceleration interconnect component determines a write transaction currently being processed, and when the write transaction currently being processed is a write transaction of cached data, initiates a write transaction operation of cached data to the cache consistency control component; when the write transaction currently being processed is a write transaction of non-cached data, initiates a write transaction operation of cached data to the controller memory interconnect component, so as to write the non-cached data into the memory; When the cache of the system on chip is full, the cache coherence control component initiates a memory coherence operation and sends a pause message to the acceleration interconnect component; The acceleration interconnect component suspends processing of any write transaction in response to the suspension information.

10. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, wherein the computer program, when executed by a processor, performs the memory transaction processing method according to claim 9.

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