Method for generating circuit layout map, computer storage medium and electronic design system

Abstract

The invention provides a method of generating an integrated circuit layout. The method includes arranging a first column and a second column of gate regions in a cell. The first column has a first width extending from the first gate region to the last gate region and equal to a first multiple of the gate interval pitch. The second column has a second width extending from the first gate region to the last gate region and equal to a second multiple of the gate interval pitch, the second multiple being greater than the first multiple. The method includes defining first to fourth cell boundary sections by extending first and second sections along a first gate region and a last gate region of a first column and extending third and fourth sections along a first gate region and a last gate region of a second column, the boundary is non-rectangular based on one or both of misalignment of the first section and the third section or misalignment of the second section and the fourth section, and storing the cell in a storage device.

Description

Technical Field

[0001] The present invention relates to a method for generating an integrated circuit layout diagram, a non-temporary computer-readable storage medium and an electronic design automation system. Background Art

[0002] The continued trend toward miniaturization of integrated circuits (ICs) has resulted in devices that are smaller, consume less power, and yet provide more functionality at faster speeds than previous technologies. Miniaturization is achieved through design and manufacturing innovations tied to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify the design of semiconductor devices while ensuring that design and manufacturing specifications are met. Summary of the invention

[0003] The present invention is directed to a method for generating an integrated circuit layout diagram. The method includes arranging a first column of gate regions in a cell, the first column of gate regions having a first width extending from a first gate region of the first column of gate regions to a last gate region, whereby the first width is equal to a first multiple of the gate region spacing. The method also includes arranging a second column of gate regions adjacent to the first column of gate regions in the cell, the second column of gate regions having a second width extending from a first gate region of the second column of gate regions to a last gate region, whereby the second width is equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple. The method also includes defining first to fourth sections of the boundary of the cell by extending the first section along the first gate region of the first column of gate regions, extending the second section along the last gate region of the first column of gate regions, extending the third section along the first gate region of the second column of gate regions, and extending the fourth section along the last gate region of the second column of gate regions, whereby the boundary of the cell is non-rectangular based on one or both of the first section and the third section not being aligned with each other or the second section and the fourth section not being aligned with each other. The method also includes storing the integrated circuit layout diagram of the cell in a storage device.

[0004] The present invention is also directed to a non-transitory computer-readable storage medium including computer program code for one or more programs. The non-transitory computer-readable storage medium and the computer program code are configured to cause a processor to: arrange one or more first integrated circuit devices of a first row in a cell, the first row having a first width extending from a first gate region to a last gate region of the one or more first integrated circuit devices, wherein the first width is equal to a first multiple of the gate region spacing; arrange one or more second integrated circuit devices of a second row in the cell adjacent to the first row, the second row having a second width extending from a first gate region to a last gate region of the one or more second integrated circuit devices, wherein the second width is equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple; define a first segment, a second segment, a third segment, and a fourth segment of a boundary of the cell by extending the first segment along the first gate region of the first row, extending the second segment along the last gate region of the first row, extending the third segment along the first gate region of the second row, and extending the fourth segment along the last gate region of the second row, wherein the boundary of the cell is non-rectangular based on one or both of the first segment and the third segment being misaligned with each other or the second segment and the fourth segment being misaligned with each other; and store an integrated circuit layout diagram of the cell in a storage device.

[0005] The present invention is also directed to an electronic design automation system. The electronic design automation system includes: a processor; and a non-transitory computer-readable storage medium including computer program code for one or more programs, the non-transitory computer-readable storage medium and the computer program code being configured to, together with the processor, cause the processor to: obtain a cell from the non-transitory computer-readable storage medium or another storage medium, wherein the cell includes a non-rectangular boundary, the non-rectangular boundary including: a first section and a second section extending along a first gate region and a last gate region of a first column of gate regions, respectively, the total number of the first column of gate regions being equal to a first multiple of the gate region spacing; and a third section and a fourth section extending along a first gate region and a last gate region of a second column of gate regions adjacent to the first column of gate regions, respectively, the total number of the second column of gate regions being equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple; and perform automatic placement and routing operations, including: placing the cell in an integrated circuit layout; and arranging a plurality of electrical connections in the first column of gate regions and the second column of gate regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An IC layout diagram is shown according to some embodiments.

[0007] Figure 2 An IC layout diagram is shown according to some embodiments.

[0008] Figure 3An IC layout diagram is shown according to some embodiments.

[0009] Figure 4 An IC layout diagram is shown according to some embodiments.

[0010] Figure 5 An IC layout diagram is shown according to some embodiments.

[0011] FIG. 6A to FIG. 6C An IC layout diagram is shown according to some embodiments.

[0012] Fig. 7A and Figure 7B An IC layout diagram is shown according to some embodiments.

[0013] Figure 8 An IC layout diagram is shown according to some embodiments.

[0014] Fig. 9 is a flow chart of a method of generating an IC layout diagram according to some embodiments.

[0015] Fig.10 is a block diagram of an IC design system according to some embodiments.

[0016] Fig.11 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith according to some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. The following describes specific examples of components, values, operations, materials, arrangements or similar elements to simplify the disclosure. Of course, these are only examples and are not intended to be limited. It is expected that there are other components, values, operations, materials, arrangements or similar elements. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than the relationship between the various embodiments and / or configurations discussed by the self-indication.

[0018] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] In various embodiments, integrated circuit (IC) layouts, methods, and IC design systems are directed to non-rectangular standard cells, where adjacent rows have unequal widths based on different numbers of gate regions spaced apart according to gate region pitches. Compared to rectangular cells, non-rectangular cell architectures achieve improved power, performance, and area (PPA) metrics by eliminating unused space and shortening internal wiring components (e.g., corresponding to external paths and timing-critical internal signals), as discussed below.

[0020] As discussed below, Figures 1 to 7B An IC layout diagram 100 - 700B depicts a non-limiting example of a non-rectangular cell, also referred to in some embodiments as cell 100 - 700B, Figure 8 An IC layout floorplan 800 is shown including a non-limiting example of a non-rectangular cell. Fig. 9 is a flow chart of a method 900 for generating an IC layout diagram (eg, IC layout diagram 100-700B), Fig.10 is a block diagram of an IC design system 1000 (eg, EDA system 1000) configured to perform some or all of the operations of method 900, and Fig.11 is a block diagram of an IC manufacturing system and related IC manufacturing flow 1100 by which one or more IC structures are manufactured based at least in part on one or more of the IC layout diagrams 100 - 800 .

[0021] Figures 1 to 8 Each of the diagrams 100-800 shows a plan view of the corresponding IC layout diagram 100-800 along the X direction and the Y direction, and for the purpose of illustration Figures 1 to 8 In various embodiments, a given IC layout 100 - 800 includes one or more features, such as active regions, source / drain (S / D) structures, isolation features, internal wiring components, or the like, that are not depicted for clarity.

[0022] exist Figure 1 In the illustrated embodiment, the cell 100 includes gate regions GR of adjacent rows R1 and R2 (only a single example is labeled for clarity). A cell (e.g., cell 100), also referred to in some embodiments as a standard cell or a standard function cell, is an IC layout diagram including a specific internal arrangement of components (e.g., gate regions GR) configured to (in operation) provide corresponding shared low-level functions, such as logic functions, such as inverters, NAND, NOR, XOR, D-latch, and-or-invert (AOI), or-and-invert (OAI), multiplexer, flip-flop, decoupling capacitor (DeCap), or the like.

[0023] In some applications (e.g., automatic placement and routing (APR) operations), electronic design automation (EDA) tools are used to select standard function cells from a library of standard cells and place the standard function cells together with non-standard cells (if any) into an initial layout. EDA tools are also used to perform routing, whereby one or more metal layers and corresponding vias and contacts can be used to connect standard function cells and non-standard cells. EDA tools are also used to test routing. The selection, placement, and routing of standard and non-standard cells are modified depending on the test results. In at least some embodiments, the overall selection, placement, routing, and testing (SPRT) process is iterative. Finally, the SPRT process iteration converges to the final layout.

[0024] Figure 1 The depicted total of two adjacent rows R1 and R2 in the cell 100 is a non-limiting example provided for illustration purposes. In some embodiments, the cell 100 includes more than two adjacent rows.

[0025] In some embodiments, each of the columns R1 and R2 corresponds to a plurality of gate regions GR spaced apart by a gate region pitch GP (also referred to as pitch GP). The column R1 includes a plurality of instances of the gate region GR extending from the first gate region FG1 to the second gate region LG1 in the X direction, and the column R2 includes a plurality of instances of the gate region GR extending from the first gate region FG2 to the second gate region LG2 in the X direction.

[0026] The gate region GR is a region in an IC layout diagram (e.g., cell 100) that at least partially defines a gate structure in a manufacturing process (e.g., manufacturing process 1100 discussed below) used to manufacture an IC corresponding to the IC layout diagram, such as a gate isolated from adjacent features by one or more gate dielectric layers.

[0027] Some or all instances of the gate region GR are components of an IC device configured to provide a predetermined function of the cell 100 and are not further illustrated for the purpose of clarity. In some embodiments, a column (e.g., column R1 or column R2) is referred to as a column of gate regions or a column of an IC device, and the IC device includes a corresponding instance of the gate region GR.

[0028] exist Figure 1 In the illustrated embodiment, the upper and lower boundaries of a given row (e.g., row R1 or row R2) include instances of cut gate regions CG (only a single instance is labeled for clarity), also referred to in some embodiments as cut poly regions CG. Cut gate regions CG are regions in an IC layout that at least partially define a gate structure discontinuity formed by using a manufacturing process (e.g., one or more etching operations) to remove gate portions and / or dielectric layer portions after their formation. Figure 1 As shown, instances of the gate regions GR aligned along the Y direction are thereby electrically isolated from each other based on instances of the cut gate regions CG.

[0029] exist Figure 1 In the illustrated embodiment, each instance of the cut gate region CG extends through the entirety of each of the rows R1 and R2. In various embodiments, a given instance of the cut gate region CG is absent, extends along a portion of a row, or includes multiple segments such that one or more pairs of instances of the gate region GR aligned along the Y direction are electrically connected to each other.

[0030] In some embodiments, one or more instances of gate region GR are dummy gate regions corresponding to gate structures and are not included in the IC device, for example, positioned according to pitch GP to provide load uniformity in one or more manufacturing processes. In some embodiments, each of gate regions FG1, LG1, FG2, and LG2 is a dummy gate region.

[0031] exist Figure 1 In the illustrated embodiment, row R1 includes a total of 8 instances of gate region GR, and row R2 includes a total of 7 instances of gate region GR, so that cell 100 includes a total of 15 instances of gate region GR, which is an odd number based on the total number of rows R1 and R2 differing by one.

[0032] In various embodiments, the cell 100 includes columns including other total gate region counts, such as other total counts that differ by 1 or differ by more than 1. In some embodiments, the cell 100 includes an even total number of gate region GR instances.

[0033] exist Figure 1In the illustrated embodiment, gate region FG1 is aligned with gate region FG2 in the Y direction, and each instance of gate region GR in row R2 is aligned with a corresponding instance of gate region GR in row R1. In some embodiments, gate region FG1 is not aligned with gate region FG2 in the Y direction, gate region LG1 is aligned with gate region LG2 in the Y direction, and each instance of gate region GR in row R2 is aligned with a corresponding instance of gate region GR in row R1.

[0034] In some embodiments, gate region FG1 is not aligned with gate region FG2 in the Y direction, gate region LG1 is not aligned with gate region LG2 in the Y direction, and a subset of instances of gate region GR in row R2 are aligned with corresponding instances of gate region GR in row R1, and the structure corresponds to that row R1 and row R2 are offset along the X direction.

[0035] In some embodiments, cell 100 includes one or more columns adjacent to column R1 and / or column R2, and corresponding additional instances of gate region GR have one or more arrangements relative to column R1 and / or column R2 and / or relative to each other similar to the arrangements of column R1 and column R2 relative to each other.

[0036] In a given column, the total number of instances of the gate region GR corresponds to the width in the X direction, and the width corresponds to a multiple of the pitch GP according to the total number. Figure 1 In the illustrated non-limiting example, the width W1 of row R1 corresponds to a multiple of 8 instances of the pitch GP and the gate region GR, and the width W2 of row R2 corresponds to a multiple of 7 instances of the pitch GP and the gate region GR.

[0037] According to the architecture of the example gate region GR discussed above, the cell 100 includes a boundary 100B, and the boundary 100B includes segments S1-S7. Figure 1 In the illustrated embodiment, segment S1 extends in the Y direction along the gate region FG1, segment S2 extends in the X direction along the width W1, segment S3 extends in the Y direction along the gate region LG1, segment S4 extends in the X direction along a portion of the width W1 that is equal to the difference between the width W1 and the width W2, segment S5 extends in the Y direction along the gate region LG2, segment S6 extends in the X direction along the width W2, and segment S7 extends in the Y direction along the gate region FG2, thereby being aligned with segment S1 along the Y direction.

[0038] In various embodiments, a cell, such as cell 100, includes a boundary including segments arranged in other ways according to one or more pairs of columns, and the one or more pairs of columns have unequal total numbers of gate region GR instances. In some embodiments, cell 100 corresponds to one of the non-limiting example cells 200-700B discussed below, where individual segments corresponding to boundary 200B-700BB are not labeled for clarity.

[0039] By including columns R1 and columns R2 having different widths (based on different total numbers of gate region GR instances as described above), the cell 100 is configured as a non-rectangular cell capable of having a reduced area or otherwise having an improved PPA metric, for example, having a reduced power level for the same or increased area compared to a rectangular cell corresponding to a cell functionally equivalent to the cell 100.

[0040] Figure 2 A cell 200 is shown according to some embodiments, the cell 200 including a row R1 extending from a gate region FG1 to a gate region LG1, a row R2 extending from a gate region FG2 to a gate region LG2, and an example of cutting a gate region CG, each of which is described above with respect to Figure 1 Discussed.

[0041] The cell 200 further includes a critical path CP, which includes via regions V0, V1, and V2, a metal region M0 extending along the X direction, and a metal region M1 extending along the Y direction, as described below.

[0042] A via region (e.g., via region V0, V1, or V2) is a region in an IC layout diagram that at least partially defines a via or other structure capable of forming an electrical connection (e.g., a structure comprising a metal such as copper) to an underlying feature, such as a gate corresponding to an instance of gate region GR, a source / drain (S / D) structure of an IC device, or an underlying metal segment.

[0043] A metal region (e.g., metal region M0 or M1) is a region in an IC layout that overlaps one or more features (e.g., corresponding instances of via regions V0 or V1), and the metal region at least partially defines a metal segment that covers and electrically connects an underlying via structure, the underlying via structure corresponding to the instance of the corresponding via region V0 or V1. In some embodiments, metal segment M1 (also referred to as metal-one segment M1 in some embodiments) is included in the lowest metal layer of a routing process (e.g., an APR process) corresponding to the IC layout.

[0044] A critical path (e.g., a critical path CP discussed below, also referred to in some embodiments as a signal path SP) is an electrical connection including one or more vias and / or metal segments configured to transmit one or more signals according to one or more key design criteria, e.g., based on signal speed, timing and / or losses, power consumption, heat generation, risk of electromigration, etc. In some embodiments, one or more design criteria for a critical path include maximum resistance, capacitance, and / or combined resistance and capacitance (RC) associated with minimum signal speed, phase shift or losses, and / or maximum power consumption.

[0045] exist Figure 2 In the embodiment illustrated in , each instance of the through-hole region V0 in row R2 overlaps an instance of the corresponding gate region GR (not labeled), the metal region M0 overlaps each instance of the through-hole region V0, the through-hole region V1 overlaps the metal region M0 at a position between the positions where the instances of the through-hole region V0 overlap the metal region M0, the metal region M1 overlaps the through-hole region V1, and the through-hole region V2 overlaps the metal region M1 at a position in row R1.

[0046] pass Figure 2 , cell 200 includes features configured to at least partially define a critical path CP as an electrical connection from a via region V2 located in column R1 (capable of being included in an electrical connection external to cell 200, e.g., in an APR operation) through metal region M1, via region V1, metal region M0, and an instance of via region V0 to a corresponding instance of gate region GR in column R2.

[0047] like Figure 2 As shown, cell 200 includes a boundary 200B including segments (not labeled) extending along respective portions of rows R1 and R2 configured as described above.

[0048] Because via region V1 overlaps metal region M0 near the midpoint between instances of via region V0, the length of critical path CP between via region V2 and a given instance of via region V0 is shorter than the corresponding length in other approaches (e.g., including a single column of rectangular cells).

[0049] Thus, cell 200 is configured as a non-rectangular cell capable of including electrical connections for critical path CP (including reduced parasitic resistance and / or capacitance, e.g., based on a shorter electrical path length) as compared to a rectangular cell (e.g., including a single column corresponding to cell functionality equivalent to cell 200).

[0050] Thereby, the cell 200 includes a critical path CP further configured to transmit signals received at via region V2 to each gate below via region V0 in operation with more nearly balanced timing than other approaches (eg, those where signals are transmitted along a single column).

[0051] Figure 3 A cell 300 is shown according to some embodiments, the cell 300 including a row R1 extending from gate region FG1 to gate region LG1, a row R2 extending from gate region FG2 to gate region LG2, and examples of cut gate region CG, via regions V0, V1 and V2, and metal regions M0 and M1, each of which is discussed above.

[0052] The cell 300 also includes a column R3 including an instance of a gate region GR (not labeled) extending from the gate region FG3 to the gate region LG3.

[0053] Compared to cell 200, cell 300 includes a critical path CP that includes a metal region M1 extending from column R2 to column R3 and overlapping with an instance of via region V1, and the instance of via region V1 further overlaps with an instance of metal region M1 at a position between the positions where the instance of metal region M0 overlaps with the instance of via region V0 in column R3, wherein each instance of via region V0 overlaps a corresponding instance of gate region GR.

[0054] pass Figure 3 , cell 300 includes features configured to at least partially define a critical path CP as an electrical connection from via region V2 located in column R1 through metal region M1 and instances of via region V1, metal region M0, and via region V0 to corresponding instances of gate region GR in each of columns R2 and R3.

[0055] like Figure 3 As shown, cell 300 includes a boundary 300B including segments (not labeled) extending along corresponding portions of rows R1 through R3 configured as described above.

[0056] Thus, compared to a rectangular cell (eg, including a total of two columns corresponding to a cell function equivalent to the cell 300), the cell 300 is configured to be able to implement the above-mentioned Figure 2 The benefits discussed include non-rectangular cells having electrical connections with reduced parasitic resistance and / or capacitance, for example, based on shorter electrical path lengths.

[0057] Figure 4 A cell 400 is shown according to some embodiments, the cell 400 including a row R1 extending from gate region FG1 to gate region LG1, a row R2 extending from gate region FG2 to gate region LG2, and instances of a cut gate region CG, a via region V0 (only a single instance is labeled for clarity), and a metal region M0 (only a single instance is labeled for clarity), and a metal region M1, each of which is discussed above.

[0058] The cell 400 includes a critical device CD, which includes two instances of a gate region LG1 and a gate region GR (not labeled). A critical device (e.g., a critical device CD) is a circuit portion, such as an oscillator, an amplifier, or a buffer configured to output (e.g., generate) one or more signals on a critical path according to one or more critical design criteria as described above.

[0059] The instance of the via area V0 located in the critical device CD corresponds to the signal source, the instance of the via area V0 outside the critical device CD corresponds to the signal receiving position, and the via area V0 and the instances of the metal areas M0 and M1 are thus configured as the internal signal path SP.

[0060] like Figure 4 As shown, cell 400 includes a boundary 400B that includes segments (not labeled) extending along respective portions of rows R1 and R2 configured as described above.

[0061] Thereby, compared to a rectangular cell (e.g., including a key device positioned to include gate region FG1, corresponding to a cell function equivalent to cell 400), cell 400 is configured as a non-rectangular cell capable of including an internal signal path SP, wherein the internal signal path SP includes reduced parasitic resistance and / or capacitance, for example, based on a shorter electrical path length. In some embodiments, cell 400 is thereby configured as a non-rectangular cell, which can also have a reduced area compared to a rectangular cell corresponding to a cell function equivalent to cell 400.

[0062] Figure 5 A cell 500 is shown according to some embodiments, and the cell 500 includes a row R1 extending from gate region FG1 to gate region LG1, a row R2 extending from gate region FG2 to gate region LG2, a row R3 extending from gate region FG3 to gate region LG3, a cut gate region CG, a via region V0 (only a single instance is labeled for clarity) and a via region V1, and a metal region M0 (only a single instance is labeled for clarity) and a metal region M1 and an instance of a critical device CD, each of which is discussed above.

[0063] Compared to cell 400, cell 500 includes a critical device CD in column R1 that is separated from other IC devices in columns R2 and R3, and includes an internal signal path SP extending from the critical device CD in column R1 to each instance of via region V0 in columns R2 and R3.

[0064] As shown in FIGS. 5 and 5 , cell 500 includes a boundary 500B including segments (not labeled) extending along corresponding portions of rows R1 to R3 configured as described above.

[0065] Thereby, compared to a rectangular cell (e.g., including a key device positioned to include gate region FG2, corresponding to a cell function equivalent to cell 500), cell 500 is configured as a non-rectangular cell capable of including an internal signal path SP, wherein the internal signal path SP includes reduced parasitic resistance and / or capacitance, for example, based on a shorter electrical path length. In some embodiments, cell 500 is thus configured as a non-rectangular cell, which can also have a reduced area compared to a rectangular cell corresponding to a cell function equivalent to cell 500.

[0066] FIG. 6A to FIG. 6C 600A-600C are shown according to some embodiments, wherein each cell is configured as a flip-flop circuit (also referred to as a flop in some embodiments), the flip-flop circuit including a clock source electrically connected to each of the clock devices (clock devices 1 to 4) via a signal path SP, as described above with respect to Figure 4 and Figure 5 The clock source is discussed above. Figure 4 and Figure 5 The non-limiting example of a key device CD is discussed.

[0067] Fig. 6A The illustrated cell 600A includes rows R1 and R2 as discussed above, and the width (not labeled) of the clock source in row R1 is greater than that in row R2. The cell 600A includes a boundary 600AB, which includes segments (not labeled) extending along respective portions of the rows R1 and R2. The rows R1 and R2 are configured as shown in FIG. Fig. 6A drawn.

[0068] Thereby, the cell 600A is configured as a non-rectangular cell, which can have a reduced area than a rectangular cell equivalent to the cell 600A corresponding to the flip-flop function.

[0069] Figure 6B The illustrated cell 600B includes rows R1 to R3 as discussed above, and the clock source located in row R1 is separated from the clock devices (clock devices 1 to 4) located in rows R2 and R3, and the signal path SP extends from row R1 to each of rows R2 and R3. The cell 600B includes a boundary 600BB, which includes a line extending along the row R1. Figure 6B The rows R1 to R3 are arranged so as to extend from corresponding portions of the sections (not labeled).

[0070] Thereby, compared to a rectangular cell (e.g., including two total columns, corresponding to a flip-flop function equivalent to cell 600B), cell 600B is configured as a non-rectangular cell capable of including a signal path SP, wherein the signal path SP includes reduced parasitic resistance and / or capacitance, for example, based on a shorter electrical path length. In some embodiments, cell 600B is thereby configured as a non-rectangular cell, which can also have an improved PPA metric, for example, a reduced area and / or power level and / or an increased speed, compared to a rectangular cell corresponding to a flip-flop function equivalent to cell 600B.

[0071] Figure 6C The cell 600C shown in FIG. 6 includes rows R1 to R3 as discussed above, and the clock source located in row R3 is separated from the clock devices (clock devices 1 to 4) located in rows R1 and R2, and the signal path SP extends from row R3 to each of rows R2 and R1. The cell 600C includes a boundary 600CB, which includes a line extending along the row R1 as shown in FIG. Figure 6C The rows R1 to R3 are arranged so as to extend from corresponding portions of the sections (not labeled).

[0072] Thereby, compared to a rectangular cell (e.g., including two columns in total, corresponding to a flip-flop function equivalent to the cell 600C), the cell 600C is configured as a non-rectangular cell capable of including a signal path SP, wherein the signal path SP includes a reduced parasitic resistance and / or capacitance, for example, based on a shorter electrical path length. In some embodiments, the cell 600C is thus configured as a non-rectangular cell, which can also have a reduced area compared to a rectangular cell corresponding to the flip-flop function equivalent to the cell 600C.

[0073] Fig. 7A and Figure 7B Cell 700A and cell 700B are depicted respectively according to some embodiments. Each of cell 700A and cell 700B includes row R1 (including gate region GR (not labeled) extending from gate region FG1 to gate region LG1), row R2 (including gate region GR (not labeled) extending from gate region FG2 to gate region LG2), an example of cut gate region CG (each of which is discussed above), and an example of performance critical device PCD.

[0074] A performance critical device PCD (also referred to in some embodiments as a power critical device PCD) is a circuit portion, such as one or more transistors, configured to meet one or more design criteria corresponding to critical power and / or timing requirements (eg, minimum current carrying capability).

[0075] like Fig. 7A and Figure 7BAs shown, row R1 and row R2 have height CH1 and height CH2 (also referred to as cell height CH1 and cell height CH2 in some embodiments), respectively. Height CH1 is greater than height CH2, corresponding to the IC device located in row R1 having a larger channel, and thus being able to perform higher power operations than the IC device located in row R2. As a result, the IC device located in row R1 consumes more power than the IC device located in row R2.

[0076] In some embodiments, the height CH1 of row R1 is greater than the height CH2 of row R2 corresponding to IC devices including rows R1 and R2 of fin field effect transistors (FinFETs), wherein the total number of FinFET fins corresponding to row R1 is greater than the total number of FinFET fins corresponding to row R2.

[0077] Fig. 7A The illustrated cell 700A includes a performance critical device PCD as a power critical device, so that the cell located in row R2 has improved power efficiency compared to the cell located in row R1. The cell 700A includes a boundary 700AB, and the boundary 700AB includes a boundary along the line as shown in FIG. Fig. 7A The rows R1 and R2 are arranged so as to extend from corresponding portions of the sections (not shown).

[0078] Figure 7B The illustrated cell 700B includes a performance critical device PCD as a timing critical device, so that the cell located in row R1 has improved timing performance than the cell located in row R2. The cell 700B includes a boundary 700BB, and the boundary 700BB includes a plurality of edges along the line such as Figure 7B The rows R1 and R2 are arranged so as to extend from corresponding portions of the sections (not shown).

[0079] Each cell 700A and cell 700B is thus configured as a non-rectangular cell, which can include a performance critical device PCD positioned to improve circuit performance compared to a rectangular cell corresponding to the cell function equivalent to the corresponding cell 700A or cell 700B (for example, including a performance critical device positioned in another way). In some embodiments, compared to a rectangular cell corresponding to the cell function equivalent to the corresponding cell 700A or cell 700B, the cell 700A and / or the cell 700B is thus configured as a non-rectangular cell that can also have a reduced area.

[0080] Figure 8 An IC layout diagram 800 according to some embodiments is shown. In some embodiments, the IC layout diagram 800 is also referred to as a floorplan 800. The IC layout diagram 800 includes the columns R1 to R3 discussed above and includes a column R4 adjacent to the column R3.

[0081] IC layout diagram 800 includes a plurality of cells located in one or more of columns R1 to R4. The cells include rectangular cells (not labeled for clarity), non-rectangular cells NR1 located in columns R1 and R2, and non-rectangular cells NR2 located in columns R3 and R4. In various embodiments, non-rectangular cells NR1 or non-rectangular cells NR2 correspond to one of the cells 100-700B discussed above.

[0082] Figure 8 The sizes and shapes (e.g., the number of rows spanned) of the non-rectangular cells NR1 and NR2 shown in FIG. 8 are non-limiting examples provided for illustration purposes. In various embodiments, in addition to one or both of the non-rectangular cells NR1 and NR2, the IC layout diagram 800 also includes one or more non-rectangular cells, such as cells spanning three of the rows R1 to R4.

[0083] In some embodiments, the IC layout diagram 800 includes one or more electrical connections (not shown) between cells, whereby the non-rectangular cell NR1 and / or the non-rectangular cell NR2 are included in an IC configured to perform one or more functions in operation based in part on low-level functions of the non-rectangular cell NR1 and / or the non-rectangular cell NR2.

[0084] By including one or more non-rectangular cells configured as described above, the IC layout diagram 800 can achieve the above-mentioned Figures 1 to 7B The benefits discussed.

[0085] Fig. 9 is a flow chart of a method 900 for generating an IC layout diagram according to some embodiments. In some embodiments, generating an IC layout diagram includes generating the above-mentioned Figures 1 to 8 Some or all of one or more of the IC layout diagrams 100-800 discussed.

[0086] In some embodiments, some or all of method 900 is performed by a processor of a computer. In some embodiments, some or all of method 900 is performed by a processor 1002 of an IC layout generation system 1000. Fig.10 Discuss.

[0087] In some embodiments, one or more operations of method 900 are a subset of operations of a method of forming an IC device. In some embodiments, one or more operations of method 900 are an IC manufacturing process (e.g., as described below with respect to manufacturing system 1100 and Fig.11 A subset of the operations of the IC manufacturing flow discussed above.

[0088] In some embodiments, the operation of method 900 is to Fig. 9In some embodiments, the operations of method 900 are performed simultaneously and / or in a sequential order. Fig. 9 In some embodiments, one or more operations are performed before, between, during, and / or after performing one or more operations of method 900.

[0089] In some embodiments, some of the operations of method 900 are performed as part of generating an IC floor plan of a non-rectangular cell (e.g., cells 100-700B discussed above). In some embodiments, some of the operations of method 900 are performed as part of generating an IC floor plan (e.g., IC floor plan 800) including one or more instances of non-rectangular cells, for example as part of an APR operation.

[0090] At operation 902, in some embodiments, an IC layout diagram is obtained from a storage device. In some embodiments, obtaining the IC layout diagram includes obtaining a rectangular cell from a storage device (e.g., a cell library). In some embodiments, obtaining the IC layout diagram includes obtaining a non-rectangular cell from a storage device, such as the cells 100-700B discussed above.

[0091] In some embodiments, obtaining the IC layout diagram from the storage device includes obtaining the IC layout diagram from the following Fig.10 The cell library 1007 discussed obtains the IC layout map.

[0092] At operation 904, in some embodiments, the cell is a rectangular cell, and the cell is modified by arranging a first column of gate regions and a second column of gate regions in the cell. Arranging the first column and the second column includes a first column having a first width, the first width extending from a first gate region of the first column to a last gate region, such that the first width is equal to a first multiple of the gate region spacing, and a second column adjacent to the first column and having a second width extending from the first gate region of the second column to the last gate region, such that the second width is equal to a second multiple of the gate region spacing, and the second multiple is greater than the first multiple.

[0093] In some embodiments, arranging the first column and the second column includes arranging one or more first IC devices of the first column in a cell and arranging one or more second IC devices of the second column adjacent to the first column in the cell, the first column having a first width extending from a first gate region to a last gate region of the one or more first IC devices, and the second column having a second width extending from a first gate region to a last gate region of the one or more second IC devices.

[0094] In some embodiments, arranging the first column and the second column includes arranging two of column R1 (including the gate region GR extending from FG1 to LG1), column R2 (including the gate region GR extending from FG2 to LG2), or column R3 (including the gate region GR extending from FG3 to LG3), each of column R1, column R2, or column R3 having a width corresponding to a multiple of the pitch GP, as described above for Figures 1 to 7B Discussed.

[0095] In some embodiments, arranging the first and second columns includes arranging a total of three or more columns, such as columns R1 - R3 as discussed above.

[0096] In various embodiments, arranging the first and second columns includes one of aligning each gate region of the first column with a corresponding gate region of the second column or aligning a subset of the gate regions of the first column with corresponding gate regions of the second column.

[0097] In some embodiments, arranging the first column includes arranging the first column to have a first height, such as the first height described above for Fig. 7A and Figure 7B One of the height CH1 or the height CH2 is discussed, and arranging the second column includes a second column having a second height different from the first height, the second height being, for example, the other of the height CH1 or the height CH2.

[0098] In some embodiments, arranging the first column and the second column includes a sum of the first multiple and the second multiple being an odd number.

[0099] In some embodiments, the first and second columns are arranged such that each of the first and last gate regions of one or both of the first and second columns is a dummy gate region.

[0100] In some embodiments, arranging the first column of gate regions includes modifying a rectangular cell, such as the rectangular cell obtained in operation 902 , by removing dummy gate regions outside the first to last gate regions in the first column.

[0101] In some embodiments, arranging the first column of gate regions includes modifying a rectangular cell, such as the rectangular cell obtained in operation 902 , by moving gate regions from one of the first column or the second column to the other of the first column or the second column.

[0102] In some embodiments, arranging the first column and the second column includes modifying the rectangular cell obtained, for example, in operation 902, and one or both of arranging the one or more first IC devices of the first column or arranging the one or more second IC devices of the second column includes moving the key device from the first position to the second position, for example, moving the key device from the first position to the second position. Figure 4 , Figure 5 , Fig. 7A and Figure 7B The examples of the key device CD discussed above are FIG. 6A to FIG. 6C Examples of clock sources discussed.

[0103] In some embodiments, arranging the one or more first IC devices or second IC devices of the first column or the second column includes configuring the one or more first IC devices or second IC devices as clock source circuits, such as described above for FIG. 6A to FIG. 6C Discuss the clock source.

[0104] In some embodiments, arranging the first column includes the first column having a first height, and the first height corresponds to a first number of fins of the FinFET of one or more first IC devices, arranging the second column includes the second column having a second height, and the second height corresponds to a second number of fins of the FinFET of one or more second IC devices, the first number of fins and the second number of fins are different from each other, and the first height and the second height are different from each other.

[0105] At operation 906, in some embodiments, after arranging the first column and the second column, a non-rectangular cell is generated from the rectangular cell by defining the first segment to the fourth segment of the boundary of the cell. In some embodiments, defining the first segment to the fourth segment includes extending the first segment along the first gate region of the first column, extending the second segment along the last gate region of the first column, extending the third segment along the first gate region of the second column, and extending the fourth segment along the last gate region of the second column, whereby the boundary of the cell is non-rectangular based on one or both of the first segment and the third segment not being aligned with each other or the second segment and the fourth segment not being aligned with each other.

[0106] In some embodiments, defining the first segment to the fourth segment includes aligning the first segment and the third segment with each other or aligning the second segment and the fourth segment with each other. In some embodiments, extending the first segment includes aligning the first segment with a gate region other than the first gate region or the last gate region of the second column, and extending the second segment includes aligning the second segment with a gate region other than the first gate region or the last gate region of the second column.

[0107] In some embodiments, defining the first to fourth segments includes defining Figure 1 Four or more of the segments S1 - S7 of the boundary 100B discussed.

[0108] In some embodiments, defining the first to fourth segments includes defining Figures 2 to 7B Four or more segments of one of the boundaries 200B-700BB are discussed.

[0109] In some embodiments, defining the first to fourth segments includes defining the fifth to seventh segments that define the cell boundaries, for example, by extending the fifth segment along the first width, extending the sixth segment along the second width, and extending the seventh segment along the second column a distance equal to the difference between the first width and the second width.

[0110] At operation 908, in some embodiments, the electrical connections of the cell are configured. In some embodiments, configuring the electrical connections includes configuring the electrical connections that can be electrically connected to the electrical connections outside the cell, for example, as described above for Figure 2 and Figure 3 Discussed.

[0111] In some embodiments, configuring the electrical connection includes configuring the internal electrical connection, for example, as described above with respect to Figure 4 and Figure 5 Discussed.

[0112] In some embodiments, configuring the electrical connection includes configuring the signal path, such as described above for FIG. 6A to FIG. 6C Discuss the signal path SP.

[0113] In some embodiments, configuring the electrical connection includes intersecting a first subset of the first gate region to the last gate region of one or more second IC devices with the first metal layer region, overlapping a first position and a second position at the intersection of the first subset and the first metal layer region with the first through-hole region, each first through-hole region corresponding to an electrical connection between a corresponding gate region of the first subset and the first metal layer region, extending the second metal layer region across the first row and the second row to intersect the first metal layer region at a third position between the first position and the second position, and overlapping the third position with a second through-hole region corresponding to the electrical connection between the first metal layer region and the second metal layer region.

[0114] In some embodiments, configuring the electrical connection includes arranging one or more third IC devices of a third column adjacent to the second column in the cell, the third column having a third width extending from the first gate region to the last gate region of the one or more third IC devices. Configuring the electrical connection also includes intersecting a second subset of the first gate region to the last gate region of the one or more third IC devices with the third metal layer region, and overlapping a fourth position and a fifth position at the intersection of the second subset and the third metal layer region with the third via region. Each third via region corresponds to an electrical connection between a corresponding gate region of the second subset and the third metal layer region, the second metal layer region extends across the third column and intersects the third metal layer region at a sixth position between the fourth position and the fifth position, and the sixth position overlaps with a fourth via region corresponding to an electrical connection between the second metal layer region and the third metal layer region.

[0115] At operation 910, in some embodiments, an APR operation including a cell is performed. Figures 1 to 7B The boundary 100B-700BB discussed herein includes a first segment and a second segment extending along a first gate region and a last gate region of a first column of gate regions, respectively, the total number of gate regions of the first column being equal to a first multiple of the gate region spacing, and a third segment and a fourth segment extending along a first gate region and a last gate region of a second column of gate regions adjacent to the first column of gate regions, respectively, the total number of gate regions of the second column being equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple.

[0116] Performing an APR operation includes placing cells in an IC layout diagram (e.g., Figure 8 The IC layout diagram 800 discussed above is shown in FIG. 8 , and a plurality of electrical connections are arranged in the first column gate region and the second column gate region.

[0117] In some embodiments, placing the cell in the IC layout diagram includes positioning the first column of gate regions in a first column of the IC layout diagram corresponding to a first number of FinFET fins, and positioning the second column of gate regions in a second column of the IC layout diagram corresponding to a second number of FinFET fins, and the second number is different from the first number, for example, as described above for Fig. 7A and Figure 7B Discussed.

[0118] In some embodiments, arranging the plurality of electrical connections at the first column gate region and the second column gate region includes configuring the electrical connections to a metal region located in the first column gate region, wherein the metal region extends from the first column gate region to the second column gate region, for example, as described above with respect to Figure 2 and Figure 3 Discussed.

[0119] At operation 912, in some embodiments, the IC layout diagram is stored in a storage device. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in an IC layout library, such as the following for Fig.10 The cell library 1007 or layout library 1009 of the IC layout generation system 1000 is discussed.

[0120] In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile computer-readable memory or a cell library (e.g., a database), and / or includes storing the IC layout diagram on a network. In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a storage device described below for Fig.10 The IC layout diagram generation system 1000 is discussed on the network 1014 .

[0121] In some embodiments, storing the IC layout in a storage device includes performing one or more manufacturing operations based on the IC layout. In some embodiments, performing one or more manufacturing operations includes performing one or more photolithography exposures based on the IC layout. Fig.11 Discussion One or more manufacturing operations, such as one or more photolithography exposures, are performed based on the IC layout.

[0122] By performing some or all of the operations of method 900 , an IC layout diagram including one or more non-rectangular cells is generated, and the benefits discussed above with respect to IC layout diagrams 100 - 800 can thereby be achieved.

[0123] Fig.10 is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments.

[0124] In some embodiments, the EDA system 1000 includes an automatic placement and routing (APR) system. The method of designing a layout diagram representing a wire routing arrangement according to one or more embodiments described herein may be implemented using the EDA system 1000, for example, according to some embodiments.

[0125] In some embodiments, EDA system 1000 is a general purpose computing device including a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. Storage medium 1004 is encoded with (i.e., stores) computer program code 1006 (i.e., a set of executable instructions), among other forms. Execution of instructions 1006 by hardware processor 1002 (at least in part) represents an EDA tool for implementing a portion or all of the methods described herein (hereinafter referred to as described processes and / or methods) according to one or more embodiments.

[0126] The processor 1002 is electrically coupled to the computer readable storage medium 1004 via a bus 1008. The processor 1002 is also electrically coupled to an input / output (I / O) interface 1010 via the bus 1008. A network interface 1012 is also electrically connected to the processor 1002 via the bus 1008. The network interface 1012 is connected to a network 1014 so that the processor 1002 and the computer readable storage medium 1004 can be connected to external components via the network 1014. The processor 1002 is configured to execute computer program code 1006 encoded in the computer readable storage medium 1004 so that the system 1000 can be used to implement part or all of the described processes and / or methods. In one or more embodiments, the processor 1002 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0127] In one or more embodiments, the computer-readable storage medium 1004 is an electronic system, a magnetic system, an optical system, an electromagnetic system, an infrared system, and / or a semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1004 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1004 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0128] In one or more embodiments, the storage medium 1004 stores computer program code 1006 configured to enable the system 1000 to be used to implement part or all of the described processes and / or methods (wherein such execution (at least in part) represents an EDA tool). In one or more embodiments, the storage medium 1004 also stores information that facilitates the implementation of part or all of the described processes and / or methods. In one or more embodiments, the storage medium 1004 stores a cell library 1007 of IC layout cells, the IC layout cells including one or more cells 100-700B as disclosed herein. In one or more embodiments, the storage medium 1004 stores one or more layout drawings 1009 corresponding to one or more layouts disclosed herein.

[0129] The EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1010 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for transmitting information and commands to the processor 1002.

[0130] The EDA system 1000 also includes a network interface 1012 coupled to the processor 1002. The network interface 1012 enables the system 1000 to communicate with a network 1014 to which one or more other computer systems are connected. The network interface 1012 includes: a wireless network interface, such as BLUETOOTH, wireless fidelity (WIFI), worldwide interoperability of microwave access (WIMAX), general packet radio service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as Ethernet (ETHERNET), universal serial bus (USB), or Institute of Electrical and Electronic Engineers (IEEE)-1364. In one or more embodiments, part or all of the described processes and / or methods are implemented in two or more systems 1000.

[0131] The system 1000 is configured to receive information via an I / O interface 1010. The information received via the I / O interface 1010 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 1002. The information is transmitted to the processor 1002 via a bus 1008. The EDA system 1000 is configured to receive information related to a user interface (UI) through the I / O interface 1010. The information is stored in a computer-readable medium 1004 as a user interface (UI) 1042.

[0132] In some embodiments, part or all of the described processes and / or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, part or all of the described processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the described processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the described processes and / or methods are implemented as a software application used by the EDA system 1000. In some embodiments, the system 1000 is implemented using, for example, a software application available from CADENCE DESIGN SYSTEMS, Inc. etc. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0133] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in memory or memory units, such as one or more of an optical disk (e.g., DVD), a magnetic disk (e.g., a hard disk), a semiconductor memory (e.g., ROM, RAM, a memory card), and similar media.

[0134] Fig.11 1 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1100 is used to make at least one of the following: (A) one or more semiconductor masks; or (B) at least one component in a layer of a semiconductor integrated circuit.

[0135] exist Fig.11In the present invention, the IC manufacturing system 1100 includes entities such as a design house 1120, a mask house 1130, and an IC manufacturer / fabricator (fab) 1150, which interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 1160. The entities in the system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design house 1120, the mask house 1130, and the IC fab 1150 are owned by a single larger company. In some embodiments, two or more of the design facility 1120, the mask facility 1130, and the IC fabrication facility 1150 exist simultaneously in a shared facility and use shared resources.

[0136] The design organization (or design team) 1120 generates an IC design layout diagram 1122. The IC design layout diagram 1122 includes, for example, Figures 1 to 8 One or more of the IC layout diagrams 100-800 discussed. The IC design layout diagram 1122 includes various geometric patterns designed for the IC device 1160. The geometric patterns correspond to the patterns of metal layers, oxide layers, or semiconductor layers that constitute the various components of the IC device 1160 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout diagram 1122 includes various IC features such as active areas, gate electrodes, source and drain electrodes, metal lines or through holes for interconnecting between layers, and openings for bonding pads to be formed in a semiconductor substrate (e.g., a silicon wafer), and various material layers disposed on the semiconductor substrate. The design organization 1120 implements an appropriate design program to form the IC design layout diagram 1122. The design program includes one or more of a logical design, a physical design, or placement and routing. The IC design layout diagram 1122 exists in one or more data files having information of the geometric patterns. For example, the IC design layout 1122 may be expressed in a GDSII file format or a Design Framework II (DFII) file format.

[0137] The mask mechanism 1130 includes data preparation 1132 and mask fabrication 1144. The mask mechanism 1130 uses the IC design layout 1122 to produce one or more masks 1145 for the various layers to be used to fabricate the IC device 1160 according to the IC design layout 1122. The mask mechanism 1130 performs mask data preparation 1132, wherein the IC design layout 1122 is translated into a representative data file (RDF). The mask data preparation 1132 provides the RDF to the mask fabrication 1144. The mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1145 or a semiconductor wafer 1153. The design layout 1122 is adjusted by the mask data preparation 1132 to comply with the specific characteristics of the mask writer and / or the requirements of the IC fabrication house 1150. exist Fig.11 , mask data preparation 1132 and mask fabrication 1144 are shown as separate components. In some embodiments, mask data preparation 1132 and mask fabrication 1144 may be collectively referred to as mask data preparation.

[0138] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts IC design layout 1122. In some embodiments, mask data preparation 1132 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0139] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that uses a set of mask creation rules containing certain geometric constraints and / or connectivity constraints to check the IC design layout 1122 that has undergone each process in OPC to ensure that there is sufficient margin to take into account the variability in the semiconductor manufacturing process and achieve similar effects. In some embodiments, MRC modifies the IC design layout 1122 to compensate for the effects of lithography implementation during mask production 1144, which can undo a portion of the modifications performed by OPC to meet the mask creation rules.

[0140] In some embodiments, mask data preparation 1132 includes lithography process checking (LPC), which simulates the process to be performed by IC fabrication plant 1150 to fabricate IC device 1160. LPC simulates this process based on IC design layout 1122 to create a simulated fabricated device (e.g., IC device 1160). Process parameters in the LPC simulation may include parameters associated with various processes of the IC fabrication cycle, parameters associated with tools used to fabricate ICs, and / or other aspects of the fabrication process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after a simulated fabricated device has been created by LPC, if the shape of the simulated device is not close enough to satisfy the design rules, OPC and / or MRC are repeated to further refine IC design layout 1122.

[0141] It should be understood that the above description of mask data preparation 1132 has been simplified for the purpose of clarity. In some embodiments, data preparation 1132 includes additional features such as logic operations (LOP) to modify IC design layout 1122 according to manufacturing rules. In addition, the processes applied to IC design layout 1122 during data preparation 1132 can be performed in a variety of different orders.

[0142] After mask data preparation 1132 and during mask fabrication 1144, a mask 1145 or a group of masks 1145 is fabricated based on the modified IC design layout 1122. In some embodiments, mask fabrication 1144 includes performing one or more lithographic exposures based on the IC design layout 1122. In some embodiments, an electron-beam (e-beam) or multiple electron-beam mechanism is used to form a pattern on a mask (reticle or stencil) 1145 based on the modified IC design layout 1122. Mask 1145 can be formed using various techniques. In some embodiments, mask 1145 is formed using a binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In another example, mask 1145 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 1145, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The masks generated by mask making 1144 are used in various processes. For example, such a mask is used in an ion implantation process for forming various doped regions in the semiconductor wafer 1153 , an etching process for forming various etched regions in the semiconductor wafer 1153 , and / or other suitable processes.

[0143] IC fabrication plant 1150 is an IC fabrication enterprise that includes one or more fabrication facilities for fabricating a variety of different IC products. In some embodiments, IC fabrication plant 1150 is a semiconductor foundry. For example, there may be a fabrication facility that provides front-end fabrication (front-end-of-line, FEOL) fabrication for multiple IC products, while a second fabrication facility may provide back-end fabrication (back-end-of-line, BEOL) fabrication for interconnects and packaging of IC products, and a third fabrication facility may provide other services for the foundry enterprise.

[0144] IC fabrication facility 1150 includes fabrication tools 1152 configured to perform various fabrication operations on semiconductor wafer 1153, thereby fabricating IC device 1160 according to a mask (e.g., mask 1145). In various embodiments, fabrication tools 1152 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or a low pressure chemical vapor deposition (LPCVD) furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes discussed herein.

[0145] IC fabrication plant 1150 uses mask 1145 produced by mask mechanism 1130 to fabricate IC device 1160. Therefore, IC fabrication plant 1150 at least indirectly uses IC design layout 1122 to fabricate IC device 1160. In some embodiments, semiconductor wafer 1153 is fabricated by IC fabrication plant 1150 using mask 1145 to form IC device 1160. In some embodiments, IC fabrication includes performing one or more photolithography exposures based at least indirectly on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other appropriate substrate with material layers formed thereon. Semiconductor wafer 1153 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and similar components (formed at subsequent manufacturing steps).

[0146] In some embodiments, a method for generating an integrated circuit layout diagram includes: arranging a first column of gate regions in a cell, the first column of gate regions having a first width extending from a first gate region of the first column of gate regions to a last gate region, whereby the first width is equal to a first multiple of the gate region spacing; arranging a second column of gate regions adjacent to the first column of gate regions in the cell, the second column of gate regions having a second width extending from the first gate region of the second column of gate regions to the last gate region, whereby the second width is equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple; defining first to fourth segments of a boundary of the cell by extending the first segment along the first gate region of the first column of gate regions, extending the second segment along the last gate region of the first column of gate regions, extending the third segment along the first gate region of the second column of gate regions, and extending the fourth segment along the last gate region of the second column of gate regions, whereby the boundary of the cell is non-rectangular based on one or both of the first segment and the third segment not being aligned with each other or the second segment and the fourth segment not being aligned with each other; and storing the integrated circuit layout diagram of the cell in a storage device. In some embodiments, arranging the first column of gate regions and the second column of gate regions includes aligning each gate region of the first column of gate regions with a corresponding gate region of the second column of gate regions. In some embodiments, defining the first segment to the fourth segment includes one of: aligning the first segment with the third segment with each other; or aligning the second segment with the fourth segment with each other. In some embodiments, extending the first segment includes aligning the first segment with a gate region of the second column of gate regions other than the first gate region or the last gate region, and extending the second segment includes aligning the second segment with a gate region of the second column of gate regions other than the first gate region or the last gate region. In some embodiments, the method includes defining the fifth to seventh segments of the boundary of the cell by extending the fifth segment along the first width, extending the sixth segment along the second width, and extending the seventh segment along the second column of gate regions a distance equal to the difference between the first width and the second width. In some embodiments, the method includes arranging a third column of gate regions adjacent to a second column of gate regions in a cell, the third column of gate regions having a third width extending from a first gate region of the third column of gate regions to a last gate region, whereby the third width is equal to a third multiple of the gate region spacing, the third multiple being greater than the first multiple; and a fifth segment and a sixth segment defining a boundary of the cell by extending the fifth segment along the first gate region of the third column of gate regions, and extending the sixth segment along the last gate region of the third column of gate regions. In some embodiments, arranging the first column of gate regions includes the first column of gate regions having a first height, and arranging the second column of gate regions includes the second column of gate regions having a second height different from the first height. In some embodiments, the sum of the first multiple and the second multiple is an odd number. In some embodiments, arranging each of the first column of gate regions and arranging the second column of gate regions includes each of the first gate region and the last gate region being a dummy gate region.In some embodiments, the method includes obtaining a cell from a memory device or another memory device before arranging the first column gate region and the second column gate region, wherein arranging the first column gate region includes removing a dummy gate region outside of the first column gate region to the last gate region of the first column gate region. In some embodiments, the method includes obtaining a cell from a memory device or another memory device before arranging the first column gate region and the second column gate region, wherein arranging the first column gate region and the second column gate region includes moving a gate region from one of the first column gate region and the second column gate region to the other of the first column gate region and the second column gate region.

[0147] In some embodiments, a non-transitory computer-readable storage medium includes computer program code for one or more programs, wherein the non-transitory computer-readable storage medium and the computer program code are configured to cause a processor to: arrange one or more first integrated circuit devices of a first column in a cell, wherein the first column has a first width extending from a first gate region of the one or more first integrated circuit devices to a last gate region, wherein the first width is equal to a first multiple of the gate region spacing; arrange one or more second integrated circuit devices of a second column adjacent to the first column in the cell, wherein the second column has a first width extending from a first gate region of the one or more second integrated circuit devices to a last gate region; A second width of the polar region, wherein the second width is equal to a second multiple of the gate region spacing, and the second multiple is greater than the first multiple; a first segment, a second segment, a third segment, and a fourth segment defining a boundary of the cell by: extending the first segment along the first gate region of the first column, extending the second segment along the last gate region of the first column, extending the third segment along the first gate region of the second column, and extending the fourth segment along the last gate region of the second column, wherein the boundary of the cell is non-rectangular based on one or both of the first segment and the third segment not being aligned with each other or the second segment and the fourth segment not being aligned with each other; and storing the integrated circuit layout diagram of the cell in a storage device. In some embodiments, the non-transitory computer-readable storage medium and the computer program code are configured to cause the processor to further: cause a first subset of the first gate region to the last gate region of one or more second integrated circuit devices to intersect with the first metal layer region; cause a first position and a second position at the intersection of the first subset and the first metal layer region to overlap with the first through-hole region, each first through-hole region corresponding to an electrical connection between a corresponding gate region of the first subset and the first metal layer region; cause the second metal layer region to extend across the first row and the second row and intersect with the first metal layer region at a third position between the first position and the second position; and cause the third position to overlap with a second through-hole region corresponding to an electrical connection between the first metal layer region and the second metal layer region. In some embodiments, a non-transitory computer-readable storage medium and a computer program code are configured to cause the processor to further: arrange one or more third integrated circuit devices of a third row adjacent to the second row in a cell, the third row having a third width extending from a first gate region to a last gate region of the one or more third integrated circuit devices; intersect a second subset of the first gate region to the last gate region of the one or more third integrated circuit devices with a third metal layer region; overlap a fourth position and a fifth position at the intersection of the second subset and the third metal layer region with a third through-hole region, each third through-hole region corresponding to an electrical connection between a corresponding gate region of the second subset and the third metal layer region; extend the second metal layer region across the third row and intersect the third metal layer region at a sixth position between the fourth position and the fifth position; and overlap the sixth position with a fourth through-hole region corresponding to an electrical connection between the second metal layer region and the third metal layer region.In some embodiments, the non-transitory computer readable storage medium and the computer program code are configured to cause the processor to arrange the one or more first integrated circuit devices of the first column by configuring the one or more first integrated circuit devices as clock source circuits. In some embodiments, the non-transitory computer readable storage medium and the computer program code are configured to cause the processor to arrange the first column by arranging the first column with a first height, the first height corresponding to a first number of fins of the fin field effect transistors of the one or more first integrated circuit devices, and to arrange the second column by arranging the second column with a second height, the second height corresponding to a second number of fins of the fin field effect transistors of the one or more second integrated circuit devices, wherein the first number of fins and the second number of fins are different from each other, and the first height and the second height are different from each other. In some embodiments, the non-transitory computer readable storage medium and the computer program code are configured to cause the processor to further: obtain cells from a storage device or another storage device before arranging the first column and the second column, wherein one or both of arranging the one or more first integrated circuit devices of the first column or arranging the one or more second integrated circuit devices of the second column include moving a key device from a first position to a second position.

[0148] In some embodiments, an electronic design automation system includes: a processor; and a non-transitory computer-readable storage medium including computer program code for one or more programs, the non-transitory computer-readable storage medium and the computer program code being configured to, together with the processor, cause the processor to: obtain a cell from the non-transitory computer-readable storage medium or another storage medium, wherein the cell includes a non-rectangular boundary, the non-rectangular boundary including: a first segment and a second segment, extending along a first gate region and a last gate region of a first column of gate regions, respectively, the total number of the first column of gate regions being equal to a first multiple of the gate region spacing; and a third segment and a fourth segment, extending along a first gate region and a last gate region of a second column of gate regions adjacent to the first column of gate regions, respectively, the total number of the second column of gate regions being equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple; and perform automatic placement and routing operations, including: placing the cell in an integrated circuit layout diagram; and arranging a plurality of electrical connections in the first column of gate regions and the second column of gate regions. In some embodiments, a non-transitory computer readable storage medium and computer program code are configured to, with a processor, cause the processor to place a cell in an integrated circuit layout by positioning a first row of gate regions in a first row of the integrated circuit layout corresponding to a first number of FinFET fins; and positioning a second row of gate regions in a second row of the integrated circuit layout corresponding to a second number of FinFET fins, the second number being different from the first number. In some embodiments, a non-transitory computer readable storage medium and computer program code are configured to, with a processor, cause the processor to arrange a plurality of electrical connections by positioning the electrical connections in a metal region at a location in the first row of gate regions, wherein the metal region extends from the first row of gate regions to the second row of gate regions.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating an integrated circuit layout diagram, characterized in that: include: Arranging a first column of gate regions in the cell, the first column of gate regions having a first width extending from a first gate region to a last gate region in the first column of gate regions, whereby the first width is equal to a first multiple of a pitch between gate regions; Arranging a second column of gate regions adjacent to the first column of gate regions in the cell, the second column of gate regions having a second width extending from a first gate region to a last gate region in the second column of gate regions, whereby the second width is equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple; The first segment, the second segment, the third segment and the fourth segment of the boundary of the cell are defined by: extending the first section along the first gate region of the first column of gate regions, extending the second section along the last gate region of the first column of gate regions, extending the third section along the first gate region of the second column of gate regions, and extending the fourth segment along the last gate region of the second column of gate regions, whereby the boundary of the cell is non-rectangular based on one or both of the first segment and the third segment being non-aligned with each other or the second segment and the fourth segment being non-aligned with each other; and The integrated circuit layout diagram of the cell is stored in a storage device.

2. The method according to claim 1, characterized in that Defining the first segment to the fourth segment includes one of the following: aligning the first section and the third section with each other; or The second section and the fourth section are aligned with each other.

3. The method according to claim 1, characterized in that: Extending the first section includes aligning the first section with gate regions of the second column of gate regions other than the first gate region or the last gate region, and Extending the second segment includes aligning the second segment with gate regions of the second column of gate regions other than the first gate region or the last gate region.

4. The method according to claim 1, characterized in that: Arranging the first column of gate regions includes the first column of gate regions having a first height, and Arranging the second column of gate regions includes the second column of gate regions having a second height different than the first height.

5. The method according to claim 1, characterized in that A sum of the first multiple and the second multiple is an odd number.

6. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer readable storage medium and the computer program code are configured to cause a processor to: Arranging a first column of one or more first integrated circuit devices in a cell, the first column having a first width extending from a first gate region to a last gate region of the one or more first integrated circuit devices, wherein the first width is equal to a first multiple of a gate region pitch; Arranging one or more second integrated circuit devices of a second column in the cell adjacent to the first column, the second column having a second width extending from a first gate region to a last gate region of the one or more second integrated circuit devices, wherein the second width is equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple; The first segment, the second segment, the third segment and the fourth segment of the boundary of the cell are defined by: extending the first section along the first gate region of the first column, extending the second section along the last gate region of the first column, extending the third segment along the first gate region of the second column, and Extending the fourth section along the last gate region of the second column, wherein the boundary of the cell is non-rectangular based on one or both of the first section and the third section being misaligned with each other or the second section and the fourth section being misaligned with each other; and storing an integrated circuit layout diagram of the cell in a storage device.

7. The non-transitory computer-readable storage medium according to claim 6, wherein: The non-transitory computer-readable storage medium and the computer program code are configured to cause the processor to arrange the one or more first integrated circuit devices of the first rank by configuring the one or more first integrated circuit devices as clock source circuits.

8. The non-transitory computer-readable storage medium of claim 6, wherein: The non-transitory computer-readable storage medium and the computer program code are configured to cause the processor arranging the first columns by arranging the first columns having a first height corresponding to a first number of fins of FinFETs of the one or more first integrated circuit devices, arranging the second columns by arranging the second columns having a second height corresponding to a second number of fins of the fin field effect transistors of the one or more second integrated circuit devices, in The first number of fins and the second number of fins are different from each other, and The first height and the second height are different from each other.

9. An electronic design automation system, characterized in that: include: processor; as well as A non-transitory computer-readable storage medium comprising computer program code for one or more programs, the non-transitory computer-readable storage medium and the computer program code being configured to, together with the processor, cause the processor to: Obtaining a cell from the non-transitory computer-readable storage medium or another storage medium, wherein the cell comprises a non-rectangular boundary, the non-rectangular boundary comprising: The first section and the second section extend along the first gate region and the last gate region of the first column of gate regions, respectively, the total number of the first column of gate regions being equal to a first multiple of the gate region spacing; and A third section and a fourth section respectively extend along a first gate region and a last gate region of a second column of gate regions adjacent to the first column of gate regions, the total number of the second column of gate regions being equal to a second multiple of the gate region spacing, the second multiple being greater than the first multiple; and Performs automated placement and routing operations, including: placing the cell in an integrated circuit layout; and A plurality of gates are arranged to be electrically connected to the first column gate region and the second column gate region.

10. The electronic design automation system according to claim 9, characterized in that: The non-transitory computer-readable storage medium and the computer program code are configured to, together with the processor, cause the processor to place the cell in the integrated circuit layout by: Positioning the first column of gate regions in a first column of the integrated circuit layout corresponding to a first number of FinFET fins; as well as The second column of gate regions is positioned in a second column of the integrated circuit layout corresponding to a second number of FinFET fins, the second number being different from the first number.

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