Memory device including page buffer

Abstract

The invention relates to a memory device including a page buffer. The memory device includes a cell string including a plurality of memory cells, and a page buffer coupled to the cell string. The page buffer includes latches having cross-coupled transistors. Data transferred from the cell string to the page buffer is input to gates of a plurality of transistors included in the page buffer.

Description

Technical Field

[0001] One or more embodiments of the present disclosure described herein relate to a memory device, and more particularly, to a page buffer included in the memory device. Background Art

[0002] The data processing system includes a memory system or a data storage device. The data processing system can be developed to store a larger capacity of data in the data storage device, to store data faster in the data storage device and to read data stored in the data storage device faster. The memory system or the data storage device can include non-volatile memory cells and / or volatile memory cells for storing data. Summary of the invention

[0003] Embodiments described herein provide a memory device including a page buffer capable of reducing current consumption.

[0004] One embodiment of the present disclosure may provide a page buffer included in a memory device, which is insensitive to fluctuations in an internal voltage in the memory device and may more easily identify or recognize data output from a nonvolatile memory cell.

[0005] In addition, one embodiment of the present disclosure can provide a page buffer including at least one transistor designed to have a shorter channel than conventional transistors (because the transistors constituting the page buffer in a memory device do not need to have a long channel), thereby reducing the size of the page buffer and increasing the integration of the memory device.

[0006] In one embodiment, a memory device may include: a cell string including a plurality of memory cells; and a page buffer coupled to the cell string, the page buffer including a latch having cross-coupled transistors. Data transmitted from the cell string to the page buffer may be input to gates of a plurality of transistors included in the page buffer.

[0007] The plurality of transistors may include: a first node of a cross-coupled transistor; a first PMOS transistor coupled to a power supply voltage node; and a first NMOS transistor coupled to the first node.

[0008] The cross-coupled transistors may include: a second NMOS transistor having a gate coupled to a first node; and a third NMOS transistor having a gate coupled to a second node temporarily storing a second value inverted from a first value temporarily stored in the first node.

[0009] The first NMOS transistor may be disposed between the first node and the third NMOS transistor.

[0010] The page buffer may further include a third PMOS transistor disposed between the first node and the first PMOS transistor. An inverted signal of the sense set signal may be input to a gate of the third PMOS transistor.

[0011] The page buffer may further include a second PMOS transistor coupled to a power supply voltage node and a fourth NMOS transistor coupled to a ground voltage node. An inverted signal of a sensing reset signal may be input to gates of the second PMOS transistor and the fourth NMOS transistor.

[0012] The page buffer may include a first node having a logic high level during a precharge section. The first node may be configured to have a logic high level when data is transferred from the cell string and to transition from the logic high level to a logic low level when no data is transferred from the cell string.

[0013] Each of the memory cells may be configured to store multi-bit data. When a read voltage is applied to at least one of the memory cells, data transmitted from the cell string may include 1-bit data identified by the read voltage among the multi-bit data.

[0014] In another embodiment, a memory device may include: a cell string including a plurality of memory cells; a page buffer connected to the cell string, the page buffer including a latch having cross-coupled transistors; a voltage generating circuit configured to generate a read voltage and a pass voltage; and a control circuit configured to generate a control signal to be input to the page buffer and the voltage generating circuit.

[0015] Data transferred from the cell strings to the page buffer may be input to gates of a plurality of transistors included in the page buffer.

[0016] The plurality of transistors may include: a first node of a cross-coupled transistor; a first PMOS transistor coupled to a power supply voltage node; and a first NMOS transistor coupled to the first node.

[0017] The cross-coupled transistors may include: a second NMOS transistor having a gate coupled to a first node; and a third NMOS transistor having a gate coupled to a second node temporarily storing a second value inverted from a first value temporarily stored in the first node.

[0018] The first NMOS transistor may be disposed between the first node and the third NMOS transistor.

[0019] The page buffer may further include a third PMOS transistor disposed between the first node and the first PMOS transistor. An inverted signal of the sense set signal may be input to a gate of the third PMOS transistor.

[0020] The page buffer may further include a second PMOS transistor coupled to a power supply voltage node and a fourth NMOS transistor coupled to a ground voltage node. An inverted signal of a sensing reset signal may be input to gates of the second PMOS transistor and the fourth NMOS transistor.

[0021] The page buffer may include a first node having a logic high level during a precharge section. The first node may be configured to have a logic high level when data is transferred from the cell string and to transition from the logic high level to a logic low level when no data is transferred from the cell string.

[0022] Each of the memory cells may be configured to store multi-bit data. When a read voltage is applied to at least one of the memory cells, data transmitted from the cell string may include 1-bit data identified by the read voltage among the multi-bit data.

[0023] The page buffer and at least one other page buffer are coupled to the cell string. The number of page buffers coupled to the cell string may be equal to or greater than the number of data bits stored in each memory cell.

[0024] The cell string and the page buffer may be connected to each other through a bit line and a sensing output node. The memory device may further include: a precharge circuit configured to precharge the bit line and the sensing output node; and at least one switch configured to control the connection between the bit line and the sensing output node.

[0025] At least one switch may be controlled by a signal output from the control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The description herein refers to the drawings, wherein like reference numerals refer to like parts throughout.

[0027] Figure 1 A memory device according to one embodiment of the present disclosure is illustrated.

[0028] Figure 2 A page buffer included in a memory device according to one embodiment of the present disclosure is illustrated.

[0029] Figure 3A first example of a page buffer according to one embodiment of the present disclosure is illustrated.

[0030] Figure 4 An operation of a page buffer according to one embodiment of the present disclosure is illustrated.

[0031] Figure 5 A second example of a page buffer according to one embodiment of the present disclosure is illustrated.

[0032] Figure 6 Illustrated Figure 3 and Figure 5 Operational comparison between page buffers is shown. DETAILED DESCRIPTION

[0033] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0034] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “an exemplary embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc.) are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiment.

[0035] In this disclosure, the terms "comprises," "includes," "contains," and "have" are open ended. As used in the appended claims, these terms specify the presence of the elements described and do not preclude the presence or addition of one or more other elements. The terms in the claims do not preclude the device from including additional components (e.g., interface units, circuits, etc.).

[0036] In the present disclosure, various units, circuits or other components may be described or claimed as being "configured to" perform one or more tasks. In this case, "configured to" is used to represent a structure by indicating that the block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. In this way, the block / unit / circuit / component can be considered to be configured to perform a task even when the specified block / unit / circuit / component is not currently working (e.g., not turned on or activated). The blocks / units / circuit / components used with the "configured to" language include hardware, such as circuits, memories storing executable program instructions to implement operations, etc. In addition, "configured to" may include a general structure (e.g., a general circuit) that is manipulated by software and / or firmware (e.g., an FPGA or a general processor executing software) to operate in a manner that can perform the tasks in question. "Configured to" may also include adjusting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture a device (e.g., an integrated circuit) suitable for implementing or performing one or more tasks.

[0037] As used in this disclosure, the term "circuit" or "logic" refers to all of the following: (a) hardware circuit implementations only (e.g., implementations in analog and / or digital circuits only) and (b) combinations of circuits and software (and / or firmware), such as (as applicable): (i) a combination of processors or (ii) portions of processors / software (including digital signal processors), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions, and (c) circuits, such as microprocessors or portions of microprocessors, that require software or firmware to operate even if the software or firmware is not physically present. The definition of "circuit" or "logic" applies to all uses of the term in this application (including in any claims). As another example, as used in this application, the term "circuit" or "logic" also covers implementations of only a processor (or multiple processors) or a portion of a processor and its (or their) accompanying software and / or firmware. The term "circuit" or "logic" also covers, for example (and if applicable to a particular claim element) an integrated circuit for a storage device.

[0038] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns that follow them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms "first" and "second" do not necessarily imply that the first value must be written before the second value. In addition, although various elements may be identified using terms herein, these elements are not limited by these terms. These terms are used to distinguish an element from another element that has the same or similar name. For example, a first circuit may be distinguished from a second circuit.

[0039] Furthermore, the term "based on" is used to describe one or more factors that influence a determination. The term does not exclude other factors that may influence the determination. That is, the determination may be based only on those factors or at least in part on those factors. Consider the phrase "determining A based on B." While in this case, B is a factor that influences the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based only on B.

[0040] In this article, an item of data, a data item, a data entry or an entry of data can be a bit sequence. For example, a data item can include the content of a file, a part of a file, a page in a memory, an object in an object-oriented program, a digital message, a digital scanned image, a part of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to one embodiment, a data item can include a discrete object. According to another embodiment, a data item can include an information unit within a transmission packet between two different components.

[0041] Embodiments will now be described with reference to the drawings, wherein like reference numerals refer to like elements throughout.

[0042] Figure 1 A memory device 150 including a memory cell array circuit formed in a memory die is illustrated according to one embodiment of the present disclosure.

[0043] Reference Figure 1 , the memory device 150 may include at least one memory group 330 having a plurality of cell strings 340. Each cell string 340 may include a plurality of nonvolatile memory cells MC0 to MCn-1 connected to corresponding bit lines in a plurality of bit lines BL0 to BLm-1. The cell strings 340 are arranged in respective columns of the memory group 330, and each cell string 340 may include at least one drain select transistor DST and at least one source select transistor SST. The nonvolatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain select transistor DST and the source select transistor SST. Each of the nonvolatile memory cells MC0 to MCn-1 may be configured as a multi-level cell (MLC) storing a data item having a plurality of bits per cell. The cell string 340 may be electrically connected to a corresponding bit line in the bit lines BL0 to BLm-1.

[0044] In one embodiment, the memory group 330 may include NAND-type flash memory cells MC0 to MCn-1. In another embodiment, the memory group 330 may be implemented as a NOR-type flash memory, a hybrid flash memory in which at least two different types of memory cells are mixed or combined, or a single-chip NAND flash memory in which a controller is embedded in a single memory chip. In one embodiment, the memory group 330 may include a flash memory cell including a charge trap flash (CTF) layer including a conductive floating gate or an insulating layer.

[0045] According to one embodiment, Figure 1 The memory device 150 shown in the figure may include at least one memory block. The memory group 330 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each memory block in the memory device 150 may be implemented as a 3D structure (e.g., a vertical structure). Each memory block may have a three-dimensional structure extending from a first direction to a third direction (e.g., an x-axis direction, a y-axis direction, and a z-axis direction).

[0046] The memory group 330 including at least one memory block may be connected to a plurality of bit lines BL, a plurality of source selection lines SSL, a plurality of drain selection lines DSL, a plurality of word lines WL, a plurality of dummy word lines DWL, and a plurality of common source lines CSL. In one embodiment, the memory group 330 may include, for example, a plurality of NAND strings NS that may correspond to the cell strings 340, respectively. Each NAND string NS may include a plurality of memory cells MC and may be connected to corresponding bit lines in the bit lines BL. In addition, the source selection transistor SST of each NAND string NS may be connected to the common source line CSL, and the drain selection transistor DST of each NAND string NS may be connected to the corresponding bit line BL. In each NAND string NS, the memory cell MC may be arranged between the source selection transistor SST and the drain selection transistor DST.

[0047] The memory device 150 may include a voltage supply circuit 170, which may supply a word line voltage, for example, one or more predetermined voltages such as a program voltage, a read voltage, and a pass voltage, to a corresponding word line among the word lines according to an operation mode, or may supply a voltage to a bulk (for example, a well region) in which each memory block including the memory cells MC is formed. In this case, a voltage generation operation of the voltage supply circuit 170 may be performed under the control of the control circuit 180. In addition, the voltage supply circuit 170 may generate a plurality of variable read voltages to distinguish a plurality of data items from each other.

[0048] In response to the control of the control circuit 180, one of the memory blocks (or sectors) of the memory cell array may be selected, and one of the word lines of the selected memory block may be selected. Word line voltages may be supplied separately to the selected word lines and unselected word lines of the memory group 330. The voltage supply circuit 170 may include a voltage generating circuit for generating target voltages having various levels that may be applied to the word lines of the memory group 330.

[0049] The memory device 150 may also include a read / write circuit 320 controlled by the control circuit 180. The read / write circuit 320 may operate as a sense amplifier or a write driver according to the operation mode. For example, in a verification operation and a read operation, the read / write circuit 320 may operate as a sense amplifier for reading data items from a memory cell array. In a programming operation, the read / write circuit 320 may operate as a write driver that controls the potential of a bit line according to a data item to be stored in the memory cell array. The read / write circuit 320 may receive data items to be programmed to the cell array from a page buffer during a programming operation. The read / write circuit 320 may drive the bit line based on an input data item. To this end, the read / write circuit 320 may include a plurality of page buffers (PB) 322, 324, 326, wherein each page buffer corresponds to each column or each bit line, or each column pair or each word line pair. According to one embodiment, a plurality of latches may be included in each of the page buffers 322, 324, 326. According to one embodiment, the number of latches or page buffers coupled to each bit line may be equal to or greater than the number of data bits stored in the memory cells MC.

[0050] The page buffers 322, 324, 326 may be coupled to a data input / output device (e.g., a serialization circuit or a serializer) through a plurality of buses BUS. When each of the page buffers 322, 324, 326 is coupled to the data input / output device through a different bus, a delay that may occur in data transmission from the page buffers 322, 324, and 326 may be reduced. For example, each page buffer 322, 324, 326 may perform data transmission without waiting time.

[0051] According to one embodiment, the memory device 150 may receive a write command, write data, and information about a location where the write data is to be stored (e.g., a physical address). The control circuit 180 causes the voltage supply circuit 170 to generate a program pulse, a pass voltage, etc. for a program operation performed in response to the write command, and to generate one or more voltages for a verification operation performed after the program operation.

[0052] When programming multi-bit data items in the nonvolatile memory cells included in the memory group 330, the error rate may be higher than the error rate when storing single-bit data items in the nonvolatile memory cells. For example, errors in the nonvolatile memory cells may be caused by inter-cell interference (CCI). In order to reduce errors in the nonvolatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the stored data items between the nonvolatile memory cells should be reduced.

[0053] To this end, the memory device 150 may perform an incremental step pulse programming (ISPP) operation to effectively form a narrow threshold voltage distribution of the non-volatile memory cells. In one embodiment, the memory device 150 may use the ISPP operation to perform a multi-step programming operation. For example, the memory device 150 may divide the programming operation into a least significant bit (LSB) programming operation and a most significant bit (MSB) operation according to a predetermined order between non-volatile memory cells or pages.

[0054] The multi-bit values ​​programmed in the memory cells in the NAND flash memory (e.g., NAND-type flash memory cells MC0 to MCn-1 in the memory group 330) can be determined based on the threshold voltage window or threshold voltage distribution to which the threshold voltage of the cell belongs. As the size of each memory cell decreases and more bits (e.g., 3, 4, or 5 bits) of data are programmed per memory cell, the width of the threshold voltage window used to represent each multi-bit value becomes narrower, thereby increasing the error rate when determining the multi-bit value stored in the memory cell. This is because when the amount of charge stored in each memory cell decreases with the feature size, the process variation becomes more extensive, resulting in large differences in the threshold voltages of different memory cells storing the same value. As a result, it becomes increasingly difficult to determine which value the threshold voltage of a memory cell corresponds to.

[0055] According to one embodiment, the control circuit 180 may include a read retry table (RRT). The RRT may be stored in the memory device 150. A read error may occur in the process of applying a read voltage to a non-volatile memory cell in the memory device 150 through a word line and reading data stored in the non-volatile memory cell. The control circuit 180 in the memory device 150 may manage information about a read retry mechanism for resolving a read error. One of the information about the read retry mechanism is to read the RRT. The read retry mechanism uses the RRT for a record position where an error has occurred, so that the memory device 150 can ensure data integrity by applying an appropriate correction value (e.g., changing the read voltage level) when rereading.

[0056] Figure 2 A page buffer included in a memory device according to one embodiment of the present disclosure is illustrated.

[0057] Reference Figure 1 and Figure 2 , the cell string 340 may include a plurality of memory cells connected between at least one transistor connected to the drain selection line DSL and at least one transistor connected to the source selection line SSL. In order to read data stored in a specific memory cell among the plurality of memory cells, a read voltage VREAD may be applied to the specific memory cell storing the data, and a pass voltage VPASS may be applied to other memory cells. When various voltages are applied to the cell string 340, a current path including the bit line BL0 may be formed depending on whether data corresponding to the read voltage VREAD is stored in a specific memory cell, so that the current I CELL A current path including the bit line BL0 may flow. Based on the current I flowing through the bit line BL0 CELL The page buffer 322 may read data stored in a specific memory cell to which the read voltage VREAD is applied and temporarily store the read data therein.

[0058] The bit line BL0 and the page buffer 322 are coupled to each other through the sensing output node SO. The bit line BL0 and the sensing output node SO can be switched by the bit line selection signal SELBL and the disconnection signal V DECOUPLE and be connected or disconnected.

[0059] The potential or voltage level of the sense output node SO may be based on data stored in and output from a memory cell included in the cell string 340 or a voltage level of the sense output node SO by a precharge signal PRECHSO_N and a clamp signal V CLAMP The precharge signal PRECHSO_N can be used to use a predetermined voltage (eg, core voltage VCORE, see Figure 4 ) precharges the sensing output node SO and clamps the signal V CLAMP It can be used to apply a predetermined voltage to the sensing output node SO at a predetermined timing point to reduce noise and increase the sensing margin. According to one embodiment, the precharge signal PRECHSO_N and the clamp signal V CLAMP The voltage level of V may be preset to shift the threshold voltage Vth of the transistor so that the core voltage VCORE may be applied to the sense output node SO.

[0060] Reference Figure 4 The read operation or verification operation can generally include three operation sections. The first section is the bit line precharge section. PRE , where the level of the bit line rises above a certain level that can be sensed. The second section is the bit line evaluation section t EVAL, wherein the level of the bit line is maintained or reduced according to the current flowing through the cell string. The third section is the bit line sensing section t SENSE , which is used to sense how much the level of the bit line drops according to the current flowing through the cell string to determine whether the corresponding memory cell is programmed.

[0061] If the memory cell to which the read voltage VREAD is applied is programmed, that is, if the threshold voltage of the corresponding cell is greater than the verification voltage, the corresponding cell will not be turned on, so that a current path is not formed in the cell string including the corresponding cell, and the voltage levels of the bit line BL0 and the sensing output node SO can be maintained at a high level (e.g., VCORE). If the corresponding cell is not programmed, that is, if the threshold voltage of the corresponding cell is less than the verification voltage, the corresponding cell will be turned on, so that a current path is formed in the cell string including the corresponding cell. In this case, the voltage levels of the bit line BL0 and the sensing output node SO, which have been precharged to a high level, can drop to a lower level. As described above, since the levels of the bit line BL0 and the sensing output node SO vary differently depending on whether the memory cell to which the read voltage VREAD is applied is programmed, the data stored in the memory cell can be sensed and stored in the page buffer 322. This will be referred to later. Figure 4 Describes a read operation.

[0062] Figure 3 A first example of a page buffer according to one embodiment of the present disclosure is illustrated.

[0063] Reference Figure 3 The page buffer 322 may include a latch implemented with a cross-coupled inverter. The cross-coupled inverter may include two nodes QS and QS_N that temporarily store opposite values, a plurality of PMOS transistors (e.g., two PMOS transistors P1 and P2), and a plurality of NMOS transistors (e.g., two NMOS transistors N1 and N2).

[0064] The page buffer 322 may further include a fifth NMOS transistor N5 connected to the sensing output node SO, a fourth NMOS transistor N4 controlled by the sensing set signal SSET, and a third NMOS transistor N3 controlled by the sensing reset signal SRST.

[0065] The fifth NMOS transistor N5 can be turned on or off in response to the voltage level of the sensing output node SO. PRE In the embodiment, the voltage level of the sensing output node SO may be maintained at the core voltage VCORE in response to the precharge signal PRECHSO_N. When the voltage level of the sensing output node SO is maintained at the core voltage VCORE, the fifth NMOS transistor N5 may be turned on.

[0066] When the sense set signal SSET is activated, the fourth NMOS transistor N4 may be turned on. Therefore, the second node QS_N may be coupled to a ground voltage node for a ground voltage. The first node QS has a value opposite to that of the second node QS_N, that is, the first node QS may be coupled to a power supply voltage node for a power supply voltage, for example, a core voltage node for a core voltage VCORE.

[0067] When the sensing reset signal SRST is activated, the third NMOS transistor N3 may be turned on. Therefore, the first node QS is coupled to the ground voltage node. The second node QS_N having a value opposite to that of the first node QS may be coupled to the core voltage VCORE node.

[0068] Figure 4 An operation of a page buffer according to one embodiment of the present disclosure is illustrated.

[0069] Reference Figure 4 , in the pre-charge section t PRE In the embodiment, the sensing output node SO can be adjusted and maintained at the core voltage VCORE. The sensing reset signal SRST is activated so that the first node QS is coupled to the ground voltage node.

[0070] In the bit line evaluation section t EVAL In the embodiment, the voltage level of the sense output node SO may be changed by a current path formed according to whether data is stored in a specific memory cell to which the read voltage VREAD is applied. For example, in the case where data corresponding to the read voltage VREAD is not stored in the memory cell (ERS), the voltage level of the sense output node SO may be reduced to a first level (V CLAMP -V TH When data corresponding to the read voltage VREAD is stored in the memory cell (PGM), the voltage level of the sense output node SO may be lowered to a second level (VCORE-V TRIP ). The first level (V CLAMP -V TH ) is lower than the second level (VCORE-V TRIP Here, a trip voltage V is generated due to a resistance component included in a current path formed by the cell string 340, the bit line BL0, and the sense output node SO. TRIP For example, the trip voltage V TRIP Can be compared with the current I flowing through the current path CELL and bit line evaluation section t EVAL In addition, the trip voltage V TRIP The capacitance C of the sensing output node SO can be SO Inversely proportional.

[0071] In one embodiment, Figure 3 The fifth NMOS transistor N5 in the embodiment can be designed to be turned on or off by a preset voltage VGS_N5. In this paper, the fifth NMOS transistor N5 can be turned on or off by a first level (V CLAMP -V TH ) is cut off, but can be turned off by the second level (VCORE-V TRIP ) is turned on.

[0072] When the bit line sensing section t SENSE When the sensing set signal SSET is activated in the READ state, the page buffer 322 may store data corresponding to the voltage level of the sensing output node SO. When data is stored in the memory cell to which the read voltage VREAD is applied (PGM), the first node QS may change to a logic high level. When data is not stored in the memory cell to which the read voltage VREAD is applied (ERS), the first node QS may change to a logic low level.

[0073] Reference Figure 3 and Figure 4 , a precharge section t before sensing data output from a cell string PRE In the bit line sensing section t SENSE When data is stored in a specific memory cell to which the read voltage VREAD is applied, the first node QS may be turned into a logic high level (QS flips). On the contrary, when it is determined that no data is stored in the specific memory cell to which the read voltage VREAD is applied, the low level of the first node QS is maintained (QS does not flip).

[0074] According to one embodiment, in the process of identifying data stored in a memory cell to which a read voltage VREAD is applied by a page buffer 322, it may be difficult to identify the data based on the position of the memory cell to which the read voltage VREAD is applied. For example, when the memory cell to which the read voltage VREAD is applied is located at the boundary between a memory cell in which data is programmed and a memory cell in which data is erased (unprogrammed), when the sense set signal SSET is activated, an error may occur in the value stored in the first node QS in the page buffer 322. In particular, a short circuit current may occur between the core voltage VCORE and the ground voltage in the page buffer 322, so that a latch fighting phenomenon may occur. Here, the latch fighting phenomenon indicates that the voltage level of the sense output node SO as the input node of the page buffer 322 may change or fluctuate. Due to the latch fighting phenomenon, a situation where the core voltage VCORE becomes low or the ground voltage becomes high may occur. In order to avoid this situation, the size of the cross-coupled inverter (i.e., latch) should be increased or the channel width of the fifth NMOS transistor N5 should be increased. In these solutions, the integration level of the memory device 150 may be reduced.

[0075] When the power supply (ie, core voltage VCORE) in the memory device 150 fluctuates, even if the current I flowing in the current path formed by the cell string 340 CELL Similarly, the page buffer 322 may also determine the voltage level of the sense output node SO differently. That is, even if the data stored in the memory cell to which the read voltage VREAD is applied is not changed, the logic value stored in the page buffer 322 may be different. This is because the second level (VCORE-V TRIP ) may be different based on the level of the core voltage VCORE. When the latch current (I LATCH , see Figure 6 ) is greater than the current flowing through the fifth NMOS transistor N5, there may be an operation problem that the logic value stored in the second node QS_N does not change. Therefore, based on the case where data corresponding to the read voltage VREAD is stored in the memory cell (PGM) and the case where data corresponding to the read voltage VREAD is not stored in the memory cell (ERS), a phenomenon in which the values ​​of the first node QS and the second node QS_N transition in a specific direction but not in the opposite direction may occur.

[0076] The sequential logic circuits such as latches included in the page buffer 322 need to store state information. Therefore, the sequential logic circuits can be distinguished from the combinational logic circuits configured to output only the combination of current input values. For the nature of state information storage, the latch is a component with two stable states that can be used to store state information. In this way, the latch has a simple purpose of storing logic values, that is, storing a logic value (e.g., 1 or 0). However, latches can be used in various static and dynamic implementations. One of the most frequently implemented forms is to use positive feedback or regeneration.

[0077] Positive feedback and negative feedback are two types of feedback systems used in electronic circuits. The main difference between positive feedback and negative feedback is the way in which the feedback signal affects the input signal. In a negative feedback scheme, the feedback signal is out of phase with the input signal. When the input signal increases, the feedback signal decreases, and when the input signal decreases, the feedback signal increases. Negative feedback schemes can have the effect of reducing operating gain and improving operating stability. Furthermore, negative feedback schemes can be used to reduce distortion and noise and improve operating linearity.

[0078] Positive feedback schemes can speed up signal conversion / transition speed. In a positive feedback scheme, the output signal is fed back to the input node in a manner that enhances the input signal, which in turn can be done in a manner that enhances the output signal. This mechanism can cause a "regeneration" or "amplification" effect that can increase the gain on the circuit and speed up the change of the signal.

[0079] Problems caused by misalignments in the CMOS latch structure in page buffer 322 (eg, imperfect manufacturing technology or design asymmetry) increase the need to adjust the strength of the positive feedback during latch operation.

[0080] Figure 5 A second example of a page buffer according to one embodiment of the present disclosure is illustrated.

[0081] Reference Figure 5 , the page buffer 422 can be configured by a plurality of transistors P 11 and N 11 The voltage level of the sensing output node SO is detected so that the sensitivity with respect to the voltage level of the sensing output node SO can be improved. In addition, the page buffer 422 may include a cross-coupled NMOS transistor NMOS transistor. 12 、N 13 The latch structure of the page buffer 422 is not a latch structure including a cross-coupled inverter, so that the latch current I LATCH The amount.

[0082] Reference Figure 3 and Figure 4, the preset voltage VGS_N5 for sensing data is determined by one transistor (ie, the fifth NMOS transistor N5). When the power supply (ie, the core voltage VCORE or the ground voltage) in the memory device 150 fluctuates, the operation stability may be deteriorated. On the other hand, referring to Figure 4 and Figure 5 , when the voltage level of the sensing output node SO is the second level (VCORE-V TRIP ), multiple transistors P 11 、N 11 The level of the reference voltage for detecting the voltage level of the sense output node SO is determined so that even if a power source (ie, a core voltage VCORE or a ground voltage) in the memory device 150 fluctuates, operation stability may be improved.

[0083] Reference Figure 5 , the page buffer 422 may include a first PMOS transistor P coupled to a core voltage VCORE node. 11 and the second PMOS transistor P 12 The first PMOS transistor P 11 and the second PMOS transistor P 12 The sensing output node SO may be connected to the first PMOS transistor P 11 The gate of the second PMOS transistor P 12 of the gate.

[0084] The third PMOS transistor P 13 The first PMOS transistor P may be arranged or provided 11 The sensing set inversion signal SSET_N may be applied to the third PMOS transistor P 13 The gate of the second PMOS transistor P 12 No additional transistor may be provided between the second node QS_N.

[0085] The first node QS and the second node QS_N are respectively coupled to a third NMOS transistor N2 constituting a cross-coupled NMOS transistor. 13 and the second NMOS transistor N 12 .

[0086] A first NMOS transistor N having a gate coupled to the sense output node SO 11 The first node QS and the third NMOS transistor N may be provided or arranged 13 between.

[0087] The third NMOS transistor N 13The fourth NMOS transistor N 14 The second NMOS transistor N 12 and ground voltage nodes.

[0088] The precharge section before sensing data is t PRE In the bit line sensing section t SENSE When it is determined that the data corresponding to the read voltage VREAD is stored in a specific memory cell, the first node QS may be maintained at a logic high level (QS does not flip). Conversely, when it is determined that the data bit corresponding to the read voltage VREAD is stored in a specific memory cell, the first node QS may transition to a logic low level (QS flips). Figure 3 and Figure 5 In the described two different page buffers 322 , 422 , the transition of the first node QS according to the data corresponding to the read voltage VREAD may be implemented differently.

[0089] Figure 6 Illustrated Figure 3 and Figure 5 Operational comparison between page buffers is shown.

[0090] Reference Figure 6 , the upper waveform shows Figure 3 The operation of the page buffer 322, and the lower waveform diagram shows Figure 5 As an example, the latch current I is described when the first node QS in the page buffer 322, 422 changes from a logic low level to a logic high level. LATCH Here, the latch current I LATCH A short-circuit current generated during the transition of the first node QS may be included.

[0091] As described above, the transition of the first node QS from a logic low level to a logic high level in the two different page buffers 322 and 422 occurs under different conditions opposite to each other. Therefore, in order to measure the latch current I generated during the transition process LATCH The voltage level of the sense output node SO can be adjusted or changed in the opposite direction (ie, from low to high, from high to low) to measure the latch current I LATCH .

[0092] According to one embodiment, the power supply (eg, core voltage VCORE or ground voltage) may vary, and the reference voltage used to determine the data transition may also vary. In addition, according to one embodiment, the trip voltage V TRIP The amplitude can also vary.

[0093] Reference Figure 6 In the upper waveform diagram of FIG. 1 , when the core voltage VCORE of the page buffer 322 is 1.9 V and the voltage of the sense output node SO is 1.055 V, the first node QS has been transformed. The short-circuit current generated when the first node QS is transformed is about 4.4 μA.

[0094] Reference Figure 6 In the lower waveform diagram of FIG. 4 , when the core voltage VCORE of the page buffer 422 is 1.9 V and the voltage of the sense output node SO is 0.977 V, the first node QS has been transformed. The short-circuit current generated when the first node QS is transformed is about 0.8 μA.

[0095] Compare Figure 6 As shown in the waveform diagram of FIG, the difference in short-circuit current generated when the first node QS of the page buffers 322 and 422 is transformed is five times or more. These short-circuit currents cause a difference in power consumption of the page buffers 322 and 422. When the short-circuit current is large, the power applied to the page buffers 322 and 422 (i.e., the core voltage VCORE or the ground voltage) may become unstable. Therefore, Figure 3 Compared with the page buffer 322 in Figure 5 The page buffer 422 in the latch current I LATCH Reducing it to about 1 / 5 times can also improve the operational stability.

[0096] in addition, Figure 5 The page buffer 422 in FIG. 4 may have advantages. Figure 3 Compared to the page buffer 322 in FIG. 4 , in the page buffer 422 , the influence of the core voltage VCORE on the reference voltage for determining data corresponding to the read voltage VREAD may be reduced by about 40%.

[0097] In addition, Figure 3 Compared with the page buffer 322, Figure 5 The page buffer 422 does not need to include a transistor having a long channel, thereby reducing the size of the page buffer 422. The integration degree of the memory device 150 can be improved.

[0098] As described above, a memory device according to one embodiment of the present invention may reduce the amount of current consumed during a data input / output operation and thus may have improved performance in a low-power operating environment.

[0099] Method described herein, process and / or operation can be performed by the code or instruction that will be performed by computer, processor, controller or other signal processing device.Computer, processor, controller or other signal processing device can be those described herein or some except the element described herein.Because the algorithm of the basis of formation method (or the operation of computer, processor, controller or other signal processing device) is described in detail, the code or instruction for realizing the operation of method embodiment can convert computer, processor, controller or other signal processing device into the special processor for performing the method herein.

[0100] In addition, another embodiment may include a computer-readable medium for storing the above code or instructions, for example, a non-transitory computer-readable recording medium. The computer-readable medium may be a volatile memory, a non-volatile memory, or other storage device, which may be removably or fixedly connected to a computer, processor, controller, or other signal processing device that executes the code or instructions for performing the operations of the method embodiments or apparatus embodiments herein.

[0101] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented, for example, in non-transitory logic including hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits, including but not limited to application specific integrated circuits, field programmable gate arrays, combinations of logic gates, systems on a chip, microprocessors, or another type of processing or control circuitry.

[0102] When implemented at least in part with software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing the code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or some in addition to the elements described herein. Because the algorithm forming the basis of the method (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) is described in detail, the code or instructions for implementing the operation of the method implementation method may convert a computer, processor, controller, or other signal processing device into a dedicated processor for performing the method described herein.

[0103] Although the present teaching has been illustrated and described with respect to a specific embodiment, it will be apparent to those skilled in the art from this disclosure that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

[0104] CROSS-REFERENCE TO RELATED APPLICATIONS

[0105] This patent application claims the benefit of priority to Korean Patent Application No. 10-2023-0072765, filed on June 7, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a cell string, the cell string comprising a plurality of memory cells; as well as a page buffer coupled to the cell string, the page buffer including a latch having cross-coupled transistors, The data transmitted from the cell string to the page buffer is input to gates of a plurality of transistors included in the page buffer.

2. The memory device according to claim 1, wherein: The plurality of transistors include: a first node of the cross-coupled transistor; a first PMOS transistor coupled to a power supply voltage node; and A first NMOS transistor is coupled to the first node.

3. The memory device according to claim 2, wherein: The cross-coupled transistor comprises: a second NMOS transistor having a gate coupled to the first node; and A third NMOS transistor has a gate coupled to a second node temporarily storing a second value inverted from the first value temporarily stored in the first node.

4. The memory device according to claim 3, wherein: The first NMOS transistor is arranged between the first node and the third NMOS transistor.

5. The memory device according to claim 2, wherein: The page buffer further includes a third PMOS transistor disposed between the first node and the first PMOS transistor, and The inverted signal of the sensing setting signal is input to the gate of the third PMOS transistor.

6. The memory device according to claim 1, wherein: The page buffer further includes a second PMOS transistor coupled to a power supply voltage node and a fourth NMOS transistor coupled to a ground voltage node, and The inverted signal of the sensing reset signal is input to the gates of the second PMOS transistor and the fourth NMOS transistor.

7. The memory device according to claim 4, wherein: The page buffer includes the first node having a logic high level during a precharge section, and Wherein, when data is transmitted from the cell string, the first node has the logic high level, and when no data is transmitted from the cell string, the first node changes from the logic high level to a logic low level.

8. The memory device according to claim 1, wherein: Each of the memory cells stores multiple bits of data, and When a read voltage is applied to at least one of the memory cells, the data transmitted from the cell string includes 1-bit data identified by the read voltage among the multi-bit data.

9. A memory device, the memory device comprising: a cell string, the cell string comprising a plurality of memory cells; a page buffer coupled to the cell string, the page buffer including a latch having cross-coupled transistors; a voltage generating circuit, the voltage generating circuit generating a read voltage and a pass voltage; as well as A control circuit generates a control signal to be input to the page buffer and the voltage generating circuit.

10. The memory device according to claim 9, wherein: Data transferred from the cell strings to the page buffer are input to gates of a plurality of transistors included in the page buffer.

11. The memory device according to claim 10, wherein: The plurality of transistors include: a first node of the cross-coupled transistor; a first PMOS transistor coupled to a power supply voltage node; and A first NMOS transistor is coupled to the first node.

12. The memory device according to claim 11, wherein: The cross-coupled transistor further comprises: a second NMOS transistor having a gate coupled to the first node; and A third NMOS transistor has a gate coupled to a second node temporarily storing a second value inverted from the first value temporarily stored in the first node.

13. The memory device according to claim 12, wherein: The first NMOS transistor is arranged between the first node and the third NMOS transistor.

14. The memory device according to claim 11, wherein: The page buffer further includes a third PMOS transistor disposed between the first node and the first PMOS transistor, and The inverted signal of the sensing setting signal is input to the gate of the third PMOS transistor.

15. The memory device according to claim 9, wherein: The page buffer further includes a second PMOS transistor coupled to a power supply voltage node and a fourth NMOS transistor coupled to a ground voltage node, and The inverted signal of the sensing reset signal is input to the gates of the second PMOS transistor and the fourth NMOS transistor.

16. The memory device according to claim 9, wherein: The page buffer includes a first node having a logic high level during a precharge section, and Wherein, when data is transmitted from the cell string, the first node has the logic high level, and when no data is transmitted from the cell string, the first node changes from the logic high level to a logic low level.

17. The memory device according to claim 9, wherein: Each of the memory cells stores multiple bits of data, and When a read voltage is applied to at least one of the memory cells, the data transmitted from the cell string includes 1-bit data identified by the read voltage among the multi-bit data.

18. The memory device according to claim 9, wherein: The page buffer and at least one other page buffer are coupled to the cell string, and the number of the page buffers coupled to the cell string is equal to or greater than the number of data bits stored in each memory cell.

19. The memory device according to claim 9, wherein: The cell string and the page buffer are coupled to each other through a bit line and a sensing output node, and Wherein, the memory device further comprises: a precharge circuit that precharges the bit line and the sense output node; and At least one switch controls a connection between the bit line and the sense output node.

20. The memory device of claim 19, wherein: The at least one switch is controlled by a signal output from the control circuit.

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