Semiconductor structure and forming method thereof

Abstract

In an embodiment, an exemplary method includes forming a source / drain opening extending into a substrate; forming a semiconductor layer in a bottom portion of the source / drain opening; forming a dielectric feature in the source / drain opening and on the semiconductor layer; epitaxially growing a source / drain feature in the source / drain opening, where the source / drain feature is in direct contact with the dielectric feature; removing the semiconductor layer and a part of the substrate arranged right below the semiconductor layer to form a groove; selectively removing the dielectric feature to enlarge the trench; forming a silicide layer in the enlarged trench after selectively removing the dielectric feature; and depositing a conductive layer in direct contact with the silicide layer in the enlarged trench. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] As integrated circuit (IC) technology moves toward smaller technology nodes, the parasitic resistance of source / drain contacts can have a serious impact on the overall performance of the IC device. Although existing source / drain contacts are generally adequate for their intended purpose, they are not satisfactory in all respects. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: receiving a workpiece, comprising: a fin-shaped active area, protruding from a substrate and including a channel area and a source / drain area; and a dummy gate stack, located above the channel area; recessing the source / drain area to form a source / drain trench exposing the substrate; forming a dielectric layer above the substrate and in the source / drain trench; epitaxially forming a source / drain component in the source / drain trench that is in direct contact with a top surface of the dielectric layer; replacing the dummy gate stack with a gate structure; removing portions of the dielectric layer and the substrate that are disposed directly below the dielectric layer to form a first contact opening; forming a silicide layer in the first contact opening and below the source / drain component; and forming a conductive layer below the silicide layer to fill the remaining portion of the first contact opening.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a source / drain opening extending into a substrate; forming a semiconductor layer in a bottom portion of the source / drain opening; forming a dielectric component in the source / drain opening and on the semiconductor layer; epitaxially growing a source / drain component in the source / drain opening, wherein the source / drain component is in direct contact with the dielectric component; removing portions of the semiconductor layer and the substrate disposed directly below the semiconductor layer to form a trench; selectively removing the dielectric component to expand the trench; after selectively removing the dielectric component, forming a silicide layer in the expanded trench; and depositing a conductive layer in direct contact with the silicide layer in the expanded trench.

[0006] Still other embodiments of the present application provide a semiconductor structure, comprising: a gate structure encapsulating a plurality of nanostructures disposed above a substrate; a first source / drain component coupled to the plurality of nanostructures and adjacent to the gate structure; a first silicide layer in direct contact with a bottom surface of the first source / drain component; a first source / drain contact disposed directly below the first source / drain component and in direct contact with the first silicide layer; and a dielectric barrier layer providing isolation between the substrate and the first source / drain contact, wherein, in a first cross-sectional view cutting through the gate structure and the first source / drain component, a portion of the first silicide layer is vertically disposed between the dielectric barrier layer and the first source / drain contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flow chart of a method for forming a semiconductor structure according to one or more aspects of an embodiment of the present disclosure is shown.

[0009] Figure 2 It shows that various aspects of the embodiments of the present disclosure will be experienced Figure 1 A partial top view of an exemplary workpiece at various stages of operation in a method.

[0010] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A, Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A ( FIG. 3A to FIG. 17A ) shows a workpiece according to one or more aspects of an embodiment of the present disclosure. Figure 1 During the various manufacturing stages of the method Figure 2 A partial cross-sectional view taken along the line AA′ shown in FIG.

[0011] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B and Fig. 17B ( FIG. 3B to FIG. 17B ) shows a workpiece according to one or more aspects of an embodiment of the present disclosure. Figure 1 During the various manufacturing stages of the method Figure 2 A partial cross-sectional view taken along line BB' shown in FIG.

[0012] Figure 3C , Figure 4C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C , Fig. 15C and Fig. 16C The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 During the various manufacturing stages of the method Figure 2 A partial cross-sectional view taken along the line CC' shown in FIG.

[0013] Fig.9D One or more aspects of the present disclosure are shown. Fig. 9C A partial top view of the workpiece shown in .

[0014] Fig.18 A partial cross-sectional view of a first optional workpiece is shown in accordance with one or more aspects of an embodiment of the present disclosure.

[0015] Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B and Fig. 20C A second optional workpiece according to one or more aspects of an embodiment of the present disclosure is shown in Figure 1 Partial cross-sectional views during various manufacturing stages in the method.

[0016] Fig.21A , Fig.21B , Fig. 21C , Fig.22A , Fig. 22B and Fig. 22C A third optional workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 Partial cross-sectional views during various manufacturing stages in the method.

[0017] Fig.23A and Fig. 23B A fourth optional workpiece according to one or more aspects of an embodiment of the present disclosure is shown in Figure 1 Partial cross-sectional views during various manufacturing stages in the method. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the terms are intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 15%.

[0021] As integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or part thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and full-all-around gate (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps the top and sidewalls of a semiconductor material "fin" extending from a substrate). Full-all-around gate (GAA) transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives GAA transistors optional names, such as nanosheet transistors or nanowire transistors.

[0022] A silicide layer and a source / drain contact may be formed below the epitaxial layer of the source / drain component from its back side. In some prior embodiments, in order to increase the junction area of ​​the backside silicide layer and the backside source / drain contact, the epitaxial layer of the source / drain component may be recessed, which adversely affects the volume and overall performance of the source / drain component.

[0023] The disclosed embodiments provide a method for increasing the contact area between the backside silicide layer and the source / drain component without substantially reducing the volume of the source / drain component from its back side. In an exemplary method, after forming a source / drain opening and refilling the lower portion of the source / drain opening with a semiconductor layer, a dielectric layer is formed to block the top surface of the semiconductor layer so that the source / drain component obtained by implementing an epitaxial growth process is not formed from the bottom up, which results in the formation of a void adjacent to the source / drain component. After forming the source / drain component, a first etching process is implemented to form a backside opening exposing the dielectric layer, and a second etching process is implemented to remove the dielectric layer to expose the bottom surface of the source / drain component. A backside silicide layer filling the void is then formed below the source / drain component. Forming a backside silicide layer in the void increases the contact area between the backside silicide layer and the source / drain component, and thus reduces the parasitic resistance of the semiconductor structure.

[0024] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart showing a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. Figure 2 and FIG. 3A to FIG. 23B Describing method 100, Figure 2 and FIG. 3A to FIG. 23B is a partial top view / cross-sectional view of a workpiece 200 at different stages of manufacturing according to an embodiment of method 100. Method 100 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown therein. Additional steps may be provided before, during, and after method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Because at the end of the manufacturing process, workpiece 200 will be manufactured into a semiconductor structure, workpiece 200 may be referred to as semiconductor structure 200 as the context requires. For the avoidance of doubt, Figure 2 and FIG. 3A to FIG. 23B The X, Y, and Z directions in the EMBODIMENT 1 are perpendicular to each other and are used consistently throughout the embodiments of the present disclosure. Throughout the embodiments of the present disclosure, the same reference numerals represent the same components unless otherwise specified.

[0025] refer to Figure 1 , Figure 2 and FIG. 3A to FIG. 3C The method 100 includes a block 102 in which a workpiece 200 including a first region 10 and a second region 20 is received. Figure 2 Describes various aspects of the present disclosure. Figure 1 2 is a partial top view of a workpiece 200 at various stages of operation in the method. Figure 3A The workpiece 200 is shown along the Figure 2A partial cross-sectional view taken along the line AA' shown in FIG. Figure 3B The workpiece 200 is shown along the Figure 2 A partial cross-sectional view taken along the line BB' shown in FIG. Figure 3C The workpiece 200 is shown along the Figure 2 The local cross-sectional view taken along the line CC' shown in FIG. FIG. 3A to FIG. 3C As shown in , the workpiece 200 includes a substrate 202. The substrate 202 can be: an elemental (single element) semiconductor, such as silicon (Si) or germanium (Ge) in a crystal structure; a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); a non-semiconductor material, such as soda lime glass, fused silica, fused quartz, and / or calcium fluoride (CaF2); and / or combinations thereof. In one embodiment, the substrate 202 is a silicon (Si) substrate. The substrate 202 may be uniform in composition or may include various layers, some of which may be selectively etched to form fin-shaped active regions (e.g., fin-shaped active regions 204A-204D). The layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thereby adjust device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates 202. In some such instances, the layers of the substrate 202 may include insulators such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, and / or other suitable insulator materials. Doped regions, such as wells, may be formed in the substrate 202. In Figure 2 In the embodiment shown in , the portion of the substrate 202 located in the first region 10 is doped with an n-type dopant and can be referred to as an n-type well (not shown), and the portion of the substrate 202 located in the second region 20 is doped with a p-type dopant and can be referred to as a p-type well (not shown). The n-type dopant can include phosphorus (P) or arsenic (As). The p-type dopant can include boron (B), boron difluoride (BF2), or indium (In). The n-type well and the p-type well can be formed using ion implantation or thermal diffusion and can be considered to be part of the substrate 202. As will be further described below, the first region 10 is a p-type field effect transistor (PFET) region for forming a PFET, and the second region 20 is an n-type field effect transistor (NFET) region for forming an NFET.

[0026] Still reference Figure 2 and FIG. 3A to FIG. 3C The workpiece 200 includes a plurality of fin-shaped active regions (e.g., fin-shaped active regions 204A, 204B, 204C, 204D) protruding from a substrate 202. In the present embodiment, the first region 10 includes a fin-shaped active region 204A and a fin-shaped active region 204B extending vertically from the substrate 202, and the second region 20 includes a fin-shaped active region 204C and a fin-shaped active region 204D extending vertically from the substrate 202. Figure 2 and FIG. 3A to FIG. 3C The number of fin-shaped active regions depicted in the drawings is merely an example, and the workpiece 200 may include any suitable number of active regions. Each of the fin-shaped active regions 204A-204D may be formed by a top portion 202t ( FIG. 3A to FIG. 3B 202ts) and a vertical stack 207 of alternating semiconductor layers disposed on a top surface 202ts of the substrate 202. In an embodiment, the vertical stack 207 includes a plurality of channel layers 208 interlaced with a plurality of sacrificial layers 206. Each of the channel layers 208 may include a semiconductor material such as silicon, germanium, silicon carbide, silicon germanium, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while each sacrificial layer 206 has a composition different from that of the channel layer 208. In an embodiment, each of the channel layers 208 includes silicon (Si) and the sacrificial layer 206 includes silicon germanium (SiGe). Although the vertical stack 207 of the depicted example includes three channel layers and three sacrificial layers, it should be understood that the vertical stack 207 may include any suitable number (e.g., 2 to 10) of channel layers and any suitable number of sacrificial layers. The vertical stack 207 and the top portion 202t of the substrate 202 are then patterned to form fin-shaped active areas 204A-204D. In some embodiments, the patterned top portion 202t of the substrate 202 may be referred to as a mesa structure 202t. Each of the fin-shaped active regions 204 extends longitudinally along the X direction and is divided into a channel region 204C overlapping with a dummy gate stack 210 (described below) and a source / drain region 204SD not overlapping with the dummy gate stack 210. The source / drain region 204SD may refer to a source region or a drain region, individually or collectively depending on the context. Each of the channel regions 204C is disposed between two source / drain regions 204SD along the X direction.

[0027] The workpiece 200 also includes an isolation feature 205 ( Figure 3C) to isolate one fin-shaped active area from an adjacent fin-shaped active area. The isolation feature 205 may include a shallow trench isolation (STI) feature 205. In an exemplary process, a dielectric material for the isolation feature 205 is first deposited over the workpiece 200, and the trenches between the fin-shaped active areas 204A-204D are filled with the dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various instances, the dielectric material may be deposited by a CVD process, a flowable CVD (FCVD) process, spin coating, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process, until the top surface of the fin-shaped active areas 204A-204D is exposed. The planarized dielectric material is further recessed or etched back by a dry etching process, a wet etching process, and / or a combination thereof to form the STI feature 205. In Figure 3C In the embodiment shown in , the upper portion of the fin-shaped active regions 204A-204D rises above the STI component 205, while the lower portion of the fin-shaped active regions 204A-204D remains covered or buried in the STI component 205. The deposited dielectric material can be a single-layer structure or a multi-layer structure. In this embodiment, at least one of the STI components 205 includes a horizontal portion 205h extending between two adjacent fin-shaped active regions (e.g., fin-shaped active regions 204B and 204C) and two vertical portions 205v extending along the bottom sidewall surfaces of the two adjacent fin-shaped active regions.

[0028] The workpiece 200 also includes a dummy gate stack 210. Each of the dummy gate stacks 210 includes a dummy gate dielectric layer 210a, a dummy gate electrode layer 210b above the dummy gate dielectric layer 210a, and a gate top hard mask layer 210c above the dummy gate electrode layer 210b. The dummy gate dielectric layer 210a may include silicon oxide. The dummy gate electrode layer 210b may include polysilicon. The gate top hard mask layer 210c may include a silicon oxide layer, silicon nitride and / or other suitable materials. The dummy gate stack 210 may be formed using suitable deposition processes, photolithography and etching processes. In this embodiment, a gate replacement process (or a gate-last process) is used, in which the dummy gate stack 210 is used as a gate for a functional gate structure (e.g., FIG. 10A to FIG. 10B 2 is a placeholder for the gate structure 230 shown in . Other processes and configurations are also possible. Figure 2 Three dummy gate stacks 210 are shown in FIG. 2 , but the workpiece 200 may include any suitable number of dummy gate stacks 210 .

[0029] The workpiece 200 also includes a gate spacer 212a extending along the sidewall surface of the dummy gate stack 210. Each of the gate spacers 212a can be a single-layer structure or a multi-layer structure. In an exemplary process, a first spacer layer (not separately labeled) is conformally deposited over the workpiece 200, and a second spacer layer (not separately labeled layer) is conformally deposited over the first spacer layer. The first spacer layer is conformally deposited over the workpiece 200 (including the fin-shaped active regions 204A-204D) by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. The term "conformal" may be used herein to describe a layer having a substantially uniform thickness over various regions of the workpiece 200. The first spacer layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or other suitable dielectric materials. In an embodiment, the first spacer layer includes silicon carbonitride (SICN). After forming the first spacer layer, a second spacer layer is conformally deposited over the first spacer layer by ALD, CVD, or any other suitable deposition process. The second spacer layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or other suitable dielectric material. The composition of the first spacer layer is different from that of the second spacer layer to introduce etching selectivity. In an embodiment, the second spacer layer includes silicon nitride (SiN). After forming the first spacer layer and the second spacer layer, an etching process is performed to remove portions of the first spacer layer and the second spacer layer located above the top-facing surface of the workpiece 200 to form gate spacers 212a extending along the sidewalls of the pseudo gate stack 210. The deposition and etching of the first spacer layer and the second spacer layer also form fin sidewall spacers 212b ( Figure 3C ).

[0030] refer to Figure 1 and FIG. 4A to FIG. 4C, the method 100 includes a block 104, in which the source / drain regions 204SD of the fin-shaped active regions 204A-204D are recessed to form source / drain openings 214. In some embodiments, the source / drain regions 204SD of the fin-shaped active regions 204A-204D are anisotropically etched by plasma etching with a suitable etchant, such as an oxygen-containing etchant, a hydrogen-containing etchant, a fluorine-containing etchant (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing etchant (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing etchant (e.g., HBr and / or CHBr3), an iodine-containing etchant, other suitable etchants, and / or combinations thereof. In the present embodiment, the source / drain openings 214 extend into the top portion 202t of the substrate 202.

[0031] refer to Figure 1 and FIG. 5A to FIG. 5B , the method 100 includes a frame 106, in which an internal spacer component 216 is formed. After the source / drain openings 214 are formed in the first region 10 and the second region 20, the sacrificial layer 206 exposed in the source / drain openings 214 is selectively and partially recessed to form an internal spacer recess (filled with the internal spacer component 216), while the exposed channel layer 208 is substantially not etched. In some embodiments, the selective recessing may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. After the internal spacer recess is formed, an internal spacer material layer is then conformally deposited over the workpiece 200 (including over and in the internal spacer recess) using CVD or ALD. The internal spacer material may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, or silicon oxynitride. The internal spacer material layer is then etched back to form the internal spacer component 216, as FIG. 5A to FIG. 5B In some embodiments, the composition of the inner spacer feature 216 is different from the composition of the gate spacer 212a, so that the etch back of the inner spacer material layer does not substantially etch the gate spacer 212a.

[0032] Reference now Figure 1 and FIG. 6A to FIG. 6B, the method 100 includes a frame 108, wherein a semiconductor layer 218 is formed in the source / drain opening 214. In the present embodiment, after forming the internal spacer component 216, the semiconductor layer 218 is formed in the source / drain opening 214 by using an epitaxial process. Each of the semiconductor layers 218 can be undoped or not intentionally doped. In some embodiments, the semiconductor layer 218 may include undoped silicon (Si), undoped germanium (Ge), undoped silicon germanium (SiGe), or other suitable materials. In an embodiment, the semiconductor layer 218 is formed simultaneously by a common epitaxial process and includes undoped silicon (Si). In the depicted example, the top surface 218ts of the semiconductor layer 218 is located above the top surface 202ts of the substrate 202 and below the bottom surface of the bottommost channel layer of the plurality of channel layers 208, and has a convex profile.

[0033] Reference now Figure 1 and FIG. 7A to FIG. 7B , the method 100 includes a frame 110, in which an insulating layer 220 is deposited over the workpiece 200 (including in the first region 10 and the second region 20). In the present embodiment, the insulating layer 220 is deposited by using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, and the deposition thickness of the insulating layer 220 may depend on the desired thickness of the final bottom portion 220c' of the insulating layer 220 formed in the source / drain opening 214. In an embodiment, the insulating layer 220 is deposited by using a physical vapor deposition (PVD) process. Due to the characteristics of the PVD process, the portion of the insulating layer 220 formed on the top or flat surface is thicker than the portion of the insulating layer 220 formed on the side. More specifically, as FIG. 7A to FIG. 7B As depicted in , the insulating layer 220 includes a top portion 220a formed above the top surface of the dummy gate stack 210, a sidewall portion 220b extending along the exposed sidewall surface of the channel region 204C of the fin-shaped active region, and a bottom portion 220c formed on the top surface of the semiconductor layer 218. For embodiments in which the insulating layer 220 is deposited by PVD, the thickness of the portion 220a / 220c is greater than the thickness of the sidewall portion 220b. The insulating layer 220 can be formed of any suitable dielectric material as long as its composition is different from those of the channel layer (e.g., channel layer 208b, 208m, 208t), the sacrificial layer 206, and the gate top hard mask layer 210c to allow selective removal by an etching process. In some embodiments, the insulating layer 220 may include silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon carbonitride (SICN), or other suitable materials.

[0034] Reference now Figure 1 and FIG. 8A to FIG. 8C, the method 100 includes a block 112, in which a portion of the insulating layer 220 is removed, thereby leaving a bottom portion 220c of the insulating layer in the source / drain openings 214 and on the undoped semiconductor layer 218. In an exemplary process, a mask layer (e.g., a bottom anti-reflective coating (BARC) layer) (not shown) is formed to cover the bottom portion 220c of the insulating layer 220 without covering other portions of the insulating layer 220. Because the mask layer has a thickness along the Z direction, it also covers the lower portion of the sidewall portion 220b of the insulating layer 220. When using the mask layer as an etching mask, a first etching process is performed to selectively remove the portion of the insulating layer 220 that is not covered by the mask layer. The mask layer can then be selectively removed using a suitable etching process. This can be followed by a second etching process to isotropically etch the remaining portion of the insulating layer 220 to remove the lower portion of the sidewall portion 220b of the insulating layer 220, thereby leaving a partially etched bottom portion 220c on the semiconductor layer 218. In some embodiments, the first and / or second etching process may slightly etch the fin sidewall spacer 212b. The partially etched bottom portion 220c of the insulating layer 220 may be referred to as a dielectric layer 220c'. The top surface 220ts of the dielectric layer 220c' is a convex top surface that substantially follows the shape of the top surface of the semiconductor layer 218 disposed thereunder. In the present embodiment, the top surface of the dielectric layer 220c' is below the top surface of the bottommost inner spacer component 216 of the inner spacer component 216. That is, the dielectric layer 220c' is not in direct contact with the bottommost one of the plurality of channel layers 208. In an embodiment, the dielectric layer 220c' has a thickness in a range between approximately 1 nm and 5 nm. For embodiments in which the final structure of the workpiece 200 includes the dielectric layer 220c', the formation of the dielectric layer 220c' will substantially inhibit and / or eliminate the formation of dielectric layers 230 ( FIG. 17A to FIG. 17B ), any parasitic transistors between the source / drain features 222N / 222P and the underlying mesa structure 202t, thereby reducing and / or blocking leakage current through the mesa structure 202t. In addition, in this embodiment, the formation of the dielectric layer 220c' will promote the formation of a backside silicide layer with increased area.

[0035] Reference now Figure 1 and 9A to 9D, the method 100 includes a block 114, in which source / drain features 222P and 222N are formed in the source / drain openings 214 in the first region 10 and the second region 20, respectively. The source / drain feature may refer to a source or a drain, individually or collectively depending on the context. The source / drain feature 222P is coupled to the channel layer 208 of the channel region 204C in the first region 10. The source / drain feature 222N is coupled to the channel layer 208 of the channel region 204C in the second region 20. Each of the source / drain features 222N and 222P can be formed epitaxially and selectively from the exposed sidewalls of the channel layer 208 using an epitaxial process such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes.

[0036] The exemplary N-type source / drain features 222N may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped by introducing N-type dopants such as phosphorus, arsenic, or antimony during the epitaxial process, or ex-situ doped using a junction implantation process. The exemplary P-type source / drain features 222P may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be in-situ doped by introducing P-type dopants such as boron or gallium during the epitaxial process, or ex-situ doped using a junction implantation process. In some embodiments, each of the N-type source / drain features 222N and the P-type source / drain features 222P may include multiple semiconductor layers having different doping concentrations. The N-type source / drain features 222N and the P-type source / drain features 222P may be formed in any suitable order.

[0037] In this embodiment, due to the presence of the dielectric layer 220c', as shown in FIG. FIG. 9A to FIG. 9B As depicted, the source / drain features 222P / 222N cannot be epitaxially grown from the bottom up (ie, along the Z direction) because the semiconductor layer 218 in the source / drain region 204SD is blocked by the dielectric layer 220c' and cannot provide an exposed semiconductor surface for epitaxial growth. Figure 8C As depicted, the workpiece 200 in the partial cross-sectional view also does not provide any exposed semiconductor surface for direct epitaxial growth along the Y direction when viewed from the X direction. Instead, the source / drain features 222N and 222P are epitaxially formed along the X direction from the exposed sidewalls of the channel layer 208 until the semiconductor layers of the source / drain features merge. The inability to epitaxially grow from the bottom up and the inability to epitaxially grow along the Y direction result in the formation of a void 224 (or air gap 224) surrounded by the source / drain features 222N / 222P, the dielectric layer 220c′, and the fin sidewall spacers 212b, as shown in FIG. Fig. 9CMore precisely, the void 224 is defined by the top surface of the dielectric layer 220', the sidewall surfaces 222ss of the source / drain features 222N / 222P, and the fin sidewall spacers 212b. The sidewall surfaces 222ss are curved upward and outward. That is, a portion of the top surface 220ts of the dielectric layer 220' is not in direct contact with the bottom surface 222bs of the source / drain features 222N / 222P. It should be noted that in FIG. 9A to FIG. 9B In the illustrated cross-sectional view, the workpiece 200 does not include a void formed between the source / drain features 222N / 222P and the dielectric layer 220c ′, and the bottom surface 222bs of the source / drain features 222N / 222P follows the shape of the dielectric layer 220c ′ thereunder. Fig.9D A top view of a P-type source / drain feature 222P and an N-type source / drain feature 222N is depicted. Each of the voids 224 extends longitudinally along the X direction. In an embodiment, in the top view, a distance D1 between the void 224 and the nearest edge of the P-type source / drain feature 222P in the first region 10 is greater than a distance D2 between the void 224 and the nearest edge of the N-type source / drain feature 222N in the second region 20. In an embodiment, the void 224 spans a width along the Y direction and a height along the Z direction, the width may be in a range between about 3 nm and 10 nm, and the height may be in a range between about 3 nm and about 10 nm.

[0038] Reference now Figure 1 and FIG. 10A to FIG. 10C, the method 100 includes block 116, where the dummy gate stack 210 and the sacrificial layer 206 are replaced by a metal gate structure 230. A contact etch stop layer (CESL) 226 and a first interlayer dielectric (ILD) layer 228 are deposited over the workpiece 200. The CESL 226 may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. After depositing the CESL 226, the first ILD layer 228 is deposited over the workpiece 200 by a PECVD process or other suitable deposition technique. The first ILD layer 228 may include a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the workpiece 200 to remove excess material and expose the top surface of the dummy gate electrode layer 210b in the dummy gate stack 210. A first etching process may be performed to selectively remove the dummy gate electrode layer 210b and the dummy gate dielectric layer 210a of the dummy gate stack 210 without substantially removing the gate spacer 212a to form a gate trench in the first region 10 and the second region 20. After removing the dummy gate stack 210, the sacrificial layer 206 in the channel region 204C is selectively removed to release the channel layer 208 as a channel member 208. Selectively removing the sacrificial layer 206 forms a gate opening below the gate trench.

[0039] After removing the dummy gate stack 210 and the sacrificial layer 206, a metal gate structure 230 is formed in the gate trenches and openings in the first region 10 and the second region 20. The formation of the metal gate structure 230 includes forming an interface layer to wrap around and above each of the channel members 208. The interface layer may include silicon oxide or other suitable materials. The interface layer may be formed using a suitable method, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation or other suitable methods. In an embodiment, the interface layer is formed by thermal oxidation and is therefore formed only on the surface of the channel member 208. That is, the interface layer does not extend along the sidewall surface of the gate spacer 212a, and does not extend along the sidewall surface of the internal spacer component 216. In another embodiment, the interface layer is formed by ALD and is therefore conformally formed on the surface of the workpiece 200. That is, the interface layer also extends along the sidewall surface of the gate spacer 212a and the sidewall surface of the internal spacer component 216. After forming the interface layer, a dielectric layer is formed over the workpiece 200 to wrap around and over each of the channel members 208. In an embodiment, the dielectric layer is conformally deposited over the workpiece 200. The term "conformal" may be used herein to facilitate describing a layer having a substantially uniform thickness over various regions. In some embodiments, the dielectric layer is a high-k dielectric layer because its dielectric constant is greater than the dielectric constant of silicon dioxide (~3.9). In some embodiments, the dielectric layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The dielectric layer and the interface layer may be collectively referred to as a gate dielectric layer.

[0040] The formation of the metal gate structure 230 also includes forming a gate electrode above the gate dielectric layer. The gate electrode can be a multilayer structure including at least one work function layer and a metal filling layer. For example, at least one work function layer can include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN) or tantalum carbide (TaC). The metal gate structure 230 formed in the first region 10 can include at least a P-type work function layer. The P-type work function layer can include titanium nitride (TiN), tungsten carbonitride (WCN), tantalum nitride (TaN) or molybdenum nitride (MoN). The metal gate structure 230 formed in the second region 20 can include at least an N-type work function layer. The N-type work function layer can include a titanium aluminum-based metal, such as titanium aluminum carbon (TiAlC) or titanium aluminum (TiAl). The metal filling layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to remove excess material above the first ILD layer 228 to provide a substantially flat top surface and facilitate the implementation of further processes.

[0041] In some embodiments, after forming the metal gate structures 230, gate isolation structures (e.g., gate isolation structures 232) may be formed to cut one or more of the metal gate structures 230 into physically and electrically isolated segments. When viewed from the top, the gate isolation structures 232 extend longitudinally in a direction (e.g., an X direction) parallel to the direction of the fin-shaped active regions 204A-204C. The gate isolation structures 232 extend into the STI features 205 and may be formed of any suitable dielectric material.

[0042] refer to Figure 1 and FIG. 11A to FIG. 11C, the method 100 includes a block 118, wherein a silicide layer 240a / 240b and a source / drain contact 242 are formed over the front side of the substrate 202. In an exemplary process, an etch stop layer 236 and a second ILD layer 238 are deposited over the workpiece 200. The etch stop layer 236 may be similar to the contact etch stop layer 226 in terms of composition and formation process, and the second ILD layer 238 may be similar to the first ILD layer 228. The etch stop layer 236 may indicate an etch stop point for forming a gate via opening over the metal gate structure 230. A combination of a photolithography process and an etching process is used to form a source / drain contact opening (now filled with the silicide layer 240a / 240b and the source / drain contact 242) to expose the p-type source / drain feature 222P and / or the n-type source / drain feature 222N. In an exemplary process, a hard mask layer and a photoresist are deposited over the workpiece 200. The photoresist layer is then exposed to patterned radiation transmitted through or reflected from the photomask, baked in a post-exposure bake process, developed in a developer solution, and then rinsed to form a patterned photoresist layer. The patterned photoresist layer is then applied as an etch mask to etch the hard mask layer to form a patterned hard mask layer. The patterned hard mask layer is then applied as an etch mask to etch the second ILD layer 238, the etch stop layer 236, the first ILD layer 228, and the CESL 226. The etching process for etching the second ILD layer 238, the first ILD layer 228, and the CESL 226 may be a dry etching process including using argon (Ar), a fluorine-containing etchant (e.g., SF6, NF3, CH2F2, CHF3, C4F8, and / or C2F6), an oxygen-containing etchant, a chlorine-containing etchant (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing etchant (e.g., HBr and / or CHBr3), an iodine-containing etchant, or a combination thereof.

[0043] After forming the source / drain contact openings, silicide layers 240a / 240b and source / drain contacts 242 are formed therein. To form the silicide layers 240a / 240b, a metal precursor (e.g., titanium, tantalum, nickel, cobalt, or tungsten) is deposited over the workpiece (including on the exposed surface of the n-type source / drain component 222N and the exposed surface of the p-type source / drain component 222P). An annealing process is then performed to produce silicide in the second region 20 and germanium in the first region 10 between the metal precursor and the exposed semiconductor surface. In some embodiments, unreacted metal precursors are selectively removed after forming the silicide layers 240a-240b. For embodiments in which the metal precursor includes nickel, the nickel may react with silicon germanium in the p-type source / drain component 222P to form the silicide layer 240a, and may react with silicon in the n-type source / drain component 222N to form the silicide layer 240b. Therefore, the silicide layer 240 a may include nickel silicide, and the silicide layer 240 b includes nickel silicide, nickel germanium, and nickel germanium silicide.

[0044] A conductive layer is then deposited over the workpiece 200, including in the source / drain contact openings and on the silicide layers 240a-240b. The conductive layer may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo), or other suitable materials, and may be formed by any suitable deposition process (e.g., CVD). A planarization process, such as a chemical mechanical polishing (CMP) process, may then be performed to remove excess portions of the conductive layer to form the source / drain contacts 242. After the planarization process is performed, the top surface of the source / drain contacts 242 is coplanar with the second ILD layer 238. Although not shown, in some embodiments, a dielectric barrier layer may be formed to extend along the sidewall surfaces of the source / drain contacts 242. Fig. 11C In the cross-sectional view depicted in , the source / drain contacts 242 also extend into the gate isolation structure 232 .

[0045] After forming the silicide layers 240a and 240b and the source / drain contacts 242, other components such as gate vias and an interconnection structure 244 may be formed above the workpiece 200. In some embodiments, the interconnection structure 244 may include multiple intermetallic dielectric (IMD) layers and multiple metal lines or contact vias in each of the IMD layers. In some instances, the IMD layer and the first ILD layer 228 may have similar compositions. The metal lines and contact vias in each IMD layer may be formed of metals such as aluminum, tungsten, ruthenium or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to insulate the metal lines and contact vias from the IMD layer and prevent electromigration. Because the interconnection structure 244 is formed above the front side of the workpiece 200, the interconnection structure 244 may also be referred to as a front side interconnection structure 244.

[0046] refer to Figure 1 and FIG. 12A to FIG. 12C , method 100 includes frame 120, wherein the thickness of substrate 202 is reduced from its back side. In an embodiment, a carrier substrate (not shown) is bonded to the interconnect structure 244. In some embodiments, the carrier substrate can be bonded to the workpiece 200 by fusion bonding, by using an adhesive layer, or a combination thereof. In some instances, the carrier substrate may include a semiconductor material (such as silicon), sapphire, glass, a polymeric material, or other suitable material. In an embodiment using fusion bonding, the carrier substrate includes a bottom oxide layer and the interconnect structure 244 includes a top oxide layer. After processing the bottom oxide layer and the top oxide layer, they are placed in close contact with each other for direct bonding at room temperature or at an elevated temperature. Once the carrier substrate is bonded to the interconnect structure 244 of the workpiece 200, the workpiece 200 is flipped over. Then, the back side of the workpiece 200 is planarized to reduce the thickness of the substrate 202 from its back side. In an embodiment, as Fig. 12C As depicted, after planarization, the bottom surface 202bs of the substrate 202 is coplanar with the portion of the CESL 226 disposed between the two fin-shaped active regions. The planarization process also removes the horizontal portion 205h of the STI feature 205 and the portion of the gate isolation structure 232 extending into the STI feature 205. For ease of description, the positional relationship will be described below based on the workpiece 200 after flipping, as depicted in the drawings.

[0047] refer to Figure 1 , FIG. 12A to FIG. 12C and FIG. 13A to FIG. 13C , the method 100 includes block 122, where the semiconductor layer 218 and the portion of the substrate 202 disposed directly thereunder are removed to form a trench. FIG. 12A to FIG. 12C In the illustrated embodiment, a hard mask layer 246 and an oxide layer 248 are formed over the bottom surface 202bs of the planarized substrate 202. The thickness of the oxide layer 248 may be in a range between about 15 nm and about 45 nm, and the thickness of the hard mask layer 246 may be in a range between about 5 nm and 15 nm. The hard mask layer 246 and the oxide layer 248 are then patterned to form an opening 250 directly over the semiconductor layer 218. When the patterned oxide layer 248 and the patterned hard mask layer 246 are used as an etch mask, as shown in FIG. FIG. 13A to FIG. 13CAs depicted in , an etching process is performed to selectively remove the portion of the substrate 202 exposed by the opening and the semiconductor layer 218 disposed directly below the portion of the substrate 202 to form a trench 252. In this embodiment, each of the first region 10 and the second region 20 includes a corresponding trench 252. The trench 252 exposes the dielectric layer 220c'. The etching process can be a selective wet etching process or a selective dry etching process. Exemplary selective dry etching processes can implement CF4, NF3, Cl2, HBr, other suitable gases and / or plasmas and / or combinations thereof.

[0048] refer to Figure 1 and FIG. 14A to FIG. 14C , the method 100 includes a block 124, in which a dielectric barrier layer 254 is formed to extend along the sidewall surface of the trench 252. After the trench 252 is formed, in the present embodiment, in order to prevent the surface of the substrate 202 exposed by the trench 252 from being affected by the subsequent silicidation process, the dielectric barrier layer 254 is formed to extend along the sidewall surface of the trench 252. In an exemplary process, the dielectric layer is conformally deposited over the workpiece 200 and then etched back to retain only the portion extending along the sidewall surface of the trench 252, thereby forming the dielectric barrier layer 254. The bottom surface of the dielectric barrier layer 254 is in direct contact with the dielectric layer 220c' and is inclined inwardly and downwardly due to the profile of the dielectric layer 220c'. The composition of the dielectric barrier layer 254 is different from that of the dielectric layer 220c', so that the dielectric layer 220c' can be selectively removed later. In some embodiments, the dielectric barrier layer 254 may include silicon nitride, silicon oxide, or other suitable materials.

[0049] refer to Figure 1 and FIG. 15A to FIG. 15C , the method 100 includes block 126, in which the dielectric layer 220c' exposed by the trench 252 is selectively removed. After the dielectric barrier layer 254 is formed, while still using the patterned hard mask layer 246 and the patterned oxide layer 248 as an etching mask, an etching process is performed to selectively remove the dielectric layer 220c' exposed by the trench 252 without substantially etching the dielectric barrier layer 254 and the source / drain features 222N / 222P to vertically extend the trench 252. FIG. 15A to FIG. 15B As shown in , the removal of the dielectric layer 220c' exposes the bottom surface 254bs of the dielectric barrier layer 254 and the sidewall surfaces of the inner spacer member 216 adjacent to the dielectric barrier layer 254. Fig. 15CAs shown, because the void 224 is surrounded by the combination of the dielectric layer 220c', a portion of the sidewall surface 222ss of the source / drain feature 222N / 222P, and the fin sidewall spacer 214b, the removal of the dielectric layer 220c' breaks this enclosure and releases the portion of the sidewall surface 222ss of the source / drain feature 222N / 222P. Therefore, the trench 252 now not only exposes the bottom surface 222bs of the source / drain feature 222N / 222P, but also exposes the portion of the sidewall surface 222ss of the source / drain feature 222N / 222P. That is, the trench 252 also expands laterally along the Y direction. The trench 252 after removing the dielectric layer 220c' can be referred to as a backside contact opening 252.

[0050] refer to Figure 1 and FIG. 16A to FIG. 16C , the method 100 includes a block 128, wherein a conformal silicide layer 256a / 256b and a backside source / drain contact 258 are formed in the backside contact opening 252. After the backside contact opening 252 is formed, the silicide layer 256a / 256b and the source / drain contact 258 are formed therein. To form the silicide layer 256a / 256b, a metal precursor (e.g., titanium, tantalum, nickel, cobalt, or tungsten) is conformally deposited over the backside of the workpiece 200 (including on the exposed bottom surface 222bs and the exposed sidewall surface 222ss of the n-type source / drain feature 222N and the exposed bottom surface 222bs and the exposed sidewall surface 222ss of the p-type source / drain feature 222P). An annealing process is then performed to produce silicide in the second region 20 and germanium in the first region 10 between the metal precursor and the exposed semiconductor surface. In some embodiments, unreacted metal precursors are selectively removed after forming the silicide layers 256 a-256 b. For embodiments where the metal precursors include nickel, the nickel may react with silicon germanium in the p-type source / drain features 222P to form a silicide layer 256 a in the first region 10 and may react with silicon in the n-type source / drain features 222N to form a silicide layer 256 b in the second region 20.

[0051] exist FIG. 16A to FIG. 16B In the depicted cross-sectional view, the silicide layer 256a has a portion disposed directly under the dielectric barrier layer 254 in the first region 10, and the silicide layer 256b has a portion disposed directly under the dielectric barrier layer 254 in the second region 20. Fig. 16CIn the depicted cross-sectional view, the silicide layer 256a also has a portion that is in direct contact with the portion of the exposed sidewall surface 222ss of the p-type source / drain feature 222P and disposed directly below the vertical portion 205v of the STI feature 205. Similarly, the silicide layer 256b also has a portion that is in direct contact with the portion of the exposed sidewall surface 222ss of the n-type source / drain feature 222N and disposed directly below the vertical portion 205v of the STI feature 205. Thus, the contact area between the silicide layers 256a / 256b and the source / drain features 222P / 222N is increased, which advantageously reduces the parasitic resistance of the workpiece 200.

[0052] A conductive layer is then deposited over the back side of the workpiece 200, including in the back side contact opening 252 and on the silicide layers 256a-256b. The conductive layer may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo), or other suitable materials, and may be formed by any suitable deposition process (e.g., CVD). A planarization process, such as a chemical mechanical polishing (CMP) process, may then be performed to remove excess material over the patterned hard mask layer 246 to define the final structure of the back side source / drain contact 258. The back side source / drain contact 258 has a flat top surface 258ts that is coplanar with the top surface of the patterned hard mask layer 246 and a bottom surface 258bs that is in direct contact with the silicide layer 256a / 256b thereunder. As shown in FIG. Fig. 16C As shown in FIG. 1 , in the first region 10 , the silicide layer 256a spans a width W1a along the Y direction, the flat top surface 258ts spans a width W2a along the Y direction, and W1a is greater than W2a; in the second region 20 , the silicide layer 256b spans a width W1b along the Y direction, the flat top surface 258ts spans a width W2b along the Y direction, and W1b is greater than W2b. Depending on the size of the void 224, the conductive layer used to form the back side source / drain contact 258 may also fill part of the void 224. Fig. 16C In the illustrated embodiment, the backside source / drain contact 258 has a portion formed in the void 224 and disposed directly under the vertical portion 205v of the STI feature 205 and a portion disposed directly under the dielectric barrier layer 254. Fig.18 In the illustrated alternative embodiment, for embodiments where the void 224 has a smaller volume, the silicide layer 256a / 256b substantially fills the void 224. In such an embodiment, the silicide layer 256a / 256b spans a width greater than the width of the backside source / drain contact 258 formed thereon. In some embodiments, the volume of the void 224 can be adjusted by adjusting the epitaxial growth method (e.g., adjusting the annealing temperature).

[0053] refer to Figure 1 and FIG. 17A to FIG. 17B , the method 100 includes a frame 130, in which a further process is performed. Such a further process may include forming an interconnect structure 260 above the top surface 258ts of the backside source / drain contact 258. In some embodiments, the interconnect structure 260 may include a plurality of intermetallic dielectric (IMD) layers and a plurality of metal lines or contact vias in each of the IMD layers. In some instances, the IMD layer and the first ILD layer 228 may share a similar composition. The metal lines and contact vias in each IMD layer may be formed of a metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to insulate the metal lines and contact vias from the IMD layer and prevent electromigration. Because the interconnect structure 260 is formed above the back side of the workpiece 200, the interconnect structure 260 may also be referred to as a backside interconnect structure 260. Such further processing may also include forming a passivation structure 262 over the backside interconnect structure 260 and an I / O 264 pad (eg, an aluminum pad) extending through the passivation structure to electrically connect to a conductive feature (eg, a metal line) of the interconnect structure 260 .

[0054] In the above embodiment, after performing the operations in blocks 108-112, the dielectric layer 220c′ has a convex top surface 220ts ( Fig. 8A ), and the source / drain features 222N / 222P formed on the dielectric layer 220c' have a bottom surface that follows the shape of the top surface 220ts of the dielectric layer 220c'. In some other embodiments, the dielectric layer 220c' may have a different profile. FIG. 19A to FIG. 19C and FIG. 20A to FIG. 20C A first optional workpiece according to one or more aspects of an embodiment of the present disclosure is depicted in Figure 1 Cross-sectional views during various manufacturing stages in the method. FIG. 19A to FIG. 19C The first optional workpiece 200 is shown similar to FIG. 8A to FIG. 8C The workpiece 200 shown in FIG. 1 is a workpiece 200, and the difference between the two workpieces includes different profiles of the top surface of the semiconductor layer 218 and the dielectric layer 220c' formed on the semiconductor layer 218. The profile of the top surface of the semiconductor layer 218 can be adjusted by the duration of the epitaxial growth process used to form the semiconductor layer 218. In this alternative embodiment, by implementing a ratio Fig. 8A The epitaxial growth process duration of the semiconductor layer 218 shown in FIG. 1 is short, and the top surface of the semiconductor layer 218 is substantially coplanar with the bottom surface of the bottommost inner spacer member 216. The dielectric layer 220c' follows the shape of the top surface of the semiconductor layer 218 and thus has a flat top surface and a flat bottom surface. The operations in blocks 114-130 may then be performed to form the final structure of the workpiece according to this alternative embodiment. FIG. 20A to FIG. 20C The resulting artifact shown in is similar to FIG. 16A to FIG. 16C2 and 3. The workpiece 200 shown in FIG. 1 and the differences between the two workpieces include different profiles of the silicide layers 256a-256b and the backside source / drain contacts 258. More specifically, the portions of the silicide layers 256a-256b and the backside source / drain contacts 258 formed in the trenches 252 of the first optional workpiece 200 have planar top and bottom surfaces. Other portions of the silicide layers 256a-256b and the backside source / drain contacts 258 that fill the voids 224 may still have non-planar surfaces.

[0055] FIG. 21A to FIG. 21C and FIG. 22A to FIG. 22C A second optional workpiece according to one or more aspects of the disclosed embodiments is depicted in Figure 1 Cross-sectional views during various manufacturing stages in the method. FIG. 21A to FIG. 21C The workpiece 200 shown is similar to FIG. 8A to FIG. 8C The workpiece 200 shown in FIG. 1 is a workpiece 200, and the difference between the two workpieces includes different profiles of the top surface of the semiconductor layer 218 and the dielectric layer 220c' formed on the semiconductor layer 218. In this alternative embodiment, by implementing a comparison Fig.19A The epitaxial growth process duration of the semiconductor layer 218 shown in FIG. 1 is short, and the top surface 218ts of the semiconductor layer 218 is located below the top surface 202ts of the substrate 202 and is a concave top surface. The dielectric layer 220c' follows the shape of the top surface of the semiconductor layer 218 and thus has a concave top surface. The dielectric layer 220c' is in direct contact with the substrate 202 and the bottommost inner spacer member 216. The operations in blocks 114-130 can then be performed to form the final structure of the workpiece according to this alternative embodiment. FIG. 22A to FIG. 22C The resulting artifact shown in is similar to FIG. 16A to FIG. 16C 200, and the differences between the two workpieces include different profiles of the silicide layers 256a-256b and the backside source / drain contacts 258. More specifically, after flipping, as shown in FIG. FIG. 22A to FIG. 22C As shown in FIG. 2 , the portion of the silicide layer 256 a - 256 b formed in the trench 252 has a convex top surface and a convex bottom surface, and the backside source / drain contact 258 formed in the trench 252 has a convex bottom surface 258 bs.

[0056] In the above embodiment, the dielectric layer 220c' is a single-layer structure. In an alternative embodiment, the dielectric layer 220c' may be a multi-layer structure, such as FIG. 23A to FIG. 23B The double-layer structure shown. FIG. 23A to FIG. 23BThe dielectric layer 220c' shown in the figure includes a first layer 220c1 in direct contact with the semiconductor layer 218 and a second layer 220c2 in direct contact with the first layer 220c1. The first layer 220c1 and the second layer 220c2 may have different compositions. The first layer 220c1 may include an oxide layer, such as silicon oxide. The second layer 220c2 may include a nitride layer, such as silicon nitride, silicon oxycarbonitride, silicon carbonitride. The thickness of the first layer 220c1 may be in the range between about 1 nm and 2 nm, and the thickness of the second layer 220c2 may be in the range between about 3 nm and about 4 nm.

[0057] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor structures and their formation. For example, the backside source / drain contact openings can be laterally enlarged to expose a larger surface of the source / drain feature without substantially reducing the volume of the source / drain feature from its backside, thereby facilitating the formation of a silicide layer having a larger contact area with the source / drain feature.

[0058] The embodiments of the present disclosure provide many different embodiments. A semiconductor structure and a method for manufacturing the same are disclosed herein. In one exemplary aspect, the embodiments of the present disclosure relate to a method. The method includes: receiving a workpiece, including: a fin-shaped active area, protruding from a substrate and including a channel area and a source / drain area; and a dummy gate stack, located above the channel area. The method also includes: recessing the source / drain area to form a source / drain trench exposing the substrate; forming a dielectric layer above the substrate and in the source / drain trench; epitaxially forming a source / drain component in direct contact with the top surface of the dielectric layer in the source / drain trench; replacing the dummy gate stack with a gate structure; removing portions of the dielectric layer and the substrate disposed directly below the dielectric layer to form a first contact opening; forming a silicide layer in the first contact opening and below the source / drain component; and forming a conductive layer below the silicide layer to fill the remaining portion of the first contact opening.

[0059] In some embodiments, the method may also include: prior to forming the dielectric layer, epitaxially forming an undoped semiconductor layer in the source / drain trench, wherein the undoped semiconductor layer is in direct contact with the substrate. In some embodiments, forming the dielectric layer includes: depositing a dielectric material layer above the workpiece, the dielectric material layer including a first portion extending along a top surface of the undoped semiconductor layer and a second portion extending along a sidewall surface of the channel region, wherein the first portion is thicker than the second portion; and removing the second portion of the dielectric material layer. In some embodiments, the workpiece may also include: an isolation component disposed between a fin-shaped active region and another fin-shaped active region; and a spacer component located on the isolation component and in direct contact with the source / drain region of the fin-shaped active region, wherein upon completion of epitaxially forming the source / drain component, the source / drain component, the dielectric layer, and the spacer component surround an air gap in a first cross-sectional view cut through the isolation component and the fin-shaped active region. In some embodiments, a portion of the silicide layer substantially fills the air gap. In some embodiments, a portion of the silicide layer and a portion of the conductive layer substantially fill the air gap. In some embodiments, the method may also include: after replacing the dummy gate stack with the gate structure, forming a second contact opening exposing the top surface of the source / drain component; and forming a source / drain contact in the second contact opening. In some embodiments, the fin-shaped active region may include a vertical stack of alternating channel layers and sacrificial layers, and replacing the dummy gate stack with the gate structure may include: selectively removing the dummy gate stack to form a gate trench; selectively removing the sacrificial layer to form a gate opening; and forming a gate structure in the gate trench and the gate opening. In some embodiments, removing the dielectric layer and the portion of the substrate disposed directly below the dielectric layer to form the first contact opening may include: performing a first etching process to selectively remove the portion of the substrate disposed directly below the dielectric layer to expose the dielectric layer to form a trench; and performing a second etching process to selectively remove the dielectric layer to expand the trench to form the first contact opening. The method may also include: after performing the first etching process and before performing the second etching process, forming a dielectric barrier layer extending along the sidewall surface of the trench.

[0060] In another exemplary aspect, the disclosed embodiments are directed to a method. The method includes: forming a source / drain opening extending into a substrate; forming a semiconductor layer in a bottom portion of the source / drain opening; forming a dielectric component in the source / drain opening and on the semiconductor layer; epitaxially growing the source / drain component in the source / drain opening, wherein the source / drain component is in direct contact with the dielectric component; removing a portion of the semiconductor layer and the substrate disposed directly below the semiconductor layer to form a trench; selectively removing the dielectric component to enlarge the trench; after selectively removing the dielectric component, forming a silicide layer in the enlarged trench; and depositing a conductive layer in direct contact with the silicide layer in the enlarged trench.

[0061] In some embodiments, the top surface of the semiconductor layer may be located above the top surface of the substrate, and wherein the dielectric component includes a convex top surface. In some embodiments, the top surface of the semiconductor layer may be substantially coplanar with the top surface of the substrate, and the dielectric component may include a substantially flat top surface. In some embodiments, the top surface of the semiconductor layer may be located below the top surface of the substrate, and the dielectric component may include a concave top surface. In some embodiments, the dielectric component may include a first dielectric layer disposed on a second dielectric layer, and the first dielectric layer and the second dielectric layer may include different compositions. The method may also include: planarizing the substrate from its back side; forming a hard mask layer below the planarized substrate; forming an oxide layer below the hard mask layer; patterning the hard mask layer and the oxide layer to form an opening exposing the semiconductor layer and a portion of the substrate disposed directly below the semiconductor layer; and after depositing the conductive layer, performing a planarization process from the back side of the conductive layer, wherein performing the planarization process also removes the oxide layer.

[0062] In yet another exemplary aspect, embodiments of the present disclosure relate to a semiconductor structure. The semiconductor structure includes: a gate structure encapsulating a plurality of nanostructures disposed above a substrate; a first source / drain component coupled to the plurality of nanostructures and adjacent to the gate structure; a first silicide layer in direct contact with a bottom surface of the first source / drain component; a first source / drain contact disposed directly below the first source / drain component and in direct contact with the first silicide layer; and a dielectric barrier layer providing isolation between the substrate and the first source / drain contact, wherein in a first cross-sectional view cut through the gate structure and the first source / drain component, a portion of the first silicide layer is vertically disposed between the dielectric barrier layer and the first source / drain contact.

[0063] In some embodiments, in a second cross-sectional view cutting through the first source / drain component and not cutting through the gate structure, the first silicide layer spans a first width, and the first source / drain contact spans a second width that is less than the first width. In some embodiments, the semiconductor structure may also include: a second silicide layer directly contacting a top surface of the first source / drain component; and a second source / drain contact directly disposed on the first source / drain component and in direct contact with the second silicide layer. In some embodiments, the semiconductor structure may also include: a second source / drain component coupled to a plurality of nanostructures, wherein the plurality of nanostructures are disposed between the first source / drain component and the second source / drain component; a dielectric layer directly contacting a bottom surface of the second source / drain component; and an undoped semiconductor layer disposed between the dielectric layer and the substrate.

[0064] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: receiving a workpiece, comprising: a fin-shaped active area, protruding from a substrate and including a channel area and a source / drain area; and a dummy gate stack, located above the channel area; recessing the source / drain area to form a source / drain trench exposing the substrate; forming a dielectric layer above the substrate and in the source / drain trench; epitaxially forming a source / drain component in the source / drain trench that is in direct contact with a top surface of the dielectric layer; replacing the dummy gate stack with a gate structure; removing portions of the dielectric layer and the substrate that are disposed directly below the dielectric layer to form a first contact opening; forming a silicide layer in the first contact opening and below the source / drain component; and forming a conductive layer below the silicide layer to fill the remaining portion of the first contact opening.

[0065] In some embodiments, the method further comprises: before forming the dielectric layer, epitaxially forming an undoped semiconductor layer in the source / drain trench, wherein the undoped semiconductor layer is in direct contact with the substrate. In some embodiments, forming the dielectric layer comprises: depositing a dielectric material layer above the workpiece, the dielectric material layer comprising a first portion extending along a top surface of the undoped semiconductor layer and a second portion extending along a sidewall surface of the channel region, wherein the first portion is thicker than the second portion; and removing the second portion of the dielectric material layer. In some embodiments, the workpiece further comprises: an isolation component disposed between the fin-shaped active region and another fin-shaped active region; and a spacer component located on the isolation component and in direct contact with the source / drain region of the fin-shaped active region, wherein upon completion of epitaxially forming the source / drain component, the source / drain component, the dielectric layer, and the spacer component surround an air gap in a first cross-sectional view cut through the isolation component and the fin-shaped active region. In some embodiments, a portion of the silicide layer substantially fills the air gap. In some embodiments, a portion of the silicide layer and a portion of the conductive layer substantially fill the air gap. In some embodiments, the method further comprises: after replacing the dummy gate stack with the gate structure, forming a second contact opening exposing a top surface of the source / drain component; and forming a source / drain contact in the second contact opening. In some embodiments, the fin-shaped active area comprises a vertical stack of alternating channel layers and sacrificial layers, wherein replacing the dummy gate stack with the gate structure comprises: selectively removing the dummy gate stack to form a gate trench; selectively removing the sacrificial layer to form a gate opening; and forming the gate structure in the gate trench and the gate opening. In some embodiments, removing the dielectric layer and the portion of the substrate disposed directly below the dielectric layer to form the first contact opening comprises: performing a first etching process to selectively remove the portion of the substrate disposed directly below the dielectric layer to expose the dielectric layer to form a trench; and performing a second etching process to selectively remove the dielectric layer to enlarge the trench to form the first contact opening. In some embodiments, the method further includes: after performing the first etching process and before performing the second etching process, forming a dielectric barrier layer extending along a sidewall surface of the trench.

[0066] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a source / drain opening extending into a substrate; forming a semiconductor layer in a bottom portion of the source / drain opening; forming a dielectric component in the source / drain opening and on the semiconductor layer; epitaxially growing a source / drain component in the source / drain opening, wherein the source / drain component is in direct contact with the dielectric component; removing portions of the semiconductor layer and the substrate disposed directly below the semiconductor layer to form a trench; selectively removing the dielectric component to expand the trench; after selectively removing the dielectric component, forming a silicide layer in the expanded trench; and depositing a conductive layer in direct contact with the silicide layer in the expanded trench.

[0067] In some embodiments, the top surface of the semiconductor layer is above the top surface of the substrate, and wherein the dielectric component comprises a convex top surface. In some embodiments, the top surface of the semiconductor layer is substantially coplanar with the top surface of the substrate, and wherein the dielectric component comprises a substantially flat top surface. In some embodiments, the top surface of the semiconductor layer is below the top surface of the substrate, and wherein the dielectric component comprises a concave top surface. In some embodiments, the dielectric component comprises a first dielectric layer disposed on a second dielectric layer, the first dielectric layer and the second dielectric layer comprising different compositions. In some embodiments, the method further comprises: planarizing the substrate from a back side thereof; forming a hard mask layer below the planarized substrate; forming an oxide layer below the hard mask layer; patterning the hard mask layer and the oxide layer to form an opening exposing the semiconductor layer and the portion of the substrate disposed directly below the semiconductor layer; and performing a planarization process from the back side of the conductive layer after depositing the conductive layer, wherein performing the planarization process also removes the oxide layer.

[0068] Still other embodiments of the present application provide a semiconductor structure, comprising: a gate structure encapsulating a plurality of nanostructures disposed above a substrate; a first source / drain component coupled to the plurality of nanostructures and adjacent to the gate structure; a first silicide layer in direct contact with a bottom surface of the first source / drain component; a first source / drain contact disposed directly below the first source / drain component and in direct contact with the first silicide layer; and a dielectric barrier layer providing isolation between the substrate and the first source / drain contact, wherein, in a first cross-sectional view cutting through the gate structure and the first source / drain component, a portion of the first silicide layer is vertically disposed between the dielectric barrier layer and the first source / drain contact.

[0069] In some embodiments, in a second cross-sectional view cutting through the first source / drain component and not cutting through the gate structure, the first silicide layer spans a first width, and the first source / drain contact spans a second width that is less than the first width. In some embodiments, the semiconductor structure further comprises: a second silicide layer directly contacting a top surface of the first source / drain component; and a second source / drain contact directly disposed on the first source / drain component and in direct contact with the second silicide layer. In some embodiments, the semiconductor structure further comprises: a second source / drain component coupled to the plurality of nanostructures, wherein the plurality of nanostructures are disposed between the first source / drain component and the second source / drain component; a dielectric layer directly contacting a bottom surface of the second source / drain component; and an undoped semiconductor layer disposed between the dielectric layer and the substrate.

[0070] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a semiconductor structure, include: Receive artifacts, including: a fin-shaped active region protruding from the substrate and including a channel region and source / drain regions; and A dummy gate stack located above the channel region; recessing the source / drain region to form a source / drain trench exposing the substrate; forming a dielectric layer over the substrate and in the source / drain trenches; epitaxially forming a source / drain feature in the source / drain trench in direct contact with a top surface of the dielectric layer; replacing the dummy gate stack with a gate structure; removing the dielectric layer and a portion of the substrate disposed directly below the dielectric layer to form a first contact opening; forming a silicide layer in the first contact opening and under the source / drain feature; and A conductive layer is formed under the silicide layer to fill a remaining portion of the first contact opening.

2. The method according to claim 1, further comprising: include: Before forming the dielectric layer, an undoped semiconductor layer is epitaxially formed in the source / drain trench, wherein the undoped semiconductor layer is in direct contact with the substrate.

3. The method according to claim 2, in, Forming the dielectric layer includes: Depositing a dielectric material layer over the workpiece, the dielectric material layer comprising a first portion extending along a top surface of the undoped semiconductor layer and a second portion extending along a sidewall surface of the channel region, wherein the first portion is thicker than the second portion; and The second portion of the dielectric material layer is removed.

4. The method according to claim 1, in, The artifacts also include: an isolation component disposed between the fin-shaped active region and another fin-shaped active region; and a spacer member located on the isolation member and in direct contact with the source / drain region of the fin-shaped active region, Wherein, upon completion of epitaxially forming the source / drain feature, the source / drain feature, the dielectric layer, and the spacer feature surround an air gap in a first cross-sectional view cutting through the isolation feature and the fin-shaped active region.

5. The method according to claim 4, in, A portion of the silicide layer substantially fills the air gap.

6. The method according to claim 4, in, A portion of the silicide layer and a portion of the conductive layer substantially fill the air gap.

7. The method according to claim 1, further comprising: include: After replacing the dummy gate stack with the gate structure, forming a second contact opening exposing a top surface of the source / drain feature; as well as Source / drain contacts are formed in the second contact openings.

8. The method according to claim 1, in, The fin-shaped active area includes a vertical stack of alternating channel layers and sacrificial layers, Wherein, replacing the dummy gate stack with the gate structure comprises: selectively removing the dummy gate stack to form a gate trench; selectively removing the sacrificial layer to form a gate opening; and The gate structure is formed in the gate trench and the gate opening.

9. A method of forming a semiconductor structure, include: forming source / drain openings extending into the substrate; forming a semiconductor layer in a bottom portion of the source / drain opening; forming a dielectric feature in the source / drain openings and on the semiconductor layer; epitaxially growing a source / drain feature in the source / drain opening, wherein the source / drain feature is in direct contact with the dielectric feature; removing the semiconductor layer and a portion of the substrate disposed directly below the semiconductor layer to form a trench; selectively removing the dielectric member to enlarge the trench; forming a silicide layer in the enlarged trench after selectively removing the dielectric feature; and A conductive layer is deposited in the enlarged trench in direct contact with the silicide layer.

10. A semiconductor structure, include: A gate structure encapsulating a plurality of nanostructures disposed above the substrate; a first source / drain feature coupled to the plurality of nanostructures and adjacent to the gate structure; a first silicide layer directly contacting a bottom surface of the first source / drain component; a first source / drain contact disposed directly below the first source / drain feature and in direct contact with the first silicide layer; as well as a dielectric barrier layer providing isolation between the substrate and the first source / drain contacts, Wherein, in a first cross-sectional view cutting through the gate structure and the first source / drain component, a portion of the first silicide layer is vertically disposed between the dielectric barrier layer and the first source / drain contact.

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