Silicon controlled electrostatic discharge protection device

Abstract

An apparatus includes: a first silicon controlled rectifier including a first PNP bipolar junction transistor (BJT) and a first NPN BJT; and a field effect transistor (FET) configured to trigger the first silicon controlled rectifier based on an electrostatic discharge occurring between an anode of the first silicon controlled rectifier and a cathode of the first silicon controlled rectifier. An emitter of the first PNP BJT corresponds to a plurality of first p + regions spaced apart from each other in a first direction. The FET is connected to the first silicon controlled rectifier through at least one first n + region disposed between the plurality of first p + regions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2023-0074383 filed in the Korean Intellectual Property Office on June 9, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to electrostatic discharge protection, and more particularly, to an apparatus for electrostatic discharge protection using a rectifier, such as a silicon-controlled rectifier. Background Art

[0004] Electrostatic discharge (ESD) may cause malfunction or even damage the integrated circuit. Therefore, the integrated circuit may include an electrostatic discharge protection component, and the electrostatic discharge protection component may protect the internal circuit from electrostatic discharge generated outside the integrated circuit. Due to the development of semiconductor technology, the size of the components in the integrated circuit can be reduced, the operating voltage of the components in the integrated circuit can be reduced to reduce power consumption, and the frequency of the signals input and output to the integrated circuit can be increased to obtain higher performance. Therefore, the components for electrostatic discharge protection may need to meet various requirements. Summary of the invention

[0005] An apparatus for providing electrostatic discharge protection with low trigger voltage and low leakage current is provided.

[0006] According to one aspect of the present disclosure, a device includes: a first thyristor rectifier, which includes a first PNP bipolar junction transistor (BJT) and a first NPN BJT whose bases and collectors are cross-coupled; and a field effect transistor (FET), which is configured to trigger the first thyristor rectifier based on an electrostatic discharge occurring between an anode and a cathode of the first thyristor rectifier, wherein an emitter of the first PNP BJT corresponds to a plurality of first p+ regions spaced apart from each other in a first direction, and wherein the FET is connected to the first thyristor rectifier through at least one first n+ region disposed between the plurality of first p+ regions.

[0007] According to another aspect of the present disclosure, a device includes: a first thyristor rectifier, which includes a first PNP bipolar junction transistor (BJT) and a first NPN BJT whose bases and collectors are cross-coupled; and a field effect transistor (FET), which is configured to trigger the first thyristor rectifier based on an electrostatic discharge occurring between an anode and a cathode of the first thyristor rectifier, wherein an emitter of the first NPN BJT corresponds to a plurality of n+ regions spaced apart from each other in a first direction, and wherein the FET is connected to the first thyristor rectifier through at least one p+ region disposed between the plurality of n+ regions.

[0008] According to another aspect of the present disclosure, a device includes: a p-well extending in a first direction; a first n-well, which is adjacent to the p-well in a second direction intersecting the first direction, and the first n-well extends in the first direction; a first n+ region, which is electrically connected to a cathode node and is disposed in the p-well; a first p+ region, which is electrically connected to the cathode node and is disposed in the p-well; a plurality of second p+ regions, which are electrically connected to an anode node, and the plurality of second p+ regions are spaced apart from each other in the first n-well in the first direction; and at least one second n+ region, which is electrically connected to a field effect transistor (FET), the field effect transistor being electrically connected to the cathode node or the anode node, and the at least one second n+ region being disposed between the plurality of second p+ regions in the first n-well.

[0009] According to another aspect of the present disclosure, a device includes: a p-well extending in a first direction; a first n-well adjacent to the p-well in a second direction intersecting the first direction, the first n-well extending in the first direction; a first n+ region electrically connected to an anode node, the first n+ region being disposed in the first n-well; a first p+ region electrically connected to the anode node, the first p+ region being disposed in the first n-well; a plurality of second n+ regions electrically connected to a cathode node, the plurality of second n+ regions being spaced apart from each other in the first direction in the p-well; and at least one second p+ region electrically connected to a field effect transistor (FET), the field effect transistor being electrically connected to a cathode node or an anode node, the at least one second p+ region being disposed between the plurality of second n+ regions in the p-well. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram showing an apparatus according to an embodiment;

[0012] Figure 2 is a cross-sectional view showing a silicon controlled rectifier according to an embodiment;

[0013] Figure 3 is a graph showing characteristics of a silicon controlled rectifier according to an embodiment;

[0014] Figure 4 is a schematic diagram showing the layout of an apparatus according to an embodiment;

[0015] Figure 5 is a circuit diagram showing an equivalent circuit of a device according to an embodiment;

[0016] Figure 6 is a graph showing characteristics of a device according to an embodiment;

[0017] Fig. 7A and Figure 7B is a schematic diagram showing an example of a layout of an apparatus according to an embodiment;

[0018] Fig. 8A and Figure 8B is a schematic diagram showing an example of a layout of an apparatus according to an embodiment;

[0019] Fig. 9 is a graph showing characteristics of a device according to an embodiment;

[0020] Fig.10 is a circuit diagram showing an equivalent circuit of a device according to an embodiment;

[0021] Fig.11 is a schematic diagram showing the layout of an apparatus according to an embodiment;

[0022] Fig.12 is a schematic diagram showing the layout of an apparatus according to an embodiment;

[0023] Fig.13 is a circuit diagram showing an equivalent circuit of a device according to an embodiment;

[0024] Fig.14 is a schematic diagram showing the layout of an apparatus according to an embodiment;

[0025] Fig.15 is a circuit diagram showing an equivalent circuit of a device according to an embodiment;

[0026] Fig.16 is a schematic diagram showing the layout of an apparatus according to an embodiment;

[0027] Fig.17 is a circuit diagram showing an equivalent circuit of a device according to an embodiment;

[0028] Fig.18 is a schematic diagram showing the layout of an apparatus according to an embodiment;

[0029] Fig.19 is a circuit diagram showing an equivalent circuit of a device according to an embodiment;

[0030] Fig. 20 is a graph showing characteristics of a device according to an embodiment;

[0031] Fig.21 is a schematic diagram showing the layout of an apparatus according to an embodiment;

[0032] Fig. 22 is a circuit diagram of an apparatus according to an embodiment;

[0033] Fig.23 is a graph showing characteristics of a device according to an embodiment;

[0034] Fig.24 is a circuit diagram of an apparatus according to an embodiment;

[0035] Fig.25 is a graph showing characteristics of a device according to an embodiment;

[0036] Fig.26 is a circuit diagram of an apparatus according to an embodiment; and

[0037] Fig. 27 is a graph showing characteristics of the device according to the embodiment. DETAILED DESCRIPTION

[0038] This description only illustrates the principles of the present disclosure. Those skilled in the art will be able to design one or more arrangements that, although not explicitly described herein, embody the principles of the present disclosure. In addition, all examples described herein are primarily intended to be explicitly used only for explanatory purposes to help the reader understand the principles of the present disclosure and the concepts contributed by the inventors to promote this area, and should be interpreted as not being limited to these specifically described examples and conditions. In addition, all statements describing the principles, aspects and embodiments of the present disclosure and their specific examples herein are intended to cover their equivalents.

[0039] The terms used in this disclosure are only used to describe specific embodiments, and may not be intended to limit the scope of another embodiment. Singular expressions may include plural expressions, unless clearly indicated differently in the context. The terms used herein (including technical or scientific terms) may have the same meaning as the meanings generally understood by the personnel of the ordinary knowledge in the technical field described in this disclosure. The terms defined in the general dictionary in the terms used in this disclosure may be interpreted with the same or similar meanings as the contextual meanings of the related art, and unless clearly defined in this disclosure, are not interpreted with ideal or overly formal meanings. In some cases, even the terms defined in this disclosure cannot be interpreted as excluding embodiments of the present disclosure.

[0040] In one or more embodiments of the present disclosure described below, a hardware method is described as an example. However, since one or more embodiments of the present disclosure include techniques using both hardware and software, one or more embodiments of the present disclosure do not exclude a software-based method.

[0041] In addition, in the present disclosure, in order to determine whether a specific condition is met or reached, the expression of greater than or less than can be used, but this is only a description for expressing an example, and does not exclude the description of greater than or equal to or less than or equal to. The condition described as "greater than or equal to" can be replaced by "greater than", the condition described as "less than or equal to" can be replaced by "less than", and the condition described as "greater than or equal to and less than" can be replaced by "greater than and less than or equal to". In addition, hereinafter, "A" to "B" means at least one of the elements from A (including A) to B (including B).

[0042] Figure 1 1 is a block diagram showing an apparatus 10 according to an embodiment. In some embodiments, the apparatus 10 may include an integrated circuit manufactured by a semiconductor process. For example, the apparatus 10 may be a chip or a die, or a semiconductor package including at least one chip or a die. Figure 1 As shown, the device 10 may include a first pad 11, a second pad 12, an ESD protection device 13, and an internal circuit 14. Herein, the ESD protection device 13 or the device 10 including the ESD protection device 13 may be referred to as a "device" for ESD protection.

[0043] The first pad 11 and the second pad 12 may be exposed to the outside of the device 10, and the first pad 11 and / or the second pad 12 may be used to send signals or power. For example, the first pad 11 may be one of an input pad for receiving a signal from the outside of the device 10, an output pad for outputting a signal generated by the device 10 to the outside, and an input / output pad for receiving or outputting a signal according to a mode. The second pad 12 may also be a power pad for receiving a positive power supply voltage and / or a negative power supply voltage to provide power to the device 10. Figure 1 As shown, the first pad 11 can be connected to the first node N1. The second pad 12 can be connected to the second node N2. In this document, when two or more components are electrically connected, the two or more components can be simply referred to as being connected. For example, when two components are connected through a resistor (e.g., a parasitic resistor), the two components can be referred to as being operatively or electrically "connected". In addition, when two or more components are directly connected, the two or more components can be referred to as being "coupled".

[0044] When electrostatic discharge occurs between the first pad 11 and the second pad 12, the electrostatic discharge protection device 13 may be a low impedance discharge path between the first pad 11 and the second pad 12. Therefore, the internal circuit 14 may be protected from electrostatic discharge by the electrostatic discharge protection device 13. In the following, positive electrostatic discharge occurs between the first pad 11 and the second pad 12, that is, between the first node N1 and the second node N2, and therefore, the electrostatic discharge protection device 13 is a low impedance path through which current flows from the first node N1 to the second node N2, but it should be noted that the embodiment is not limited thereto.

[0045] Due to the development of semiconductor technology, the size of the elements in the internal circuit 14 may be reduced, and the junction depth and thickness of the gate oxide may be reduced. In addition, for low power consumption and high operating speed, the operating voltage of the internal circuit 14, that is, the voltage difference between the positive power supply voltage and the negative power supply voltage, may be reduced, and the frequency of the signal input and output through the first pad 11 and / or the second pad 12 may be increased. Therefore, the electrostatic discharge protection device 13 may need to meet more stringent requirements, such as high current driving capability, low operating start voltage, low leakage current, low capacitance, etc.

[0046] like Figure 1 As shown, the electrostatic discharge protection device 13 may include a thyristor rectifier (SCR) 13_1 and a trigger transistor 13_2. The anode of the thyristor rectifier 13_1 may be connected to the first node N1, and the cathode of the thyristor rectifier 13_1 may be connected to the second node N2. In this article, the first node N1 may be referred to as an anode or an anode node, and the second node N2 may be referred to as a cathode or a cathode node.

[0047] As reference below Figure 2 As described above, the thyristor 13_1 can have a high current density based on double injection, and can provide high electrostatic discharge performance per unit area, reduced area, and reduced capacitance. However, as shown below with reference to Figure 3 As described above, due to the high breakdown voltage between the wells, the thyristor rectifier (SCR) as a rapid return element may have a very high operation start voltage, and therefore, the internal circuit 14 with a low operating voltage may be damaged by electrostatic discharge. The trigger transistor 13_2 can generate a trigger current when electrostatic discharge occurs, and the trigger current can cause the thyristor rectifier 13_1 to form a low impedance path in advance. Therefore, the elements of the internal circuit 14 with a low operating voltage can be safely protected from electrostatic discharge, and the malfunction of the device 10 can be prevented.

[0048] As described below with reference to the accompanying drawings, a low trigger voltage is provided by the trigger transistor 13_2. At the same time, the leakage current caused by the trigger transistor 13_2 can be reduced or eliminated. In addition, the holding voltage can be increased, and therefore, the latching of the thyristor 13_1 can be prevented.

[0049] Figure 2 is a cross-sectional view showing a silicon controlled rectifier 20 according to an embodiment, Figure 3 is a graph showing the characteristics of the thyristor 20 according to the embodiment. For example, Figure 2 The cross-sectional view shows a cross section of the thyristor 20 along a plane formed by the X-axis and the Z-axis and an equivalent circuit, and Figure 3 The graph of FIG. 1 shows a sharp return curve of the thyristor rectifier 20 .

[0050] Here, the X-axis direction and the Y-axis direction may be referred to as the first direction and the second direction, respectively, and the Z-axis direction may be referred to as the vertical direction. The plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, a component arranged in the +Z direction relative to other components may be referred to as above other components, and a component arranged in the -Z direction relative to other components may be referred to as below other components. In addition, the "area" of a component may refer to the size occupied by the component on a plane parallel to the horizontal plane, and the "width" of a component may refer to the length in a direction orthogonal to the direction in which the component extends. The surface exposed in the +Z direction may be referred to as a "top surface", the surface exposed in the -Z direction may be referred to as a "bottom surface", and the surface exposed in the ±X direction or the ±Y direction may be referred to as a "side surface". A pattern comprising a conductive material may be referred to as a "conductive pattern" or may be simply referred to as a "pattern".

[0051] exist Figure 2 In the embodiment, the thyristor 20 may include a PNP bipolar junction transistor (BJT) (Qp) and an NPN BJT (Qn), and the base and collector of the PNP bipolar transistor and the NPN BJT (Qn) may be cross-coupled. The emitter of the PNP BJT may be referred to as the anode of the thyristor 20, the collector (Qp) of the PNP BJT and the base (Qn) of the NPN BJT that are interconnected may be referred to as the gate of the thyristor 20, and the emitter (Qn) of the NPN BJT may be referred to as the cathode of the thyristor 20. The resistor Ra connected between the anode and the base of the PNP BJT (Qp) (or the collector of the NPN BJT (Qn)) may include an n-well (NW) resistor. In addition, the resistor Rp connected between the cathode and the base of the NPN BJT (Qn) (or the collector of the PNP BJT (Qp)) may include a p-well (PW) resistor.

[0052] like Figure 2 As shown, the silicon controlled rectifier 20 can be configured by a well and a doped region disposed in the well, each doped region having its own conductivity type (e.g., p-type or n-type). For example, the n-well NW and the p-well PW can be disposed on a p-type substrate SUB. The first n+ region n1 and the first p+ region p1 can be disposed in the n-well NW, and the second n+ region n2 and the second p+ region p2 can be disposed in the p-well PW. Here, the n+ region can have an n-type dopant concentration higher than the n-type dopant concentration of the n-well NW, and the p+ region can have a p-type dopant concentration higher than the p-type dopant concentration of the p-well PW. In some embodiments, the p-well PW can be omitted, and the p-type substrate SUB can be used as the p-well PW.

[0053] The first contact C1 and the second contact C2 may be disposed on the first n+ region n1 and the first p+ region p1, respectively, and the first contact C1 and the second contact C2 may be interconnected through the first conductive pattern N11. The third contact C3 and the fourth contact C4 may be disposed on the second n+ region n2 and the second p+ region p2, respectively, and the third contact C3 and the fourth contact C4 may be interconnected through the second conductive pattern N12. Therefore, the PNP BJT (Qp) may be formed by the first p+ region p1 (i.e., emitter), the n-well (NW) (i.e., base), and the p-well PW (i.e., collector), and the NPN BJT (Qn) may be formed by the second n+ region (i.e., emitter), the p-well PW (i.e., base), and the n-well NW (i.e., collector). In some embodiments, the first n+ region n1 and / or the second p+ region p2 may be omitted, and thus the resistor Ra and / or the resistor Rp may be omitted. In some embodiments, a through hole may be disposed between the contact and the conductive pattern.

[0054] exist Figure 3 In the embodiment of the present invention, the thyristor 20 may have a characteristic corresponding to a sharp return curve. For example, as the voltage between the anode and the cathode increases, a breakdown between the n-well NW and the p-well PW may occur at a first point 31. At a second point 32, since the voltage reaches a trigger voltage (Vt), the PNP BJT (Qp) and the NPN BJT (Qn) may be turned on respectively, whereby the voltage may be reduced and the current may be increased. At a third point 33, the voltage may reach a bipolar holding voltage Vh, and an electrostatic discharge current may flow in a latching mode.

[0055] Due to the high breakdown voltage between the n-well NW and the p-well PW (i.e., the voltage at the first point 31), the trigger voltage Vt can reach, for example, 18V to 20V, and may not be suitable for protecting components of internal circuits with low operating voltages such as 3V or 1.5V. In addition, the bipolar holding voltage Vh may depend on the forward voltage drop. After an electrostatic discharge occurs, if the bipolar holding voltage Vh is less than the sum of the operating voltage and the margin of the internal circuit, the PNP BJT (Qp) and the NPN BJT (Qn) may not be turned off, and signal distortion, device degradation and / or damage may occur. As described below with reference to the accompanying drawings, the trigger circuit can reduce the trigger voltage Vt in the thyristor 20 while increasing the bipolar holding voltage Vh.

[0056] Figure 4 4 is a schematic diagram showing a layout 40 of a device according to an embodiment. For ease of illustration, contacts and conductive patterns for interconnecting p+ regions, n+ regions and gates are omitted. Figure 4 In the embodiment, the p+ region and the n+ region respectively disposed in the first n-well NW1 and the second n-well NW2 are additionally shown at the bottom as a first segment SEG1 and a second segment SEG2. Figure 4 The structure may be formed in a p-type substrate, and the first p-well PW1 and the second p-well PW2 may correspond to the p-type substrate.

[0057] exist Figure 4 In the embodiment, the layout 40 may include an SCR structure 41 and a FET structure 42. Figure 5 As described, the SCR structure 41 may correspond to two silicon controlled rectifiers, and the FET structure 42 may correspond to a field effect transistor (FET) as a trigger transistor.

[0058] The SCR structure 41 may include a first n-well NW1, a second n-well NW2, and a first p-well PW1. Figure 4 As shown, the first n-well NW1, the second n-well NW2 and the first p-well PW1 extend in the X-axis direction. Figure 4 As shown, the first n-well NW1 and the second n-well NW2 may be adjacent to the first p-well PW1 in the Y-axis direction. The first segment SEG1 may be disposed in the first n-well NW1, and the first segment SEG1 may include a first p+ region p1 and a first n+ region n1. Figure 4As shown, the first p+ regions p1 may be spaced apart from each other in the X-axis direction, and the first n+ region n1 may be disposed between the first p+ regions p1. The first p+ region p1 may be electrically connected to the first node N1, and the first n+ region n1 may be electrically connected to the third node N3. The second n+ region n2, the second p+ region p2, and the third n+ region n3 may be disposed in the first p-well PW1. The second n+ region n2, the second p+ region p2, and the third n+ region n3 may be electrically connected to the second node N2. The second segment SEG2 may be disposed in the second n-well NW2, and the second segment SEG2 may include the third p+ region p3 and the fourth n+ region n4. Figure 4 As shown, the third p+ regions p3 may be spaced apart from each other in the X-axis direction, and the fourth n+ region n4 may be disposed between the third p+ regions p3. The third p+ region p3 may be electrically connected to the first node N1, and the fourth n+ region may be electrically connected to the third node N3.

[0059] The FET structure 42 may include a second p-well PW2 extending in the X-axis direction. A fifth n+ region n5, a sixth n+ region n6, and a fourth p+ region p4 may be disposed in the second p-well PW2, and a gate electrode G may be disposed on a region between the fifth n+ region n5 and the sixth n+ region n6. The fifth n+ region n5 may be electrically connected to a third node N3, and the sixth n+ region n6, the fourth p+ region p4, and the gate electrode G may be electrically connected to the second node N2. The fifth n+ region n5, the sixth n+ region n6, and the gate electrode G may correspond to an n-channel field effect transistor (NFET), and therefore, the NFET may be connected to two thyristors through the first n+ region n1 and the fourth n+ region n4 connected to the third node N3, respectively.

[0060] Figure 5 is a circuit diagram showing an equivalent circuit 50 of a device according to an embodiment. For example, Figure 5 The circuit diagram shows the corresponding Figure 4 The equivalent circuit 50 of the layout 40 is shown in FIG. Figure 4 describe Figure 5 .

[0061] The equivalent circuit 50 may include a first silicon controlled rectifier SCR1, a second silicon controlled rectifier SCR2, an NFET Mn, a third NPN BJT Qn3, a first segment resistor R SEG1 , the second segment resistor R SEG2and a third p-well resistor Rp3. The first thyristor rectifier SCR1 may include a first PNP BJT Qp1, a first NPN BJT Qn1, and a first p-well resistor Rp1, and the second thyristor rectifier SCR2 may include a second PNP BJT Qp2, a second NPN BJT Qn2, and a second p-well resistor Rp2. In the present disclosure, the first thyristor rectifier SCR1 and the second thyristor rectifier SCR2 are examples of various rectifiers that can be used in the embodiments. In the present disclosure, the first thyristor rectifier SCR1 may be referred to as a "first rectifier", and the second thyristor rectifier SCR2 may be referred to as a "second rectifier".

[0062] The first PNP BJT Qp1 may include an emitter corresponding to the first p+ region p1, a base corresponding to the first n-well NW1, and a collector corresponding to the first p-well PW1. The first NPN BJT Qn1 may include a collector corresponding to the first n-well NW1, a base corresponding to the first p-well PW1, and an emitter corresponding to the second n+ region n2. The second PNP BJT Qp2 may include an emitter corresponding to the second p+ region p2, a base corresponding to the second n-well NW2, and a collector corresponding to the first p-well PW1. The second NPN BJT (Qn2) may include a collector corresponding to the second n-well NW2, a base corresponding to the first p-well PW1, and an emitter corresponding to the third n+ region n3. Figure 5 The first segment resistor R SEG1 The second segment resistor R SEG2 It may correspond to a resistor between the second n well NW2 and the fourth n+ region n4. Figure 5 The first p-well resistor Rp1 and the second p-well resistor Rp2 may correspond to resistors between the first p-well PW1 and the second p+ region p2, respectively.

[0063] The emitter of the PNP BJT may correspond to a p+ region divided by an n+ region as in the first segment SEG1 and the second segment SEG2, rather than one p+ region formed as a whole, and therefore, due to the divided p+ region, the emitter injection efficiency may be suppressed and the base recombination may be increased. Therefore, the voltage drop between the first node N1 and the second node N2 may be increased, and the holding voltage may be increased. In addition, in the silicon controlled rectifier, the well junction path may be opened, and the leakage current of the NFET Mn may be controlled by designing the leakage current of the NFET Mn to be through the split emitter. Therefore, the punch-through and penetration phenomena of the NFET Mn may be solved, and the leakage current may be reduced or eliminated, which is a non-limiting advantage of the present disclosure. Due to the low trigger voltage, the internal circuit with a low operating voltage may be safely protected, and at the same time, due to the low leakage current, unnecessary power consumption may be eliminated.

[0064] The NFET Mn may include a drain corresponding to the fifth n+ region n5, a gate corresponding to the gate electrode G, and a source corresponding to the sixth n+ region n6. The third NPN BJT Qn3 may include a collector corresponding to the fifth n+ region n5, a base corresponding to the second p-well PW2, and an emitter corresponding to the sixth n+ region n6. Figure 5 The third p-well resistor Rp3 may correspond to a resistor between the second p-well PW2 and the fourth p+ region p4.

[0065] Figure 6 is a graph showing the characteristics of the device according to the embodiment. For example, Figure 6 Shows the corresponding Figure 5 The rapid return curves S1 to S4 of the equivalent circuit 50 are shown in FIG. Figure 5 describe Figure 6 .

[0066] In some embodiments, you can adjust Figure 5 For example, when the channel width of the NFET Mn increases, the current driving capability of the NFET Mn can be improved, and the first silicon controlled rectifier SCR1 and the second silicon controlled rectifier SCR2 can operate earlier. That is, as the channel width of the NFET Mn increases, the trigger voltage can be reduced, as shown in the first to fourth sharp return curves S1 to S4.

[0067] Fig. 7A and Figure 7B is a schematic diagram showing an example of the layout of the device according to the embodiment. For example, Fig. 7A and Figure 7B It shows the implementation Figure 5 An example of the layout of the equivalent circuit 50 is shown below. Fig. 7A and Figure 7B Overlapping descriptions.

[0068] exist Fig. 7A In the example, the layout 70a may include an SCR region 71 and a FET region 72. Fig. 7A As shown in FIG. 1 , each of the SCR region 71 and the FET region 72 may be surrounded by a first p+ region p1 on a p-well. In the SCR region 71, the first to third n-wells NW1 to NW3 may extend in the X-axis direction. Figure 4 As described above, the n+ region and the p+ region may be alternately disposed in each of the first to third n-wells NW1 to NW3 in the X-axis direction, and thus each emitter of the PNP BJT may be separated.

[0069] In the FET region 72, the first n+ region n1, the gate electrode G, and the second n+ region n2 may extend in the X-axis direction. The first n+ region n1, the gate electrode G, and the second n+ region n2 may correspond to the NFET Mn. Fig. 7A In the example of FIG. 4 , the NFET Mn may be a planar transistor, and thus the gate electrode G may be disposed on a region between the first n+ region n1 and the second n+ region n2 .

[0070] exist Figure 7B In the example, the layout 70b may include an SCR region 71 and a FET region 72. Figure 7B As shown in FIG. 1 , each of the SCR region 71 and the FET region 72 may be surrounded by a first p+ region p1 on a p-well. In the SCR region 71, the first to third n-wells NW1 to NW3 may extend in the X-axis direction. Figure 4 As described above, the n+ region and the p+ region may be alternately disposed in each of the first to third n-wells NW1 to NW3 in the X-axis direction, and thus, each emitter of the PNP BJT may be separated.

[0071] The layout 70b may include a gate electrode G extending in the Y-axis direction. Figure 7B As shown, in the FET region 72, the gate electrode G may extend in the Y-axis direction, and the gate electrode G may be formed corresponding to Figure 5 The NFET Mn is a plurality of NFETs connected in parallel with each other. Figure 7BIn the example of , each of the plurality of NFETs may be a three-dimensional transistor. For example, as a non-limiting example, the NFET may include a FinFET formed by a gate electrode crossing a fin-shaped active pattern extending in the X-axis direction, a gate all-around field effect transistor (GAAFET) including a nanowire as an active pattern passing through the gate electrode, a multi-bridge channel field effect transistor (MBCFET) including a nanosheet as an active pattern passing through the gate electrode, and a vertical field effect transistor (VFET) including an active pattern passing through the gate electrode in a vertical direction.

[0072] In some embodiments, Figure 7B The layout 70b may include an MBCFET, and at least one nanosheet may pass through each gate electrode G in the X-axis direction. At least one nanosheet may be connected to a doped region (or diffusion region) disposed on both sides of the gate electrode. Therefore, the gate electrode may extend in the Y-axis direction between adjacent regions in the n+ region and the p+ region respectively disposed in the first n-well NW1 to the third n-well NW3. In some embodiments, the gate electrode may be removed from regions other than the FET region 72.

[0073] Fig. 8A and Figure 8B is a schematic diagram showing an example of a layout of a device according to an embodiment, and Fig. 9 is a graph showing the characteristics of the device according to the embodiment. For example, Fig. 8A and Figure 8B It shows the implementation Figure 5 An example of a layout of an equivalent circuit 50, and Fig. 9 Shows the corresponding Figure 5 The rapid return curves S1 to S4 of the equivalent circuit 50 are shown below. Fig. 8A and Figure 8B In the description of Fig. 7A and Figure 7B Description given.

[0074] exist Fig. 8A and Figure 8B , each of the layouts 80a and 80b may include an SCR region 81 and a FET region 82. Each of the SCR region 81 and the FET region 82 may be surrounded by a first p+ region p1 on a p-well. In the SCR region 81, the first to third n-wells NW1 to NW3 may extend in the X-axis direction. In each of the first to third n-wells NW1 to NW3, n+ regions and p+ regions may be alternately arranged in the X-axis direction, and thus, the emitter of the PNP BJT may be separated.

[0075] The ratio between the n+ region and the p+ region provided in each of the first to third n-wells NW1 to NW3 may be determined according to the required specifications. Fig. 8A As shown, more p+ regions can be provided than n+ regions, and as Figure 8B As shown, more n+ regions can be provided than p+ regions.

[0076] Fig. 9 The first to fourth sharp return curves S1 to S4 are shown, in which the holding voltage and the leakage current may increase as the ratio of the n+ region increases.

[0077] Fig.10 1 is a circuit diagram showing an equivalent circuit 100 of a device according to an embodiment. Figure 5 Compared with the equivalent circuit 50, Fig.10 The equivalent circuit 100 of may include a p-channel field effect transistor (PFET) Mp as a trigger transistor. Fig.10 In the description of the drawings, the description already given with reference to the accompanying drawings will be omitted.

[0078] In some embodiments, the equivalent circuit 100 may include a first thyristor SCR1 and a second thyristor SCR2, a PFET Mp, a third PNP BJT Qp3, a first segment resistor R SEG1 and the second segment resistor R SEG2 and an n-well resistor Rn. The first thyristor SCR1 may include a first PNP BJT Qp1, a first NPN BJT Qn1, and a first p-well resistor Rp1, and the second thyristor SCR2 may include a second PNP BJT Qp2, a second NPN BJT Qn2, and a second p-well resistor Rp2. When electrostatic discharge occurs between the first node N1 and the second node N2, the PFET Mp may generate a trigger current, and thus the first thyristor SCR1 and the second thyristor SCR2 may be driven in advance.

[0079] Fig.11 is a schematic diagram showing a layout 110 of an apparatus according to an embodiment. For example, Fig.11 Shows the corresponding Fig.10 Layout 110 of the equivalent circuit 100. For ease of illustration, contacts and conductive patterns for interconnecting the p+ region, n+ region and gate are omitted. Fig.11 In the embodiment, the p+ region and the n+ region respectively disposed in the first n-well NW1 and the second n-well NW2 are additionally shown at the bottom as the first segment SEG1 and the second segment SEG2. Fig.11The structure may be formed in a p-type substrate, and the first p-well PW1 and the second p-well PW2 may correspond to the p-type substrate. Fig.11 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0080] exist Fig.11 In the embodiment, the layout 110 may include an SCR structure 111 and a FET structure 112. The SCR structure 111 may include a first n-well NW1, a second n-well NW2, and a p-well PW extending in the X-axis direction. Fig.11 As shown, the first n-well NW1 and the second n-well NW2 may be adjacent to the p-well PW in the Y-axis direction. The first segment SEG1 may be disposed in the first n-well NW1, and the first segment SEG1 may include a first p+ region p1 and a first n+ region n1. Fig.11 As shown, the first p+ regions p1 may be spaced apart from each other in the X-axis direction, and the first n+ region n1 may be disposed between the first p+ regions p1. The first p+ region p1 may be electrically connected to the first node N1, and the first n+ region n1 may be electrically connected to the third node N3. The second n+ region n2, the second p+ region p2, and the third n+ region n3 may be disposed in the p-well PW. The second n+ region n2, the second p+ region p2, and the third n+ region n3 may be electrically connected to the second node N2. The second segment SEG2 may be disposed in the second n-well NW2, and the second segment SEG2 may include the third p+ region p3 and the fourth n+ region n4. Fig.11 As shown, the third p+ regions p3 may be spaced apart from each other in the X-axis direction, and the fourth n+ regions n4 may be disposed between the third p+ regions p3. The third p+ regions p3 may be electrically connected to the first node N1, and the fourth n+ regions n4 may be electrically connected to the third node N3.

[0081] The FET structure 112 may include a third n-well NW3 extending in the X-axis direction. A fourth p+ region p4, a fifth p+ region p5, and a fifth n+ region n5 may be disposed in the third n-well NW3, and a gate electrode G may be disposed on a region between the fourth p+ region p4 and the fifth p+ region p5. The fourth p+ region p4 may be electrically connected to a third node N3, and the fifth p+ region p5, the fifth n+ region n5, and the gate electrode G may be electrically connected to the second node N2. The fourth p+ region p4, the fifth p+ region p5, and the gate electrode G may correspond to Fig.10 Therefore, the PFET Mp can be connected to two thyristors through the first n+ region n1 and the fourth n+ region n4 connected to the third node N3, respectively, that is, Fig.10 The first silicon controlled rectifier SCR1 and the second silicon controlled rectifier SCR2.

[0082] Fig.10The first PNP BJT Qp1 may include an emitter corresponding to the first p+ region p1, a base corresponding to the first n-well NW1, and a collector corresponding to the p-well PW. The first NPN BJT Qn1 may include a collector corresponding to the first n-well NW1, a base corresponding to the p-well PW, and an emitter corresponding to the second n+ region n2. The second PNP BJT Qp2 may include an emitter corresponding to the second p+ region p2, a base corresponding to the second n-well NW2, and a collector corresponding to the p-well PW. The second NPN BJT Qn2 may include a collector corresponding to the second n-well NW2, a base corresponding to the p-well PW, and an emitter corresponding to the third n+ region n3. The first segment resistor R SEG1 The resistor between the first n-well NW1 and the first n+ region n1 may correspond to the second segment resistor R SEG2 It may correspond to a resistor between the second n-well NW2 and the fourth n+ region n4. In addition, the first p-well resistor Rp1 and the second p-well resistor Rp2 may correspond to a resistor between the p-well PW and the second p+ region p2, respectively.

[0083] The PFET Mp may include a source corresponding to the fourth p+ region p4, a gate corresponding to the gate electrode G, and a drain corresponding to the fifth p+ region p5. The third PNP BJT Qp3 may include a collector corresponding to the fourth p+ region p4, a base corresponding to the third n-well NW3, and an emitter corresponding to the fifth p+ region p5. Fig.10 The n-well resistor Rn may correspond to a resistor between the second n-well NW2 and the fifth n+ region n5.

[0084] Fig.12 1 is a diagram showing a layout 120 of a device according to an embodiment. For example, Fig.12 It shows the implementation Fig.10 An example of the layout of the equivalent circuit 100 is shown below. Fig.12 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0085] exist Fig.12 In the embodiment, the layout 120 may include an SCR region 121 and a FET region 122. Fig.12 As shown, each of the SCR region 121 and the FET region 122 may be surrounded by a first p+ region p1 on the p-well. In the SCR region 121, the first to third n-wells NW1 to NW3 may extend in the X-axis direction. Fig.11 As described above, the n+ region and the p+ region may be alternately disposed in each of the first to third n-wells NW1 to NW3 in the X-axis direction, and thus each emitter of the PNP BJT may be separated.

[0086] In the FET region 122, the fourth n-wells NW4 may extend in the X-axis direction and are connected in parallel to each other and correspond to Fig.10 A plurality of PFETs of the PFET Mp may be disposed in the fourth n-well NW4. For example, the layout 120 may include MBCFETs, and at least one nanosheet may pass through each of the gate electrodes G in the X-axis direction. The first n+ region n1 may surround the plurality of PFETs on the fourth n-well NW4.

[0087] Fig.13 1 is a circuit diagram showing an equivalent circuit 130 of a device according to an embodiment. Figure 5 Compared with the equivalent circuit 50, Fig.13 In the equivalent circuit 130, instead of the PNP BJT transistor, the NPN BJT transistor may include a separate emitter. Fig.13 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0088] The equivalent circuit 130 may include a first silicon controlled rectifier SCR1 and a second silicon controlled rectifier SCR2, an NFET Mn, a third NPN BJT Qn3, a segment resistor R SEG and a p-well resistor Rp. The first thyristor SCR1 may include a first PNP BJT Qp1, a first NPN BJT Qn1, and a first n-well resistor Rn1, and the second thyristor SCR2 may include a second PNP BJT Qp2, a second NPN BJT Qn2, and a second n-well resistor Rn2. When electrostatic discharge occurs between the first node N1 and the second node N2, the NFET Mn may generate a trigger current, and thus the first thyristor SCR1 and the second thyristor SCR2 may be driven in advance.

[0089] Fig.14 is a schematic diagram showing a layout 140 of an apparatus according to an embodiment. For example, Fig.14 Shows the corresponding Fig.13 Layout 140 of an equivalent circuit 130. For ease of illustration, contacts and conductive patterns for interconnecting the p+ region, n+ region, and gate are omitted. Fig.14 In the embodiment, the p+ region and the n+ region disposed in the first p-well PW1 are additionally shown as segments SEG at the bottom. Fig.14 The structure may be formed in a p-type substrate, and the first p-well PW1 and the second p-well PW2 may correspond to the p-type substrate. Fig.14 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0090] exist Fig.14In the embodiment, the layout 140 may include an SCR structure 141 and a FET structure 142. The SCR structure 141 may include a first n-well NW1 and a second n-well NW2 and a first p-well PW1 extending in the X-axis direction. Fig.14 As shown, the first n-well NW1 and the second n-well NW2 may be adjacent to the first p-well PW1 in the Y-axis direction. The segment SEG may be disposed in the first p-well PW1, and the segment SEG may include a second n+ region n2 and a second p+ region p2. Fig.14 As shown, the second n+ regions n2 may be spaced apart from each other in the X-axis direction, and the second p+ region p2 may be disposed between the second n+ regions n2. The second n+ region n2 may be electrically connected to the second node N2, and the second p+ region p2 may be electrically connected to the third node N3. The first n+ region n1 and the first p+ region p1 may be disposed in the first n-well NW1, and the first n+ region n1 and the first p+ region p1 may be electrically connected to the first node N1. In addition, the third p+ region p3 and the third n+ region n3 may be disposed in the second n-well NW2, and the third p+ region p3 and the third n+ region n3 may be electrically connected to the first node N1.

[0091] The FET structure 142 may include a second p-well PW2 extending in the X-axis direction. The fourth n+ region n4, the fifth n+ region n5, and the fourth p+ region p4 may be disposed in the second p-well PW2, and the gate electrode G may be disposed on a region between the fourth n+ region n4 and the fifth n+ region n5. The fourth n+ region n4 may be electrically connected to the first node N1, the gate electrode G and the fourth p+ region p4 may be electrically connected to the second node N2, and the fifth n+ region n5 may be electrically connected to the third node N3. The fourth n+ region n4, the fifth n+ region n5, and the gate electrode G may correspond to Fig.13 Therefore, the NFET Mn can be connected to two thyristors through the second p+ region p2 connected to the third node N3, that is, connected to Fig.13 The first silicon controlled rectifier SCR1 and the second silicon controlled rectifier SCR2.

[0092] Fig.13The first PNP BJT Qp1 may include an emitter corresponding to the first p+ region p1, a base corresponding to the first n-well NW1, and a collector corresponding to the first p-well PW1. The first NPN BJT Qn1 may include a collector corresponding to the first n-well NW1, a base corresponding to the first p-well PW1, and an emitter corresponding to the second n+ region n2. The second PNP BJT Qp2 may include an emitter corresponding to the third p+ region p3, a base corresponding to the second n-well NW2, and a collector corresponding to the first p-well PW1. The second NPN BJT Qn2 may include a collector corresponding to the second n-well NW2, a base corresponding to the first p-well PW1, and an emitter corresponding to the second n+ region n2. Segment resistor R SEG The first n-well resistor Rn1 may correspond to a resistor between the first n-well NW1 and the first n+ region n1, and the second n-well resistor Rn2 may correspond to a resistor between the second n-well NW2 and the third n+ region n3.

[0093] NFET Mn may include a drain corresponding to the fourth n+ region n4, a gate corresponding to the gate electrode G, and a source corresponding to the fifth n+ region n5. The third NPN BJT Qn3 may include a collector corresponding to the fourth n+ region n4, a base corresponding to the second p-well PW2, and an emitter corresponding to the fifth n+ region n5. Fig.13 The p-well resistor Rp may correspond to a resistor between the second p-well PW2 and the fourth p+ region p4.

[0094] Fig.15 1 is a circuit diagram showing an equivalent circuit 150 of a device according to an embodiment. Fig.13 Compared with the equivalent circuit 130, Fig.15 The equivalent circuit 150 of may include a PFET Mp instead of an NFET. Fig.15 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0095] The equivalent circuit 150 may include a first thyristor SCR1 and a second thyristor SCR2, a PFET Mp, a third PNP BJT Qp3, a segment resistor R SEGand a third n-well resistor Rn3. The first silicon controlled rectifier SCR1 may include a first PNP BJT Qp1, a first NPN BJT Qn1, and a first n-well resistor Rn1, and the second silicon controlled rectifier SCR2 may include a second PNP BJT Qp2, a second NPN BJT Qn2, and a second n-well resistor Rn2. When electrostatic discharge occurs between the first node N1 and the second node N2, the PFET Mp may generate a trigger current, and thus, the first silicon controlled rectifier SCR1 and the second silicon controlled rectifier SCR2 may be driven in advance.

[0096] Fig.16 is a schematic diagram showing a layout 160 of an apparatus according to an embodiment. For example, Fig.16 Shows the corresponding Fig.15 Layout 160 of an equivalent circuit 150 of FIG. For ease of illustration, contacts and conductive patterns for interconnecting the p+ region, n+ region, and gate are omitted. Fig.16 In the embodiment, the p+ region and the n+ region disposed in the p-well PW are additionally shown as segments SEG at the bottom. Fig.16 The structure may be formed in a p-type substrate, and the p-well PW may correspond to the p-type substrate. Fig.16 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0097] exist Fig.16 In the embodiment, the layout 160 may include an SCR structure 161 and a FET structure 162. The SCR structure 161 may include a first n-well NW1 and a second n-well NW2 and a p-well PW extending in the X-axis direction. Fig.16 As shown, the first n-well NW1 and the second n-well NW2 may be adjacent to the p-well PW in the Y-axis direction. The segment SEG may be disposed in the p-well PW, and the segment SEG may include a second n+ region n2 and a second p+ region p2. Fig.16 As shown, the second n+ regions n2 may be spaced apart from each other in the X-axis direction, and the second p+ region p2 may be disposed between the second n+ regions n2. The second n+ region n2 may be electrically connected to the second node N2, and the second p+ region p2 may be electrically connected to the third node N3. The first n+ region n1 and the first p+ region p1 may be disposed in the first n-well NW1, and the first n+ region n1 and the first p+ region p1 may be electrically connected to the first node N1. In addition, the third p+ region p3 and the third n+ region n3 may be disposed in the second n-well NW2, and the third p+ region p3 and the third n+ region n3 may be electrically connected to the first node N1.

[0098] The FET structure 162 may include a third n-well NW3 extending in the X-axis direction. A fourth p+ region p4, a fifth p+ region p5, and a fourth n+ region n4 may be disposed in the third n-well NW3, and a gate electrode G may be disposed on a region between the fourth p+ region p4 and the fifth p+ region p5. The fourth p+ region n4, the gate electrode G, and the fourth n+ region n4 may be electrically connected to the first node N1, and the fifth p+ region p5 may be electrically connected to the third node N3. The fourth p+ region p4, the fifth p+ region p5, and the gate electrode G may correspond to Fig.15 Therefore, the PFET Mp can be connected to two thyristors through the second p+ region p2 connected to the third node N3, that is, connected to Fig.15 The first silicon controlled rectifier SCR1 and the second silicon controlled rectifier SCR2.

[0099] Fig.15 The first PNP BJT Qp1 may include an emitter corresponding to the first p+ region p1, a base corresponding to the first n-well NW1, and a collector corresponding to the p-well PW. The first NPN BJT Qn1 may include a collector corresponding to the first n-well NW1, a base corresponding to the p-well PW, and an emitter corresponding to the second n+ region n2. The second PNP BJT Qp2 may include an emitter corresponding to the third p+ region p3, a base corresponding to the second n-well NW2, and a collector corresponding to the p-well PW. The second NPN BJT Qn2 may include a collector corresponding to the second n-well NW2, a base corresponding to the p-well PW, and an emitter corresponding to the second n+ region n2. Segment resistor R SEG The first n-well resistor Rn1 may correspond to a resistor between the first n-well NW1 and the first n+ region n1, and the second n-well resistor Rn2 may correspond to a resistor between the second n-well NW2 and the third n+ region n3.

[0100] The PFET Mp may include a source corresponding to the fourth p+ region p4, a gate corresponding to the gate electrode G, and a drain corresponding to the fifth p+ region p5. The third PNP BJT Qp3 may include an emitter corresponding to the fourth p+ region p4, a base corresponding to the third n-well NW3, and a collector corresponding to the fifth p+ region p5. Fig.15 The third n-well resistor Rn3 may correspond to a resistor between the third n-well NW3 and the fourth n+ region n4.

[0101] Fig.17 1 is a circuit diagram showing an equivalent circuit 170 of a device according to an embodiment. Figure 5 Compared with the equivalent circuit 50, Fig.17 The equivalent circuit 170 may include an external resistor REXT Note that the external resistor R EXT Can be added to other embodiments as well Fig.17 The equivalent circuit 170. In the following, Fig.17 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0102] The equivalent circuit 170 may include a first silicon controlled rectifier SCR1 and a second silicon controlled rectifier SCR2, an NFET Mn, and a first segment resistor R SEG1 and the second segment resistor R SEG2 The first silicon controlled rectifier SCR1 may include a first PNP BJT Qp1, a first NPN BJT Qn1, and a first p-well resistor Rp1, and the second silicon controlled rectifier SCR2 may include a second PNP BJT Qp2, a second NPN BJT Qn2, and a second p-well resistor Rp2. When electrostatic discharge occurs between the first node N1 and the second node N2, the NFET Mn may generate a trigger current, and thus the first silicon controlled rectifier SCR1 and the second silicon controlled rectifier SCR2 may be driven in advance. The resistance of the path through which the leakage current flows may be controlled by the external resistor R EXT to increase or adjust.

[0103] Fig.18 1 is a diagram showing a layout 180 of a device according to an embodiment. For example, Fig.18 Shows the corresponding Fig.17 Layout 180 of an equivalent circuit 170 of FIG. For ease of illustration, contacts and conductive patterns for interconnecting the p+ region, n+ region, and gate are omitted. Fig.18 In the embodiment, the p+ region and the n+ region respectively disposed in the first n-well NW1 and the second n-well NW2 are additionally shown at the bottom as the first segment SEG1 and the second segment SEG2. Fig.18 The structure may be formed in a p-type substrate, and the first p-well PW1 and the second p-well PW2 may correspond to the p-type substrate. Fig.18 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0104] exist Fig.18 In the embodiment, the layout 180 may include an SCR structure 181 and a FET structure 182. The SCR structure 181 may include a first n-well NW1 and a second n-well NW2 and a first p-well PW1 extending in the X-axis direction. Fig.18 As shown, the first n-well NW1 and the second n-well NW2 may be adjacent to the first p-well PW1 in the Y-axis direction. The first segment SEG1 may be disposed in the first n-well NW1, and the first segment SEG1 may include a first p+ region p1 and a first n+ region n1. Fig.18As shown, the first p+ regions p1 may be spaced apart from each other in the X-axis direction, and the first n+ region n1 may be disposed between the first p+ regions p1. The first p+ region p1 may be electrically connected to the first node N1, and the first n+ region N1 may be electrically connected to the third node N3. The second n+ region n2, the second p+ region p2, and the third n+ region n3 may be disposed in the first p-well PW1. The second n+ region n2, the second p+ region p2, and the third n+ region n3 may be electrically connected to the second node N2. The second segment SEG2 may be disposed in the second n-well NW2, and the second segment SEG2 may include the third p+ region p3 and the fourth n+ region n4. Fig.18 As shown, the third p+ regions p3 may be spaced apart from each other in the X-axis direction, and the fourth n+ regions n4 may be disposed between the third p+ regions p3. The third p+ regions p3 may be electrically connected to the first node N1, and the fourth n+ regions n4 may be electrically connected to the third node N3.

[0105] The FET structure 182 may include a second p-well PW2 extending in the X-axis direction. The fifth n+ region n5, the sixth n+ region n6, and the fourth p+ region p4 may be disposed in the second p-well PW2, and the gate electrode G may be disposed on a region between the fifth n+ region n5 and the sixth n+ region n6. The fifth n+ region n5 may be connected to the gate electrode by an external resistor R EXT The gate electrode G, the sixth n+ region n6, and the fourth p+ region p4 may be electrically connected to the second node N2. The fifth n+ region n5, the sixth n+ region n6, and the gate electrode G may correspond to Fig.17 NFET Mn, therefore, NFET Mn can be connected to the third node N3 through the external resistor R EXT , the first n+ region n1 and the fourth n+ region n4 are connected to two thyristor rectifiers, that is, Fig.17 The first silicon controlled rectifier SCR1 and the second silicon controlled rectifier SCR2.

[0106] Fig.17 The first PNP BJT Qp1 includes an emitter corresponding to the first p+ region p1, a base corresponding to the first n-well NW1, and a collector corresponding to the first p-well PW1. The first NPN BJT Qn1 may include a collector corresponding to the first n-well NW1, a base corresponding to the first p-well PW1, and an emitter corresponding to the second n+ region n2. The second PNP BJT Qp2 may include an emitter corresponding to the second p+ region p2, a base corresponding to the second n-well NW2, and a collector corresponding to the first p-well PW1. The second NPN BJT Qn2 may include a collector corresponding to the second n-well NW2, a base corresponding to the first p-well PW1, and an emitter corresponding to the third n+ region n3. The first segment resistor R SEG1The resistor between the first n-well NW1 and the first n+ region n1 may correspond to the second segment resistor R SEG2 The NFET Mn may include a drain corresponding to the fifth n+ region n5, a gate corresponding to the gate electrode G, and a source corresponding to the sixth n+ region n6.

[0107] Fig.19 is a circuit diagram showing an equivalent circuit 190 of a device according to an embodiment, and Fig. 20 is a graph showing the characteristics of the device according to the embodiment. Figure 5 Compared with the equivalent circuit 50, Fig.19 The equivalent circuit 190 of may include a capacitor C and a resistor R connected to the gate of NFET Mn. Note that the capacitor C and the resistor R may be added to other embodiments as well. Fig.19 In the equivalent circuit 190 of FIG. 190 . For example, when a capacitor and a resistor are connected to the gate of a PFET as a trigger transistor, one end of the capacitor may be connected to the second node N2, and one end of the resistor may be connected to the first node N1. Fig.19 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0108] The equivalent circuit 190 may include a first silicon controlled rectifier SCR1 and a second silicon controlled rectifier SCR2, an NFET Mn, and a first segment resistor R SEG1 and the second segment resistor R SEG2 The first silicon controlled rectifier SCR1 may include a first PNP BJT Qp1, a first NPN BJT Qn1, and a first p-well resistor Rp1, and the second silicon controlled rectifier SCR2 may include a second PNP BJT Qp2, a second NPN BJT Qn2, and a second p-well resistor Rp2. When electrostatic discharge occurs between the first node N1 and the second node N2, the gate voltage of the NFET Mn may increase in advance due to the capacitor C and the resistor R, and the trigger current generated by the NFET Mn may drive the first silicon controlled rectifier SCR1 and the second silicon controlled rectifier SCR2 in advance.

[0109] In order to adjust the trigger voltage, the capacitance of the capacitor C and the resistance value of the resistor R may be adjusted. For example, the trigger voltage may depend on a time constant according to the capacitance of the capacitor C and the resistance value of the resistor R. Therefore, as Fig. 20 As shown, as the time constant increases, the trigger voltage may decrease sequentially, as shown by the first rapid return curve S1 to the third rapid return curve S3.

[0110] Fig.21 2 is a diagram showing a layout 210 of a device according to an embodiment. For example, Fig.21 Shows the corresponding Fig.19 Layout 210 of the equivalent circuit 190 of FIG. For ease of illustration, contacts and conductive patterns for interconnecting the p+ region, n+ region, and gate are omitted. Fig.21 In the embodiment, the p+ region and the n+ region respectively disposed in the first n-well NW1 and the second n-well NW2 are additionally shown at the bottom as the first segment SEG1 and the second segment SEG2. Fig.21 The structure may be formed in a p-type substrate, and the first p-well PW1 and the second p-well PW2 may correspond to the p-type substrate. Fig.21 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0111] exist Fig.21 In the embodiment, the layout 210 may include an SCR structure 211 and a FET structure 212. The SCR structure 211 may include a first n-well NW1 and a second n-well NW2 and a first p-well PW1 extending in the X-axis direction. Fig.21 As shown, the first n-well NW1 and the second n-well NW2 may be adjacent to the first p-well PW1 in the Y-axis direction. The first segment SEG1 may be disposed in the first n-well NW1, and the first segment SEG1 may include a first p+ region p1 and a first n+ region n1. Fig.21 As shown, the first p+ regions p1 may be spaced apart from each other in the X-axis direction, and the first n+ region n1 may be disposed between the first p+ regions p1. The first p+ region p1 may be electrically connected to the first node N1, and the first n+ region N1 may be electrically connected to the third node N3. The second n+ region n2, the second p+ region p2, and the third n+ region n3 may be disposed in the first p-well PW1. The second n+ region n2, the second p+ region p2, and the third n+ region n3 may be electrically connected to the second node N2. The second segment SEG2 may be disposed in the second n-well NW2, and the second segment SEG2 may include the third p+ region p3 and the fourth n+ region n4. Fig.21 As shown, the third p+ regions p3 may be spaced apart from each other in the X-axis direction, and the fourth n+ regions n4 may be disposed between the third p+ regions p3. The third p+ regions p3 may be electrically connected to the first node N1, and the fourth n+ regions n4 may be electrically connected to the third node N3.

[0112] The FET structure 212 may include a second p-well PW2 extending in the X-axis direction. The fifth n+ region n5, the sixth n+ region n6, and the fourth p+ region p4 may be disposed in the second p-well PW2, and the gate electrode G may be disposed on a region between the fifth n+ region n5 and the sixth n+ region n6. The fifth n+ region n5 may be electrically connected to a third node N3. The gate electrode G may be electrically connected to the second node N2 through a resistor R, and a capacitor C may be electrically connected between the first node N1 and the gate electrode G. The sixth n+ region n6 and the fourth p+ region p4 may be electrically connected to the second node N2. The fifth n+ region n5, the sixth n+ region n6, and the gate electrode G may correspond to Fig.17 NFET Mn, therefore NFET Mn can be connected to two thyristors through the first n+ region n1 and the fourth n+ region n4 connected to the third node N3, respectively, that is, Fig.17 In addition, due to the resistor R and the capacitor C, the gate voltage of the NFET Mn may increase in advance.

[0113] Fig.19 The first PNP BJT Qp1 may include an emitter corresponding to the first p+ region p1, a base corresponding to the first n-well NW1, and a collector corresponding to the first p-well PW1. The first NPN BJT Qn1 may include a collector corresponding to the first n-well NW1, a base corresponding to the first p-well PW1, and an emitter corresponding to the second n+ region n2. The second PNP BJT Qp2 may include an emitter corresponding to the second p+ region p2, a base corresponding to the second n-well NW2, and a collector corresponding to the first p-well PW1. The second NPN BJT Qn2 may include a collector corresponding to the second n-well NW2, a base corresponding to the first p-well PW1, and an emitter corresponding to the third n+ region n3. The first segment resistor R SEG1 The resistor between the first n-well NW1 and the first n+ region n1 may correspond to the second segment resistor R SEG2 The NFET Mn may include a drain corresponding to the fifth n+ region n5, a gate corresponding to the gate electrode G, and a source corresponding to the sixth n+ region n6.

[0114] Fig. 22 is a circuit diagram showing a device 220 according to an embodiment, and Fig.23 2 is a graph showing characteristics of the device 220 according to an embodiment. The device 220 may include a segmented resistor R having p+ regions and n+ regions arranged alternately. SEG, as referenced above Figure 4 and others described. Fig. 22 and 23 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0115] exist Fig. 22 In the embodiment, the device 220 may include a silicon controlled rectifier SCR, a first NFET M1 to a kth NFET Mk, and a segment resistor R SEG , where k is an integer greater than 1. The silicon controlled rectifier SCR may include a PNP BJT Qp, an NPN BJT Qn, and a p-well resistor Rp. The first to k-th NFETs M1 to Mk may be connected in series between the second node N2 and the third node N3, and may have gates and bodies connected to the second node N2, respectively.

[0116] The trigger voltage of the silicon controlled rectifier SCR may depend on the number of the first NFET M1 to the kth NFET Mk. Fig.23 As shown in FIG. 1 , as the number of NFETs connected in series increases, as in the first sharp return curve S1 to the fourth sharp return curve S4, the voltage generating the trigger current (i.e., the trigger voltage) can gradually increase. Note that in the embodiments described above with reference to the accompanying drawings, the trigger voltage can also be adjusted using two or more PFETs connected in series.

[0117] Fig.24 is a circuit diagram showing a device 240 according to an embodiment, and Fig.25 2 is a graph showing characteristics of the device 240 according to an embodiment. The device 240 may include a segmented resistor R having p+ regions and n+ regions arranged alternately. SEG , as referenced above Figure 4 and others described. Fig.24 and Fig.25 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0118] exist Fig.24 In the embodiment, the device 240 may include a silicon controlled rectifier SCR, an NFET Mn, at least one diode D and a segment resistor R SEG The silicon controlled rectifier SCR may include a PNP BJT Qp, an NPN BJT Qn, and a p-well resistor Rp. At least one diode D may be connected between the first node N1 and the silicon controlled rectifier SCR in a forward direction.

[0119] The holding voltage of the silicon controlled rectifier SCR may depend on at least one diode D. For example, the holding voltage may correspond to the sum of the base-collector voltage of the NPN BJT Qn, the emitter-collector voltage of the PNP BJT Qp, and the forward voltage of the at least one diode D. Therefore, Fig.25 As shown, as the number of at least one diode D increases, the holding voltage may gradually increase as shown in the first to fourth sharp return curves S1 to S4. Note that in the embodiments described above with reference to the drawings, at least one diode D may be inserted to adjust the holding voltage.

[0120] Fig.26 is a circuit diagram showing a device 260 according to an embodiment, and Fig. 27 2 is a graph showing characteristics of the device 260 according to an embodiment. The device 260 may include a segmented resistor R having p+ regions and n+ regions arranged alternately. SEG , as referenced above Figure 4 and others described. Fig.26 and Fig. 27 In the description of the drawings, the description previously given with reference to the accompanying drawings is omitted.

[0121] exist Fig.26 In the embodiment, the device 260 may include a silicon controlled rectifier SCR, an NFET Mn, at least one diode D and a segment resistor R SEG The silicon controlled rectifier SCR may include a PNP BJT Qp, an NPN BJT Qn, and a p-well resistor Rp. At least one diode D may be connected between the silicon controlled rectifier SCR and the second node N2 in a forward direction.

[0122] The trigger voltage and the holding voltage of the silicon controlled rectifier SCR may depend on at least one diode D. For example, the trigger voltage and the holding voltage may depend on the forward voltage of at least one diode D. Therefore, Fig. 27 As shown, as the number of at least one diode D increases, the trigger voltage and the holding voltage can gradually increase, as shown in the first rapid return curve S1 to the fourth rapid return curve S4. Note that in the embodiments described above with reference to the accompanying drawings, at least one diode D can be inserted to adjust the trigger voltage and the holding voltage.

[0123] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A device, include: a first silicon controlled rectifier including a first PNP bipolar junction transistor (BJT) and a first NPN BJT having bases and collectors cross-coupled; as well as a field effect transistor (FET) configured to trigger the first silicon-controlled rectifier based on an electrostatic discharge occurring between an anode of the first silicon-controlled rectifier and a cathode of the first silicon-controlled rectifier, wherein the emitter of the first PNP BJT corresponds to a plurality of first p+ regions spaced apart from each other in a first direction, and The FET is connected to the first silicon controlled rectifier via at least one first n+ region disposed between the plurality of first p+ regions.

2. The device according to claim 1, in, The base of the first PNP BJT corresponds to a first n-well in which the plurality of first p+ regions and the at least one first n+ region are disposed, and the first n-well extends in the first direction, and The collector of the first PNP BJT corresponds to a p-well adjacent to the first n-well in a second direction crossing the first direction, and the p-well extends in the first direction.

3. The device according to claim 2, in, The collector of the first NPN BJT corresponds to the first n-well, wherein the base of the first NPN BJT corresponds to the p-well, and The emitter of the first NPN BJT corresponds to an n+ region in the p-well.

4. The device according to claim 2, in, The collector of the first PNP BJT and the base of the first NPNBJT are connected to the cathode through a p+ region provided in the p-well.

5. The apparatus of claim 2, further comprising a second silicon controlled rectifier, the second silicon controlled rectifier comprising a second PNP BJT and a second NPN BJT with base and collector cross-coupled, in, The second thyristor rectifier is connected in parallel with the first thyristor rectifier, wherein the emitter of the second PNP BJT corresponds to a plurality of second p+ regions spaced apart from each other in the first direction, and The FET is connected to the second silicon controlled rectifier via at least one second n+ region disposed between the plurality of second p+ regions.

6. The device according to claim 5, in, The base of the second PNP BJT corresponds to a second n-well in which the plurality of second p+ regions and the at least one second n+ region are disposed, the second n-well is adjacent to the p-well in the second direction, and the second n-well extends in the first direction, and Wherein, the collector of the second PNP BJT corresponds to the p-well.

7. The device according to claim 6, in, The collector of the second NPN BJT corresponds to the second n-well, wherein the base of the second NPN BJT corresponds to the p-well, and The emitter of the second NPN BJT corresponds to the n+ region in the p-well.

8. The device according to claim 1, in, A first sum of lengths of the plurality of first p+ regions in the first direction is greater than a second sum of at least one length of the at least one first n+ region in the first direction.

9. The device according to claim 1, in, A first sum of lengths of the plurality of first p+ regions in the first direction is smaller than a second sum of at least one length of the at least one first n+ region in the first direction.

10. The apparatus of claim 1, further comprising a resistor connected between the at least one first n+ region and the FET.

11. The device according to claim 1, in, The FET is an n-channel field effect transistor NFET, Wherein, the NFET comprises: a gate electrically connected to the cathode; a source electrode electrically connected to the cathode; and A drain is electrically connected to the at least one first n+ region.

12. The device according to claim 11, further comprising: include: a capacitor connected between the anode and the gate; as well as A resistor is connected between the gate and the cathode.

13. The device according to claim 1, in, The FET is a p-channel field effect transistor PFET, Wherein, the PFET comprises: a gate electrically connected to the anode; a drain electrode electrically connected to the cathode; and A source is connected to the at least one first n+ region.

14. The device according to claim 13, further comprising: include: a resistor connected between the anode and the gate; as well as A capacitor is connected between the gate and the cathode.

15. The device according to claim 1, in, Each of the at least one first n+ region and the plurality of first p+ regions is disposed between two adjacent gate electrodes extending in a second direction crossing the first direction.

16. A device, include: a first silicon controlled rectifier including a first PNP bipolar junction transistor (BJT) and a first NPN BJT having bases and collectors cross-coupled; as well as a field effect transistor (FET) configured to trigger the first thyristor rectifier based on an electrostatic discharge occurring between an anode and a cathode of the first thyristor rectifier, wherein the emitter of the first NPN BJT corresponds to a plurality of n+ regions spaced apart from each other in a first direction, and The FET is connected to the first silicon controlled rectifier via at least one p+ region disposed between the plurality of n+ regions.

17. The device according to claim 16, in, The base of the first NPN BJT corresponds to a p-well in which the plurality of n+ regions and the at least one p+ region are disposed, and the p-well extends in the first direction, and The collector of the first NPN BJT corresponds to a first n-well adjacent to the p-well in a second direction crossing the first direction, and the first n-well extends in the first direction.

18. The device according to claim 17, in, The collector of the first PNP BJT corresponds to the p-well, wherein the base of the first PNP BJT corresponds to the first n-well, and The emitter of the first PNP BJT corresponds to the p+ region in the first n-well.

19. A device, include: a p-well extending in a first direction; a first n-well adjacent to the p-well in a second direction crossing the first direction, and the first n-well extends in the first direction; a first n+ region electrically connected to a cathode node and disposed in the p-well; a first p+ region electrically connected to the cathode node and disposed in the p-well; a plurality of second p+ regions electrically connected to an anode node, the plurality of second p+ regions being spaced apart from each other in the first direction in the first n-well; as well as At least one second n+ region electrically connected to a field effect transistor electrically connected to the cathode node or the anode node, the at least one second n+ region being disposed between the plurality of second p+ regions in the first n-well.

20. The device according to claim 19, further comprising: include: a second n-well adjacent to the p-well in the second direction, the second n-well extending in the first direction; a third n+ region electrically connected to the cathode node, the third n+ region being disposed in the p-well; a plurality of third p+ regions electrically connected to the anode node, the plurality of third p+ regions being spaced apart from each other in the first direction in the second n-well; as well as At least one fourth n+ region is electrically connected to the FET, the at least one fourth n+ region being disposed between the plurality of third p+ regions in the second n-well.

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