Complementary metal oxide semiconductor circuit
By building a silicon island overly on the insulating layer on the semiconductor substrate and forming a local isolation layer, the high cost, leakage current and latch problems of traditional insulating layer overlying silicon transistors is solved, and a more efficient complementary metal oxide semiconductor circuit design is achieved. .
Patent Information
- Application Number
- CN202410747339.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-09
- Filing Date
- 2024-06-11
- Publication Date
- 2024-12-10
AI Technical Summary
Traditional insulating silicon-overlapping (SOI) transistors are costly and difficult to meet the cost reduction requirements of Moore's Law, and there are leakage current and latch problems, which affect the performance of complementary metal oxide semiconductor circuits.
The insulating layer is built on the semiconductor substrate to cover silicon islands, and the local isolation layer is formed under the p-type and n-type metal oxide semiconductor transistors to reduce leakage current and latch phenomenon, and the source region is formed through selective growth technology/ Drain region to avoid ion implantation process.
Reduces circuit costs, reduces noise interference and power consumption, improves latch resistance and channel conduction performance, solves the floating body effect problem, and achieves a higher frequency operating range and a smaller circuit area.
Smart Images
Figure CN119108400A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a complementary metal-oxide-semiconductor (CMOS) circuit, and in particular to a complementary metal-oxide-semiconductor (CMOS) circuit, which can reduce costs, improve leakage current and latch-up problems in complementary metal-oxide-semiconductor circuits, solve the floating body effect in traditional silicon-on-insulator (SOI) wafers, do not require ion placement processes to dope source / drain regions, and reduce leakage current. Background Art
[0002] Conventional silicon on insulator (SOI) transistors are usually manufactured on an entire silicon on insulator (SOI) wafer, where the SOI wafer is much more expensive than a silicon wafer. Therefore, one disadvantage of SOI transistor technology is that the cost of each transistor manufactured in the SOI wafer is much higher than the cost of manufacturing in the silicon wafer. Another disadvantage of SOI transistor technology is that the cost of each SOI transistor is difficult to meet the cost reduction requirements of each miniaturized process node required by Moore's Law, so the SOI technology has not become a mainstream or commodity process technology based on silicon substrate technology. In addition, a variety of novel methods can be used to prepare SOI wafers; for example, two wafers are bonded together, each silicon wafer has silicon oxide on its surface, and then a wafer-oxide-wafer sandwich structure is formed by flipping one wafer onto the other wafer, and due to the mutual oxide bonding force, a wafer-oxide layer-wafer sandwich structure is formed. A wafer is then ground to a specific thickness to form a SOI wafer. Another method is to implant oxide atoms through the surface of the silicon wafer, which forms a thin silicon film on the implanted oxide layer created on the original silicon substrate. Both of the above methods are used to manufacture the entire silicon-on-insulator wafer, which is much more expensive than silicon wafers, especially for larger wafer diameters (such as 8 inches or 12 inches). Then the well-known silicon process method can be used to manufacture Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) on the silicon-on-insulator wafer.
[0003] Although SOI transistors are more expensive to manufacture, there are several advantages to using SOI transistors to create integrated circuits: (1) Each transistor is completely isolated from the other transistors; (2) the parasitic capacitance between the source and drain regions of the MOS field effect transistor is significantly reduced; (3) if a complementary metal-oxide-semiconductor (CMOS) configuration is required, there is no latch-up problem between the n-type metal-oxide-semiconductor (NMOS) transistor and the p-type metal-oxide-semiconductor (NMOS) transistor, which significantly reduces the planar area compared to silicon-based complementary metal-oxide-semiconductor technology; and (4) since FinFET or Tri-gate technology is used for fully-depleted SOI transistors, there is no substrate leakage problem.
[0004] On the other hand, Metal-Oxide-Semiconductor (MOS) transistor circuits, such as Complementary Metal-Oxide-Semiconductor Field-Effect Transistors (CMOSFET), are widely used in the semiconductor industry. Figure 1The schematic diagram is a cross-sectional view of the most advanced complementary metal oxide semiconductor field effect transistor 100 which is widely used in integrated circuits (ICs) today. The complementary metal oxide semiconductor field effect transistor 100 includes an n-type metal oxide semiconductor (NMOS) transistor 104 and a p-type metal oxide semiconductor (NMOS) transistor 1021, wherein a shallow trench isolation (STI) region is located between the n-type metal oxide semiconductor transistor 1041 and the p-type metal oxide semiconductor transistor 1021. The gate structure of the n-type metal oxide semiconductor transistor 1041 or the p-type metal oxide semiconductor transistor 1021 uses some conductive materials (such as metal, polysilicon or polycrystalline silicon, etc.) on an insulator (such as oxide, oxide / nitride or some high-k material, etc.), wherein the gate structure is formed on the top of a plane (planar complementary metal oxide semiconductor field effect transistor) or a three-dimensional silicon surface (such as a tri-gate, or a fin field effect transistor (FinFET), or a gate-all-around (GAA) complementary metal oxide semiconductor field effect transistor), and the sidewall of the gate structure is isolated from the sidewalls of other transistors by using an insulating material (such as oxide or oxide / nitride or other dielectric). For the n-type metal oxide semiconductor transistor 1041, an n-type dopant is implanted into the p-type substrate (or p-well 106) by ion implantation heating annealing technology to form a source region 1042 and a drain region 1044 of the n-type metal oxide semiconductor transistor 1041, thereby forming two separated n+ / p junction regions. For the p-type metal oxide semiconductor transistor 1021, a p-type dopant is injected into the n-well 108 by ion implantation heating annealing technology to form a source region 1022 and a drain region 1024 of the p-type metal oxide semiconductor transistor 1021, thereby forming two p+ / n junction regions. In addition, in order to reduce impact ionization and hot carrier injection before the highly doped n+ / p or p+ / n junction, a lightly doped-drain (LDD) region is usually formed under the gate structure. Because the n-type metal oxide semiconductor transistor 1041 and the p-type metal oxide semiconductor transistor 1021 are respectively located in some adjacent regions of the p-well 106 and the n-well 108, and these adjacent regions are adjacent to each other, a parasitic junction structure is formed, which is called n+ / p / n / p+ ( Figure 1The path marked by the dashed line is referred to as an n+ / p / n / p+ latch path) parasitic bipolar element, wherein the profile of the parasitic bipolar element starts from the drain region 1044 of the n-type metal oxide semiconductor transistor 1041 to the p-well 106 to the adjacent n-well 108 and further reaches the source region 1022 of the p-type metal oxide semiconductor transistor 1021.
[0005] Once significant noise appears on the n+ / p junction or p+ / n junction, an abnormally large current may abnormally flow through the n+ / p / n / p+ junction, which may shut down certain operations of the CMOS field effect transistor 100 and cause failure of the entire chip. This abnormal phenomenon, known as latch-up, is detrimental to the operation of the CMOS field effect transistor 100 and must be avoided. One way to improve the latch-up resistance is to increase the distance from the drain region 1044 to the source region 1022 ( Figure 1 In the embodiment of the present invention, the drain region 1044 and the source region 1022 must be isolated by some vertical oxide (or other suitable insulator material) as an isolation region. In this case, the isolation region is usually a shallow trench isolation (STI) region. In order to avoid latch-up, a guard-band structure must be designed to further increase the distance between the drain region 1044 and the source region 1022 and / or additional n+ regions or p+ regions must be added to collect abnormal charges from noise sources. However, these isolation schemes always increase additional planar area, thereby sacrificing the chip size of the complementary metal oxide semiconductor field effect transistor 100.
[0006] The present invention is to realize a single-crystalline silicon island on insulator (SC-SIOI), in which a silicon-on-insulator transistor can be made without using the entire silicon-on-insulator wafer (usually adopted by the most advanced silicon-on-insulator substrate), thereby eliminating the main cost disadvantage caused by the use of expensive silicon-on-insulator wafers, but retaining all the advantages of using silicon-on-insulator technology to achieve high-performance circuits, especially in CMOS circuits to create a higher frequency operating range, reduce noise, reduce power consumption and achieve a smaller circuit area. It is particularly important. Utilizing the present invention, a silicon-on-insulator transistor can be created in a silicon (or semiconductor) substrate by using the silicon-on-insulator island technology without using the entire silicon-on-insulator wafer. A transistor or multiple components are constructed in the single-crystal silicon island on the insulating layer, wherein the multiple components can be well connected with conductive (e.g., metal layer) interconnects, so compared with the current technology using the entire silicon-on-insulator wafer, there is less noise interference, lower power consumption, higher energy efficiency and lower cost. For CMOS configurations created in separate single-crystal silicon islands on an insulating layer, there is no need to create additional space to avoid latch-up issues in conventional CMOS technology. Summary of the invention
[0007] One embodiment of the present invention discloses a complementary metal-oxide-semiconductor (CMOS) circuit. The complementary metal-oxide-semiconductor circuit includes a semiconductor substrate body, a first active region and a second active region, a first-type transistor, a first localized isolating layer, a second-type transistor, and a second localized isolating layer. The semiconductor substrate body has an original semiconductor surface. The first active region and the second active region are formed on the basis of the semiconductor substrate body. The first-type transistor is formed on the basis of the first active region and has a first dopant. The first localized isolating layer is located below the first-type transistor and at least isolates the first dopant from the semiconductor substrate body. The second-type transistor is formed on the basis of the second active region and has a second dopant. The second localized isolating layer is located below the second-type transistor and at least partially isolates the second dopant from the semiconductor substrate body.
[0008] In one embodiment of the present invention, the complementary metal oxide semiconductor circuit further comprises a first shallow trench isolation region and a second shallow trench isolation region. The first shallow trench isolation region surrounds the first active region and the first local isolation layer. The second shallow trench isolation region surrounds the second active region and the second local isolation layer.
[0009] In one embodiment of the present invention, the first local isolation layer completely isolates the first-type transistor from the semiconductor substrate body, and the second local isolation layer only partially isolates the second-type transistor from the semiconductor substrate body, wherein the first-type transistor is a p-type metal-oxide-semiconductor transistor, and the second-type transistor is an n-type metal-oxide-semiconductor transistor.
[0010] In one embodiment of the present invention, the second local isolation layer has an opening, and the second doped body of the n-type metal oxide semiconductor transistor is electrically coupled to the semiconductor substrate body through the opening.
[0011] In one embodiment of the present invention, the length of the opening is 2-4 nanometers (nm).
[0012] In an embodiment of the present invention, the opening is in a star shape or an irregular shape.
[0013] In one embodiment of the present invention, the first local isolation layer only partially isolates the first-type transistor from the semiconductor substrate body, and the second local isolation layer completely isolates the second-type transistor from the semiconductor substrate body, wherein the first-type transistor is a p-type metal oxide semiconductor transistor, and the second-type transistor is an n-type metal oxide semiconductor transistor.
[0014] In one embodiment of the present invention, the first local isolation layer has an opening, and the first doped body of the p-type metal oxide semiconductor transistor is electrically coupled to the semiconductor substrate body through the opening.
[0015] In one embodiment of the present invention, the first local isolation layer completely isolates the first-type transistor from the semiconductor substrate body, and the second local isolation layer completely isolates the second-type transistor from the semiconductor substrate body, wherein the first-type transistor is a p-type metal oxide semiconductor transistor, and the second-type transistor is an n-type metal oxide semiconductor transistor.
[0016] In one embodiment of the present invention, the source region of the first-type transistor is close to the first local isolation layer.
[0017] In one embodiment of the present invention, the complementary metal oxide semiconductor circuit further includes a metal region contacting a top surface and a sidewall of the source region.
[0018] In one embodiment of the present invention, the channel length of the first-type transistor is the same as the channel length of the second-type transistor.
[0019] An embodiment of the present invention discloses a complementary metal oxide semiconductor circuit. The complementary metal oxide semiconductor circuit includes a semiconductor substrate body, a first active region and a second active region, a p-type metal oxide semiconductor transistor, a first local isolation layer, a first shallow trench isolation region, an n-type metal oxide semiconductor transistor, a second local isolation layer and a second shallow trench isolation region. The semiconductor substrate body has an original semiconductor surface. The first active region and the second active region are formed on the basis of the semiconductor substrate body. The p-type metal oxide semiconductor transistor is formed on the basis of the first active region and has a first dopant and a first channel. The first local isolation layer is located below the p-type metal oxide semiconductor transistor and at least isolates the first dopant from the semiconductor substrate body. The first shallow trench isolation region surrounds the first active region and the first local isolation layer. The n-type metal oxide semiconductor transistor is formed on the basis of the second active region and has a second dopant and a second channel. The second local isolation layer is located below the n-type metal oxide semiconductor transistor and at least partially isolates the second dopant from the semiconductor substrate body. The second shallow trench isolation region surrounds the second active region and the second local isolation layer. The length of the first channel is the same as the length of the second channel.
[0020] In one embodiment of the present invention, the second local isolation layer has an opening, and the second dopant of the n-type metal oxide semiconductor transistor is electrically coupled to the semiconductor substrate body through the opening.
[0021] In one embodiment of the present invention, the length of the opening is between 2 nm and 4 nm.
[0022] In an embodiment of the present invention, the shape of the opening is a star shape or an irregular shape.
[0023] In one embodiment of the present invention, the drain region of the p-type metal oxide semiconductor transistor is close to the first local isolation layer.
[0024] In one embodiment of the present invention, the complementary metal oxide semiconductor circuit further includes a metal region contacting a top surface and a sidewall of the drain region. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a schematic diagram illustrating a complementary metal oxide semiconductor transistor in the prior art.
[0026] Figure 2A It is a flow chart of a method for manufacturing an oxide-PMOS Complementary Metal-Oxide-Semiconductor Field-Effect Transistor (OP-CMOSFET) based on a semiconductor substrate body disclosed in one embodiment of the present invention.
[0027] Figure 2B , Figure 2C , Figure 2D , Figure 2E Yes Description Figure 2A Flowchart of the process.
[0028] Figure 3 2 is a schematic diagram illustrating the definition of an active region of an OP-C MOSFET based on the semiconductor substrate.
[0029] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 is a schematic diagram illustrating forming an underground insulating layer under the active region of an OP-C MOSFET.
[0030] Fig.15 , Fig.16 , Fig.17 , Fig.18 is a schematic diagram illustrating the formation of a source region and a drain region in an active region of an OP-C MOSFET.
[0031] Fig.19 is a schematic diagram illustrating forming a gate region on an active region of an OP-C MOSFET.
[0032] Fig. 20 , Fig. 22 , Fig.23 , Fig.24 is a schematic diagram illustrating the formation of different subsurface isolation layers under the active region of the OP-C MOSFET.
[0033] Fig.21 is a schematic diagram illustrating a simulation result of a Technology Computer-Aided Design (TCAD) of an n-type metal oxide semiconductor transistor with a damascene gate region.
[0034] The reference numerals are described as follows:
[0035] 100 CMOS transistor
[0036] 1021 p-type metal oxide semiconductor transistor
[0037] 1041 n-type metal oxide semiconductor transistor
[0038] 106 p well
[0039] 108 N Well
[0040] 1024, 1042 Source / Drain Region
[0041] 204 Pad Oxide Layer
[0042] 206 liner nitride layer
[0043] 208、2012 Oxidation spacer
[0044] 210、2010 Nitrided spacer
[0045] 212, 1602 Shallow Trench Isolation Area
[0046] 214 Anti-breakdown layer
[0047] 402, 1702 Silicon carbide layer
[0048] 502 Polysilicon spacer
[0049] 504, 1808 Titanium nitride layer
[0050] 506, 1810, 1906, 2016 Tungsten layer
[0051] 508, 702, 802 Silicon carbide hydroxide spacer
[0052] 602 Depression
[0053] 1102 Star-Shaped Through Silicon Via
[0054] 1202, UGOX, 1502, 2004, 2006 Subsurface insulation
[0055] 1802 n-type lightly doped drain region
[0056] 1804 n+ doped source region
[0057] 1806 n+ doped drain region
[0058] 1902 Work function metals
[0059] 1904 Low-k main spacer
[0060] 1908 High K Dielectric Layer
[0061] 2008 Silicon opening / via
[0062] 2002 OP-C MOSFET
[0063] 2202 ON-CMOSFET
[0064] 2302 PO-CMOSFET
[0065] 2402 OPN-CMOSFET
[0066] 2014 Oxide Layer
[0067] 2018 Cap Nitride Layer
[0068] 2020 Cap Oxide Layer
[0069] 2022 Titanium / Titanium Nitride Metal Layer
[0070] 2024 N+ Polysilicon
[0071] 2026 Gate Oxide
[0072] 2028 P+ Zone
[0073] 2030 P-Zone
[0074] 2032 N+ Zone
[0075] 2034 N-Zone
[0076] AA, BB cross-section
[0077] LDD Lightly Doped Drain
[0078] GL_PMOS, GL_NMOS length
[0079] OSS Original Semiconductor Surface
[0080] STI Shallow Trench Isolation
[0081] N-SSRW N-type super steep retreat well
[0082] P-SSRW P-type super steep retreat well
[0083] Steps 10-60, 102-134 DETAILED DESCRIPTION
[0084] The present invention discloses a novel oxide-pMOS complementary metal-oxide-semiconductor field-effect transistor (OP-CMOSFET or OPCMOS) structure based on a semiconductor substrate body instead of a silicon on insulator (SOI), wherein local isolation layers are formed under a p-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor in the oxide-pMOS complementary metal oxide semiconductor field effect transistor, respectively, and the local isolation layer under the p-type metal oxide semiconductor transistor completely isolates the body of the p-type metal oxide semiconductor transistor from the semiconductor substrate body, but the local isolation layer under the n-type metal oxide semiconductor transistor may not completely isolate the body of the n-type metal oxide semiconductor transistor from the semiconductor substrate body, but leaves an opening, so that electrons accumulated in the body of the n-type metal oxide semiconductor transistor can leak into the semiconductor substrate body to improve the floating body effect. Therefore, the present invention greatly improves or even solves most of the problems caused by further improving the design of complementary metal oxide semiconductor field effect transistors in the process of component and circuit development, especially minimizing the current leakage of the complementary metal oxide semiconductor field effect transistor, improving the channel conduction performance and control of the complementary metal oxide semiconductor field effect transistor, and improving the higher anti-latch capability of the complementary metal oxide semiconductor field effect transistor and minimizing the floating body effect.
[0085] Next, you can Figure 2A The manufacturing method shown is used to realize OP-C MOSFET. The detailed steps are as follows:
[0086] Step 10: Start.
[0087] Step 20: Based on the semiconductor substrate body, define an active region of the OP-CMOSFET; Step 30: Form a subsurface insulating layer under the active region of the OP-CMOSFET
[0088] (underground insulating layer, i.e., the localized isolating layer described in the claims);
[0089] Step 40: forming a source region and a drain region in the active region of the OP-CMOSFET;
[0090] Step 50: forming a gate region above the active region of the OP-CMOSFET;
[0091] Step 60: End.
[0092] Please refer to Figure 2B , Figure 3 , step 20 comprises:
[0093] Step 102: forming a pad oxide layer 204 and a pad nitride layer 206 on the semiconductor substrate body ( Figure 3 );
[0094] Step 104: Using a photolithographic masking technique, an active region of an n-type metal oxide semiconductor transistor of the OP-C MOSFET is defined in the semiconductor substrate body to create a trench region (e.g., about 300 nanometers (nm) deep) for future shallow trench isolation (STI) ( Figure 3 );
[0095] Step 106: Deposit an oxide spacer layer (~1 nm) 208, and then deposit a nitride spacer layer (~
[0096] 2nm) 210 as a solid wall to clamp the active region or narrow convex structure ( Figure 3 ); Step 108: forming a shallow trench isolation layer 212 (or a thick oxide layer) in the trench region and removing excess oxide using a chemical and mechanical polishing (CMP) technique ( Figure 3 ).
[0097] Then please refer to Figure 2C , Figure 4 ,picture, Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , step 30 comprises:
[0098] Step 110: forming a thin amorphous
[0099] (thin-amorphous) silicon carbide (SiC) layer 402 ( Figure 4 );
[0100] Step 112: Use a photolithography mask to define a future gate-related region, remove the silicon carbide layer 402 in the gate-related region to expose the pad nitride layer 206, and then etch back the exposed portion of the pad nitride layer 206 ( Figure 4 );
[0101] Step 114: Based on the damascene process, a polysilicon spacer 502, a titanium nitride (TiN) layer 504 and a tungsten (W) layer 506 are deposited to form a dummy gate ( Figure 5 ); Step 116: remove the remaining silicon carbide layer 402 to expose the shallow trench isolation layer 212 and etch the exposed shallow trench isolation layer 212 to regenerate the convex structure ( Figure 5 );
[0102] Step 118: Form a silicon carbide hydroxide (SiCOH) spacer layer 508 along the sidewall of the convex structure ( Figure 5 );
[0103] Step 120: Anisotropically etch the polysilicon spacer layer 502, and further etch the exposed shallow trench isolation layer 212 to form two recesses 602 ( Figure 6 );
[0104] Step 122: forming a silicon carbide hydroxide spacer layer 702 in the two recesses 602, etching the shallow trench isolation layer 212 not covered by the dummy gate, and removing the previous sandwiching spacer layer (nitride spacer layer 210 (Si 3 N 4 ) / oxidized spacer 208 = 2nm / 1nm) to expose the semiconductor sidewall ( Figure 7 );
[0105] Step 124: Form a subsurface insulating layer (SSI) below the active region of the n-type metal oxide semiconductor transistor. Fig.11 ).
[0106] Then please refer to Figure 2D , Fig.15 ,picture, Fig.16 , Fig.17 , Fig.18, wherein step 40 is used to form the source region and the drain region of the n-type metal oxide semiconductor transistor, and step 40 includes: step 126: removing the silicon carbide hydroxide spacer layer 508, 702, and depositing and etching back the shallow trench isolation layer 1602 ( Fig.16 );
[0107] Step 128: Deposit an amorphous silicon carbide layer 1702 as a virtual mask, and then remove the exposed pad nitride layer 206 corresponding to the source region / drain region to expose the silicon body ( Fig.17 );
[0108] Step 130: First, the exposed silicon surface is etched to form a groove and expose two
[0109] A vertical silicon edge with a (110) orientation is formed, and then a n-type lightly doped drain (LDD) region 1802 is formed by a selective growth technique, and then an n+ doped source region 1804 and an n+ doped drain region 1806 are formed which also have a crystal orientation (110);
[0110] Step 132: Deposit and etch back the titanium nitride layer 1808 and the tungsten layer 1810 ( Fig.18 ).
[0111] Then please refer to Figure 2E , Fig.19 The step 50 of forming the gate region of the n-type metal oxide semiconductor transistor comprises:
[0112] Step 134: Form the gate region of the n-type metal oxide semiconductor transistor by using a well-known gate-last process ( Fig.19 ).
[0113] Next, the manufacturing process of OP-CMOSFET is introduced. In step 102, as Figure 3 As shown in (a), a pad oxide layer 204 and a pad nitride layer 206 are formed above the semiconductor substrate body.
[0114] In step 104, if Figure 3 As shown in (a), the active area of the n-type metal oxide semiconductor transistor is defined in the semiconductor substrate body by using the photolithography mask technology and the anisotropic etching technology to create a trench area (about 300nm deep) for future shallow trench isolation (STI), for example, to create a convex structure of the active area (AA) of the n-type metal oxide semiconductor transistor.
[0115] Next, in step 106, if Figure 3 As shown in (a), an oxide spacer (about 1 nm thick) 208 is formed, and then a nitride spacer (about 2 nm thick) 210 is deposited as the solid wall to clamp the active region (or the narrow convex structure), especially to clamp the sidewall of the convex structure. In another embodiment of the present invention, the solid wall can be a single layer or other composite layers to protect the active region (or the narrow convex structure) from collapse during the subsequent formation of the source / drain region and gate region of the n-type metal oxide semiconductor transistor. Then, the excess oxide spacer 208 and nitride spacer 210 are removed by the chemical mechanical polishing technology to make the top surface of the pad nitride layer 206 flush with the original semiconductor surface (OSS) of the semiconductor substrate body.
[0116] Then in step 108, if Figure 3 As shown in (a), a shallow trench isolation layer 212 (or a thick oxide layer) is formed in the trench region and the chemical mechanical polishing technique is used to remove excess oxide to achieve that the top surface of the shallow trench isolation layer 212 is flush with the top surface of the liner nitride layer 206. Again, the shallow trench isolation layer 212 (or the thick oxide layer) further surrounds or clamps the active region (or the narrow convex structure), and in particular, clamps the sidewall of the convex structure to protect the active region (or the narrow convex structure) from collapse during the subsequent formation of the source / drain region and gate region of the n-type metal oxide semiconductor transistor. In addition, as Figure 3 As shown in (a), the active region is located on the anti-punch-through layer 214, wherein the anti-punch-through layer 214 is used to prevent the body and drain region of the n-type metal oxide semiconductor transistor from being punched through. In addition, Figure 3 (b) corresponds to Figure 3 (a) is a top view, wherein Figure 3 (a) Included in Figure 3 (b) Two cross-sectional views ("AA" and "BB") obtained at the position shown, the cross-sectional view "AA" corresponds to the coordinates (X, 0, Z), and the cross-sectional view "BB" corresponds to the coordinates (0, Y, Z).
[0117] Next, in step 110, Figure 4 As shown in FIG. 5( a ), a thin amorphous silicon carbide layer 402 is then formed over the pad nitride layer 206 and the shallow trench isolation layer 212 .
[0118] Then in step 112, if Figure 4As shown in (a), a photolithography mask is used to define the gate-related region that will span the active region and the isolation region (shallow trench isolation layer 212) in the future, and the silicon carbide layer 402 in the gate-related region is removed to expose the pad nitride layer 206. Then, the exposed portion of the pad nitride layer 206 (about 5 to 10 nm) is etched back. Therefore, the smooth line edge roughness of the damascene gate region is provided for the subsequent dummy gate. In addition, Figure 4 (b) corresponds to Figure 4 (a) is a top view, wherein Figure 4 (a) Included in Figure 4 (b) Two cross-sectional views ("AA" and "BB") obtained at the position shown, the cross-sectional view "AA" corresponds to the coordinates (X, 0, Z), and the cross-sectional view "BB" corresponds to the coordinates (0, Y, Z).
[0119] Then in step 114, if Figure 5 As shown in (a), a polysilicon spacer 502, a titanium nitride layer 504 and a tungsten layer 506 are deposited on the basis of the inlay process to form a dummy gate, wherein the width of the polysilicon spacer 502 is about 4 nm, and the width of the dummy gate (including the titanium nitride layer 504 and the tungsten layer 506) is about 10 nm.
[0120] Then in step 116, if Figure 5 As shown in (a), the remaining amorphous silicon carbide layer 402 is then removed to expose the shallow trench isolation layer 212. The exposed shallow trench isolation layer 212 ( Figure 5 The dotted circle in (b) can be etched down to recreate the convex structure outside the damascene gate region.
[0121] Next, in step 118, Figure 5 As shown in (a), a silicon carbide hydroxide spacer 508 is formed along the sidewall of the convex structure outside the embedded gate region. In addition, Figure 5 (b) corresponds to Figure 5 (a) is a top view, wherein Figure 5 (a) Included in Figure 5 (b) Two cross-sectional views ("AA" and "BB") obtained at the position shown, the cross-sectional view "AA" corresponds to the coordinates (X, 0, Z), and the cross-sectional view "BB" corresponds to the coordinates (0, Y, Z).
[0122] Then in step 120, if Figure 6 As shown in (a), the polysilicon spacer 502 is anisotropically etched. Then, the shallow trench isolation layer ( Figure 6(b) as shown by the dotted circle to form two recesses 602. In addition, Figure 6 (b) corresponds to Figure 6 (a) is a top view, wherein Figure 6 (a) Included in Figure 6 (b) Four cross-sectional views ("AA", "BB", "CC", "DD") obtained at the positions shown, cross-sectional view "AA" corresponds to coordinates (X, 0, Z), cross-sectional view "BB" corresponds to coordinates (0, Y, Z), cross-sectional view "CC" corresponds to coordinates (7, Y, Z), and cross-sectional view "DD" corresponds to coordinates (15, Y, Z).
[0123] Then in step 122, if Figure 7 As shown in (a), a silicon carbide oxyhydroxide spacer 702 is then formed in the two recesses 602 (the inlaid gate region) as an inlaid silicon carbide oxyhydroxide spacer. Thereafter, the shallow trench isolation layer 212 not covered by the dummy gate is etched, and the previous sandwiching spacer (nitride spacer 210 (SiO2)) is removed. 3 N 4 ) / oxidation spacer 208=2nm / 1nm) to expose the semiconductor sidewall. It should be noted that the semiconductor sidewall under the dummy gate is not exposed. In addition, Figure 7 (b) corresponds to Figure 7 (a) is a top view, wherein Figure 7 (a) includes four cross-sectional views corresponding to coordinates (X, 0, Z), (0, Y, Z), (7, Y, Z) and (15, Y, Z) respectively.
[0124] On the other hand, in one embodiment of the present invention, for the p-type metal oxide semiconductor transistor of OP-CMOSFET, there is no embedded gate region, so Figures 4 to 7 The process can be skipped. Thus, for the p-type metal oxide semiconductor transistor, Figure 3 After the process, Figure 8 As shown in (a), the shallow trench isolation layer 212 is etched downward, and then a silicon carbide hydroxide spacer 802 is formed to cover the sidewalls of the convex structure. Figure 8 As shown in (a), the shallow trench isolation layer 212 is etched downward again, and the previous sandwiching spacer (nitride spacer 210 (Si 3 N 4 ) / oxidized spacer 208 = 2nm / 1nm) to expose the semiconductor sidewalls. Different from the active region of the n-type metal oxide semiconductor transistor of the OP-CMOSFET mentioned above, all the semiconductor sidewalls of the convex structure under the silicon carbide hydroxide spacer 802 are exposed. In addition, Figure 8 (b) corresponds to Figure 8(a) is a top view, wherein Figure 8 (a) Included in Figure 8 (b) Two cross-sectional views ("AA" and "BB") obtained at the position shown, the cross-sectional view "AA" corresponds to the coordinates (X, 0, Z), and the cross-sectional view "BB" corresponds to the coordinates (0, Y, Z).
[0125] in addition, Fig. 9 (a) illustrates the 3D structure of the active region of a p-type metal oxide semiconductor transistor without an embedded gate region, and Fig. 9 (b) is a 3D structure of an active region of an n-type MOS transistor with a damascene gate region. Again, for the n-type MOS transistor, the semiconductor sidewalls below the dummy gate region are covered by the shallow trench isolation layer 212 and are not exposed, whereas for the p-type MOS transistor, all the semiconductor sidewalls of the convex structure below the silicon carbide spacer 802 are exposed.
[0126] A subsurface insulating layer (ie, a local isolation layer) may be formed on the basis of the exposed semiconductor sidewalls. Fig.10 It is the simulation result of Technology Computer-Aided Design (TCAD), such as Fig.10 As shown, the active region of the p-type metal oxide semiconductor transistor is subjected to repeated oxidation and oxide removal processes on the exposed semiconductor sidewalls. When the width of the active region is 10nm, after three 700 degree thermal oxidation cycles, a subsurface insulating layer 1002 is formed under the active region of the p-type metal oxide semiconductor transistor, and the silicon body between the silicon oxycarbon spacer 802 is completely insulated from the semiconductor substrate. Then, a chemical vapor deposition (CVD) oxide 1004 can be deposited under the silicon oxycarbon spacer 802.
[0127] On the other hand, in step 124, for the active region of the n-type metal oxide semiconductor transistor, based on the simulation of the technical computer-aided design, after three cycles of thermal oxidation process, although a subsurface insulating layer is also formed under the active region of the n-type metal oxide semiconductor transistor, Fig.11 As shown, the silicon body between the silicon oxycarbide spacers 508 is not completely insulated from the semiconductor substrate by the subsurface insulating layer, wherein a star-shaped silicon via 1102 exists between the silicon body between the silicon oxycarbide spacers 508 and the semiconductor substrate.
[0128] In another embodiment of the present invention, the subsurface insulating layer may be formed by a one-step thermal oxidation process at a relatively high temperature, such as 950 degrees or higher (1000 degrees to 1250 degrees). Fig.12 It is explained that a one-step thermal oxidation process (TCAD simulation) at 950 degrees forms a subsurface insulating layer 1202 under the active region of the p-type metal oxide semiconductor transistor, and the silicon body between the silicon oxycarbide spacers 802 is completely insulated from the semiconductor substrate again. Fig.13 In the figure, for the active region of the n-type metal oxide semiconductor transistor, after a one-step thermal oxidation process at 1000 degrees (TCAD simulation), a subsurface insulating layer is formed, but the silicon body between the silicon carbide hydroxide spacer 508 is not completely insulated from the semiconductor substrate.
[0129] Fig.14 (a) is a schematic diagram illustrating a 3D structure of an active region of a p-type metal oxide semiconductor transistor without an embedded gate region after forming a subsurface insulating layer ("UGOX"), and Fig.14 (b) is a schematic diagram illustrating the 3D structure of an active region of an n-type metal oxide semiconductor transistor with a embedded gate region. Fig.14 (b) is not shown, but there is a through silicon via (TSV) between the silicon body of the n-type metal oxide semiconductor transistor and the semiconductor substrate (e.g. Fig.11 Star-shaped through silicon vias 1102 as shown).
[0130] Afterwards, a real gate structure and source / drain region may be formed for the p-type metal oxide semiconductor transistor and the n-type metal oxide semiconductor transistor. Taking the n-type metal oxide semiconductor transistor as an example, Fig.15 (a) is a cross-sectional view of the active region of the n-type metal oxide semiconductor transistor at coordinates (X, 0, Z), (0, Y, Z), (7, Y, Z), and (15, Y, Z) after the subsurface insulating layer 1502 is completed. Fig.15 (b) corresponds to Fig.15 (a) Top view.
[0131] Then in step 126, if Fig.16 As shown in (a), the silicon carbide hydroxide spacer layers 508 and 702 are removed, and then the shallow trench isolation layer 1602 is deposited and etched back. In addition, Fig.16 (b) corresponds to Fig.16 (a) is a top view, wherein Fig.16 (a) includes four cross-sectional views corresponding to coordinates (X, 0, Z), (0, Y, Z), (7, Y, Z) and (15, Y, Z) respectively.
[0132] Then in step 128, if Fig.17 As shown in (a), an amorphous silicon carbide layer 1702 is deposited as a virtual mask. Then, the exposed pad nitride layer 206 (and the pad oxide layer 204 located below the exposed pad nitride layer 206) corresponding to the source region / drain region of the n-type metal oxide semiconductor transistor is removed to expose the silicon body. In addition, Fig.17 (b) corresponds to Fig.17 (a) is a top view, wherein Fig.17 (a) includes four cross-sectional views corresponding to coordinates (X, 0, Z), (0, Y, Z), (7, Y, Z) and (15, Y, Z) respectively.
[0133] Next, in step 130, Fig.18 As shown in (a), the exposed silicon surface is first etched to form the trench and expose two vertical silicon edges with a crystal direction (110). Then, on the basis of the two vertical silicon edges with a crystal direction (110), the selective growth technology (e.g., selective epitaxygrowth) is used to form an n-type lightly doped drain region 1802, and then an n+ doped source region 1804 and an n+ doped drain region 1806 are formed. It should be mentioned that ion implantation for forming the channel, drain region, and source region is not required, and high temperature thermal annealing is not required to remove damage caused by the strong bombardment of ion implantation for forming these channels, drain region, and source region.
[0134] Finally, in step 132, if Fig.18 As shown in (a), a titanium nitride layer 1808 and a tungsten layer 1810 are deposited (wherein the deposition of the titanium nitride layer 1808 and the tungsten layer 1810 can be performed by atomic layer deposition) and etched back (as shown in the AA cross-sectional view and the BB cross-sectional view). In another embodiment of the present invention, the top of the shallow trench isolation layer 212 is higher than the original semiconductor surface of the semiconductor substrate (the top of the shallow trench isolation layer 212 is flush with the top of the dummy gate). In addition, both sides (top and one sidewall) of the n+ doped drain region 1806 (or the n+ doped source region 1804) are in contact with the titanium nitride layer 1808 / tungsten layer 1810 (as well as with the bonding pads above the n+ doped drain region 1806 and the n+ doped source region 1804 (if any)), so the contact resistance of the n+ doped drain region 1806 (or the n+ doped source region 1804) is reduced accordingly. In addition, Fig.18 (b) corresponds to Fig.18 (a) is a top view, wherein Fig.18 (a) Included in Fig.18(b) Two cross-sectional views ("AA" and "BB") obtained at the position shown, the cross-sectional view "AA" corresponds to the coordinates (X, 0, Z), and the cross-sectional view "BB" corresponds to the coordinates (0, Y, Z).
[0135] Thereafter, in step 134, if Fig.19 As shown in (a), a well-known gate-last process is used to form a true gate region of an n-type metal oxide semiconductor transistor having a suitable work function metal (WFM) 1902 and a low-k main spacer layer 1904. Fig.19 As shown in (a), a tungsten layer 1906 is then deposited, wherein a high-K dielectric layer 1908 is formed between the active region and the work function metal 1902. In addition, Fig.19 (b) corresponds to Fig.19 (a) is a top view, wherein Fig.19 (a) Included in Fig.18 (b) Two cross-sectional views ("AA" and "BB") obtained at the position shown, the cross-sectional view "AA" corresponds to the coordinates (X, 0, Z), and the cross-sectional view "BB" corresponds to the coordinates (0, Y, Z).
[0136] therefore, Fig. 20 The invention is to describe a novel oxide-p-type metal-oxide-semiconductor complementary metal-oxide-semiconductor field effect transistor (OP-CMOSFET) 2002 based on the semiconductor substrate body instead of silicon on an insulating layer. Fig. 20 As shown in (a), the OP-CMOSFET 2002 has subsurface insulating layers 2004 and 2006 formed respectively under the p-type metal oxide semiconductor transistor and the n-type metal oxide semiconductor transistor to improve the leakage current and latch-up problems of the OP-CMOSFET 2002. In addition, the subsurface insulating layer 2004 under the p-type metal oxide semiconductor transistor completely isolates the body of the p-type metal oxide semiconductor transistor from the semiconductor substrate body (i.e., the N-well). However, the subsurface insulating layer 2006 under the n-type metal oxide semiconductor transistor only partially isolates the body of the n-type metal oxide semiconductor transistor from the semiconductor substrate body (i.e., the p-type silicon substrate). Fig. 20 As shown in (a), the subsurface insulating layer 2006 below the body of the n-type metal oxide semiconductor transistor retains a silicon opening / via (<4nm, such as 2nm or between 2nm and 4nm) 2008, so that the body of the n-type metal oxide semiconductor transistor can still be electrically coupled to the semiconductor substrate body. Therefore, the floating body effect in the n-type metal oxide semiconductor transistor can be improved. In addition, Fig. 20 (b) is related to Fig. 20 (a) The corresponding top view, where Fig. 20 (a) is along Fig. 20 (b) is a cross-sectional view of a cutting line in the X direction. In addition, the length of the channel of the p-type metal oxide semiconductor transistor (GL_PMOS) is the same or substantially the same as the length of the channel of the n-type metal oxide semiconductor transistor (GL_NMOS).
[0137] like Fig.21 As shown, even if a silicon opening 2012 is left in the subsurface insulating layer below the body of the n-type metal oxide semiconductor transistor, it can be known through the simulation of the computer-aided design of the technology that the subsurface insulating layer 2006 in the structure of the n-type metal oxide semiconductor transistor using the above-mentioned embedded dummy gate / spacer layer process has a bottom residual silicon of <= 4nm and can have the same leakage (Ioff) as the subsurface insulating layer 2004 in the structure of the p-type metal oxide semiconductor transistor that does not use the above-mentioned embedded dummy gate / spacer layer process.
[0138] In addition, if Fig. 22 As shown, the present invention can also be applied to an oxide-N-type metal-oxide-semiconductor complementary metal-oxide-semiconductor field effect transistor (ON-CMOSFET) 2202 based on the semiconductor substrate body instead of silicon on an insulating layer. Fig. 22 As shown, the ON-CMOSFET 2202 has subsurface insulating layers 2004 and 2006 formed respectively under the p-type metal oxide semiconductor transistor and the n-type metal oxide semiconductor transistor to improve the leakage current and latch-up problems of the ON-CMOSFET 2202. In addition, the subsurface insulating layer 2006 under the n-type metal oxide semiconductor transistor completely isolates the body of the n-type metal oxide semiconductor transistor from the semiconductor substrate body. However, the subsurface insulating layer 2004 under the p-type metal oxide semiconductor transistor only partially isolates the body of the p-type metal oxide semiconductor transistor from the semiconductor substrate body, so that the body of the active region of the p-type metal oxide semiconductor transistor can still be electrically coupled to the semiconductor substrate body. Therefore, the floating body effect in the p-type metal oxide semiconductor transistor can be improved.
[0139] Of course, in another embodiment of the present invention, a Fig.23The partial-oxide complementary metal-oxide-semiconductor field-effect transistor (Partial-Oxide Complementary Metal-Oxide-Semiconductor Field-Effect Transistor, PO-C MOSFET) 2302 is shown. Fig.23 As shown, the PO-CMOSFET 2302 has subsurface insulating layers 2004 and 2006 respectively formed under the p-type metal oxide semiconductor transistor and the n-type metal oxide semiconductor transistor to improve the leakage current and latch-up problems of the PO-CMOSFET 2302, wherein the subsurface insulating layer 2006 under the n-type metal oxide semiconductor transistor only isolates the body of the n-type metal oxide semiconductor transistor from the main part of the semiconductor substrate, and the subsurface insulating layer 2004 under the p-type metal oxide semiconductor transistor also only isolates the body of the p-type metal oxide semiconductor transistor from the main part of the semiconductor substrate. Therefore, the body of the p-type metal oxide semiconductor transistor and the body of the n-type metal oxide semiconductor transistor can still be electrically coupled to the main part of the semiconductor substrate, so the floating body effect in the p-type metal oxide semiconductor transistor and the n-type metal oxide semiconductor transistor can be improved.
[0140] In addition, in another embodiment of the present invention, an oxide-p-type metal oxide semiconductor transistor-n-type metal oxide semiconductor transistor complementary metal oxide semiconductor field effect transistor (Oxide-PMOS-NMOSComplementary Metal-Oxide-Semiconductor Field-Effect Transistor, OPN-CMOSFET2402, such as Fig.24 As shown. 24.OPN-CMOSFET 2402 has subsurface insulating layers 2004 and 2006 formed under the p-type metal oxide semiconductor transistor and the n-type metal oxide semiconductor transistor, respectively, so that leakage current and latch-up problems can be improved. The subsurface insulating layer 2006 under the n-type metal oxide semiconductor transistor completely isolates the NMOS body from the semiconductor substrate body, and the subsurface insulating layer 2004 under the p-type metal oxide semiconductor transistor also completely isolates the PMOS body from the semiconductor substrate body. In addition, GL_PMOS represents the gate region of the p-type metal oxide semiconductor transistor, and GL_NMOS represents the gate region of the n-type metal oxide semiconductor transistor.
[0141] In addition, if Fig. 20 , Fig. 22 , Fig.23 and Fig.24 As shown, Fig. 20 , Fig. 22 , Fig.23 and Fig.24 The nitride spacer 2010, the oxide spacer 2012, the oxide layer 2014, the tungsten 2016, the cap nitride layer 2018, the cap oxide layer 2020, the titanium / titanium nitride metal layer 2022, the N+ polysilicon 2024, the gate oxide layer 2026, the P+ region 2028, the P- region 2030, the N+ region 2032 and the N- region 2034 are also included, wherein the relative positions of the nitride spacer 2010, the oxide spacer 2012, the oxide layer 2014, the tungsten 2016, the cap nitride layer 2018, the cap oxide layer 2020, the titanium / titanium nitride metal layer 2022, the N+ polysilicon 2024, the gate oxide layer 2026, the P+ region 2028, the P- region 2030, the N+ region 2032 and the N- region 2034 can be referred to Fig. 20 , so I will not go into details here.
[0142] In summary, the present invention has the following advantages:
[0143] 1. The present invention can form a subsurface insulating layer in the semiconductor substrate without the need to purchase a very expensive entire silicon-on-insulator (SOI) wafer.
[0144] 2. Providing a subsurface insulating layer below the p-type metal oxide semiconductor transistor and the n-type metal oxide semiconductor transistor can improve leakage current and latch-up problems in the complementary metal oxide semiconductor transistor structure.
[0145] 3. The subsurface insulating layer below the p-type metal oxide semiconductor transistor and / or the n-type metal oxide semiconductor transistor can isolate the p-type metal oxide semiconductor transistor and / or the n-type metal oxide semiconductor transistor from the main body of the semiconductor substrate, thereby solving the floating body effect in the traditional silicon-on-insulator (SOI) wafer.
[0146] 4. The source region / drain region is formed by selectively growing a lightly / heavily doped layer, and there is no need to perform an ion implantation process for doping the source region / drain region.
[0147] 5. Since the vertical length of the body of the p-type metal oxide semiconductor transistor and / or the body of the n-type metal oxide semiconductor transistor is about 5-10 nm, the reduction of the junction area of the source region / drain region will also lead to a reduction in leakage current.
[0148] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A complementary metal oxide semiconductor circuit, characterized in that Include: A semiconductor substrate body having an original semiconductor surface; A first active region and a second active region are formed on the basis of the semiconductor substrate body; a first-type transistor formed on the basis of the first active region and having a first doped body; a first local isolation layer located below the first-type transistor and isolating at least the first doped body from the semiconductor substrate body; a second-type transistor formed on the basis of the second active region and having a second dopant; and A second local isolation layer is located below the second-type transistor and at least partially isolates the second doped body from the semiconductor substrate body.
2. The complementary metal oxide semiconductor circuit as claimed in claim 1, characterized in that Also includes: a first shallow trench isolation region surrounding the first active region and the first local isolation layer; and A second shallow trench isolation region surrounds the second active region and the second local isolation layer.
3. The complementary metal oxide semiconductor circuit as claimed in claim 1, characterized in that The first local isolation layer completely isolates the first-type transistor from the semiconductor substrate body, and the second local isolation layer only partially isolates the second-type transistor from the semiconductor substrate body, wherein the first-type transistor is a p-type metal oxide semiconductor transistor, and the second-type transistor is an n-type metal oxide semiconductor transistor.
4. The complementary metal oxide semiconductor circuit as claimed in claim 3, characterized in that The second local isolation layer has an opening, and the second doped body of the n-type metal oxide semiconductor transistor is electrically coupled to the semiconductor substrate body through the opening.
5. The complementary metal oxide semiconductor circuit as claimed in claim 4, characterized in that The length of the opening is 2 to 4 nanometers (nm).
6. The complementary metal oxide semiconductor circuit as claimed in claim 5, characterized in that The opening is in a star shape or an irregular shape.
7. The complementary metal oxide semiconductor circuit as claimed in claim 1, characterized in that The first local isolation layer only partially isolates the first-type transistor from the semiconductor substrate body, and the second local isolation layer completely isolates the second-type transistor from the semiconductor substrate body, wherein the first-type transistor is a p-type metal oxide semiconductor transistor, and the second-type transistor is an n-type metal oxide semiconductor transistor.
8. The complementary metal oxide semiconductor circuit as claimed in claim 7, characterized in that The first local isolation layer has an opening, and the first doped body of the p-type metal oxide semiconductor transistor is electrically coupled to the semiconductor substrate body through the opening.
9. The complementary metal oxide semiconductor circuit as claimed in claim 1, characterized in that The first local isolation layer completely isolates the first type transistor from the semiconductor substrate body, and the second local isolation layer completely isolates the second type transistor from the semiconductor substrate body, wherein the first type transistor is a p-type metal oxide semiconductor transistor, and the second type transistor is an n-type metal oxide semiconductor transistor.
10. The complementary metal oxide semiconductor circuit as claimed in claim 1, characterized in that The source region of the first-type transistor is adjacent to the first local isolation layer.
11. The complementary metal oxide semiconductor circuit as claimed in claim 10, characterized in that Also included is a metal region contacting a top surface and a sidewall of the source region.
12. The complementary metal oxide semiconductor circuit as claimed in claim 1, characterized in that The channel length of the first-type transistor is the same as the channel length of the second-type transistor.
13. A complementary metal oxide semiconductor circuit, characterized in that Include: A semiconductor substrate body having an original semiconductor surface; A first active region and a second active region are formed on the basis of the semiconductor substrate body; a p-type metal oxide semiconductor transistor is formed on the basis of the first active region and has a first doped body and a first channel; a first local isolation layer, located below the p-type metal oxide semiconductor transistor and isolating at least the first doped body from the semiconductor substrate body; a first shallow trench isolation region surrounding the first active region and the first local isolation layer; an n-type metal oxide semiconductor transistor formed on the basis of the second active region and having a second dopant and a second channel; a second local isolation layer, located below the n-type metal oxide semiconductor transistor and at least partially isolating the second doped body from the semiconductor substrate body; and a second shallow trench isolation region surrounding the second active region and the second local isolation layer; The length of the first channel is the same as the length of the second channel.
14. The complementary metal oxide semiconductor circuit as claimed in claim 13, characterized in that The second local isolation layer has an opening, and the second doped body of the n-type metal oxide semiconductor transistor is electrically coupled to the semiconductor substrate body through the opening.
15. The complementary metal oxide semiconductor circuit as claimed in claim 14, characterized in that The length of the opening is between 2 nm and 4 nm.
16. The complementary metal oxide semiconductor circuit as claimed in claim 14, characterized in that The shape of the opening is a star shape or an irregular shape.
17. The complementary metal oxide semiconductor circuit as claimed in claim 13, characterized in that The drain region of the p-type metal oxide semiconductor transistor is adjacent to the first local isolation layer.
18. The complementary metal oxide semiconductor circuit according to claim 17, characterized in that The invention also includes a metal region contacting the top surface and a side wall of the drain region.