Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first well region laterally separated from a second well region in a substrate, a shallow trench isolation (STI) structure in the substrate laterally between the first well region and the second well region, a first well region in the substrate, a dopant type opposite to a dopant type of the first well region in the substrate, a first implant region vertically lower than the STI structure and laterally between the first well region and a lateral center of the STI structure, and a dopant type opposite to a dopant type of a second well region in the substrate, and a second implant region vertically lower than the STI structure and laterally between the second well region and a lateral center of the STI structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, and capacitors). However, the continued integration density in semiconductor devices has led to tighter well spacing, which may result in increased leakage current between adjacent well regions forming, for example, transistors, thereby reducing the quality and productivity of semiconductor devices. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor device is provided, including: a first well region, laterally separated from a second well region in a substrate; a shallow trench isolation structure, laterally located between the first well region and the second well region in the substrate; a first injection region of a third dopant type, opposite to the first dopant type of the first well region in the substrate, and arranged vertically lower than the shallow trench isolation structure; and a second injection region of a fourth dopant type, opposite to the second dopant type of the second well region in the substrate, and arranged vertically lower than the shallow trench isolation structure.

[0004] According to another aspect of an embodiment of the present application, a semiconductor device is provided, including: a first well region, laterally separated from a second well region in a substrate; a shallow trench isolation structure, laterally located between the first well region and the second well region in the substrate; a first deep injection region of a first dopant type, opposite to the dopant type of the first well region, and vertically lower than the shallow trench isolation structure; a second deep injection region of a second dopant type, opposite to the dopant type of the second well region, and vertically lower than the shallow trench isolation structure; a first shallow injection region of the first dopant type, vertically located above the first deep injection region, and laterally located between the first well region and the shallow trench isolation structure; and a second shallow injection region of the second dopant type, vertically located above the second deep injection region, and laterally located between the second well region and the shallow trench isolation structure.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: etching a shallow trench isolation trench in a substrate; forming a first well region and a second well region on both lateral sides of the shallow trench isolation trench in the substrate; forming a first injection region, a first dopant type of the first injection region is opposite to the dopant type of the first well region and is vertically lower than the shallow trench isolation trench; and forming a second injection region, a second dopant type of the second injection region is opposite to the dopant type of the second well region and is vertically lower than the shallow trench isolation trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A perspective view of a semiconductor device according to some embodiments is shown.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E Cross-sectional views of various semiconductor devices are shown in accordance with some embodiments.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Cross-sectional views of various semiconductor devices according to other embodiments are shown.

[0010] Figure 3F According to some embodiments, Figure 3A The doping profile of the semiconductor device is shown.

[0011] Figure 3G According to some embodiments, Figure 3A Results of simulations performed on the semiconductor device shown.

[0012] Figure 4A and Figure 4B Cross-sectional views of a semiconductor device during various fabrication stages are shown in accordance with some embodiments.

[0013] Figure 5A and Figure 5B Cross-sectional views of semiconductor devices during various fabrication stages according to other embodiments are shown.

[0014] Figure 6 is a flow chart illustrating a method of manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0017] Shallow trench isolation deposited in a semiconductor device substrate can allow for tighter well spacing, however, this can result in increased leakage current between adjacent well regions forming, for example, CMOS transistors, thereby severely reducing the performance and productivity of the semiconductor device. Therefore, it is desirable to reduce the well-to-well leakage current between adjacent wells caused by tighter well spacing in semiconductor devices.

[0018] The present disclosure provides various embodiments of a semiconductor device, which includes an STI in a substrate, a first deep injection region of a dopant type opposite to that of an adjacent first well region, and a second deep injection region of a dopant type opposite to that of an adjacent second well region on both sides of the STI. The first deep injection region is formed to be vertically lower than the STI structure and laterally located between the first well region and the lateral center of the STI structure. The second deep injection region is formed to be vertically lower than the STI structure and laterally located between the second well region and the lateral center of the STI structure. Therefore, due to the first and second deep anti-well injection regions, the well-to-well leakage current level in the semiconductor device can be reduced, thereby obtaining a more compact chip design and more robust chip performance of the semiconductor device.

[0019] Figure 1 1 shows a perspective view of a semiconductor device 100 according to some embodiments. Figure 1As shown, the semiconductor device 100 includes a substrate 10, a plurality of implanted well regions (e.g., 20A and 20B) laterally separated from each other in the substrate 10, and an isolation structure 30 that laterally separates adjacent implanted well regions in the substrate 10. The implanted well regions may be N-type and / or P-type. In some embodiments, the isolation structure 30 may include a shallow trench isolation (STI) structure. However, it should be understood that the isolation structure 30 may be implemented as any of a variety of other structures, such as a field oxide or a deep trench isolation structure. Figure 1 In the illustrative example of FIG. 1 , STI structure 30 surrounds any one of implanted well regions 20A and 20B. Other arrangements of STI structure 30 are also contemplated while remaining within the scope of the present disclosure.

[0020] In some embodiments, the semiconductor device 100 includes a first deep implantation region 40A and a second deep implantation region 40B, wherein the first deep implantation region 40A has a dopant type opposite to that of the adjacent first well region 20A, is disposed vertically lower than the STI structure 30, and is laterally located between the first well region 20A and the lateral center C of the STI structure 30, and the second deep implantation region 40B has a dopant type opposite to that of the adjacent second well region 20B, is disposed vertically lower than the STI structure 30, and is laterally located between the second well region 20B and the lateral center C of the STI structure 30. The lateral center C of the STI structure 30 is a line passing through the midpoint between the STI boundaries. In some embodiments, the STI structure 30 is rectangular in shape. In other embodiments, the STI structure 30 is in the shape of an inverted trapezoid.

[0021] In some embodiments, the semiconductor device 100 includes a first shallow implantation region 50A and a second shallow implantation region 50B, wherein the first shallow implantation region 50A has the same dopant type as the first deep implantation region 40A, is vertically disposed above the first deep implantation region 40A, and is laterally located between the first well region 20A and the STI structure 30, and the second shallow implantation region 50B has the same dopant type as the second deep implantation region 40B, is vertically disposed above the second deep implantation region 40B, and is laterally located between the second well region 20B and the STI structure 30 (also as shown in FIG. 1 ). Figure 3A In some embodiments, the lengths of the first deep implant region 40A and the second deep implant region 40B in the Y direction are longer than the lengths of the first well region 20A and the second well region 20B. In some embodiments, the lengths of the first shallow implant region 50A and the second shallow implant region 50B in the Y direction are longer than the lengths of the first well region 20A and the second well region 20B.

[0022] The semiconductor device 100 may also include transistors, each transistor including a source / drain 22 and a gate structure 24 formed on any one of the implanted well regions 20A and 20B. The source and drain are used interchangeably in the present disclosure. Depending on the context, the source / drain region may refer to the source or drain individually or collectively. The semiconductor device 100 may also include a capping layer 15 of, for example, a silicide material partially on the top surface of the substrate 10, and a well capping layer 18 of, for example, a silicide material partially on any one of the implanted well regions 20A and 20B.

[0023] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E A cross-sectional view of various semiconductor devices 200 is shown in accordance with some embodiments. Figure 2A-2E The semiconductor devices 200 shown in FIG. 2 may each be Figure 1 An embodiment of a semiconductor device 100 is shown in FIG.

[0024] like Figure 2A As shown, the semiconductor device 200 includes a substrate 10, a first well region 20A laterally separated from a second well region 20B in the substrate 10, an STI structure 30 laterally located between the first well region 20A and the second well region 20B in the substrate 10, and a first deep implant region 40A having a dopant type opposite to that of the first well region 20A of the substrate 10 and a second deep implant region 40B having a dopant type opposite to that of the second well region 20B. In some embodiments, the STI structure 30 is flush with the top surface of the substrate 10, as shown in FIG. Figure 1 In other embodiments, the STI structure 30 is lower than the top surface of the substrate 10, such as Figure 2A-2E shown.

[0025] The first deep implant region 40A is deeply implanted to be vertically lower than the STI structure 30 and is laterally located between the first well region 20A in the substrate 10 and the lateral center C of the STI structure 30. The second deep implant region 40B is deeply implanted to be vertically lower than the STI structure 30 and is laterally located between the second well region 20B in the substrate 10 and the lateral center C of the STI structure 30.

[0026] In some embodiments, the STI structure 30 includes an isolation oxide (eg, Figure 4A and Figure 4B Various etching and deposition methods may be used to form and deposit the STI trenches 30 ′ in the substrate 10 of the semiconductor device 200 .

[0027] In some embodiments, the ratio of the width of the first deep implant region 40A to the width of the STI structure 30 is in the range of 5 / 100 to 95 / 100, and the ratio of the width of the second deep implant region 40B to the width of the STI structure 30 is in the range of 5 / 10 to 95 / 100. In other embodiments, the ratio of the width of the first deep implant region 40A to the width of the STI structure 30 is in the range of 20 / 100 to 60 / 100, and the ratio of the width of the second deep implant region 40B to the width of the STI structure 30 is in the range of 20 / 00 to 60 / 100.

[0028] In some embodiments, Figure 2B and Figure 2C As shown, the dopant type of the first deep implant region 40A and the second deep implant region 40B is the same. Figure 2B As shown, the dopant type of the first deep implantation region 40A and the second deep implantation region 40B is N-type. Figure 2C As shown, the dopant type of the first deep implantation region 40A and the second deep implantation region 40B is P type.

[0029] In other embodiments, Figure 2D and Figure 2E As shown, the dopant types of the first deep implant region 40A and the second deep implant region 40B are opposite to each other. Figure 2D As shown in FIG. 4 , the dopant type of the first deep implant region 40A is N-type, and the dopant type of the second deep implant region 40B is P-type. Figure 2E As shown, the dopant type of the first deep implantation region 40A is P-type, and the dopant type of the second deep implantation region 40B is N-type.

[0030] The doping conditions include, for example, dopant type, implantation dose, implantation energy, and implantation tilt angle of the implanted material. In some embodiments, the implanted material for P-type implantation is selected from any one of B, Ga, In, and BF2, and the implanted material for N-type implantation is selected from any one of As and P. In some embodiments, the implanted material has an implantation dose of 1e12 ions / cm 2 to 5e12 ions / cm 2 In some embodiments, the implantation energy of the implanted material is in the range of 200 KeV to 500 KeV. In some embodiments, the implantation tilt angle of the implanted material is in the range of 0 degrees to 7 degrees. The implantation conditions can be independently adjusted to improve the separation quality between adjacent well regions.

[0031] According to the present disclosure, the dopant type of the deep implant regions 40A and 40B is opposite to that of the adjacent well regions 20A and 20B, and the deep implant regions 40A and 40B are disposed on both sides of the STI structure 30 in the substrate 10 and are lower than the STI structure 30, which can be used as a charge barrier between adjacent well regions, thereby improving the isolation between adjacent implanted well regions, thereby reducing the well-to-well leakage current level. Therefore, the performance of the semiconductor device is enhanced.

[0032] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E A cross-sectional view of various semiconductor devices 300 is shown in accordance with some embodiments. Figure 3A-3E Each of the semiconductor devices 300 shown in FIG. Figure 1 An embodiment of a semiconductor device 100 is shown in FIG.

[0033] like Figure 3A As shown, the semiconductor device 300 includes a substrate 10, a first well region 20A laterally separated from a second well region 20B in the substrate 10, an STI structure 30 laterally between the first well region 20A and the second well region 20B in the substrate 10, a first deep injection region 40A of a first dopant type (e.g., N-type or P-type) opposite to the dopant type (e.g., N-type or P-type) of the first well region, the first deep injection region 40A being arranged to be vertically lower than the STI structure 30 and laterally located between the first well region 20A and a lateral center C of the STI structure 30, and a second deep injection region 40B of a second dopant type (e.g., N-type or P-type) opposite to the dopant type (e.g., N-type or P-type) of the second well region 20B, the second deep injection region 40B being vertically lower than the STI structure 30 and laterally located between the second well region 20B in the substrate 10 and a lateral center C of the STI structure 30.

[0034] In addition, in some embodiments, the semiconductor device 300 also includes a first shallow injection region 50A and a second shallow injection region 50B, the first shallow injection region 50A has a dopant type that is the same as the dopant type of the first deep injection region 40A, and is vertically arranged above the first deep injection region 40A, and is laterally arranged between the first well region 20A and the STI structure 30, and the second shallow injection region 50B has a dopant type that is the same as the dopant type of the second deep injection region 40B, and is vertically arranged above the second deep injection region 40B, and is laterally located between the second well region 20B in the substrate 10 and the STI structure 30.

[0035] Shallow implantation regions 50A and 50B having opposite dopant types relative to adjacent well regions 20A and 20B at both sides of the STI structure 30 in the substrate 10 can form additional PN junctions as potential barriers to further improve the isolation between the adjacent well regions 20A and 20B, thereby further reducing the well-to-well leakage current level in the semiconductor device 300.

[0036] In the case where the STI structure 30 between the well regions 20A and 20B provides separation at a depth in the substrate 10 below the STI structure 30, the dopant concentration applied in the deep implant regions 40A and 40B is higher than the dopant concentration in the shallow implant regions 50A and 50B. In some embodiments, the dopant concentration in the first deep implant region 40A is higher than the dopant concentration in the first shallow implant region 50A, and the dopant concentration in the second deep implant region 40B is higher than the dopant concentration in the second shallow implant region 50B. In some embodiments, the dopant concentrations in the deep implant regions 40A and 40B and the shallow implant regions 50A and 50B increase in a gradient manner in the depth direction in the substrate 10.

[0037] like Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E As shown, the first deep injection region 40A and the first shallow injection region 50A have the same dopant type (e.g., N-type) opposite to the dopant type (e.g., P-type) of the adjacent first well region 20A, and the second deep injection region 40B and the second shallow injection region 50B have the same dopant type (e.g., P-type) opposite to the dopant type (e.g., N-type) of the adjacent second well region 20B.

[0038] like Figure 3B and Figure 3C As shown, in some embodiments, the dopant type of the first deep implant region 40A and the first shallow implant region 50A is the same as the dopant type of the second deep implant region 40B and the second shallow implant region 50B. Figure 3B As shown, in some embodiments, the dopant type of the first deep implant region 40A and the first shallow implant region 50A and the dopant type of the second deep implant region 40B and the second shallow implant region 50B are all N-type. Figure 3C As shown, in other embodiments, the dopant types of the first deep implant region 40A and the first shallow implant region 50A and the dopant types of the second deep implant region 40B and the second shallow implant region 50B are all P-type.

[0039] like Figure 3D and Figure 3E As shown, in other embodiments, the dopant type of the first deep implant region 40A and the first shallow implant region 50A is opposite to the dopant type of the second deep implant region 40B and the second shallow implant region 50B. Figure 3D As shown, in some embodiments, the dopant type of the first deep implant region 40A and the first shallow implant region 50A is N-type, and the dopant type of the second deep implant region 40B and the second shallow implant region 50B is P-type. Figure 3E As shown, in other embodiments, the dopant type of the first deep implant region 40A and the first shallow implant region 50A is P type, and the dopant type of the second deep implant region 40B and the second shallow implant region 50B is N type.

[0040] In some embodiments, semiconductor device 300 further includes a first planar CMOS transistor formed in first well region 20A and a second planar CMOS transistor formed in second well region 20B. In some embodiments, first and second planar MOSFET transistors each include source / drain 22 and gate structure 24 .

[0041] like Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E As shown, the above doping conditions for doping the deep implantation region of the semiconductor device 200 are also applicable to Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E The semiconductor device 300 shown in FIG. Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E As shown, doping conditions may be independently adjusted to improve the separation quality between adjacent well regions 20A and 20B.

[0042] Figure 3F According to some embodiments, Figure 3A The doping profile of the semiconductor device is shown. Figure 3G According to some embodiments, Figure 3A The results of the simulation performed on the semiconductor device 300 are shown in FIG. Figure 3F and Figure 3G As shown, the semiconductor device 300 including deep implant regions 40A and 40B and shallow implant regions 50A and 50B on both sides of the STI structure 30 in the substrate 10 has a smaller inter-well spacing, which is the distance between wells (e.g., about 0.5 to 1 μm), but has a comparable or even lower inter-well leakage current.

[0043] Figure 4A and Figure 4BA cross-sectional view of a semiconductor device 400 during various manufacturing stages is shown in accordance with some embodiments, wherein two implantation processes are performed after forming STI trenches 30 ′ in substrate 10 and before depositing dielectric material in the STI trenches 30 ′.

[0044] like Figure 4A As shown, STI trenches 30' are formed in the semiconductor substrate 10 of the semiconductor device 400. Various photolithography and etching methods can be used to form the STI trenches 30' in the substrate 10 of the semiconductor device 400. In some embodiments, first well regions 20A and second well regions 20B of opposite dopant types are laterally formed on both sides of the STI trenches 30' in the substrate 10. Various methods of photolithography and implantation can be used to form the first well region 20A and the second well region 20B in the substrate 10.

[0045] Likewise Figure 4A As shown, in some embodiments, by implanting a first deep implant region 40A of a dopant type opposite to that of the adjacent first well region 20A through a hard mask 101, and partially implanting through the STI trench 30' where no dielectric material has been deposited, implantation energy can be saved. The first deep implant region 40A is formed vertically below the STI trench 30' and is laterally located between the first well region 20A in the substrate 10 and the lateral center C of the STI trench 30'.

[0046] Furthermore, in some embodiments, a first shallow implant region 50A having the same dopant type as the first deep implant region 40A is also implanted through the hard mask 101. The first shallow implant region 50A is formed vertically above the deep implant region 40A and laterally between the first well region 20A and the STI trench 30'.

[0047] Afterwards, if Figure 4B As shown, in some embodiments, a second deep implant region 40B of a dopant type opposite to that of the second well region 20B is implanted through another hard mask 102 via another implant, and the other implant partially passes through the STI trench 30', thereby saving implantation energy. The second deep implant region 40B is formed vertically below the STI trench 30' and is laterally located between the second well region 20B in the substrate 10 and the lateral center C of the STI trench 30'.

[0048] Furthermore, in some embodiments, a second shallow implant region 50B having the same dopant type as that of the second deep implant region 40B is also implanted through the hard mask 102. The second shallow implant region 50B is formed vertically above the deep implant region 40B and laterally between the second well region 20B and the STI trench 30'.

[0049] Figure 5A and Figure 5B A cross-sectional view of a semiconductor device 500 at different manufacturing stages according to other embodiments is shown, wherein two implantation processes are performed after depositing a dielectric material in the STI trenches 30 ′.

[0050] like Figure 5A and Figure 5B As shown, through the STI trench (eg Figure 4A and Figure 4B A dielectric material is filled or deposited in the STI trench 30′ as shown to form the STI structure 30. The STI structure 30 may be formed in the substrate 10 of the semiconductor device 500 using various photolithography and deposition methods.

[0051] like Figure 5A As shown, in some embodiments, a first deep implant region 40A having a dopant type opposite to that of the first well region 20A is implanted through a hard mask 101 by implantation, and the implantation partially passes through the STI structure 30. The first deep implant region 40A is formed to be vertically lower than the STI structure 30 and laterally located between the first well region 20A in the substrate 10 of the semiconductor device 500 and a lateral center C of the STI structure 30.

[0052] Furthermore, in some embodiments, a first shallow implant region 50A having the same dopant type as the first deep implant region 40A is also implanted through the hard mask 101. The first shallow implant region 50A is formed vertically above the deep implant region 40A and laterally between the first well region 20A and the STI structure 30.

[0053] Afterwards, if Figure 5B As shown, a second deep implant region 40B of a dopant type opposite to that of the second well region 20B is implanted through another hard mask 102 by another implant, and the another implant partially passes through the STI structure 30. The second deep implant region 40B is formed vertically in the substrate 10 to be lower than the STI structure 30, and is laterally formed between the second well region 20B and the lateral center C of the STI structure 30.

[0054] Furthermore, in some embodiments, second shallow implant region 50B having the same dopant type as that of second deep implant region 40B is implanted through hard mask 102. Second shallow implant region 50B is vertically formed above deep implant region 40B and laterally formed between second well region 20B and STI structure 30.

[0055] Figure 6 is a diagram showing the manufacture of an Figure 2A or Figure 3A 600 of the method for a semiconductor device shown in FIG. It should be understood that additional embodiments of the method may be Figure 6 Additional operations may be provided before, during, and after the processes discussed in the description, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable, and at least some operations or processes may be performed in different orders. In some embodiments, at least two or more operations or processes overlap in time or are performed almost simultaneously.

[0056] In operation S610, a shallow trench isolation (STI) trench 30 ′ (eg, Figure 4A and Figure 4B ). Various photolithography and etching methods may be used to form STI trenches 30' in the depth direction of substrate 10 of the semiconductor device. In some embodiments, STI trenches 30' are etched in substrate 10 by dry etching. In other embodiments, STI trenches 30' are etched in substrate 10 by wet etching.

[0057] In some embodiments, dielectric material is deposited in the STI trench 30' to form the STI structure 30. Various deposition methods may be used to fill the STI trench 30' with dielectric material to form the STI structure 30. In some embodiments, dielectric material is deposited in the STI trench 30' to form the STI structure 30 by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, high density plasma chemical vapor deposition (HDP-CVP) is used to deposit dielectric material in the STI trench 30' to form the STI structure 30. The trench 30' filled with dielectric material may improve the doping profile and concentration of the deep implant regions 40A and 40B.

[0058] In some embodiments, the substrate 10 includes a single crystal semiconductor layer at least on a surface portion thereof. The substrate 10 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 10 is a silicon wafer. The substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain region. The buffer layer may be formed of an epitaxially grown single crystal semiconductor material, such as but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a specific embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on the silicon substrate 10.

[0059] In operation S620, a first well region 20A and a second well region 20B are formed on both lateral sides of the STI trench 30' in the substrate 10. Various methods of photolithography and implantation may be used to form the first well region 20A and the second well region 20B in the substrate 10. In some embodiments, the first well region 20A and the second well region 20B have the same dopant type, such as Figure 2B and Figure 2C In other embodiments, the dopant types of the first well region 20A and the second well region 20B are opposite to each other, such as Figure 2D and Figure 2E In some embodiments, the STI trench 30' surrounds any one of the first well region 20A and the second well region 20B, such as Figure 1 shown.

[0060] In operation S630, a first deep implant region 40A of a first dopant type opposite to that of the first well region 20A is implanted. In the substrate 10 of the semiconductor device, the first deep implant region 40A is formed vertically below the STI trench 30' and laterally between the first well region 20A and the lateral center C of the STI trench 30'.

[0061] In operation S640, a second deep implant region 40B of a second dopant type opposite to the dopant type of the second well region 20B is implanted. The second deep implant region 40B is formed vertically below the STI trench 30' and laterally between the second well region 20B of the substrate 10 of the semiconductor device and the lateral center C of the STI trench 30'.

[0062] Various photolithography and implantation methods can be used to form the first deep implantation region 40A and the second deep implantation region 40B on both sides of the STI trench 30' in the substrate 10 of the semiconductor device. In some embodiments, the first deep implantation region 40A and the second deep implantation region 40B having the same dopant type can be formed by a single photolithography process and a single implantation process. In other embodiments, two photolithography processes and two implantation processes (e.g., Figure 4A and Figure 4B As shown in the figure, a first deep implantation region 40A and a second deep implantation region 40B having dopant types opposite to each other are formed.

[0063] In some embodiments, after forming the first implant region 40A and the second implant region 40B, a dielectric material is filled in the STI trench 30' to form the STI structure 30 (eg, Figure 2A shown).

[0064] In other embodiments, before forming the first deep implant region 40A and the second deep implant region 40B, a dielectric material is filled in the STI trench 30' to form the STI structure 30 (eg, Figure 2AIn some embodiments, the dielectric material includes an isolation oxide.

[0065] In some embodiments, the first shallow implant region 50A having the same dopant type as the first deep implant region 40A is vertically implanted above the first deep implant region 40A (eg, Figure 3A As shown), and is laterally implanted between the first well region 20A and the STI structure 30 in the substrate 10 of the semiconductor device 300.

[0066] In some embodiments, a second shallow implant region 50B having the same dopant type as the second deep implant region 40B is implanted above the second deep implant region 40B (eg, Figure 3A As shown), and laterally between the second well region 20B and the STI structure 30 in the substrate 10 of the semiconductor device 300.

[0067] In some embodiments, the dopant concentration in the first deep implant region 40A is higher than the dopant concentration in the first shallow implant region 50A, and the dopant concentration in the second deep implant region 40B is higher than the dopant concentration in the second shallow implant region 50B.

[0068] In the present disclosure, two deep implantation regions having a dopant type opposite to that of two adjacent implantation well regions are deposited on both sides of the STI structure and below the STI structure, which can improve the isolation between the two adjacent implantation wells, thereby advantageously minimizing the well-to-well leakage current, thereby leading to a more compact chip design and more robust chip performance.

[0069] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first well region, which is laterally separated from a second well region in a substrate; a shallow trench isolation (STI) structure, which is laterally located between the first well region and the second well region in the substrate; a first implant region of a third dopant type, which is opposite to the first dopant type of the first well region in the substrate and is disposed vertically below the STI structure; and a second implant region of a fourth dopant type, which is opposite to the second dopant type of the second well region in the substrate and is disposed vertically below the STI structure.

[0070] In some embodiments, the semiconductor device also includes: a third injection region of a third dopant type, located in the substrate, arranged above the first injection region and laterally located between the first well region and the STI structure; and a fourth injection region of a fourth dopant type, located in the substrate, arranged above the second injection region and laterally located between the second well region and the STI structure.

[0071] In some embodiments, the first dopant concentration in the first implant region is higher than the third dopant concentration in the third implant region, and wherein the second dopant concentration in the second implant region is higher than the fourth dopant concentration in the fourth implant region.

[0072] In some embodiments, the first dopant type and the second dopant type are the same.

[0073] In some embodiments, the first dopant type and the second dopant type are opposite.

[0074] In some embodiments, the STI structure surrounds each of the first well region and the second well region, wherein the first implant region is laterally disposed between the first well region and a lateral center of the STI structure, and wherein the second implant region is laterally disposed between the second well region and a lateral center of the STI structure.

[0075] In some embodiments, the STI structure is in the shape of an inverted trapezoid.

[0076] In some embodiments, a ratio of a width of the first implant region to a width of the STI structure is in a range of 5 / 100 to 95 / 100, and wherein a ratio of a width of the second implant region to a width of the STI structure is in a range of 5 / 100 to 95 / 100.

[0077] In some embodiments, the semiconductor device further comprises a first CMOS device formed in the first well region and a second CMOS device formed in the second well region, wherein the first CMOS device comprises a first planar MOSFET transistor, and wherein the second CMOS device comprises a second planar MOSFET transistor.

[0078] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first well region, which is laterally separated from a second well region in a substrate; a shallow trench isolation (STI) structure, which is laterally located between the first well region and the second well region in the substrate; a first deep implant region of a first dopant type, which is opposite to the dopant type of the first well region and vertically lower than the STI structure; a second deep implant region of a second dopant type, which is opposite to the dopant type of the second well region and vertically lower than the STI structure; a first shallow implant region of the first dopant type, which is vertically located above the first deep implant region and laterally located between the first well region and the STI structure; and a second shallow implant region of the second dopant type, which is vertically located above the second deep implant region and laterally located between the second well region and the STI structure.

[0079] In some embodiments, the dopant concentration in the first deep implant region is higher than the dopant concentration in the first shallow implant region, and wherein the dopant concentration in the second deep implant region is higher than the dopant concentration in the second shallow implant region.

[0080] In some embodiments, the semiconductor device further includes a first planar CMOS device located in the first well region and a second planar CMOS device located in the second well region.

[0081] In some embodiments, the first dopant type of the first deep implant region and the second dopant type of the second deep implant region are opposite to each other.

[0082] In some embodiments, the first dopant type of the first deep implant region and the second dopant type of the second deep implant region are the same.

[0083] In some embodiments, the STI structure surrounds each of the first well region and the second well region.

[0084] In another aspect of the present disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes: etching a shallow trench isolation (STI) trench in a substrate; forming a first well region and a second well region on both lateral sides of the STI trench in the substrate; forming a first implant region, the first implant region having a first dopant type opposite to the dopant type of the first well region and vertically lower than the STI trench; and forming a second implant region, the second dopant type of the second implant region being opposite to the dopant type of the second well region and vertically lower than the STI trench.

[0085] In some embodiments, the method further includes: after forming the first implant region and the second implant region, filling the STI trench with a dielectric material to form an STI structure.

[0086] In some embodiments, the method further includes: before forming the first implant region and the second implant region, filling the STI trench with a dielectric material to form an STI structure.

[0087] In some embodiments, the method also includes: forming a third injection region of the first dopant type, the third injection region is located above the first injection region and laterally between the first well region in the substrate and the STI trench; and forming a fourth injection region of the second dopant type, the fourth injection region is located above the second injection region and laterally between the second well region in the substrate and the STI trench.

[0088] In some embodiments, the dopant concentration in the first implant region is higher than the dopant concentration in the third implant region, and wherein the dopant concentration in the second implant region is higher than the dopant concentration in the fourth implant region.

[0089] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, include: a first well region laterally separated from a second well region in the substrate; a shallow trench isolation structure, laterally located between the first well region and the second well region in the substrate; a first implant region of a third dopant type opposite to the first dopant type of the first well region in the substrate and disposed vertically below the shallow trench isolation structure; as well as A second implantation region of a fourth dopant type is opposite to the second dopant type of the second well region in the substrate and is disposed vertically below the shallow trench isolation structure.

2. The semiconductor device according to claim 1, further comprising: include: The third implantation region of the third dopant type is located in the substrate, disposed above the first implantation region and laterally located between the first well region and the shallow trench isolation structure; as well as The fourth implantation region of the fourth dopant type is located in the substrate, is disposed above the second implantation region and is laterally located between the second well region and the shallow trench isolation structure.

3. The semiconductor device according to claim 2, in, The first dopant concentration in the first implant region is higher than the third dopant concentration in the third implant region, and wherein the second dopant concentration in the second implant region is higher than the fourth dopant concentration in the fourth implant region.

4. The semiconductor device according to claim 1, in, The shallow trench isolation structure surrounds each of the first well region and the second well region, wherein the first injection region is laterally disposed between the first well region and a lateral center of the shallow trench isolation structure, and wherein the second injection region is laterally disposed between the second well region and the lateral center of the shallow trench isolation structure.

5. The semiconductor device according to claim 1, in, The shallow trench isolation structure is in an inverted trapezoidal shape.

6. A semiconductor device, include: a first well region laterally separated from the second well region in the substrate; a shallow trench isolation structure, laterally located between the first well region and the second well region in the substrate; a first deep implant region of a first dopant type, having a dopant type opposite to that of the first well region and vertically lower than the shallow trench isolation structure; a second deep implant region of a second dopant type, having a dopant type opposite to that of the second well region and vertically lower than the shallow trench isolation structure; a first shallow implant region of the first dopant type, vertically located above the first deep implant region and laterally located between the first well region and the shallow trench isolation structure; as well as The second shallow implant region of the second dopant type is vertically located above the second deep implant region and laterally located between the second well region and the shallow trench isolation structure.

7. The semiconductor device according to claim 6, in, The dopant concentration in the first deep implant region is higher than the dopant concentration in the first shallow implant region, and wherein the dopant concentration in the second deep implant region is higher than the dopant concentration in the second shallow implant region.

8. The semiconductor device according to claim 6, in, The shallow trench isolation structure surrounds each of the first well region and the second well region.

9. A method of manufacturing a semiconductor device, include: etching shallow trench isolation trenches in the substrate; forming a first well region and a second well region on lateral sides of the shallow trench isolation trench in the substrate; forming a first implantation region, wherein a first dopant type of the first implantation region is opposite to a dopant type of the first well region and the first implantation region is vertically lower than the shallow trench isolation trench; as well as A second implantation region is formed, the second implantation region having a second dopant type opposite to the dopant type of the second well region and the second implantation region being vertically lower than the shallow trench isolation trench.

10. The method according to claim 9, further comprising: include: forming a third implant region of the first dopant type, the third implant region being located above the first implant region and laterally between the first well region and the shallow trench isolation trench in the substrate; as well as A fourth implant region of the second dopant type is formed, the fourth implant region being located above the second implant region and laterally between the second well region and the shallow trench isolation trench in the substrate.

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