Formation method of semiconductor device
By forming transistors with opposite conductivity types on the memory area of the static random access memory and performing stress stack annealing, the problem of high minimum supply voltage of the circuit is solved, and the static noise tolerance and write noise tolerance are improved, and the The effect of improving device performance while saving costs and area.
Patent Information
- Application Number
- CN202411204227.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2024-12-10
AI Technical Summary
The circuit supply voltage of the existing static random access memory is relatively large, resulting in insufficient reliability and energy consumption in high and low temperature environments, and the existing methods increase process cost and chip area.
The first transistor and the second transistor with opposite conductivity types are formed on the memory area of the semiconductor device, and a stress stack is formed thereon, and the annealing process is performed to remove stress uniformity and reduce the minimum value of the power supply voltage of the device circuit. Improve static noise tolerance and write noise tolerance.
Without increasing process cost and chip area, the minimum value of the power supply voltage of the device circuit is reduced, the static noise tolerance and write noise tolerance are improved, the working window of the memory device is increased, the failure efficiency is reduced, and the improvement of the improvement of the Stability.
Smart Images
Figure CN119110574A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor device. Background Art
[0002] With the popularization of portable electronic devices and the advancement of process nodes, higher requirements are placed on chip energy consumption, environmental adaptability and anti-interference capabilities. The minimum value of the circuit power supply voltage (Volt Current Condenserminimum, referred to as Vccmin) in static random access memory (Static Random Access Memory, referred to as SRAM) devices is an important parameter for measuring device yield. It represents the minimum normal operating voltage of static random access memory devices. The lower the value, the larger the voltage fluctuation range allowed by the static random access memory, and the more advantages in reliability and energy consumption in high and low temperature environments.
[0003] However, current static random access memories still have shortcomings. Summary of the invention
[0004] The problem solved by the present invention is how to reduce the minimum value of the circuit power supply voltage of the semiconductor device without increasing the process cost and the additional circuit and chip area, and improve the static noise tolerance and write noise tolerance of the storage device to reduce the failure rate of the device.
[0005] To solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, the substrate comprising a storage area, the storage area having a first transistor and a second transistor, the conductivity type of a channel of the first transistor and the channel of the second transistor being opposite; forming a stress stack on the first transistor and the second transistor; performing annealing on the stress stack located on the first transistor and the second transistor; and removing the stress stack after the annealing.
[0006] Optionally, the step of forming a stress stack on the first transistor and the second transistor includes: forming an initial stress stack on the substrate, on the first transistor and on the second transistor; forming a mask layer on the initial stress stack, wherein the mask layer exposes a portion of the initial stress stack; using the mask layer as a mask, etching the initial stress stack to form stress stacks located on the first transistor and the second transistor.
[0007] Optionally, the stress stack includes: a buffer layer and a stress material layer located on the buffer layer.
[0008] Optionally, the material of the buffer layer includes silicon oxide; and the material of the stress material layer includes silicon nitride.
[0009] Optionally, the thickness of the buffer layer ranges from 40 angstroms to 100 angstroms; and the thickness of the stress material layer ranges from 250 angstroms to 300 angstroms.
[0010] Optionally, the annealing process is spike annealing.
[0011] Optionally, the temperature range of the annealing treatment is: 1000° C. to 1060° C.; the time range of the annealing treatment is: 5 seconds to 30 seconds.
[0012] Optionally, in the process of removing the stress stack, the stress stack located on the first transistor and the second transistor are removed simultaneously.
[0013] Optionally, the stress stack is located on an N-type pull-down transistor in the storage area, an N-type transfer transistor in the storage area, and a P-type pull-up transistor in the storage area.
[0014] Optionally, the storage area includes a first well area and a second well area, the first transistor is located on the first well area, the second transistor is located on the second well area, and the first well area and the second well area have opposite conductivity types.
[0015] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0016] In the method for forming a semiconductor device of the technical solution of the present invention, stress stacks are formed on both the first transistor and the second transistor in the storage area, and the conductivity types of the channel of the first transistor and the channel of the second transistor are opposite, that is, stress stacks are formed on both the NMOS and the PMOS in the storage area. Annealing treatment is performed on the first transistor and the second transistor with the stress stack formed on the surface, so that stress is applied to both the first transistor and the second transistor, thereby reducing the minimum value of the device circuit power supply voltage. Compared with redesigning the circuit structure or adding additional circuits and chip area to reduce the minimum circuit power supply voltage of the first transistor and the second transistor, this solution saves process cost and production time, and makes the stress on the first transistor and the second transistor in the storage area uniform, and there is no stress isolation between the first transistor and the second transistor, which reduces the probability of mismatch of the device in the storage area, thereby saving process cost and reducing the minimum circuit power supply voltage of the device; and, the first transistor and the second transistor with the stress stack formed on the surface are both annealed, so that the stress on the first transistor and the second transistor in the storage area is uniform, which improves the static noise tolerance and write noise tolerance of the storage device, increases the working window of the storage device, and reduces the failure rate of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figures 1 to 3 is a schematic cross-sectional structural diagram of each step of a method for forming a semiconductor device according to an embodiment of the present invention;
[0018] Figure 4 is a test characterization diagram of the minimum value of the circuit power supply voltage of the semiconductor device of the embodiment of the present invention;
[0019] Figure 5 is a test characterization diagram of the saturation current of the semiconductor device according to an embodiment of the present invention;
[0020] Figure 6 is a test characterization diagram of the minimum value of the circuit power supply voltage of the semiconductor device of the embodiment of the present invention;
[0021] Figure 7 is a test characterization diagram of the static noise margin and the write noise margin of the semiconductor device according to the embodiment of the present invention;
[0022] Figure 8 This is a schematic diagram of the butterfly line. DETAILED DESCRIPTION
[0023] As can be seen from the background art, the static random access memory in the prior art still has the problem that the minimum value of the circuit power supply voltage is relatively large.
[0024] The threshold voltage of SRAM has a slower change trend as the size of SRAM decreases, which results in a smaller voltage window for SRAM operation. The minimum value of the circuit power supply voltage in SRAM is an important parameter for measuring device yield, indicating the minimum normal operating voltage of SRAM devices. The lower the value, the larger the voltage fluctuation range allowed by SRAM, and the more advantages in terms of reliability and energy consumption in high and low temperature environments.
[0025] In one embodiment, a peripheral auxiliary circuit is introduced to reduce the minimum value of the circuit power supply voltage of the static random access memory and improve the overall performance of the static random access memory. However, the peripheral auxiliary circuit will increase the area of the static random access memory and reduce the effective density of the static random access memory.
[0026] In another embodiment, the circuit structure is redesigned to separate the read operation from the write operation, so as to reduce the minimum value of the circuit power supply voltage of the static random access memory and improve the overall performance of the static random access memory. However, redesigning the circuit structure requires higher costs and consumes a lot of manpower and time.
[0027] In another embodiment, the circuit layout (GeometyData Standard, GDS for short) of the bit unit of the static random access memory is revised to reduce the minimum value of the circuit power supply voltage of the static random access memory and improve the overall performance of the static random access memory. However, the circuit layout revision requires re-modifying the mask and adjusting the process window, which is time-consuming and costly.
[0028] To solve the technical problem, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, the substrate comprising a storage area, the storage area having a first transistor and a second transistor, the channel of the first transistor and the channel of the second transistor having opposite conductivity types; forming a stress stack on the first transistor and the second transistor; annealing the stress stack located on the first transistor and the second transistor; and removing the stress stack after the annealing.
[0029] In the method for forming a semiconductor device of the technical solution of the present invention, stress stacks are formed on both the first transistor and the second transistor in the storage area, and the conductivity types of the channel of the first transistor and the channel of the second transistor are opposite, that is, stress stacks are formed on both the NMOS and PMOS in the storage area. The first transistor and the second transistor with the stress stack formed on the surface are both annealed, so that the stress on the first transistor and the second transistor in the storage area is uniform, there is no stress isolation between the first transistor and the second transistor, and the probability of mismatch of the device in the storage area is reduced, thereby reducing the minimum value of the power supply voltage of the semiconductor device circuit; and the first transistor and the second transistor with the stress stack formed on the surface are both annealed, so that the stress on the first transistor and the second transistor in the storage area is uniform, the static noise tolerance and write noise tolerance of the storage device are improved, the working window of the storage device is increased, and the failure rate of the storage device is reduced; in addition, the scheme does not require major changes and does not require the addition of additional circuits and chip areas, and achieves device performance improvement while saving process costs.
[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0031] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a storage area I, wherein the storage area I has a first transistor 101 and a second transistor 102, wherein the conductivity types of a channel of the first transistor 101 and the channel of the second transistor 102 are opposite.
[0032] The substrate 100 is one of single crystal silicon, polycrystalline silicon, amorphous silicon and silicon on insulator; the substrate 100 may also be a silicon substrate, a germanium substrate, a germanium silicon substrate or a gallium arsenide substrate. In some embodiments of the present invention, the substrate 100 is a silicon substrate.
[0033] The storage area I of the substrate 100 includes a first well region and a second well region. The first transistor 101 is located on the first well region, and the second transistor 102 is located on the second well region. Specifically, in some embodiments of the present invention, the first well region and the second well region have opposite conductivity types. The first well region is a P-type well region, and the second well region is an N-type well region.
[0034] In some other embodiments of the present invention, the first well region is an N-type well region, and the second well region is a P-type well region.
[0035] In some embodiments of the present invention, the channel of the first transistor 101 is an N-type channel, and the first transistor 101 is an N-type transistor; the channel of the second transistor 102 is a P-type channel, and the second transistor 102 is a P-type transistor.
[0036] In some embodiments of the present invention, the first transistor 101 includes: an N-type pull-down transistor (Negative-type Pull Down, PPU for short, NPD for short) and an N-type pass transistor (Negative-type Pass Gate, NPG for short); the second transistor 102 includes: a P-type pull-up transistor (Positive-type Pull Up, PPU for short).
[0037] In some other embodiments of the present invention, the channel of the first transistor 101 is a P-type channel, and the first transistor 101 is a P-type transistor; the channel of the second transistor 102 is an N-type channel, and the second transistor 102 is an N-type transistor.
[0038] The substrate 100 further includes: a peripheral circuit region; a third transistor (not shown) is disposed on the peripheral circuit region. Specifically, in some embodiments of the present invention, the channel of the third transistor is an N-type channel, and the third transistor is an N-type transistor.
[0039] Please refer to Figure 2 , a stress stack 103 is formed on the first transistor 101 and the second transistor 102 .
[0040] The step of forming a stress stack 103 on the first transistor 101 and the second transistor 102 includes: forming an initial stress stack (not shown) on the substrate 100, on the first transistor 101 and on the second transistor 102; forming a mask layer on the initial stress stack, wherein the mask layer exposes a portion of the initial stress stack; and etching the initial stress stack using the mask layer as a mask to form the stress stack 103 located on the first transistor 101 and the second transistor 102.
[0041] The stress stack 103 provides a structural basis for introducing stress into the first transistor 101 and the second transistor 102. The purpose of etching the initial stress stack to form the stress stack 103 on the first transistor 101 and the second transistor 102 is to retain the stress stack 103 on the first transistor 101 and the second transistor 102 located in the storage area I, and provide a structural basis for subsequently introducing stress into the first transistor 101 and the second transistor 102.
[0042] The initial stress stack comprises: a buffer material layer and an initial stress layer located on the buffer material layer.
[0043] The process of forming the buffer material layer and the initial stress layer includes a deposition process, which includes an atomic layer deposition process, a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, a sputtering deposition process, an ion beam deposition process or an ion beam assisted deposition process.
[0044] Stress Memorization Technique (SMT) is a stress engineering technology that has emerged below the 90nm technology node and aims to improve the speed of transistor devices. The characteristics of stress memory technology are that it can significantly accelerate the electron mobility of transistor devices by means of tensile stress, thereby increasing the driving current of transistor devices; and after the process flow is completed, stress memory technology will not cause any structural changes to transistor devices.
[0045] Specifically, in some embodiments of the present invention, the stress stack 103 formed on the first transistor 101 and the second transistor 102 does not directly introduce stress to the channel of the first transistor 101 and the channel of the second transistor 102, but conducts the stress to the source and drain of the first transistor 101 and the gate of the first transistor 101, the source and drain of the second transistor 102, and the gate of the second transistor 102 through high-temperature annealing, and transmits the stress to the channel of the first transistor 101 and the channel of the second transistor 102 through them, and the stress will form a memory effect and remain, thereby accelerating the electron mobility of the transistor device and improving the driving current of the transistor device.
[0046] The stress stack 103 includes: a buffer layer and a stress material layer located on the buffer layer. Specifically, in some embodiments of the present invention, the material of the buffer layer includes silicon oxide; the material of the stress material layer includes silicon nitride. The thickness of the buffer layer ranges from 40 angstroms to 100 angstroms; the thickness of the stress material layer ranges from 250 angstroms to 300 angstroms.
[0047] If the thickness of the stress material layer is too large, the degree of wafer warpage (bow value) will increase after annealing, affecting the uniformity of subsequent processes; if the thickness of the stress material layer is too small, insufficient stress will result, and the speed of the semiconductor device cannot be effectively improved.
[0048] After forming the stress stack 103 , an annealing process is performed on the stress stack 103 located on the first transistor 101 and the second transistor 102 .
[0049] Specifically, in some embodiments of the present invention, the annealing treatment is spike annealing. The temperature range of the annealing treatment is: 1000° C. to 1060° C.; the time range of the annealing treatment is: 5 seconds to 30 seconds.
[0050] The purpose of the annealing process is to introduce stress into the first transistor 101 and the second transistor 102 .
[0051] In stress memory technology, the high temperature annealing process is very critical, because nano-scale devices are very sensitive to heat budget, so the high temperature annealing process must adopt an annealing technology with very short process time and precise control of process time.
[0052] The spike annealing focuses on the rapid heating / cooling process. The spike annealing has a very short residence time at the high temperature point, and the main function of the spike annealing at the high temperature point is to activate the doping elements. In practical applications, the wafer is rapidly heated from a certain stable standby temperature point and immediately cooled down after reaching the target temperature point. Since the maintenance time at the target temperature point (i.e., the peak temperature point) is very short, the annealing process can maximize the degree of impurity activation and minimize the degree of impurity diffusion, and at the same time has good defect annealing repair characteristics, resulting in a higher joint quality and lower leakage current.
[0053] Please refer to Figure 3 After the annealing process, the stress stack 103 is removed.
[0054] In the process of removing the stress stack 103 , the stress stack 103 located on the first transistor 101 and the second transistor 102 are removed simultaneously.
[0055] In some embodiments of the present invention, phosphoric acid is used to remove the stress stack 103. After removing the stress stack 103, the surface of the semiconductor device is no longer covered with the stress stack, which does not affect the subsequent process; and after the process is completed, the stress memory technology will not cause any structural changes to the transistor device, which does not affect the subsequent process.
[0056] Please refer to Figure 4 , Figure 4 1 is a comparative characterization diagram of the minimum circuit power supply voltage of the semiconductor device of the embodiment of the present invention and the minimum circuit power supply voltage of the baseline corner of a memory having a speed similar to that of the semiconductor device of the embodiment of the present invention. Figure 4 In the case of a 320K semiconductor device, the capacity is 320K.
[0057] Figure 4 The horizontal axis represents the minimum value of the circuit supply voltage (Volt Current Condenserminimum, referred to as Vccmin). Figure 4 The vertical axis represents the yield of the device. Figure 4 The middle broken line 1 reflects the relationship between the minimum current supply voltage and the yield of the semiconductor device of the embodiment of the present invention; Figure 4 The middle broken line 2 reflects the relationship between the minimum circuit power supply voltage and the yield of the baseline corner of the memory having a speed similar to that of the semiconductor device in the embodiment of the present invention.
[0058] from Figure 4 It can be seen that compared with the minimum circuit power supply voltage of the baseline corner of the memory with a speed similar to that of the semiconductor device in the embodiment of the present invention, the minimum circuit power supply voltage of the semiconductor device in the embodiment of the present invention is reduced by 37 millivolts. That is, under the condition of ensuring the yield of the semiconductor device, the minimum circuit power supply voltage of the semiconductor device obtained by annealing the stress stack 103 covering the first transistor 101 and the second transistor 102 is reduced to a certain extent.
[0059] Please refer to Figure 5 , Figure 5 It is a comparative characterization diagram of the saturation current of the semiconductor device according to the embodiment of the present invention and the saturation current of the baseline corner (Baseline Corner) of a memory having a speed similar to that of the semiconductor device according to the embodiment of the present invention.
[0060] Figure 5 The horizontal axis represents the saturation current of the N-type transfer transistor, Figure 5 The vertical axis represents the saturation current of the P-type pull-up transistor. Figure 5 The midpoint A and the point B reflect the saturation current of the semiconductor device of the embodiment of the present invention; Figure 5The midpoint C reflects the saturation current of the baseline corner of a memory having a speed similar to that of the semiconductor device of the embodiment of the present invention.
[0061] The saturation current is the maximum current flowing between the source and the drain when the gate voltage is constant. The magnitude of the saturation current is positively correlated with the excellence of the transistor performance.
[0062] from Figure 5 It can be concluded that the saturation current of the baseline corner of the memory with a speed similar to that of the semiconductor device in the embodiment of the present invention is similar to the saturation current of the semiconductor device in the embodiment of the present invention. That is, under the premise that the minimum value of the circuit power supply voltage of the semiconductor device decreases to a certain extent, the saturation current of the semiconductor device in the embodiment of the present invention does not decrease significantly, and the maximum current between the source / drain of the semiconductor device in the present invention does not decrease significantly.
[0063] Please refer to Figure 6 , Figure 6 1 is a comparative characterization diagram of the minimum circuit power supply voltage of the semiconductor device of the embodiment of the present invention and the minimum circuit power supply voltage of the baseline corner of a memory having a speed similar to that of the semiconductor device of the embodiment of the present invention. Figure 6 In the test, the capacity of the semiconductor device is 6.4M.
[0064] Figure 6 The horizontal axis represents the minimum value of the circuit supply voltage. Figure 6 The vertical axis represents the yield of the device. Figure 6 The middle broken line 3 reflects the relationship between the minimum current supply voltage and the yield of the semiconductor device of the embodiment of the present invention; Figure 6 The middle broken line 4 reflects the relationship between the minimum circuit power supply voltage and the yield of the baseline corner of the memory having a speed similar to that of the semiconductor device in the embodiment of the present invention.
[0065] from Figure 6 It can be seen that compared with the minimum circuit power supply voltage of the baseline corner of the memory with a speed similar to that of the semiconductor device in the embodiment of the present invention, the minimum circuit power supply voltage of the semiconductor device in the embodiment of the present invention is reduced by 37 millivolts to 47 millivolts. That is, under the condition of ensuring the yield of the semiconductor device, the minimum circuit power supply voltage of the semiconductor device obtained by annealing the stress stack 103 covering the first transistor 101 and the second transistor 102 is reduced to a certain extent.
[0066] Please refer to Figure 7 , Figure 7It is a comparative characterization diagram of the static noise margin and the write noise margin of the semiconductor device according to the embodiment of the present invention and the static noise margin and the write noise margin of the baseline corner (Baseline Corner) of a memory having a speed similar to that of the semiconductor device according to the embodiment of the present invention.
[0067] Figure 7 The horizontal axis is the static noise margin (SNM). Figure 7 The vertical axis is the write noise margin (WM). Figure 7 The middle line 5 shows the relationship between the static noise margin and the write noise margin of the semiconductor device of the embodiment of the present invention. Figure 7 The middle line 6 shows the relationship between the static noise margin and the write noise margin of the baseline corner of a memory having a speed similar to that of the semiconductor device of the embodiment of the present invention.
[0068] Please refer to Figure 8 The butterfly curve is an important indicator that can reflect the stability of static random access memory. To be precise, it is the side length of the largest square inscribed in the butterfly curve, which we call static noise margin (SNM for short). The larger this value is, the more stable the static random access memory is, and the less likely the stored signal is to be reversed.
[0069] from Figure 7 It can be seen that, compared with the baseline corner of a memory having a speed similar to that of the semiconductor device of the embodiment of the present invention, the static noise margin and write noise margin of the semiconductor device of the embodiment of the present invention are improved by 15%. That is, under the premise that the minimum value of the circuit power supply voltage of the semiconductor device obtained by annealing the stress stack 103 covering the first transistor 101 and the second transistor 102 is reduced to a certain extent, the static noise margin and write noise margin of the semiconductor device of the embodiment of the present invention are improved, so that the process window is enlarged and the failure rate of the semiconductor device is reduced.
[0070] In summary, the technical solution of the present invention forms stress stacks on the first transistor and the second transistor of the storage area with opposite channel conductivity types, and performs annealing treatment on the first transistor and the second transistor with the stress stack formed on the surface, so that the stress on the first transistor and the second transistor on the storage area is uniform, and there is no stress isolation between the first transistor and the second transistor, which reduces the probability of mismatching of the device on the storage area, thereby reducing the minimum value of the device circuit power supply voltage; and the stress on the first transistor and the second transistor on the storage area is uniform, and on the premise of reducing the minimum value of the semiconductor device circuit power supply voltage, the static noise tolerance and write noise tolerance of the storage device are improved, so that the working window of the storage device is increased, the failure rate of the storage device is reduced, and the stability of the semiconductor device is improved; in addition, the solution does not require major changes and does not require the addition of additional circuits and chip areas, and achieves the improvement of device performance while saving process cost and time; thirdly, the stress memory technology will not cause any structural changes to the transistor device and will not affect the subsequent process flow; finally, the solution of the present invention is suitable for various static random access memories and has a wide range of applications.
[0071] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a storage area, the storage area having a first transistor and a second transistor, the conductivity type of a channel of the first transistor and the conductivity type of a channel of the second transistor being opposite; forming a stress stack on the first transistor and the second transistor; performing an annealing process on the stress stack located on the first transistor and the second transistor; After the annealing process, the stress stack is removed.
2. The method for forming a semiconductor device according to claim 1, wherein: The step of forming a stress stack on the first transistor and the second transistor comprises: forming an initial stress stack on the substrate, on the first transistor, and on the second transistor; forming a mask layer on the initial stress stack, wherein the mask layer exposes a portion of the initial stress stack; The initial stress stack is etched using the mask layer as a mask to form stress stacks located on the first transistor and the second transistor.
3. The method for forming a semiconductor device according to claim 1, wherein: The stress stack includes a buffer layer and a stress material layer located on the buffer layer.
4. The method for forming a semiconductor device according to claim 3, wherein: The material of the buffer layer includes silicon oxide; the material of the stress material layer includes silicon nitride.
5. The method for forming a semiconductor device according to claim 4, wherein: The thickness of the buffer layer ranges from 40 angstroms to 100 angstroms; the thickness of the stress material layer ranges from 250 angstroms to 300 angstroms.
6. The method for forming a semiconductor device according to claim 1, wherein: The annealing process is spike annealing.
7. The method for forming a semiconductor device according to claim 6, wherein: The temperature range of the annealing treatment is: 1000° C. to 1060° C.; the time range of the annealing treatment is: 5 seconds to 30 seconds.
8. The method for forming a semiconductor device according to claim 1, wherein: In the process of removing the stress stack, the stress stacks located on the first transistor and the second transistor are removed simultaneously.
9. The method for forming a semiconductor device according to claim 1, wherein: The stress stack is located on the N-type pull-down transistor of the storage area, the N-type pass transistor of the storage area, and the P-type pull-up transistor of the storage area.
10. The method for forming a semiconductor device according to claim 1, wherein: The storage area includes a first well area and a second well area, the first transistor is located on the first well area, the second transistor is located on the second well area, and the first well area and the second well area have opposite conductivity types.