Storage unit, memory and preparation method thereof

Abstract

The present disclosure relates to a memory cell, a memory and a method for preparing the same. The memory cell comprises: one or more floating bodies, an epitaxial layer, a word line and a first insulating layer. The epitaxial layer is located on two opposite side walls of any floating body in a first direction. The epitaxial layer comprises: a channel region in contact with the corresponding side wall surface of the floating body, and a source extension region and a drain extension region located on opposite sides of the channel region in a second direction; the second direction intersects with the first direction. The word line is located on the side of the channel region away from the floating body. The first insulating layer is located between the word line and the channel region. The present disclosure can improve the sensing margin and data retention function of the memory cell, thereby improving the storage performance of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a storage unit, a memory and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. The memory cell may adopt a 1T1C architecture, that is, it includes a transistor and a capacitor.

[0003] Currently, with the increasing demand for memory storage capacity, memory cells are beginning to be arranged in three dimensions. In addition, in order to overcome the scalability issues and process complexity of DRAM memory cells using a 1T1C architecture, the latest technology has proposed and studied the application of the floating body effect in DRAM. For example, a memory cell can adopt a 1T0C (i.e., including one transistor and zero capacitors) architecture, and the mainstream transistor in this 1T0C architecture is a floating body transistor (FBC), which can be applied to 3D-DRAM.

[0004] However, floating-body transistors also have some problems, such as having lower body potential and lower sensing margin, which easily lead to shorter read time after programming. Summary of the Invention

[0005] Based on this, the embodiments of the present disclosure provide a storage unit, a memory and a method for manufacturing the same, which are beneficial to improving the sensing margin and data retention function of the storage unit, thereby improving the storage performance of the memory.

[0006] In one aspect, embodiments of the present disclosure provide a memory cell comprising: one or more floating bodies, an epitaxial layer, a word line, and a first insulating layer. The epitaxial layer is located on two opposing sidewalls of any floating body in a first direction. The epitaxial layer includes: a channel region contacting the corresponding sidewall surface of the floating body, and a source extension region and a drain extension region located on opposite sides of the channel region in a second direction; the second direction intersects the first direction. The word line is located on a side of the channel region facing away from the floating body. The first insulating layer is located between the word line and the channel region.

[0007] According to some embodiments, the memory cell further comprises: a second insulating layer, a source line, and a bit line. The second insulating layer is located on two opposite side walls of any floating body in the second direction. The second insulating layer comprises: a first sub-insulating layer located between opposing source extension regions, and a second sub-insulating layer located between opposing drain extension regions. The source line is located on a side wall of the first sub-insulating layer facing away from the floating body, and is in contact with and connected to the source extension region. The bit line is located on a side wall of the second sub-insulating layer facing away from the floating body, and is in contact with and connected to the drain extension region.

[0008] According to some embodiments, a sidewall of the source line facing away from the first sub-insulating layer is flush with a sidewall of the source extension region facing away from the channel region. A sidewall of the bit line facing away from the second sub-insulating layer is flush with a sidewall of the drain extension region facing away from the channel region.

[0009] According to some embodiments, the memory cell further comprises a support structure. The support structure is located on two opposing sides of the word line in the second direction. The support structure comprises a first support layer located on the sidewall of the source extension region facing away from the source line, and a second support layer located on the sidewall of the drain extension region facing away from the bit line. The sidewall of the first support layer facing away from the word line is flush with the sidewall of the source line facing away from the first sub-insulating layer. The sidewall of the second support layer facing away from the word line is flush with the sidewall of the bit line facing away from the second sub-insulating layer.

[0010] According to some embodiments, the floating body includes a silicon germanium layer, and the epitaxial layer includes a silicon epitaxial layer.

[0011] According to some embodiments, the floating body and the epitaxial layer have the same size in a third direction. The third direction is perpendicular to an intersection plane of the first direction and the second direction.

[0012] According to some embodiments, there are multiple floating bodies. The memory cell further includes: multiple third insulating layers alternately stacked with the multiple floating bodies in a third direction. The third direction is perpendicular to the intersecting plane of the first and second directions, and the multiple floating bodies are arranged in a row in the third direction. A word line is located on a side of a column of channel regions facing away from the floating bodies.

[0013] On the other hand, an embodiment of the present disclosure further provides a memory, comprising: a substrate and one or more memory units arranged on the substrate and as described in any of the above embodiments.

[0014] On the other hand, an embodiment of the present disclosure further provides a method for preparing a memory, comprising the following steps.

[0015] A substrate is provided, and one or more initial floating bodies are formed on the substrate.

[0016] An epitaxial layer is grown on two opposite side walls of any initial floating body in the first direction.

[0017] A sacrificial word line is formed on a sidewall of the epitaxial layer away from the initial floating body.

[0018] Ion implantation is performed on the epitaxial layer exposed on opposite sides of the sacrificial word line in the second direction to form a source extension region and a drain extension region; wherein the second direction intersects with the first direction, and the region of the epitaxial layer between the source extension region and the drain extension region constitutes a channel region.

[0019] The two side walls of the initial floating body opposite to each other in the second direction are etched back to obtain the floating body.

[0020] The sacrificial word line is removed, and a first insulating layer and a word line are sequentially formed in the removed area of ​​the sacrificial word line.

[0021] According to some embodiments, the method for preparing the memory further includes the following steps.

[0022] A second insulating layer is formed on two opposite sidewalls of any floating body in the second direction. The second insulating layer includes a first sub-insulating layer located between opposite source extension regions and a second sub-insulating layer located between opposite drain extension regions.

[0023] A source line is formed on the side wall of the first sub-insulating layer away from the floating body and is in contact with the source extension region.

[0024] A bit line is formed on the side wall of the second sub-insulating layer away from the floating body and is in contact with the drain extension region.

[0025] According to some embodiments, before removing the sacrificial word line and sequentially forming a first insulating layer and a word line in the removed region of the sacrificial word line, the memory manufacturing method further includes: forming a support structure on two opposite sidewalls of the sacrificial word line in the second direction.

[0026] According to some embodiments, the material of the sacrificial word line comprises oxide. Removing the sacrificial word line and sequentially forming a first insulating layer and a word line in the region where the sacrificial word line was removed further comprises: etching away a portion of the oxide so that the remaining oxide constitutes the first insulating layer; and forming the word line on a surface of the first insulating layer away from the channel region.

[0027] According to some embodiments, there are multiple initial floating bodies. The step of forming multiple initial floating bodies on the substrate includes the following steps.

[0028] A plurality of sacrificial material layers and a plurality of compound semiconductor layers are alternately stacked and formed on a substrate.

[0029] Two side walls of each sacrificial material layer opposite to each other in the second direction are etched back to form a sacrificial pattern layer.

[0030] A temporary support structure is formed to cover the sidewalls of each sacrificial pattern layer and the sidewalls of each compound semiconductor layer.

[0031] Each sacrificial pattern layer is removed, and a third insulating layer is formed in the removed region of each sacrificial pattern layer.

[0032] In this manner, the compound semiconductor layer constitutes an initial floating body.

[0033] According to some embodiments, forming the third insulating layer in the removed regions of each sacrificial pattern layer includes: sequentially depositing a silicon nitride layer and a silicon oxide layer in the removed regions of each sacrificial pattern layer.

[0034] According to some embodiments, before etching back the two opposite side walls of the initial floating body in the second direction to obtain the floating body, the memory preparation method further includes: etching back the two opposite side walls of the temporary support structure in the second direction until the two opposite side walls of the initial floating body in the second direction are exposed.

[0035] According to some embodiments, the substrate comprises a silicon substrate, the sacrificial material layer comprises a silicon layer, and the method of forming a plurality of alternating sacrificial material layers and a plurality of compound semiconductor layers on the substrate further comprises the following steps.

[0036] A first compound semiconductor layer having a doping concentration higher than that of other layers is formed on the substrate; and a first sacrificial material layer is formed on the surface of the first compound semiconductor layer facing away from the substrate.

[0037] After forming each sacrificial material layer and each compound semiconductor layer, the first compound semiconductor layer is etched, and an isolation layer is formed between the first sacrificial material layer and the substrate simultaneously.

[0038] According to some embodiments, the compound semiconductor layer includes a germanium silicon layer; wherein the molar percentage of the germanium element in the first compound semiconductor layer ranges from 40% to 85%; the molar percentage of the germanium element in the compound semiconductor layers other than the first compound semiconductor layer ranges from 15% to 30%.

[0039] The embodiments of the present disclosure may or may have at least the following advantages:

[0040] In the embodiment of the present disclosure, an epitaxial layer can be selectively grown on both side walls of any floating body to obtain a channel region and a source extension region and a drain extension region respectively using the epitaxial layer. In this way, the embodiment of the present disclosure can selectively control the energy difference (i.e., the electron volt Ev difference) between the epitaxial layer and the floating body to facilitate the acquisition of a deeper hole well, thereby increasing the amount of hole accumulation in the floating body. Moreover, in a memory cell in which multiple floating bodies are stacked along a third direction (e.g., the Z direction), the implementation of the multiple floating body stacking process is also conducive to reducing defects in the floating body film formation process, thereby correspondingly increasing the turn-on current I of the transistor in which the floating body is located. ONTherefore, the embodiments of the present disclosure can effectively improve the sensing margin and data retention function of the storage unit, thereby improving the storage performance of the memory.

[0041] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 A schematic structural diagram of a storage unit provided in some embodiments;

[0044] Figure 2 A schematic flow chart of a method for preparing a memory provided in some embodiments;

[0045] Figure 3 A schematic flow chart of another method for preparing a memory provided in some embodiments;

[0046] Figure 4 for Figure 2 and Figure 3 A schematic flow chart of step S100 in the preparation method shown;

[0047] Figure 5 for Figure 4 A schematic flow chart of a step S110 in step S100 is shown;

[0048] Figure 6 A schematic structural diagram of a structure obtained after forming multiple initial sacrificial material layers and multiple initial compound semiconductor layers, provided in some embodiments;

[0049] Figure 7 A schematic structural diagram of a structure obtained after forming multiple stacked structures provided in some embodiments;

[0050] Figure 8 A schematic structural diagram of a structure obtained after forming an isolation layer provided in some embodiments;

[0051] Figure 9 A schematic structural diagram of a structure obtained after forming a temporary support structure provided in some embodiments;

[0052] Figure 10 A schematic structural diagram of a structure obtained after forming a first trench provided in some embodiments;

[0053] Figure 11 A schematic structural diagram of a structure obtained after forming a third nitride layer and a second oxide layer in a first trench provided in some embodiments;

[0054] Figure 12 A schematic structural diagram of a structure obtained after forming an epitaxial layer provided in some embodiments;

[0055] Figure 13 A schematic structural diagram of a structure obtained after forming a dummy word line provided in some embodiments;

[0056] Figure 14 A schematic structural diagram of a structure obtained after forming a source extension region and a drain extension region provided in some embodiments;

[0057] Figure 15 A schematic structural diagram of a structure obtained after forming a peripheral insulating layer provided in some embodiments;

[0058] Figure 16 is a schematic structural diagram of a structure obtained after forming a second trench provided in some embodiments;

[0059] Figure 17 A schematic structural diagram of a structure obtained after forming a floating body provided in some embodiments;

[0060] Figure 18 for Figure 17 The structure shown is a cross-sectional schematic diagram along the AA direction in the XZ plane;

[0061] Figure 19 A schematic structural diagram of a structure obtained after forming a source line and a bit line provided in some embodiments;

[0062] Figure 20 A schematic structural diagram of a memory cell after forming a source line and a bit line provided in some embodiments;

[0063] Figure 21 for Figure 20 The structure shown is a cross-sectional schematic diagram along the AA direction in the XZ plane;

[0064] Figure 22 A schematic structural diagram of a structure obtained after forming a word line provided in some embodiments;

[0065] Figure 23 A schematic diagram of a structure of a memory cell after word lines are formed, provided in some embodiments;

[0066] Figure 24 is a schematic structural diagram of a storage unit provided in some embodiments in the YZ plane;

[0067] Figure 25 A schematic diagram of the distribution of external electrical signals of a storage unit provided in some embodiments.

[0068] Description of reference numerals:

[0069] 1-substrate, 2-memory cell, 2A-stacked structure, 21-floating body, 21A-initial floating body, 22-epitaxial layer, 221-channel region, 222-source extension region, 223-drain extension region, WL-word line, DWL-sacrificial word line, 23-first insulating layer, 24-second insulating layer, 241-first sub-insulating layer, 242-second sub-insulating layer, SL-source line, BL-bit line, 25-support structure, 251-first supporting layer, 252-second supporting layer, 26-third insulating layer, 3-isolation layer , L1A-initial sacrificial material layer, L2A-initial compound semiconductor layer, L1B-sacrificial material layer, L2-compound semiconductor layer, L1-sacrificial pattern layer, L21-first compound semiconductor layer, 41-first oxide layer, 42-first nitride layer, 43-second nitride layer, 44-third nitride layer, 45-second oxide layer, 46-fourth nitride layer, 47-third oxide layer, G1-first trench, G2-second trench, G3-third trench, 5-isolation structure, 5A-temporary support structure. DETAILED DESCRIPTION

[0070] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0071] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0072] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0073] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0074] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the present disclosure.

[0075] The present disclosure provides a memory cell and memory that facilitates stacking and expansion of ITOC architecture memory cells and reduces process complexity. Furthermore, the memory cell and memory provided by the present disclosure can have a high sensing margin and data retention capability, thereby improving the memory's storage performance.

[0076] See also Figure 1In the memory cell provided in the embodiment of the present disclosure, the memory cell 2 includes: one or more floating bodies 21, an epitaxial layer 22, a word line WL, and a first insulating layer 23. The epitaxial layer 22 is located on two opposite side walls of any floating body 21 in a first direction (e.g., the Y direction). The epitaxial layer 22 includes: a channel region 221 in contact with the corresponding sidewall surface of the floating body 21, and a source extension region 222 and a drain extension region 223 located on opposite sides of the channel region 221 in a second direction (e.g., the X direction); the second direction (e.g., the X direction) intersects with the first direction (e.g., the Y direction), and can be, for example, orthogonal. The word line WL is located on the side of the channel region 221 facing away from the floating body 21. The first insulating layer 23 is located between the word line WL and the channel region 221.

[0077] For example, the floating body 21 includes a silicon germanium layer. For example, the floating body 21 is a P-type lightly doped silicon germanium layer.

[0078] In some examples, the molar percentage of germanium in the floating body 21 ranges from 15% to 30%. For example, the molar percentage of germanium in the floating body 21 can be 15%, 18%, 20%, 25%, 28%, or 30%.

[0079] In some examples, the floating body 21 is a P-type lightly doped silicon germanium layer, and the doping concentration of the P-type doping element in the floating body 21 can be 1E17 / cm 3 ~9E18 / cm 3 The P-type doping elements include, for example, Group III elements, such as boron.

[0080] For example, the epitaxial layer 22 includes a silicon epitaxial layer. The source extension region 222 and the drain extension region 223 in the epitaxial layer 22 may be, for example, N-type doped silicon layers formed using a lightly doped drain (LDD) process.

[0081] Here, the lightly doped drain process refers to an ion implantation process using low energy and low current. The lightly doped drain process can effectively suppress the hot electron effect, thereby improving the reliability of the memory cell 2.

[0082] For example, the source extension region 222 and the drain extension region 223 are N-type doped silicon layers. The doping concentration of the N-type doping element in the source extension region 222 and the drain extension region 223 may be 1E18 / cm 3 ~8E19 / cm 3 N-type doping elements include, for example, Group V elements, such as phosphorus or arsenic.

[0083] For example, the word line WL includes but is not limited to a metal word line, and the word line WL can be formed of metal tungsten or metal copper.

[0084] Illustratively, the first insulating layer 23 includes but is not limited to a gate oxide layer.

[0085] In some embodiments, please refer to Figure 1 The memory cell 2 further includes: a second insulating layer 24, a source line SL, and a bit line BL. The second insulating layer 24 is located on two opposite side walls of any floating body 21 in the second direction (e.g., the X direction). The second insulating layer 24 includes: a first sub-insulating layer 241 located between opposing source extension regions 222, and a second sub-insulating layer 242 located between opposing drain extension regions 223. The source line SL is located on the side wall of the first sub-insulating layer 241 facing away from the floating body 21, and is in contact with and connected to the source extension region 222. The bit line BL is located on the side wall of the second sub-insulating layer 242 facing away from the floating body 21, and is in contact with and connected to the drain extension region 223.

[0086] For example, the source line SL and the bit line BL can be formed of the same material. In some examples, the source line SL and the bit line BL can be formed of a metal material, such as tungsten or copper. In other examples, the source line SL and the bit line BL can be formed of heavily doped polysilicon.

[0087] For example, the source line SL and the bit line BL each include an N-type heavily doped polysilicon layer. The doping concentration of the N-type doping element in the source line SL and the bit line BL may be 1E20 / cm 3 ~1E21 / cm 3 N-type doping elements include, for example, Group V elements, such as phosphorus or arsenic.

[0088] For example, the first sub-insulating layer 241 and the second sub-insulating layer 242 may have a single-layer structure or a stacked-layer structure. In some examples, the first sub-insulating layer 241 and the second sub-insulating layer 242 include, but are not limited to, a stacked layer of silicon oxide and silicon nitride. In other examples, the first sub-insulating layer 241 and the second sub-insulating layer 242 include, but are not limited to, a single layer of silicon oxide.

[0089] In some embodiments, please refer to Figure 1 The sidewall of the source line SL facing away from the first sub-insulating layer 241 is flush with the sidewall of the source extension region 222 facing away from the channel region 221 . The sidewall of the bit line BL facing away from the second sub-insulating layer 242 is flush with the sidewall of the drain extension region 223 facing away from the channel region 221 .

[0090] In some embodiments, please refer to Figure 1The memory cell 2 further includes a support structure 25. The support structure 25 is located on two opposing sides of the word line WL in a second direction (e.g., the X direction). The support structure 25 includes a first support layer 251 located on the sidewall of the source extension region 222 facing away from the source line SL, and a second support layer 252 located on the sidewall of the drain extension region 223 facing away from the bit line BL. The sidewall of the first support layer 251 facing away from the word line WL is flush with the sidewall of the source line SL facing away from the first sub-insulating layer 241. The sidewall of the second support layer 252 facing away from the word line WL is flush with the sidewall of the bit line BL facing away from the second sub-insulating layer 242.

[0091] For example, the first supporting layer 251 and the second supporting layer 252 may be formed of a low-K dielectric material having a dielectric constant K less than 3.0.

[0092] By way of example, the first supporting layer 251 and the second supporting layer 252 include, but are not limited to, a silicon nitride layer or a silicon carbonitride layer.

[0093] It is worth mentioning that in some embodiments, the floating body 21 and the epitaxial layer 22 have the same size in a third direction (eg, Z direction) which is perpendicular to the intersection plane of the first direction (eg, Y direction) and the second direction (eg, X direction).

[0094] For example, the memory cell 2 may be disposed on a substrate and stacked from bottom to top along a third direction (eg, Z direction), so that the floating body 21 and the corresponding epitaxial layer 22 in the memory cell 2 may have the same height dimension.

[0095] In some embodiments, there are multiple floating bodies 21. The memory cell 2 further includes a plurality of third insulating layers 26 alternately stacked with the floating bodies 21 in a third direction (e.g., the Z direction). The third direction (e.g., the Z direction) is perpendicular to the intersection of the first direction (e.g., the Y direction) and the second direction (e.g., the X direction), and the floating bodies 21 are arranged in a row in the third direction (e.g., the Z direction). A word line WL is located on a side of a column of channel regions 221 facing away from the floating bodies 21.

[0096] In summary, the memory cell 2 provided by the embodiment of the present disclosure can selectively grow an epitaxial layer 22 on both side walls of any floating body 21, so as to utilize the epitaxial layer 22 to obtain a channel region 221, a source extension region 222, and a drain extension region 223, respectively. In this way, the embodiment of the present disclosure can selectively control the energy difference (i.e., the electron volt Ev difference) between the epitaxial layer 22 and the floating body 21, so as to facilitate the acquisition of a deeper hole well, thereby increasing the amount of hole accumulation in the floating body 21. Moreover, in a memory cell 2 in which multiple floating bodies 21 are stacked along a third direction (e.g., the Z direction), the implementation of the stacking process of multiple floating bodies 21 is also conducive to reducing defects in the film formation process of the floating body 21, thereby correspondingly increasing the turn-on current I of the transistor in which the floating body 21 is located. ON Therefore, the embodiment of the present disclosure can effectively improve the sensing margin and data retention function of the storage unit 2, thereby improving the storage performance of the memory.

[0097] Some embodiments of the present disclosure further provide a memory, comprising: a substrate and one or more memory cells disposed on the substrate and as described in any of the above embodiments. The structure of the memory can be understood in conjunction with the structure obtained in the subsequent memory manufacturing method.

[0098] Furthermore, the memory provided by the embodiments of the present disclosure includes, but is not limited to, DRAM. Furthermore, the memory can be used, but is not limited to, to manufacture various types of storage devices, such as solid-state drives (SSDs), universal serial bus (USB) drives, memory cards, and the like.

[0099] The present disclosure also provides a method for preparing a memory device, for use in preparing the memory device and memory unit described in some of the aforementioned embodiments. This method also possesses the technical advantages of the aforementioned memory device and memory unit. Furthermore, the method provided by the present disclosure is simple and easy to implement, and it also helps improve the production efficiency and yield of the memory device.

[0100] See also Figure 2 and Figure 3 , some embodiments of the present disclosure provide a method for preparing a memory, comprising the following steps.

[0101] S100 , providing a substrate, and forming one or more initial floating bodies on the substrate.

[0102] S200 , growing an epitaxial layer on two opposite side walls of any initial floating body in a first direction.

[0103] S300 , forming a sacrificial word line on a sidewall of the epitaxial layer away from the initial floating body.

[0104] S400, ion implantation is performed on the epitaxial layer exposed on two opposite sides of the sacrificial word line in the second direction to form a source extension region and a drain extension region; wherein the second direction intersects with the first direction, and the region of the epitaxial layer between the source extension region and the drain extension region constitutes a channel region.

[0105] S500 , back-etching two opposite side walls of the initial floating body in the second direction to obtain a floating body.

[0106] S600 , removing the sacrificial word line, and sequentially forming a first insulating layer and a word line in the removed region of the sacrificial word line.

[0107] In some embodiments, see Figure 3 , the preparation method of the memory also includes the following steps.

[0108] S700 , forming a second insulating layer on two opposite sidewalls of any floating body in a second direction. The second insulating layer includes a first sub-insulating layer located between opposing source extension regions, and a second sub-insulating layer located between opposing drain extension regions.

[0109] S800 , forming a source line in contact with and connected to the source extension region on a sidewall of the first sub-insulating layer facing away from the floating body.

[0110] S900 , forming a bit line in contact with and connected to the drain extension region on a sidewall of the second sub-insulating layer facing away from the floating body.

[0111] In some embodiments, before performing step S600 to remove the sacrificial word line and sequentially forming a first insulating layer and a word line in the removed area of ​​the sacrificial word line, the memory manufacturing method further includes: S550, forming a support structure on two opposite side walls of the sacrificial word line in the second direction.

[0112] In some embodiments, the sacrificial word line material comprises oxide. Step S600 removes the sacrificial word line and sequentially forms a first insulating layer and a word line in the region where the sacrificial word line was removed. The step further includes: etching away a portion of the oxide so that the remaining oxide forms the first insulating layer; and forming the word line on a surface of the first insulating layer away from the channel region.

[0113] In some embodiments, the number of initial floating bodies is multiple. Figure 4 In step S100, a plurality of initial floating bodies are formed on the substrate, including the following steps.

[0114] S110 , forming multiple layers of sacrificial material layers and multiple layers of compound semiconductor layers alternately stacked on a substrate.

[0115] S120 , back-etching two opposite side walls of each sacrificial material layer in the second direction to form a sacrificial pattern layer.

[0116] S130 , forming a temporary support structure covering the sidewalls of each sacrificial pattern layer and each compound semiconductor layer.

[0117] S140 , removing each sacrificial pattern layer, and forming a third insulating layer in the removed region of each sacrificial pattern layer.

[0118] In this manner, the compound semiconductor layer constitutes an initial floating body.

[0119] In some embodiments, forming a third insulating layer in the removed regions of each sacrificial pattern layer in step S140 includes: sequentially depositing a silicon nitride layer and a silicon oxide layer in the removed regions of each sacrificial pattern layer.

[0120] In some embodiments, before executing step S500 to back-etch the two opposite side walls of the initial floating body in the second direction to obtain the floating body, the memory preparation method also includes: S450, back-etching the two opposite side walls of the temporary support structure in the second direction until the two opposite side walls of the initial floating body in the second direction are exposed.

[0121] In some embodiments, the substrate comprises a silicon substrate. The sacrificial material layer comprises a silicon layer. Figure 5 In step S110, multiple layers of sacrificial material layers and multiple layers of compound semiconductor layers are alternately stacked on the substrate, and the following steps are also included.

[0122] S111 , forming a first compound semiconductor layer having a higher doping concentration than other layers on a substrate; and forming a first sacrificial material layer on a surface of the first compound semiconductor layer facing away from the substrate.

[0123] S112 , after forming each sacrificial material layer and each compound semiconductor layer, etching the first compound semiconductor layer, and simultaneously forming an isolation layer between the first sacrificial material layer and the substrate.

[0124] In some embodiments, the compound semiconductor layer includes a germanium silicon layer; wherein the molar percentage of the germanium element in the first compound semiconductor layer ranges from 40% to 85%; and the molar percentage of the germanium element in the compound semiconductor layers other than the first compound semiconductor layer ranges from 15% to 30%.

[0125] It should be understood that although the above Figures 2 to 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2 and Figure 3At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0126] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 6 to 24 Understand some embodiments of the present disclosure.

[0127] In step S100, refer to Figures 6 to 10 , providing a substrate 1, and forming one or more initial floating bodies 21A on the substrate 1. For example, step S100 may include the following steps S110 to S140.

[0128] In step S110, refer to Figure 6-Figure 7 , a plurality of sacrificial material layers L1B and a plurality of compound semiconductor layers L2 are alternately stacked on a substrate 1 .

[0129] Here, it can be understood that the sacrificial material layer L1B and the compound semiconductor layer L2 correspond to the layer structure in the stacked structure 2A. Figure 6 As shown in FIG, multiple initial sacrificial material layers L1A and multiple initial compound semiconductor layers L2A may be alternately stacked on the substrate 1, and then Figure 7 As shown in , the multi-layer initial sacrificial material layer L1A and the multi-layer initial compound semiconductor layer L2A are divided into an array to obtain a plurality of stacked structures 2A arranged in an array, and corresponding memory cells 2 are prepared based on each stacked structure 2A.

[0130] For example, substrate 1 can be composed of one or more layers of semiconductor material, insulating material, conductive material, or any combination thereof. For example, substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate including Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The disclosed embodiments do not limit the type, number of layers, and other aspects of substrate 1.

[0131] For example, see Figure 7Before the multi-layer initial sacrificial material layer L1A and the multi-layer initial compound semiconductor layer L2A are divided into an array, a protective layer can be formed on the surface of the top initial sacrificial material layer L1A. The protective layer includes, for example, a first oxide layer 41 and a first nitride layer 42 that are stacked.

[0132] It should be added that, unless otherwise specified, the nitride layers mentioned in the embodiments of the present disclosure may be, for example, silicon nitride layers, and the oxide layers mentioned may be, for example, silicon oxide layers.

[0133] In some embodiments, step S110 may further include steps S111 and S112.

[0134] In step S111, refer to Figure 6 and Figure 7 , a first compound semiconductor layer L21 having a higher doping concentration than other layers is formed on the substrate 1 ; a first sacrificial material layer L1B is formed on a surface of the first compound semiconductor layer L21 facing away from the substrate 1 .

[0135] For example, the compound semiconductor layer L2 includes a silicon germanium layer. The molar percentage of germanium in the first compound semiconductor layer L21 ranges from 40% to 85%, and the molar percentage of germanium in the compound semiconductor layers L2 other than the first compound semiconductor layer L21 ranges from 15% to 30%.

[0136] For example, the compound semiconductor layer L2 includes but is not limited to a P-type lightly doped silicon germanium layer. The doping concentration of the P-type doping element in the compound semiconductor layer L2 may be 1E17 / cm 3 ~9E18 / cm 3 The P-type doping elements include, for example, Group III elements, such as boron.

[0137] For example, the thickness of the compound semiconductor layer L2 ranges from, but is not limited to, 20 nm to 30 nm; for example, it may be 20 nm, 24 nm, 28 nm, or 30 nm.

[0138] In the embodiment of the present disclosure, the multi-layer sacrificial material layer L1B and the multi-layer compound semiconductor layer L2 are alternately stacked using a deposition process, which is beneficial to reducing defects in the film formation process of the compound semiconductor layer L2, thereby correspondingly improving the electrical performance of the floating body 21 subsequently formed based on the compound semiconductor layer L2.

[0139] In step S112, refer to Figure 8 After forming each sacrificial material layer L1B and each compound semiconductor layer L2, the first compound semiconductor layer L21 is etched, and an isolation layer 3 is simultaneously formed between the first sacrificial material layer L1B and the substrate 1.

[0140] Here, it can be understood that the different molar percentages of germanium in the first compound semiconductor layer L21 and the other compound semiconductor layers L2, as well as the different ion doping concentrations in the first compound semiconductor layer L21 and the other compound semiconductor layers L2, can result in different etching selectivities between the first compound semiconductor layer L21 and the other compound semiconductor layers L2. This facilitates removal of the first compound semiconductor layer L21 and forms an isolation layer 3 between the first sacrificial material layer L1B and the substrate 1, thereby utilizing the isolation layer 3 to provide insulation between the stacked structure 2A and the substrate 1.

[0141] For example, the substrate 1 is a silicon substrate; and / or the sacrificial material layer L1B is a silicon-containing layer or a silicon layer. The isolation layer 3 can be formed between the first sacrificial material layer L1B and the substrate 1 by a thermal oxidation process.

[0142] In steps S120 and S130, please combine Figure 8 and Figure 9 It is understood that the two opposite sidewalls of each sacrificial material layer L1B in the second direction (eg, X direction) are etched back to form a sacrificial pattern layer L1 and a temporary support structure 5A covering the sidewalls of each sacrificial pattern layer L1 and each compound semiconductor layer L2 is formed.

[0143] For example, the temporary support structure 5A may also cover the top surface of the top sacrificial pattern layer L1 .

[0144] In some examples, the temporary support structure 5A can be formed of nitride. For example, a third nitride layer 44 can be formed to cover the sidewalls of each sacrificial pattern layer L1 and the sidewalls of each compound semiconductor layer L2 to serve as the temporary support structure 5A. For example, the third nitride layer 44 can cover the top surface of the first nitride layer 42 in the aforementioned protective layer. For example, in an example where the third nitride layer 44 and the first nitride layer 42 are made of the same material, the third nitride layer 44 and the first nitride layer 42 can be fused into a single structure, together serving as the temporary support structure 5A.

[0145] In step S140, refer to Figure 10 and Figure 11 , each sacrificial pattern layer L1 is removed, and a third insulating layer 26 is formed in the removed region of each sacrificial pattern layer L1. In this way, the remaining compound semiconductor layer L2 can constitute the initial floating body 21A.

[0146] Here, after each sacrificial pattern layer L1 is removed, a plurality of first trenches G1 extending along a first direction (eg, a Y direction) may be formed.

[0147] For example, see Figure 11In step S140 , a third insulating layer 26 is formed in the removed area of ​​each sacrificial pattern layer L1 (ie, the first trench G1 ), including: sequentially depositing a third nitride layer 44 and a second oxide layer 45 on the inner wall of each first trench G1 .

[0148] In step S200, refer to Figure 12 An epitaxial layer 22 is grown on two opposite side walls of any initial floating body 21A in a first direction (eg, Y direction).

[0149] Here, the epitaxial layer 22 can be selectively grown. The epitaxial layer 22 is, for example, a silicon layer. There is an energy difference (ie, an electron volt Ev difference) between the epitaxial layer 22 and the initial floating body 21A.

[0150] In step S300, refer to Figure 13 A sacrificial word line DWL is formed on the sidewall of the epitaxial layer 22 away from the initial floating body 21A.

[0151] For example, the sacrificial word line DWL may be formed using oxide, such as silicon oxide.

[0152] For example, the sacrificial word line DWL extends along a third direction (eg, the Z direction) to define a formation space for the word line WL.

[0153] In step S400, refer to Figure 14 , ion implantation is performed on the epitaxial layer 22 exposed on opposite sides of the sacrificial word line DWL in a second direction (e.g., X direction) to form a source extension region 222 and a drain extension region 223; wherein the second direction (e.g., X direction) intersects with the first direction (e.g., Y direction), for example, is orthogonal.

[0154] Accordingly, the region of the epitaxial layer 22 between the source extension region 222 and the drain extension region 223 constitutes a channel region 221 .

[0155] For example, the source extension region 222 and the drain extension region 223 may be N-type doped silicon layers formed using a lightly doped drain (LDD) process, which refers to an ion implantation process using low energy and low current.

[0156] For example, the source extension region 222 and the drain extension region 223 are N-type doped silicon layers. The doping concentration of the N-type doping element in the source extension region 222 and the drain extension region 223 may be 1E18 / cm 3 ~8E19 / cm 3 N-type doping elements include, for example, Group V elements, such as phosphorus or arsenic.

[0157] In step S550, refer to Figure 15 , support structures 25 are formed on two opposite sidewalls of the sacrificial word line DWL in the second direction (eg, the X direction).

[0158] For example, the support structure 25 includes a first support layer 251 located on a sidewall of the source extension region 222 away from the source line SL, and a second support layer 252 located on a sidewall of the drain extension region 223 away from the bit line BL.

[0159] For example, the first supporting layer 251 and the second supporting layer 252 may be formed of a low-K dielectric material having a dielectric constant K less than 3.0. Alternatively, the first supporting layer 251 and the second supporting layer 252 may be formed of silicon nitride or silicon carbonitride.

[0160] In step S450, refer to Figure 16 , two opposite side walls of the temporary supporting structure 5A in the second direction (eg, X direction) are back-etched until two opposite side walls of the initial floating body 21A in the second direction (eg, X direction) are exposed.

[0161] Here, after etching back the temporary support structure 5A to expose the corresponding sidewall of the initial floating body 21A, a Figure 16 The second trench G2 shown in FIG2 extends along a third direction (eg, Z direction) and penetrates the stacked structure 2A. The remaining portion of the temporary support structure 5A can serve as a partial isolation structure 5 of the memory cell 2 to insulate and isolate the corresponding conductive elements.

[0162] In step S500, please combine Figure 16 、 Figure 17 and Figure 18 It is understood that the floating body 21 is obtained by etching back the two opposite side walls of the initial floating body 21A in the second direction (eg, the X direction).

[0163] Here, the sidewall of the initial floating body 21A is etched back to form Figure 18 The third trench G3 shown in FIG. 5 extends along the second direction (eg, the X direction).

[0164] In step S700, please combine Figure 19 、 Figure 20 and Figure 21 A second insulating layer 24 is formed on two opposite sidewalls of any floating body 21 in a second direction (e.g., the X direction). The second insulating layer 24 includes a first sub-insulating layer 241 located between opposing source extension regions 222 and a second sub-insulating layer 242 located between opposing drain extension regions 223.

[0165] For example, the first sub-insulating layer 241 and the second sub-insulating layer 242 may have a single-layer structure or a stacked-layer structure. In some examples, the first sub-insulating layer 241 and the second sub-insulating layer 242 include, but are not limited to, a stacked layer of silicon oxide and silicon nitride. In other examples, the first sub-insulating layer 241 and the second sub-insulating layer 242 include, but are not limited to, a single layer of silicon oxide.

[0166] In some examples, a fourth nitride layer 46 may be first formed in the third trench G3, with the sidewalls of the fourth nitride layer 46 facing away from the floating body 21 flush with the sidewalls of the second nitride layer 43 retained in the isolation structure 5. A third oxide layer 47 may then be formed to cover the fourth nitride layer 46 and the corresponding sidewalls of the second nitride layer 43. In this manner, both the first sub-insulating layer 241 and the second sub-insulating layer 242 may include a stacked fourth nitride layer 46 and a third oxide layer 47.

[0167] In other examples, a third oxide layer 47 can be directly formed to fill the third trench G3 and cover the sidewalls of the second nitride layer 43 retained in the aforementioned isolation structure 5, so that the third oxide layer 47 directly constitutes the corresponding first sub-insulating layer 241 or second sub-insulating layer 242.

[0168] In step S800 and step S900, please continue to refer to Figure 19 、 Figure 20 and Figure 21 A source line SL is formed on the sidewall of the first sub-insulating layer 241 away from the floating body 21 and connected to the source extension region 222. A bit line BL is formed on the sidewall of the second sub-insulating layer 242 away from the floating body 21 and connected to the drain extension region 223.

[0169] For example, the source line SL and the bit line BL can be formed of the same material. In some examples, the source line SL and the bit line BL can be formed of a metal material, such as tungsten or copper. In other examples, the source line SL and the bit line BL can be formed of heavily doped polysilicon.

[0170] For example, the source line SL and the bit line BL each include an N-type heavily doped polysilicon layer. The doping concentration of the N-type doping element in the source line SL and the bit line BL may be 1E20 / cm 3 ~1E21 / cm 3 N-type doping elements include, for example, Group V elements, such as phosphorus or arsenic.

[0171] In step S600, please combine Figure 22 、 Figure 23 and Figure 24It is understood that the sacrificial word line DWL is removed, and the first insulating layer 23 and the word line WL are sequentially formed in the removed region of the sacrificial word line DWL.

[0172] For example, the material of the sacrificial word line DWL includes oxide. In step S600 , the sacrificial word line DWL is removed, and a first insulating layer 23 and a word line WL are sequentially formed in the area where the sacrificial word line DWL was removed. The process also includes: etching away a portion of the oxide so that the remaining oxide forms the first insulating layer 23; and forming the word line WL on a surface of the first insulating layer 23 facing away from the channel region 221.

[0173] For example, the word line WL may be formed of a metal material, such as metal tungsten or metal copper.

[0174] For example, the first insulating layer 23 may be formed of oxide, such as silicon oxide.

[0175] In summary, the structure of the storage unit and memory provided in the embodiments of the present disclosure is as described above. This storage unit and memory can employ a gate-induced drain leakage (GIDL) mechanism to replace the impact ionization mechanism employed by 1T0C architecture storage units in related art. This mechanism serves as the primary storage mechanism for the storage unit and memory in the embodiments of the present disclosure, thereby ensuring lower power consumption and a larger sensing margin.

[0176] In some embodiments, see Figure 25 The word lines WL located on both sides of the floating body 21 in the memory cell can be connected to a word line driver to receive a gate voltage Vg and perform data read and write operations in response to the gate voltage Vg. The source line SL can be connected to a ground voltage terminal to receive a source voltage Vs. The bit line BL can provide different data voltages (e.g., Vdata1 and Vdata0) when writing data "1" or "0", respectively. It can also provide a first reference voltage V1 during the data read phase and a second reference voltage V2 during the data hold phase.

[0177] For example, the gate voltage Vg, the source voltage Vs, the data voltage Vdata, the first reference voltage V1 and the second reference voltage V2 corresponding to the memory cell at different stages can be specifically implemented as described in Table 1 below.

[0178] Table 1

[0179]

[0180] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0181] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0182] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A storage unit, characterized in that: include: one or more floating bodies; an epitaxial layer located on two opposite side walls of any one of the floating bodies in the first direction; The epitaxial layer includes: a channel region in contact with the corresponding sidewall surface of the floating body, and a source extension region and a drain extension region located on opposite sides of the channel region in a second direction; the second direction intersects the first direction; a word line, located on a side of the channel region away from the floating body; A first insulating layer is located between the word line and the channel region.

2. The storage unit according to claim 1, wherein Also includes: a second insulating layer located on two opposite side walls of any one of the floating bodies in the second direction; The second insulating layer includes: a first sub-insulating layer located between the source extension regions and a second sub-insulating layer located between the drain extension regions; a source line, located on a sidewall of the first sub-insulating layer facing away from the floating body and in contact with and connected to the source extension region; The bit line is located on a side wall of the second sub-insulating layer away from the floating body and is in contact with and connected to the drain extension region.

3. The storage unit according to claim 2, wherein: The side wall of the source line away from the first sub-insulating layer is flush with the side wall of the source extension region away from the channel region; the side wall of the bit line away from the second sub-insulating layer is flush with the side wall of the drain extension region away from the channel region.

4. The storage unit according to claim 2, wherein: Also includes: a supporting structure, located on two opposite side walls of the word line in the second direction; The support structure includes: a first support layer located on the side wall of the source extension region away from the source line, and a second support layer located on the side wall of the drain extension region away from the bit line; wherein, The sidewall of the first supporting layer away from the word line is flush with the sidewall of the source line away from the first sub-insulating layer; A sidewall of the second supporting layer facing away from the word line is flush with a sidewall of the bit line facing away from the second sub-insulating layer. The storage unit according to claim 1 , wherein: The floating body includes a germanium silicon layer; and the epitaxial layer includes a silicon epitaxial layer. The storage unit according to claim 1 , wherein: The floating body and the epitaxial layer have the same size in a third direction; the third direction is perpendicular to an intersection plane of the first direction and the second direction.

7. The storage unit according to any one of claims 1 to 6, wherein: There are multiple floating bodies; the storage unit also includes: multiple third insulating layers alternately stacked with the multiple floating bodies in a third direction; the third direction is perpendicular to the intersection plane of the first direction and the second direction, and the multiple floating bodies are arranged in a column in the third direction; wherein, one word line is correspondingly located on the side of a column of the channel region away from the floating body.

8. A memory, characterized in that: include: A substrate and one or more memory cells according to any one of claims 1 to 7, disposed on the substrate.

9. A method for preparing a memory, characterized in that: include: providing a substrate, and forming one or more initial floating bodies on the substrate; growing an epitaxial layer on two opposite side walls of any one of the initial floating bodies in the first direction; forming a sacrificial word line on a sidewall of the epitaxial layer away from the initial floating body; Ion implantation is performed on the epitaxial layer exposed on two opposite sides of the sacrificial word line in a second direction to form a source extension region and a drain extension region; wherein the second direction intersects the first direction, and the region of the epitaxial layer between the source extension region and the drain extension region constitutes a channel region; Carving back two opposite side walls of the initial floating body in the second direction to obtain a floating body; The sacrificial word line is removed, and a first insulating layer and a word line are sequentially formed in the removed region of the sacrificial word line.

10. The method for preparing a memory according to claim 9, wherein: Also includes: forming a second insulating layer on two opposite side walls of any one of the floating bodies in the second direction; The second insulating layer includes: a first sub-insulating layer located between the source extension regions and a second sub-insulating layer located between the drain extension regions; forming a source line in contact with and connected to the source extension region on a sidewall of the first sub-insulating layer facing away from the floating body; A bit line is formed on a side wall of the second sub-insulating layer away from the floating body and in contact with the drain extension region.

11. The method for preparing a memory according to claim 9, wherein: Before removing the sacrificial word line and sequentially forming a first insulating layer and a word line in the area where the sacrificial word line is removed, the preparation method further includes: Support structures are formed on two opposite sidewalls of the sacrificial word line in the second direction.

12. The method for preparing a memory according to claim 9, wherein: The material of the sacrificial word line includes oxide; removing the sacrificial word line and sequentially forming a first insulating layer and a word line in the removed area of ​​the sacrificial word line further includes: Etching and removing a portion of the oxide so that the remaining oxide constitutes the first insulating layer; The word line is formed on a surface of the first insulating layer away from the channel region.

13. The method for preparing a memory according to claim 9, wherein: There are multiple initial floating bodies; forming the multiple initial floating bodies on the substrate includes: forming a plurality of sacrificial material layers and a plurality of compound semiconductor layers alternately stacked on the substrate; Carving back opposite side walls of each sacrificial material layer in the second direction to form a sacrificial pattern layer; forming a temporary support structure covering the sidewalls of each sacrificial pattern layer and the sidewalls of each compound semiconductor layer; removing each of the sacrificial pattern layers and forming a third insulating layer in the removed region of each of the sacrificial pattern layers; Wherein, the compound semiconductor layer constitutes the initial floating body.

14. The method for preparing a memory according to claim 13, wherein: The forming of the third insulating layer in the removed regions of each sacrificial pattern layer includes: sequentially depositing a silicon nitride layer and a silicon oxide layer in the removed regions of each sacrificial pattern layer.

15. The method for preparing a memory according to claim 13, wherein: Before back-etching the two opposite side walls of the initial floating body in the second direction to obtain the floating body, the preparation method further comprises: The two opposite side walls of the temporary support structure in the second direction are back-etched until the two opposite side walls of the initial floating body in the second direction are exposed.

16. The method for preparing a memory according to claim 13, wherein: The substrate comprises a silicon substrate; the sacrificial material layer comprises a silicon layer; the method of forming a plurality of sacrificial material layers and a plurality of compound semiconductor layers alternately stacked on the substrate further comprises: forming a first compound semiconductor layer having a higher doping concentration than other layers on the substrate; forming a first sacrificial material layer on a surface of the first compound semiconductor layer facing away from the substrate; After forming each of the sacrificial material layers and each of the compound semiconductor layers, the first compound semiconductor layer is etched, and an isolation layer is simultaneously formed between the first sacrificial material layer and the substrate.

17. The method for preparing a memory according to claim 16, wherein: The compound semiconductor layer includes a germanium silicon layer; wherein, The molar percentage of germanium in the first compound semiconductor layer ranges from 40% to 85%. The molar percentage of germanium in the compound semiconductor layers other than the first compound semiconductor layer ranges from 15% to 30%.

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