SRAM cell structure and memory

Abstract

The present application relates to the field of semiconductor technology, and specifically to an SRAM cell structure and a memory. The SRAM cell structure includes: a semiconductor substrate, a first transistor and a second transistor are formed on the semiconductor substrate, the first transistor includes: a first gate structure, a first spacer and a second spacer are formed on the two side walls of the first gate structure, respectively, the second transistor includes a second gate structure and an active area, a doped area is formed in the active area, the doped area is located outside the second gate structure, the second spacer is close to the doped area, and the height of the second spacer is lower than the height of the first gate structure; a shared contact hole, the shared contact hole electrically connects the first gate structure of the first transistor and the doped area of ​​the second transistor, the shared contact hole includes a first part, and the first part covers at least part of the second spacer. In the SRAM cell structure of the present invention, the shared contact hole will not fall directly on the silicon layer, which solves the problem of high leakage caused by excessive etching of the shared contact hole.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an SRAM unit structure and a memory. Background Art

[0002] Strip type static random access memory (SRAM) is a commonly used storage device in logic platforms. Common SRAM cell layouts are as follows: Figure 1 As shown, it includes a long strip active area (Activearea, AA) 1, a gate (Gate, GT) 2, a contact hole (Contact, CT) 3 and a metal connection (Metal-1, M1) 4.

[0003] As the device size shrinks with the iteration of advanced device processes, the size of SRAM also shrinks, resulting in the stripe structure SRAM using shared contact (shared-CT) instead of the original two square contact holes (square-CT). However, the inherent defects and weaknesses formed in the manufacturing process of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) make it difficult to meet the etching requirements under traditional shared contact holes. In addition, when etching contact holes, it is difficult to take into account the etching amount and depth under different morphologies and different contact hole sizes. Usually, Share-CT is large in size and has a wide etching range, which easily leads to excessive etching and high leakage. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a SRAM cell structure, including:

[0006] A semiconductor substrate, on which a first transistor and a second transistor are formed, the first transistor comprising: a first gate structure, on both side walls of the first gate structure are respectively formed a first spacer and a second spacer, the second transistor comprising a second gate structure and an active region, a doped region is formed in the active region, the doped region is located outside the second gate structure, the second spacer is close to the doped region, and the height of the second spacer is lower than the height of the first gate structure;

[0007] A shared contact hole electrically connects the first gate structure of the first transistor and the doped region of the second transistor, the shared contact hole comprises a first portion, and the first portion covers at least a portion of the second spacer.

[0008] In one embodiment, the shared contact hole further includes a second portion and a third portion, the third portion covers at least a portion of the surface of the doped region, and the second portion is located between the first portion and the third portion, wherein:

[0009] The width of the second portion is smaller than the width of the first portion, and smaller than the width of the third portion; and / or

[0010] The width of the third portion is greater than the width of the first portion.

[0011] In one embodiment, it further includes a metal silicide, which is formed in the doped region, and the shared contact hole covers at least a portion of the metal silicide, wherein the second portion spans over an edge of the metal silicide close to the second spacer.

[0012] In one embodiment, at the bottom of the shared contact hole, the second portion and the third portion form a step.

[0013] In one embodiment, the shared contact hole further includes a fourth portion, the fourth portion covers at least a portion of the surface of the doped region, and the fourth portion is located between the second portion and the third portion, wherein:

[0014] The width of the fourth portion is greater than the width of the second portion and smaller than the width of the third portion.

[0015] In one embodiment, a bottom surface of the second portion and / or the fourth portion is spaced apart from a surface of the doping region by a predetermined distance, and the predetermined distance is greater than 0 and less than or equal to a height of the second spacer.

[0016] In one embodiment, a first interlayer dielectric is further included, and the first interlayer dielectric is located at the junction of the second spacer and the doped region, and the second portion also covers the first interlayer dielectric.

[0017] In one embodiment, a second interlayer dielectric is further included, wherein the second interlayer dielectric is located above the doped region, and the fourth portion further covers the second interlayer dielectric.

[0018] In one embodiment, the first transistor and the second transistor are fin field effect transistors or metal-oxide semiconductor field effect transistors.

[0019] A second aspect of an embodiment of the present invention provides a memory, wherein the memory includes the SRAM cell structure as described above.

[0020] In the SRAM cell structure provided by the present invention, the shared contact hole covers at least a portion of the spacer, so that the shared contact hole does not directly fall on the silicon layer, thereby solving the problem of high leakage caused by excessive etching of the shared contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The following drawings of the present invention are used as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and their descriptions to explain the principles of the present invention. In the drawings:

[0022] Figure 1 shows the layout of an existing SRAM cell;

[0023] Figure 2 A cross-sectional view of a conventional SRAM cell structure after a corner of a spacer is pierced is shown;

[0024] Figure 3 A cross-sectional schematic diagram of an SRAM cell according to an embodiment of the present invention is shown;

[0025] Figure 4 A cross-sectional schematic diagram of an SRAM unit before etching of a shared contact hole according to an embodiment of the present invention is shown;

[0026] Figure 5 A cross-sectional schematic diagram of an SRAM unit before etching of a shared contact hole according to an embodiment of the present invention is shown;

[0027] Figure 6 A cross-sectional schematic diagram of an SRAM unit after etching of a shared contact hole according to an embodiment of the present invention is shown;

[0028] Figure 7 A cross-sectional schematic diagram of an SRAM unit after etching of a shared contact hole according to another embodiment of the present invention and a layout corresponding to the shared contact hole are shown;

[0029] Figure 8 The layout of the SRAM cell where the shared contact hole 3a is located is shown. DETAILED DESCRIPTION

[0030] Next, the present invention will be more fully described in conjunction with the accompanying drawings, in which embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0031] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0032] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present invention. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined as such herein.

[0036] Due to the large size and wide etching range of Share-CT, and the inherent defects and weaknesses of the metal-oxide-semiconductor field-effect transistor (MOSFET) manufacturing process, such as the corner of the spacer and the corner of the active area, it is difficult to meet the etching requirements under the traditional shared contact hole. For example, the spacer covered by the shared contact hole will be completely etched, because metal silicide cannot be made under the spacer, resulting in the shared contact hole falling on the silicon layer, and the corner of the active area (the arrow in the circle in the figure) is pierced to form high leakage; such as Figure 2As shown, the shared contact hole is prone to over-etching during wet etching, and the oxide layer is easily etched away to form side digging during etching of the spacer, resulting in the silicon nitride (SiN) deposited here being thinner and just located at the end of the metal silicide, thereby piercing the corner of the spacer (indicated by the arrow in the circle in the figure).

[0037] In order to avoid high leakage caused by over-etching at defects and weak points of MOSFET, an embodiment of the present invention proposes a SRAM cell structure, such as Figure 3 As shown, including:

[0038] A semiconductor substrate, on which a first transistor and a second transistor are formed, the first transistor comprising: a first gate structure 11, on both side walls of the first gate structure 11 are respectively formed a first spacer 21 and a second spacer 22, the second transistor comprising a second gate structure (not shown) and an active area 30, a doping area 31 is formed in the active area 30, the doping area 31 is located outside the second gate structure, the second spacer 22 is close to the doping area 31, and the height of the second spacer 22 is lower than the height of the first gate structure 11;

[0039] A shared contact hole 40 electrically connects the first gate structure 11 of the first transistor and the doping region 31 of the second transistor. The shared contact hole 40 includes a first portion 41 . The first portion 41 covers at least a portion of the second spacer 22 .

[0040] In the present application, the semiconductor substrate may be silicon or silicon on insulator (SOI). An isolation structure is formed in the semiconductor substrate, and the isolation structure is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure. Various well structures and a channel layer on the surface of the substrate are also formed in the semiconductor substrate. Generally speaking, the ion doping conductivity type forming the well structure is the same as the ion doping conductivity type of the channel layer, but the concentration is lower than that of the gate channel layer, and the depth of the ion implantation is wider, and at the same time, it needs to reach a depth greater than that of the isolation structure.

[0041] Here, the first gate structure 11 and the second gate structure may include various materials, including but not limited to: certain metals, metal alloys, metal nitrides and metal silicides, and laminates and composites thereof. The gate may also include doped polysilicon and polysilicon-germanium alloy materials (i.e., having a doping concentration of about 1e18 to about 1e22 doping atoms per cubic centimeter) and polysilicon metal silicide (polycide) materials (doped polysilicon / metal silicide stacked materials). Similarly, any of several methods may be used to form the aforementioned materials. In one embodiment, the gate is composed of polysilicon material. The gate formation process may adopt any prior art known to those skilled in the art, preferably a chemical vapor deposition method, such as a low-pressure plasma chemical vapor deposition or a plasma enhanced chemical vapor deposition process. The thickness of the gate is 800 to 3000 angstroms.

[0042] Figure 4 FIG. 4 shows a cross-sectional schematic diagram of an SRAM unit before etching of a shared contact hole according to an embodiment of the present invention. Figure 4 As shown, a doped region 31 is formed in the active region 30 by implantation, and a first spacer 21 and a third spacer 23 are formed on both side walls of the first gate structure 11, respectively, to isolate the gate from the drain / source, and can be used as a mask for the ion implantation process of forming the drain / source region. The first gate structure 11, the first spacer 21, the third spacer 23 and the active region 30 are covered with a contact hole etch stop layer 50 and an interlayer dielectric 60, and the interlayer dielectric 60 is formed on the contact hole etch stop layer 50. The contact hole etch stop layer 50 is usually a silicon nitride film.

[0043] If the process is not optimized, the third spacer 23 will be completely etched away, and the shared contact hole will stop on the active area 30. Since metal silicide cannot be made under the spacer and over-etching is prone to occur at the metal silicide, leakage problems can easily occur.

[0044] In the present application, when etching the shared contact hole, the etching depth needs to be reduced above the spacer to retain part of the spacer, so that after the etching of the shared contact hole 40 is completed, the second spacer 22 is obtained due to the etching of part of the third spacer 23, that is, the second spacer 22 is the residual spacer formed after etching the shared contact hole.

[0045] The first spacer 21 and the second spacer 22 may include nitride, oxynitride or a combination thereof and are formed by deposition and etching. The spacer structure may have different thicknesses, but the thickness of the spacer structure is generally 10 to 30 nm measured from the bottom surface.

[0046] In the present application, the shared contact hole 40 is composed of at least a first contact hole and a second contact hole, and the division of the first contact hole and the second contact hole is based on the etching process, rather than the structure. During etching, the first contact hole needs to be etched first, and then the second contact hole is etched. Through the above steps, a shared contact hole composed of the first contact hole and the second contact hole is finally formed in the SRAM area.

[0047] Specifically, when etching the contact hole, the following steps are included:

[0048] Deposit contact layer (optional): Deposit a layer of specific material (such as a barrier layer or contact layer) over the area where contact holes are required to form precise contact holes in the subsequent etching process.

[0049] Coating photoresist and exposing and developing: In order to form contact holes, photoresist needs to be coated again, and a photolithography machine is used to project the designed contact hole pattern onto the photoresist for exposure and development.

[0050] Etching to form contact holes: Use etching technology to etch away the insulating layer and form contact holes above the active area and drain area respectively to connect with the metal interconnection lines.

[0051] After the contact hole is etched, a tungsten filling and tungsten planarization process is used to finally form a shared contact hole 3.

[0052] In the SRAM cell structure provided by the present invention, the shared contact hole covers at least a portion of the spacer, so that the shared contact hole does not directly fall on the silicon layer, thereby solving the problem of high leakage caused by excessive etching of the shared contact hole.

[0053] Next, see Figure 5 and Figure 6 It is worth mentioning that, in order to avoid repetition, the same components and structures as those in the previous embodiment will not be described in detail, and their specific explanations and descriptions can refer to the descriptions in the previous embodiment.

[0054] like Figure 6 As shown, according to one embodiment of the present application, the shared contact hole 40 further includes a second portion 42 and a third portion 43, the third portion covers at least a portion of the surface of the doped region 31, and the second portion 42 is located between the first portion 41 and the third portion 43. At the bottom of the shared contact hole, the second portion and the third portion form a step.

[0055] In this embodiment, the shared contact hole 40 further includes a gate upper portion 401 covering the gate 11. That is, in this embodiment, the shared contact hole 40 is composed of four portions in total.

[0056] The characteristic dimensions of the first portion 41, the second portion 42 and the third portion 43 in the cross-sectional view are a, b and c respectively. Figure 5 The method for determining the characteristic dimensions a, b, and c is described in detail.

[0057] Figure 5 FIG. 4 shows a cross-sectional schematic diagram of an SRAM unit before etching of a shared contact hole according to an embodiment of the present invention. Figure 5 As shown, the SRAM cell structure includes: an active region 30, a first gate structure 11, a third spacer 23, a doped region 31, an interlayer dielectric 60 and an etch stop layer 50. In the figure, a is the maximum thickness of the spacer to be etched, i.e., the third spacer 23. In the figure, b is the thickness of the contact hole etch stop layer 50, and c is the distance from the contact hole etch stop layer to the edge of the shared contact hole located above the doped layer.

[0058] In a specific implementation, the device may be measured by a transmission electron microscope (TEM) to obtain a critical dimension (CD).

[0059] Exemplarily, a and b are 115 nm and 35 nm, respectively.

[0060] When etching the shared contact holes, the characteristic sizes of the shared contact holes at different MOSFETs can be designed by controlling the sizes and morphologies of the first portion of the contact holes, the second portion of the contact holes, and the third portion of the shared contact holes.

[0061] According to one embodiment of the present application, the SRAM cell structure further includes a metal silicide, which is formed in the doped region, and the shared contact hole covers at least a portion of the metal silicide, wherein the second portion spans an edge of the metal silicide close to the second spacer.

[0062] In this embodiment, the metal silicide process can achieve precise control and alignment of the contact area between metal and silicon, thereby reducing contact resistance. In addition, since the second portion spans the edge of the metal silicide close to the second spacer, it can be ensured that the shared contact hole on the self-aligned silicide of the doped region does not fall at the end of the self-aligned silicide.

[0063] In this embodiment, a bottom surface of the second portion is spaced apart from a surface of the doping region by a predetermined distance, and the predetermined distance is greater than 0 and less than or equal to a height of the second spacer.

[0064] In a specific implementation, when the bottom surface of the second portion is spaced from the surface of the doped region by a predetermined distance greater than the thickness of the etch stop layer, the SRAM cell structure further includes a first interlayer dielectric, the first interlayer dielectric is located at the junction of the second spacer and the doped region, and the second portion also covers the first interlayer dielectric. Specifically, the height of the first interlayer dielectric is greater than 0 and less than or equal to the height of the second spacer.

[0065] According to one embodiment of the present application, the width of the second portion 42 is smaller than the width of the first portion 41, and smaller than the width of the third portion 43; and / or

[0066] The width of the third portion 43 is greater than the width of the first portion 41 .

[0067] Here, the width of the second portion 42, the width of the first portion 41 and the width of the third portion 43 are all the widths of the respective portions when viewed from above the chip, that is, the widths corresponding to the respective portions in the layout.

[0068] Due to the design requirements of the SRAM storage unit, the distance from the contact hole to the polysilicon gate needs to be fixed, otherwise the switching speed will change, and the overlap between the contact hole and the polysilicon cannot be too small, otherwise it will cause high resistance, resulting in failure of reading and writing at different voltages. Therefore, this embodiment appropriately reduces the overlap area between the shared contact hole and the polysilicon layer. When the shared contact hole window is reduced, the etching energy is reduced, the etching depth is reduced, but the contact hole will not be opened.

[0069] Specifically, during the etching process, the size of the etching shared contact hole window is controlled, thereby controlling the etching speed, and improving the over-etching phenomenon of the shared contact hole while ensuring that the resistance is not increased.

[0070] This embodiment improves the leakage problem in SRAM reading, writing / storage by designing the SRAM shared contact hole layout. In addition, it is compatible with square contact holes and avoids the risk of bypassing / short circuits, reduces the process difficulty, and can flexibly adjust the contact hole size to increase the process window for contact hole etching, thereby reducing damage to the device.

[0071] Next, see Figure 7-Figure 8 A shared contact hole according to another embodiment of the present application is described. Figure 7 In the figure, the red part is a cross-sectional schematic diagram of the shared contact hole 3a in the SRAM unit, and the blue part is the layout of the shared contact hole 3a. Figure 8 The layout of the SRAM cell where the shared contact hole 3a is located is shown.

[0072] In this embodiment, the shared contact hole includes a gate upper portion 3a0, a first portion 3a1, a second portion 3a2, a third portion 3a3 and a fourth portion 3a4, wherein the fourth portion 3a4 covers at least a portion of the surface of the doped region, and the fourth portion 3a4 is located between the second portion 3a2 and the third portion 3a3, wherein:

[0073] The width of the fourth portion 3a4 is greater than the width of the second portion 3a2 and smaller than the width of the third portion.

[0074] Specifically, the width of the fourth portion is also the width of each portion when viewed from above the chip, that is, the width corresponding to each portion in the layout.

[0075] Here, a bottom surface of the fourth portion is spaced apart from a surface of the doping region by a predetermined distance, and the predetermined distance is greater than 0 and less than or equal to a height of the second spacer.

[0076] When the bottom surface of the fourth portion is spaced a predetermined distance from the surface of the doped region greater than the thickness of the etch stop layer, the SRAM cell structure further includes a second interlayer dielectric located above the doped region, and the fourth portion also covers the second interlayer dielectric.

[0077] According to an embodiment of the present application, the first transistor and the second transistor are fin field effect transistors or metal-oxide semiconductor field effect transistors.

[0078] When the transistors are all metal-oxide semiconductor field effect transistors, the SRAM structure in the present application is a strip type SRAM.

[0079] Embodiment 2

[0080] The present invention further provides a memory, which includes the SRAM unit structure in the aforementioned first embodiment.

[0081] The memory of the embodiment of the present invention has better storage performance because it adopts the SRAM unit structure of the first embodiment.

[0082] Embodiment 3

[0083] Another embodiment of the present invention provides an electronic device including the aforementioned memory.

[0084] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because it uses the above-mentioned memory.

[0085] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed in the present invention. More particularly, various modifications and changes may be made to the arrangements and / or components of the combined arrangements of the subject matter within the scope of the present disclosure, the drawings, and the appended claims. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious option for those skilled in the art.

Claims

1. A SRAM cell structure, characterized in that: include: A semiconductor substrate, on which a first transistor and a second transistor are formed, the first transistor comprising: a first gate structure, on both side walls of the first gate structure are respectively formed a first spacer and a second spacer, the second transistor comprising a second gate structure and an active region, a doped region is formed in the active region, the doped region is located outside the second gate structure, the second spacer is close to the doped region, and the height of the second spacer is lower than the height of the first gate structure; a shared contact hole, wherein the shared contact hole electrically connects the first gate structure of the first transistor and the doped region of the second transistor, the shared contact hole comprises a first portion, a second portion and a third portion, the first portion covers at least a portion of the second spacer, the third portion covers at least a portion of the surface of the doped region, the second portion is located between the first portion and the third portion, wherein a width of the second portion is smaller than a width of the first portion and smaller than a width of the third portion; and / or The width of the third portion is greater than the width of the first portion.

2. The SRAM cell structure according to claim 1, characterized in that: It also includes a metal silicide, which is formed in the doped region, and the shared contact hole covers at least a portion of the metal silicide, wherein the second portion spans over an edge of the metal silicide close to the second spacer.

3. The SRAM cell structure according to claim 1, characterized in that: At the bottom of the shared contact hole, the second portion and the third portion form a step.

4. The SRAM cell structure according to claim 1, characterized in that: The shared contact hole further includes a fourth portion, the fourth portion covers at least a portion of the surface of the doped region, and the fourth portion is located between the second portion and the third portion, wherein: The width of the fourth portion is greater than the width of the second portion and smaller than the width of the third portion.

5. The SRAM cell structure according to claim 4, characterized in that: A bottom surface of the second portion and / or the fourth portion is spaced apart from a surface of the doping region by a predetermined distance, and the predetermined distance is greater than 0 and less than or equal to a height of the second spacer.

6. The SRAM cell structure according to claim 4, characterized in that: It also includes a first interlayer dielectric, which is located at the junction of the second spacer and the doping region, and the second portion also covers the first interlayer dielectric.

7. The SRAM cell structure according to claim 6, characterized in that: The invention also includes a second interlayer dielectric, wherein the second interlayer dielectric is located above the doped region, and the fourth portion further covers the second interlayer dielectric.

8. The SRAM cell structure according to any one of claims 1 to 7, characterized in that: The first transistor and the second transistor are fin field effect transistors or metal-oxide semiconductor field effect transistors.

9. A memory, characterized in that: The memory comprises the SRAM cell structure according to any one of claims 1 to 8.

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