Storage unit and storage structure

Abstract

The present disclosure relates to a memory cell and a memory structure, the memory cell comprising a magnetic memory, a full-surrounding gate word line structure, a first selection line, a first bit line and a magnetic tunnel junction. The magnetic memory comprises a magnetic racetrack, and a plurality of magnetic domains are arranged in the magnetic racetrack. The full-surrounding gate word line structure is arranged at one end of the magnetic racetrack and connected to the magnetic racetrack. The first selection line is arranged at the end of the full-surrounding gate word line structure away from the magnetic racetrack and connected to the full-surrounding gate word line structure. The first bit line is arranged at the end of the magnetic racetrack away from the full-surrounding gate word line structure and connected to the magnetic racetrack. The magnetic tunnel junction is arranged outside the magnetic racetrack. The memory cell realizes 3D stacking of the magnetic memory, improves the structure of the magnetic memory, realizes high-density magnetic memory, and further improves the comprehensive performance of the memory cell.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory unit and a memory structure. Background Art

[0002] Magnetic memory is a non-volatile memory composed of magnetic tracks and magnetic tunnel junctions connected by circuits. Compared to existing storage methods such as static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory, magnetic memory offers advantages such as higher read and write speeds, lower power consumption, enhanced erasure endurance, and non-volatility. As a result, it has attracted widespread attention and research both domestically and internationally in recent years.

[0003] However, in existing magnetic random access memories, the arrangement of storage cells and the connection between magnetic tunnel junctions and transistors are limited, which restricts further improvement of the comprehensive performance of magnetic random access memories, thereby limiting the widespread application of magnetic random access memories.

[0004] Therefore, how to improve the structure of magnetic memory, realize high-density magnetic memory, and further enhance the overall performance of storage units is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Based on this, the embodiments of the present disclosure provide a storage unit and a storage structure, which can improve the structure of the magnetic memory, realize high-density magnetic memory, and further enhance the overall performance of the storage unit.

[0006] On the one hand, some embodiments of the present disclosure provide a storage unit comprising: a magnetic memory, a full-surround gate word line structure, a first selection line, a first bit line, and a magnetic tunnel junction. The magnetic memory comprises a magnetic track, in which a plurality of magnetic domains are provided. The full-surround gate word line structure is located at one end of the magnetic track and is connected to the magnetic track. The first selection line is located at an end of the full-surround gate word line structure away from the magnetic track and is connected to the full-surround gate word line structure. The first bit line is located at an end of the magnetic track away from the full-surround gate word line structure and is connected to the magnetic track. The magnetic tunnel junction is located outside the magnetic track.

[0007] In some embodiments of the present disclosure, a fully wrapped gate wordline structure includes an active pillar and a fully wrapped gate wordline. The active pillar includes a source region, a channel region, and a drain region sequentially arranged along an extension direction. The source region contacts one end of a magnetic racetrack, and the drain region contacts a first select line. The fully wrapped gate wordline surrounds the channel region.

[0008] In some embodiments of the present disclosure, a magnetic tunnel junction includes a free layer, a first insulating layer, a pinned layer, and a selection layer stacked sequentially from bottom to top.

[0009] In some embodiments of the present disclosure, the magnetic tunnel junction further includes a second bit line. The second bit line is located between the magnetic tunnel junction and the magnetic racetrack and is in contact with the magnetic tunnel junction.

[0010] In some embodiments of the present disclosure, the magnetic tunnel junction further includes a second selection line. The second selection line is located on a surface of the magnetic tunnel junction away from the second bit line.

[0011] In some embodiments of the present disclosure, the memory cell further includes a second insulating layer. The second insulating layer is located between the second bit line and the magnetic racetrack and is in contact with both the second bit line and the magnetic racetrack.

[0012] In some embodiments of the present disclosure, multiple magnetic domains are arranged at intervals.

[0013] In some embodiments of the present disclosure, the number of magnetic domains in the magnetic runway is 10 to 100.

[0014] In some embodiments of the present disclosure, the magnetization direction of the magnetic domain is parallel or antiparallel to the magnetization direction of the free layer.

[0015] In some embodiments of the present disclosure, a magnetic tunnel junction surrounds a magnetic racetrack.

[0016] On the other hand, some embodiments of the present disclosure provide a storage structure comprising a plurality of storage units as described in any one of the above embodiments.

[0017] In some embodiments of the present disclosure, the memory cells are arranged along a first direction, and adjacent memory cells share a first bit line, and adjacent magnetic tunnel junctions are located on opposite sides of a magnetic racetrack.

[0018] In some embodiments of the present disclosure, each fully surrounding gate word line structure includes an active pillar and a fully surrounding gate word line, the active pillar includes a source region, a channel region and a drain region arranged in sequence along the extension direction; the source region contacts one end of the magnetic runway, and the drain region contacts the first selection line; the fully surrounding gate word line surrounds the channel region; the magnetic runway and the active pillar both extend along the first direction, and multiple magnetic runways are arranged in parallel and at intervals along the second direction, and the second direction is perpendicular to the first direction; each fully surrounding gate word line structure shares the same fully surrounding gate word line extending along the second direction.

[0019] In some embodiments of the present disclosure, a magnetic track extends along a first direction, and a plurality of magnetic tracks are arranged in parallel and spaced apart along a third direction, the third direction being perpendicular to the first direction; each magnetic track shares a same first bit line extending along the third direction; each fully surrounding gate word line structure shares a same first selection line extending along the third direction.

[0020] In some embodiments of the present disclosure, each memory cell further includes a second bit line and a second selection line; the second bit line and the second selection line both extend along a third direction to connect the magnetic tunnel junctions of each memory cell in series.

[0021] In some embodiments of the present disclosure, each fully surrounding gate word line structure includes an active pillar and a fully surrounding gate word line, the active pillar includes a source region, a channel region and a drain region arranged in sequence along the extension direction; the source region contacts one end of the magnetic runway, and the drain region contacts the first selection line; the fully surrounding gate word line surrounds the channel region; multiple magnetic runways and multiple active pillars are arranged in multiple rows and columns; each magnetic runway and each active pillar extends along the first direction; the fully surrounding gate word line extends along the second direction to connect the active pillars in the same column in series in sequence; the first bit line extends along the third direction to connect the magnetic runways in the same row in series; the first selection line extends along the third direction to connect the active pillars in the same row in series in sequence; the first direction is perpendicular to the second direction, and the third direction is perpendicular to both the first direction and the second direction.

[0022] In some embodiments of the present disclosure, each memory cell further includes a second bit line and a second selection line; the second bit line and the second selection line both extend along a third direction to connect the magnetic tunnel junctions of each memory cell in series.

[0023] The memory cell and memory structure provided by the embodiments of the present disclosure are as described above. In the memory cell, by providing a fully surround gate wordline structure, multiple magnetic memories can be stacked in 3D, thereby improving the structure of the magnetic memory, achieving high-density magnetic memory, and thus improving the overall performance of the memory cell.

[0024] Furthermore, the magnetic tunnel junction can also wrap around the magnetic track, which helps to further achieve continuous scaling of the memory cell, thereby increasing the capacity of the memory cell and thus improving the overall performance of the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 is a schematic diagram of a three-dimensional structure of a storage unit provided in one embodiment;

[0027] Figure 2 is a schematic cross-sectional structural diagram of another storage unit provided in one embodiment;

[0028] Figure 3 is a schematic diagram of a three-dimensional structure of a storage structure provided in one embodiment;

[0029] Figure 4A schematic diagram of another storage structure provided in one embodiment;

[0030] Figure 5 A schematic structural diagram of another storage structure provided in an embodiment;

[0031] Figure 6 A schematic structural diagram of another storage structure provided in an embodiment;

[0032] Figure 7 A schematic structural diagram of another storage structure provided in an embodiment;

[0033] Figure 8 A schematic structural diagram of another storage structure provided in an embodiment;

[0034] Figure 9 This is a structural diagram of another storage structure provided in an embodiment.

[0035] Description of reference numerals:

[0036] 1-magnetic memory; 11-magnetic racetrack; 111-magnetic domain;

[0037] 2-all-around gate word line structure; 21-active pillar; 211-source region; 212-channel region; 213-drain region; WL-all-around gate word line, gate;

[0038] SL1 - first selection line; BL1 - first bit line; 5 - magnetic tunnel junction; 51 - free layer; 52 - first insulating layer; 53 - pinned layer; 54 - selection layer; BL2 - second bit line; 56 - second selection line; 6 - second insulating layer. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0040] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0041] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] Magnetic memory (MRI) is a non-volatile memory composed of magnetic tracks and magnetic tunnel junctions connected by circuits. Compared to existing storage methods such as static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory, MRI offers advantages such as higher read and write speeds, lower power consumption, enhanced erasure endurance, and non-volatility, attracting widespread attention and research both domestically and internationally in recent years. The development of MRI has progressed from the first generation, which used magnetic field writing, to the second generation, which used spin-transfer torque current writing, to the third generation, which uses spin-orbit torque current writing.

[0043] However, in existing magnetic random access memories, the arrangement of storage cells and the connection between magnetic tunnel junctions and transistors are limited, which restricts further improvement of the comprehensive performance of magnetic random access memories, thereby limiting the widespread application of magnetic random access memories.

[0044] Based on this, the embodiments of the present disclosure provide a storage unit and a storage structure, which can improve the structure of the magnetic memory, realize high-density magnetic memory, and further enhance the overall performance of the storage unit.

[0045] See also Figure 1Some embodiments of the present disclosure provide a memory cell, including: a magnetic memory 1, a full-surround gate word line structure 2, a first selection line SL1, a first bit line BL1, and a magnetic tunnel junction 5. The magnetic memory 1 includes a magnetic track 11, in which a plurality of magnetic domains 111 are provided. The full-surround gate word line structure 2 is located at one end of the magnetic track 11 and is connected to the magnetic track 11. The first selection line SL1 is located at one end of the full-surround gate word line structure 2 away from the magnetic track 11 and is connected to the full-surround gate word line structure 2. The first bit line BL1 is located at one end of the magnetic track 11 away from the full-surround gate word line structure 2 and is connected to the magnetic track 11. The magnetic tunnel junction 5 is located outside the magnetic track 11.

[0046] In this application, please refer to Figure 1 In the storage cell, the magnetic memory 1, the first selection line SL1, the first bit line BL1, and the magnetic tunnel junction 5 all extend along the first direction (e.g., X direction) or the second direction (e.g., Y direction). In this way, after one end of the magnetic runway 11 of the magnetic memory 1 is connected to the full-surround gate word line structure 2, the storage cell can be extended not only in the first direction (e.g., X direction) and the second direction (e.g., Y direction), but also in the third direction (e.g., Z direction). In this way, the magnetic memory 1 can be arranged not only along the first direction (e.g., X direction) and the second direction (e.g., Y direction), but also along the third direction (e.g., Z direction). That is, the embodiment of the present application realizes 3D stacking of the magnetic memory 1, improves the structure of the magnetic memory, realizes high-density magnetic memory, and thereby improves the overall performance of the storage cell.

[0047] 3D stacked magnetic memory can double its capacity and bandwidth, making it increasingly applicable to various industrial and technological fields to meet the big data storage needs of electronic devices. Compared to single magnetic memory, 3D stacked magnetic memory can more effectively expand data capacity, so the widespread application of 3D stacked magnetic memory has extremely important practical significance for the development of data storage technology.

[0048] For example, magnetic domains 111 refer to small, differently oriented magnetized regions that differentiate during the spontaneous magnetization of ferromagnetic materials to reduce static magnetic energy. Each region contains a large number of atoms whose magnetic moments are neatly arranged like small magnets, but the directions of the atomic magnetic moments in adjacent regions differ. The interface between each magnetic domain 111 is called a domain wall. In other words, adjacent magnetic domains 111 are separated by domain walls. The arrangement of magnetic domains 111 represents the information stored within the magnetic track 11.

[0049] In some embodiments, please refer to Figure 1The all-around gate wordline structure 2 includes an active pillar 21 and an all-around gate wordline WL. The active pillar 21 includes a source region 211, a channel region 212, and a drain region 213 arranged in sequence along an extension direction (e.g., the X direction). The source region 211 contacts one end of the magnetic track 11, and the drain region 213 contacts the first select line SL1. The all-around gate wordline WL surrounds the channel region 212.

[0050] Here, the all-around gate word line WL can contact the channel region 212 from all sides, which helps to further achieve continuous scaling of the memory cell to increase the capacity of the memory cell.

[0051] In some examples, the all-around gate word line structure 2 includes a transistor including a source region 211 , a channel region 212 , and a drain region 213 sequentially arranged along an extension direction (eg, an X direction). The gate WL surrounds the channel region 212 .

[0052] Here, the gate WL can contact the channel region 212 from all sides, which helps to further achieve continuous scaling of the memory cell to increase the capacity of the memory cell.

[0053] In some embodiments, the magnetic tunnel junction 5 includes a free layer 51 , a first insulating layer 52 , a pinned layer 53 , and a selection layer 54 stacked sequentially from bottom to top.

[0054] In some embodiments, a plurality of magnetic domains 111 are defined within the magnetic track 11 .

[0055] For example, the shape of the magnetic tunnel junction 5 can be cylindrical, square, or other possible shapes. That is, the shapes of the free layer 51, the first insulating layer 52, the pinned layer 53, and the selection layer 54 can all be cylindrical, square, or other possible shapes.

[0056] In some examples, the first insulating layer 52 serves to isolate the free layer 51 and the pinned layer 53. When the magnetization directions of the free layer 51 and the pinned layer 53 are the same, the magnetic tunnel junction 5 is in a low-resistance state (i.e., "0" state); when the magnetization directions of the free layer 51 and the pinned layer 53 are opposite, the magnetic tunnel junction 5 is in a high-resistance state (i.e., "1" state).

[0057] In some examples, the gate-all-around wordline structure 2 includes a transistor, and the transistor is turned on when the gate-all-around wordline WL is in the “1” state.

[0058] For example, the free layer 51 and the pinned layer 53 can be made of the same or different materials, such as iron (Fe), cobalt (Co), nickel (Ni), or alloys thereof. The free layer 51 and the pinned layer 53 can have the same or different thicknesses, the same or different sizes, and the same or different shapes, such as cylindrical or square pillars.

[0059] For example, the first insulating layer 52 may include at least one of magnesium oxide (MgO), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), and silicon oxide (SiO 2 ).

[0060] In some embodiments, the magnetic tunnel junction 5 further includes a second selection line SL2 . The second selection line SL2 is located on a surface of the magnetic tunnel junction 5 away from the second bit line BL2 . That is, the second selection line SL2 is electrically connected to the selection layer 54 .

[0061] In some embodiments, the magnetic tunnel junction 5 further includes a second bit line BL2 . The second bit line BL2 is located between the magnetic tunnel junction 5 and the magnetic racetrack 11 and is in contact with the magnetic tunnel junction 11 .

[0062] In some embodiments, the memory cell further includes a second insulating layer 6 . The second insulating layer 6 is located between the second bit line BL2 and the magnetic track 11 , and is in contact with both the second bit line BL2 and the magnetic track 11 .

[0063] In some embodiments, multiple magnetic domains 111 are arranged at intervals. The magnetic track 11 may contain multiple different magnetic domains 111, and adjacent magnetic domains 111 are separated by magnetic domain walls. The arrangement of the magnetic domains (walls) represents the information stored in the magnetic track. A new magnetic domain state can be written into the magnetic track by writing a magnetic tunnel junction, and the arrangement of the magnetic domains can be read out by reading a magnetic tunnel junction, thereby extracting the stored information. The magnetic domains 111 in the magnetic track 11 can move under the action of an external current. When the direction of the external current is changed, the direction of movement of the magnetic domains 111 also changes accordingly. Therefore, the stored magnetic domain pattern can be driven by an external current to pass through the read magnetic tunnel junction or the write magnetic tunnel junction in sequence along the magnetic track, and the magnetic domains 111 can be read or written bit by bit.

[0064] In some embodiments, the number of magnetic domains 111 in the magnetic track 11 is 10 to 100, which helps to achieve ultra-high-density magnetic storage.

[0065] In some embodiments, the magnetization direction of the magnetic domain 111 is parallel or antiparallel to the magnetization direction of the free layer 51 . The magnetic domain 111 directly below the magnetic tunnel junction 5 is tightly coupled to the free layer 51 .

[0066] For example, when the first bit line BL1 is in the "1" state and the first selection line SL1 is in the "0" state, a current flows from the first bit line BL1 to the first selection line SL1, and the current drives the magnetic domain 111 to move toward the first bit line BL1.

[0067] Accordingly, when the first bit line BL1 is in the “0” state and the first selection line SL1 is in the “1” state, current flows from the first bit line BL1 to the first selection line SL1 , and the current drives the magnetic domain 111 to move toward the first selection line SL1 .

[0068] In some examples, the selection layer 54 includes a selection switch. When the selection switch is closed, current flows through the magnetic tunnel junction 5 .

[0069] For example, when the second bit line BL2 is in the "1" state, the second selection line SL2 is in the "0" state, and the selection switch is closed, a current will pass through the magnetic tunnel junction 5. The magnitude of the current determines the "writing" (large current) or "reading" (small current) of the magnetic tunnel junction 5.

[0070] Accordingly, in some examples, the second bit line BL2 is in the "0" state, the second selection line SL2 is in the "1" state, and when the selection switch is closed, a current will pass through the magnetic tunnel junction 5, and the magnitude of the current determines the "writing" (large current) or "reading" (small current) of the magnetic tunnel junction 5.

[0071] In some examples, during "writing", the magnetic tunnel junction 5 is determined to be in a "1" state or a "0" state according to the direction of the current in the magnetic tunnel junction 5. Then, the magnetic domain 111 directly below the magnetic tunnel junction 5 is switched to a "1" state or a "0" state accordingly through the magnetic coupling effect.

[0072] Accordingly, in some examples, during "reading," the magnetic tunnel junction 5 is determined to be in a "1" state or a "0" state based on the direction of the current flowing through the magnetic tunnel junction 5. The magnetic domain 111 directly below the magnetic tunnel junction 5 is then switched to a "1" state or a "0" state accordingly through the magnetic coupling effect.

[0073] In some embodiments, see Figure 2 The magnetic tunnel junction 5 can also surround the magnetic track 11. This helps to further achieve continuous scaling of the memory cell, thereby increasing the capacity of the memory cell and further improving the overall performance of the memory cell.

[0074] In some embodiments, see Figure 3 The memory cells are arranged along a first direction (eg, X direction), and adjacent memory cells may also share a first bit line BL1 . Adjacent magnetic tunnel junctions 5 are located on opposite sides of a magnetic track 11 .

[0075] For some examples, see Figure 4In order to further achieve continuous miniaturization of storage cells, adjacent storage cells share the first bit line BL1, and adjacent magnetic tunnel junctions 5 are located on opposite sides of the magnetic track 11. The magnetic tunnel junctions 5 can also surround the magnetic track 11 to achieve high-density magnetic storage, thereby improving the overall performance of the storage structure.

[0076] In some embodiments, see Figure 5 Each all-around gate word line structure 2 includes an active pillar 21 and an all-around gate word line WL. The active pillar 21 includes a source region 211, a channel region 212, and a drain region 213 arranged in sequence along an extension direction (e.g., the X direction). The source region 211 contacts one end of the magnetic track 11, and the drain region 213 contacts the first select line SL1. The all-around gate word line WL surrounds the channel region 212. The magnetic track 11 and the active pillar 21 both extend along a first direction (e.g., the X direction). The plurality of magnetic tracks 11 are arranged in parallel and spaced apart along a second direction (e.g., the Y direction). The second direction (e.g., the Y direction) is perpendicular to the first direction (e.g., the X direction). Each all-around gate word line structure 2 shares the same all-around gate word line WL extending along the second direction (e.g., the Y direction).

[0077] Here, each all-around gate word line structure 2 shares the same all-around gate word line WL extending along the second direction (eg, Y direction), and the all-around gate word line WL can contact the channel region 212 from all sides, thereby further helping to achieve continuous scaling of the memory structure.

[0078] In some examples, the all-around gate word line structure 2 includes a transistor including a source region 211 , a channel region 212 , and a drain region 213 sequentially arranged along an extension direction (eg, an X direction). The gate WL surrounds the channel region 212 .

[0079] Here, each transistor shares the same gate WL extending along the second direction (eg, the Y direction), and the gate WL can contact the channel region 212 from all sides, which helps to further achieve dense stacking of the storage structure and realize a high-density magnetic memory.

[0080] For some examples, see Figure 6 In order to further achieve continuous scaling of memory cells, the memory cells are arranged along a first direction (e.g., the X direction), and adjacent memory cells share a first bit line BL1. Adjacent magnetic tunnel junctions 5 are located on opposite sides of a magnetic track 11, thereby achieving high-density magnetic storage and improving the overall performance of the storage structure.

[0081] For other examples, see Figure 7 In order to further achieve continuous miniaturization of the storage unit, the magnetic tunnel junction 5 can also surround the magnetic runway 11 to achieve high-density magnetic storage, thereby improving the overall performance of the storage structure.

[0082] In some embodiments, see Figure 8 The magnetic track 11 extends along a first direction (e.g., X direction), and multiple magnetic tracks 11 are arranged in parallel and spaced apart along a third direction (e.g., Z direction), which is perpendicular to the first direction (e.g., X direction). The magnetic tracks 11 share a first bit line BL1 extending along the third direction (e.g., Z direction); and the all-around gate word line structures 2 share a first selection line SL1 extending along the third direction (e.g., Z direction).

[0083] In some embodiments of the present disclosure, each memory cell further includes: a second bit line BL2 and a second selection line SL2; the second bit line BL2 and the second selection line SL2 both extend along a third direction (eg, Z direction) to connect the magnetic tunnel junctions 5 of each memory cell in series.

[0084] In some embodiments, the memory cell further includes a second insulating layer 6 . The second insulating layer 6 is located between the second bit line BL2 and the magnetic track 11 , and is in contact with both the second bit line BL2 and the magnetic track 11 .

[0085] In some embodiments, multiple magnetic domains 111 are arranged at intervals. The magnetic track 11 may contain multiple different magnetic domains 111, and adjacent magnetic domains 111 are separated by magnetic domain walls. The arrangement of the magnetic domains (walls) represents the information stored in the magnetic track. A new magnetic domain state can be written into the magnetic track by writing a magnetic tunnel junction, and the arrangement of the magnetic domains can be read out by reading a magnetic tunnel junction, thereby extracting the stored information. The magnetic domains 111 in the magnetic track 11 can move under the action of an external current. When the direction of the external current is changed, the direction of movement of the magnetic domains 111 also changes accordingly. Therefore, the stored magnetic domain pattern can be driven by an external current to pass through the read magnetic tunnel junction or the write magnetic tunnel junction in sequence along the magnetic track, and the magnetic domains 111 can be read or written bit by bit.

[0086] In some embodiments, the number of magnetic domains 111 in the magnetic track 11 is 10 to 100, which helps to achieve ultra-high-density magnetic storage.

[0087] In some embodiments, the magnetization direction of the magnetic domain 111 is parallel or antiparallel to the magnetization direction of the free layer 51 . The magnetic domain 111 directly below the magnetic tunnel junction 5 is tightly coupled to the free layer 51 .

[0088] In some embodiments, see Figure 2 The magnetic tunnel junction 5 surrounds the magnetic track 11. This helps to further achieve continuous scaling of the memory cell, thereby increasing the capacity of the memory cell and further improving the overall performance of the memory cell.

[0089] In some embodiments, a plurality of magnetic domains 111 are defined within the magnetic track 11 .

[0090] For example, the shape of the magnetic tunnel junction 5 can be cylindrical, square, or other possible shapes. That is, the shapes of the free layer 51, the first insulating layer 52, the pinned layer 53, and the selection layer 54 can all be cylindrical, square, or other possible shapes.

[0091] Here, each magnetic track 11 also shares the same second bit line BL2 and second selection line SL2 extending along a third direction (eg, Z direction).

[0092] It can be understood that each magnetic track 11 shares the first bit line BL1, the second bit line BL2 and the second selection line SL2 extending along the third direction (such as the Z direction), and the full-surrounding gate word line WL can contact the channel region 212 from all sides, which helps to further achieve continuous scaling of the storage structure.

[0093] In some examples, the all-around gate word line structure 2 includes a transistor including a source region 211 , a channel region 212 , and a drain region 213 sequentially arranged along an extension direction (eg, an X direction). The gate WL surrounds the channel region 212 .

[0094] Here, each transistor shares the same first bit line BL1, second bit line BL2, and second selection line SL2 extending along a third direction (e.g., the Z direction). Furthermore, the gate WL can contact the channel region 212 from all sides, thereby further achieving dense stacking of the storage structure and realizing a high-density magnetic memory.

[0095] For some examples, see Figure 9 In order to further achieve continuous scaling of memory cells, the memory cells are arranged along a first direction (e.g., the X direction), and adjacent memory cells share a first bit line BL1. Adjacent magnetic tunnel junctions 5 are located on opposite sides of a magnetic track 11, thereby achieving high-density magnetic storage and improving the overall performance of the storage structure.

[0096] In other examples, in order to further achieve continuous scaling of storage units, the magnetic tunnel junction 5 may also surround the magnetic track 11 to achieve high-density magnetic storage, thereby improving the overall performance of the storage structure.

[0097] In some embodiments, see Figure 5 and Figure 8Each all-around gate word line structure 2 includes an active pillar 21 and an all-around gate word line WL. The active pillar 21 includes a source region 211, a channel region 212, and a drain region 213 sequentially arranged along an extension direction (e.g., X direction); the source region 211 contacts one end of the magnetic track 11, and the drain region 213 contacts the first selection line SL1; the all-around gate word line WL surrounds the channel region 212; multiple magnetic tracks 11 and multiple active pillars 21 are arranged in multiple rows and columns ( Figure 5 This is a front view of the storage structure of this embodiment. Figure 8 ( is a top view of the memory structure of this embodiment). Each magnetic track 11 and each active pillar 21 extends along a first direction (e.g., the X direction); a fully surrounding gate word line WL extends along a second direction (e.g., the Y direction) to sequentially connect the active pillars 21 in the same column; a first bit line BL1 extends along a third direction (e.g., the Z direction) to sequentially connect the magnetic tracks 11 in the same row; and a first select line SL1 extends along a third direction (e.g., the Z direction) to sequentially connect the active pillars 21 in the same row. The first direction (e.g., the X direction) is perpendicular to the second direction (e.g., the Y direction), and the third direction (e.g., the Z direction) is perpendicular to both the first direction (e.g., the X direction) and the second direction (e.g., the Y direction).

[0098] In some embodiments of the present disclosure, each memory cell further includes: a second bit line BL2 and a second selection line SL2; the second bit line BL2 and the second selection line SL2 both extend along a third direction (eg, Z direction) to connect the magnetic tunnel junctions 5 of each memory cell in series.

[0099] Here, each magnetic track 11 also shares the same second bit line BL2 and second selection line SL2 extending along a third direction (eg, Z direction).

[0100] It can be understood that each magnetic track 11 shares a first bit line BL1, a second bit line BL2, and a second selection line SL2 extending along a third direction (e.g., the Z direction), and each fully surrounding gate word line structure 2 shares the same fully surrounding gate word line WL extending along the second direction (e.g., the Y direction), and the fully surrounding gate word line WL can contact the channel region 212 from all sides, which helps to further achieve continuous scaling of the storage structure.

[0101] In some examples, the all-around gate word line structure 2 includes a transistor including a source region 211 , a channel region 212 , and a drain region 213 sequentially arranged along an extension direction (eg, an X direction). The gate WL surrounds the channel region 212 .

[0102] Here, each transistor shares the same first bit line BL1, second bit line BL2 and second selection line SL2 extending along the second direction (for example, the Y direction), and each transistor shares the same gate WL extending along the second direction (for example, the Y direction), and the gate WL can contact the channel region 212 from all sides, which helps to further achieve tight stacking of the storage structure and realize high-density magnetic memory.

[0103] In some examples, in order to further achieve continuous scaling of storage cells, the storage cells are arranged along a first direction (e.g., the X direction), and adjacent storage cells share a first bit line BL1, and adjacent magnetic tunnel junctions 5 are located on opposite sides of the magnetic track 11, thereby achieving high-density magnetic storage and improving the overall performance of the storage structure.

[0104] In other examples, in order to further achieve continuous scaling of storage units, the magnetic tunnel junction 5 may also surround the magnetic track 11 to achieve high-density magnetic storage, thereby improving the overall performance of the storage structure.

[0105] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A storage unit, characterized in that: include: A magnetic memory includes a magnetic racetrack having a plurality of magnetic domains disposed therein; a full surround gate wordline structure, located at one end of the magnetic racetrack and connected to the magnetic racetrack; A first selection line is located at one end of the full-surround gate word line structure away from the magnetic racetrack and is connected to the full-surround gate word line structure; a first bit line, located at an end of the magnetic track away from the all-around gate word line structure and connected to the magnetic track; The magnetic tunnel junction is located outside the magnetic racetrack.

2. The storage unit according to claim 1, wherein The all-around gate wordline structure includes: an active pillar, the active pillar comprising a source region, a channel region, and a drain region sequentially arranged along an extension direction; the source region contacts one end of the magnetic track, and the drain region contacts the first selection line; A fully surrounding gate word line surrounds the channel region.

3. The storage unit according to claim 1, wherein The magnetic tunnel junction includes a free layer, a first insulating layer, a pinning layer and a selection layer stacked in sequence from bottom to top.

4. The storage unit according to claim 3, wherein: The magnetic tunnel junction further comprises: The second bit line is located between the magnetic tunnel junction and the magnetic racetrack and contacts the magnetic tunnel junction.

5. The storage unit according to claim 4, wherein: The magnetic tunnel junction further comprises: The second selection line is located on a surface of the magnetic tunnel junction away from the second bit line. The storage unit according to claim 5 , wherein: Also includes: The second insulating layer is located between the second bit line and the magnetic track, and is in contact with both the second bit line and the magnetic track.

7. The storage unit according to claim 1, wherein: The plurality of magnetic domains are arranged at intervals.

8. The storage unit according to claim 1, wherein: In the magnetic runway, the number of the magnetic domains is 10 to 100.

9. The storage unit according to claim 3, wherein: The magnetization direction of the magnetic domain is parallel or antiparallel to the magnetization direction of the free layer.

10. The storage unit according to claim 1, wherein The magnetic tunnel junction surrounds the magnetic racetrack.

11. A storage structure, characterized in that: include: A plurality of storage cells according to any one of claims 1 to 10.

12. The storage structure according to claim 11, characterized in that: The memory cells are arranged along a first direction, and adjacent memory cells share a first bit line. Adjacent magnetic tunnel junctions are located on two opposite sides of a magnetic track.

13. The storage structure according to claim 11 or 12, characterized in that: Each of the fully surrounding gate word line structures includes an active pillar and a fully surrounding gate word line, the active pillar includes a source region, a channel region and a drain region arranged in sequence along the extension direction; the source region contacts one end of the magnetic runway, and the drain region contacts the first selection line; the fully surrounding gate word line surrounds the channel region; the magnetic runway and the active pillar both extend along the first direction, and multiple magnetic runways are arranged in parallel and at intervals along the second direction, and the second direction is perpendicular to the first direction; each of the fully surrounding gate word line structures shares the same fully surrounding gate word line extending along the second direction.

14. The storage structure according to claim 11 or 12, characterized in that: The magnetic track extends along a first direction, and a plurality of the magnetic tracks are arranged in parallel and spaced apart along a third direction, wherein the third direction is perpendicular to the first direction; each of the magnetic tracks shares the same first bit line extending along the third direction; each of the full-surround gate word line structures shares the same first selection line extending along the third direction.

15. The storage structure according to claim 14, characterized in that: Each of the storage units further includes: A second bit line and a second selection line; the second bit line and the second selection line both extend along the third direction to connect the magnetic tunnel junctions of the memory cells in series.

16. The storage structure according to claim 11 or 12, characterized in that: Each of the fully surrounding gate word line structures includes an active pillar and a fully surrounding gate word line, the active pillar includes a source region, a channel region and a drain region arranged in sequence along the extension direction; the source region is in contact with one end of the magnetic runway, and the drain region is in contact with the first selection line; the fully surrounding gate word line surrounds the channel region; multiple magnetic runways and multiple active pillars are arranged in multiple rows and columns; each of the magnetic runways and each of the active pillars extends along the first direction; the fully surrounding gate word line extends along the second direction to connect the active pillars in the same column in series in sequence; the first bit line extends along the third direction to connect the magnetic runways in the same row in series; the first selection line extends along the third direction to connect the active pillars in the same row in series in sequence; the first direction is perpendicular to the second direction, and the third direction is perpendicular to both the first direction and the second direction.

17. The storage structure according to claim 16, characterized in that: Each of the memory cells further includes a second bit line and a second selection line. The second bit line and the second selection line both extend along the third direction to connect the magnetic tunnel junctions of each of the memory cells in series.

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