Display device

Abstract

A display device includes a first pixel and a second pixel. Each of the first pixel and the second pixel includes: a first transistor; a portion of a via layer disposed on the first transistor; and a portion of a first metal layer disposed on the via layer. The first pixel further comprises a first pixel electrode arranged in the first metal layer, and the second pixel further comprises a second pixel electrode arranged in the first metal layer. And the first pixel electrode has a first end portion facing the second pixel electrode and positioned at a height lower than a height of the second pixel electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0072708 filed in the Korean Intellectual Property Office on June 7, 2023 and all the benefits obtained therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As multimedia technologies develop, the importance of display devices has steadily increased. Therefore, various types of display devices, such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices, have been developed.

[0005] Among the display devices, the self-luminous display device includes a self-luminous element such as an organic light-emitting element. The self-luminous element may include two opposing electrodes and a light-emitting layer disposed therebetween. As a next-generation display device, the self-luminous display device has attracted much attention because it can meet high display quality requirements such as a wide viewing angle, high brightness and contrast, and a fast response speed, and because it does not require a separate light source such as a backlight unit, it can provide low power consumption, light weight, and a thin profile.

[0006] The self-luminous display device may include various circuit layers for driving the light-emitting layer. Such a circuit layer may be formed by one or more patterning processes using a mask. As the number of masks and the number of layers constituting the circuit layer decreases, the process efficiency may be improved. In addition, the height difference or spacing between the light-emitting layer and the transistor for driving the light-emitting layer may be reduced. Summary of the invention

[0007] Aspects of the present disclosure provide a display device that reduces, minimizes, or prevents light emitted from a pixel from being incident on a transistor within the pixel.

[0008] Aspects of the present disclosure also provide a display device that reduces, minimizes, or prevents light-induced degradation of transistors.

[0009] The aspects of the present disclosure are not limited to the specific examples set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description given below.

[0010] According to one aspect of the present disclosure, a display device includes a first pixel and a second pixel, wherein the first pixel and the second pixel each include: a first transistor; a portion of a via layer disposed on the first transistor; and a portion of a first metal layer disposed on the via layer. The first pixel and the second pixel may also include a first pixel electrode and a second pixel electrode disposed in the first metal layer, respectively, and a first end portion of the first pixel electrode facing the second pixel electrode is positioned at a height lower than that of the second pixel electrode.

[0011] In an embodiment, the via layer includes a peak and a valley, a thickness of the peak is greater than a thickness of the valley, the first end is positioned on the valley, and the second pixel electrode is positioned on the peak.

[0012] In an embodiment, the thickness of the peak is 3 to 5 times the thickness of the valley.

[0013] In an embodiment, the via layer includes a valley region, the valley region being a region where the valley is located, and the valley region is disposed between the first transistor and the second pixel electrode of the first pixel in a plan view.

[0014] In an embodiment, the display device may further include a pixel defining layer disposed on the first metal layer, wherein the pixel defining layer includes a plurality of opening portions overlapping at least a portion of the first pixel electrode and the second pixel electrode, and the plurality of opening portions do not overlap the valley region.

[0015] In an embodiment, the plurality of opening portions are disposed on the peaks.

[0016] In an embodiment, the valley region is disposed to surround at least a portion of the first transistor of the first pixel in a plan view.

[0017] In an embodiment, the valley region is disposed to surround one side of the first transistor of the first pixel, the one side facing the second pixel electrode, in a plan view.

[0018] In an embodiment, the display device may further include a third pixel including a third pixel electrode disposed in the first metal layer, and a second end portion of the second pixel electrode facing the third pixel electrode is positioned at a height lower than that of the third pixel electrode.

[0019] In an embodiment, the valley region includes: a first region overlapping the first end; a second region overlapping the second end; and a third region connecting the first region to the second region.

[0020] In an embodiment, the first region is disposed to surround one side of the first transistor of the first pixel in a plan view, the one side facing the second pixel electrode.

[0021] In an embodiment, in a plan view, the second region is disposed between the third pixel electrode and one side of the first transistor of the second pixel, the one side facing the third pixel electrode.

[0022] In an embodiment, the third region is disposed to surround one side of the first transistor of the second pixel in a plan view, the one side facing the first pixel electrode.

[0023] In an embodiment, the first region overlaps with the first transistor of the first pixel.

[0024] In an embodiment, the valley region further includes a fourth region protruding from the third region, and in a plan view, the fourth region is disposed between the first pixel electrode and the first transistor of the second pixel.

[0025] In an embodiment, each of the first pixel and the second pixel further includes a first capacitor connected to the corresponding first transistor, and the first capacitor of each of the first pixel and the second pixel overlaps the corresponding peak.

[0026] In an embodiment, in a thickness direction of the via layer, no other metal layer is disposed between the first metal layer and the first transistor of the first pixel.

[0027] In an embodiment, each of the first pixel and the second pixel further includes: a light-emitting layer disposed on the first metal layer; and a second metal layer disposed on the light-emitting layer, wherein the first transistor of each of the first pixel and the second pixel is a driving transistor configured to drive light emission of the light-emitting layer.

[0028] According to one aspect of the present disclosure, a display device is provided, the display device comprising a first pixel and a second pixel. The first pixel and the second pixel each comprise: a first transistor; a portion of a via layer disposed on the first transistor; and a portion of a first metal layer disposed on the via layer. The first pixel and the second pixel further comprise a first pixel electrode and a second pixel electrode disposed in the first metal layer, respectively, and a portion of the first pixel electrode overlapping with the first transistor of the first pixel is positioned at a height lower than a height of the second pixel electrode.

[0029] In an embodiment, a first end portion of the first pixel electrode facing the second pixel electrode is positioned at the same height as the second pixel electrode.

[0030] In an embodiment, the via layer includes peaks and valleys, the thickness of the peaks is greater than the thickness of the valleys, the portion of the first pixel electrode overlapping the first transistor of the first pixel is positioned on the valleys, and the second pixel electrode is positioned on the peaks.

[0031] In an embodiment, in a thickness direction of the via layer, no other metal layer is disposed between the first metal layer and the first transistor of the first pixel.

[0032] In a display device according to one embodiment of the present disclosure, the incidence of light emitted from an adjacent pixel on a transistor within its own pixel can be reduced or minimized.

[0033] In the display device according to one embodiment of the present disclosure, light-induced degradation of transistors may be reduced or minimized.

[0034] However, the effects according to the embodiments of the present disclosure are not limited to the effects exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0036] Figure 1 is a plan view showing a display device according to an embodiment.

[0037] Figure 2 An arrangement of pixels and lines in a portion of a display device according to an embodiment is shown.

[0038] Figure 3 is an equivalent circuit diagram of a pixel according to one embodiment.

[0039] Figure 4 A layout diagram of a portion of a display panel including pixels according to an embodiment is shown.

[0040] Figure 5 is a cross-sectional view of a display panel according to a comparative example.

[0041] Figure 6 is along Figure 4 A cross-sectional view taken along line X1-X1'.

[0042] Figure 7 is along Figure 4 A cross-sectional view taken along line X2-X2' and line X3-X3'.

[0043] Figure 8 is along Figure 4 A cross-sectional view taken along line X4-X4'.

[0044] Fig. 9 is a plan view of a valley region according to one embodiment.

[0045] Fig.10 is a layout diagram of a portion of a display panel according to another embodiment.

[0046] Fig.11 is along Fig.10 A cross-sectional view taken along line X5-X5'.

[0047] Fig.12 yes Fig.10 Floor plan of the valley area in the layout.

[0048] Fig.13 is a layout diagram of a portion of a display panel according to another embodiment.

[0049] Fig.14 is along Fig.13 A cross-sectional view taken along line X6-X6'.

[0050] Fig.15 yes Fig.13 A plan view of the valley region of an embodiment of the present invention.

[0051] Fig.16 is a layout diagram of a portion of a display panel according to another embodiment.

[0052] Fig.17 is along Fig.16 A cross-sectional view taken along line X7-X7'.

[0053] Fig.18 yes Fig.16 A plan view of the valley region of an embodiment of the present invention.

[0054] Fig.19 is a layout diagram of a portion of a display panel according to another embodiment.

[0055] Fig. 20 is along Fig.19 A cross-sectional view taken along line X8-X8'.

[0056] Fig.21 is a layout diagram of a display panel according to another embodiment.

[0057] Fig. 22 is a layout diagram of a display panel according to another embodiment. DETAILED DESCRIPTION

[0058] Now, embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the disclosed subject matter to those skilled in the art.

[0059] It will be understood below that when a layer or structure is referred to as being "on" another layer or structure (e.g., a substrate), the layer or structure may be directly on the other layer or structure (e.g., substrate), or intervening layers or structures may also be present. Throughout the specification, the same reference numerals represent the same components.

[0060] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0061] Figure 1 is a plan view showing a display device according to an embodiment.

[0062] refer to Figure 1 The display device 1, which is a device for displaying moving images or still images, can be used as a display screen of various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0063] The display device 1 may include a display panel 100 , a flexible film 210 , a display driver 220 , a circuit board 230 , a timing controller 240 , a power supply unit 250 , and a gate driver 260 .

[0064] The display panel 100 may have a rectangular shape in a plan view. For example, the display panel 100 may have a rectangular shape in a plan view, the rectangular shape having a long side extending in the first direction DR1 and a short side extending in the second direction DR2. The corner where the long side and the short side intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangular shape, and may be formed in other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 may be flat, but is not limited thereto. For example, the display panel 100 may be curved with a predetermined curvature.

[0065] In the illustrated figures, the first direction DR1 and the second direction DR2 intersect each other as horizontal directions and define a horizontal plane. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. The third direction DR3 intersects the plane of the first direction DR1 and the second direction DR2, and the first direction DR1, the second direction DR2, and the third direction DR3 may be, for example, vertical directions orthogonal to each other. In this specification, the direction indicated by the arrow of the first direction DR1, the arrow of the second direction DR2, and the arrow of the third direction DR3 may be referred to as one side, and the opposite direction may be referred to as the other side.

[0066] The display panel 100 may include a display area DA and a non-display area NDA.

[0067] The display area DA, which is an area for displaying an image, may be defined as a central area of ​​the display panel 100 . Figure 1 The display area DA is shown to include pixels SP, gate lines GL, data lines DL, initialization voltage lines VIL, first voltage lines VDL, horizontal voltage lines HVDL, vertical voltage lines VVSL, and second voltage lines VSL. More generally, the display area DA includes a plurality of pixel areas each arranged in an array.

[0068] The pixel SP may be formed in each pixel area where the data line DL and the gate line GL intersect. The pixel SP may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. In particular, each of the pixels SP may include a group of three pixels SP1, SP2, and SP3, and the pixels SP1, SP2, and SP3 may be considered as sub-pixels of the pixel SP including the pixels SP1, SP2, and SP3. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be connected to the gate line GL and the data line DL. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be a minimum unit area of ​​output light.

[0069] Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may include an organic light emitting diode (OLED) having an organic light emitting layer, a quantum dot light emitting diode (LED) including a quantum dot light emitting layer, a micro LED, or an inorganic LED having an inorganic semiconductor.

[0070] The first pixel SP1 may emit light of a first color such as red light, the second pixel SP2 may emit light of a second color such as green light, and the third pixel SP3 may emit light of a third color such as blue light. The pixel circuits of the second pixel SP2, the first pixel SP1, and the third pixel SP3 among the pixels SP may be sequentially arranged in the reverse direction of the second direction DR2, but the arrangement direction of the pixel circuits is not limited thereto.

[0071] Each of the gate lines GL may include a first gate line GL1 and a second gate line GL2 .

[0072] The first gate lines GL1 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The first gate lines GL1 may receive a first gate signal from the gate driver 260 and may supply the first gate signal to the first, second, and third pixels SP1, SP2, and SP3.

[0073] The second gate lines GL2 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The second gate lines GL2 may receive a second gate signal from the gate driver 260 and may supply the second gate signal to the first, second, and third pixels SP1, SP2, and SP3.

[0074] The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3. Each of the first data line DL1, the second data line DL2, and the third data line DL3 may supply a data voltage to a corresponding one of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0075] The initialization voltage lines VIL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The initialization voltage lines VIL may supply an initialization voltage received from the display driver 220 to a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The initialization voltage lines VIL may receive a sensing signal from a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 to supply the sensing signal to the display driver 220.

[0076] The first voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The first voltage lines VDL may supply a driving voltage or a high potential voltage received from the power supply unit 250 to the first, second, and third pixels SP1, SP2, and SP3.

[0077] The horizontal voltage lines HVDL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The horizontal voltage lines HVDL may be connected to the first voltage lines VDL. The horizontal voltage lines HVDL may receive a driving voltage or a high potential voltage from the first voltage lines VDL.

[0078] The vertical voltage lines VVSL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The vertical voltage lines VVSL may be connected to the second voltage line VSL. The vertical voltage lines VVSL may supply a low potential voltage received from the power supply unit 250 to the second voltage line VSL.

[0079] The second voltage lines VSL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2 The second voltage line VSL may supply a low potential voltage to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0080] The connection relationship among the pixels SP, the gate line GL, the data line DL, the initialization voltage line VIL, the first voltage line VDL, and the second voltage line VSL may be changed according to the number and arrangement of the pixels SP.

[0081] The non-display area NDA may be defined as the remaining area outside the display area DA of the display panel 100. The non-display area NDA may include, for example, a fan-out line connecting the data line DL, the initialization voltage line VIL, the first voltage line VDL, and the vertical voltage line VVSL to the display driver 220, the gate driver 260, and a pad portion (not shown) connected to the flexible film 210.

[0082] The flexible film 210 may be connected to the pad portion and may extend under the non-display area NDA. The input terminal provided on one side of the flexible film 210 may be attached to the circuit board 230 by a film attachment process, and the output terminal provided on the other side of the flexible film 210 may be attached to the pad portion by a film attachment process. For example, the flexible film 210 may be bent like a tape carrier package or a chip on film. The flexible film 210 may be bent toward the lower portion of the display panel 100 to reduce the frame area of ​​the display device 1.

[0083] The display driver 220 may be mounted on the flexible film 210. For example, the display driver 220 may be implemented as an integrated circuit (IC). The display driver 220 may receive digital video data and a data control signal from the timing controller 240, and according to the data control signal, the display driver 220 may convert the digital video data into an analog data voltage to supply the analog data voltage to the data line DL through the fan-out line.

[0084] The circuit board 230 may support the timing controller 240 and the power supply unit 250, and supply signals and power to the display driver 220. For example, the circuit board 230 may supply a signal from the timing controller 240 and a power voltage from the power supply unit 250 to the flexible film 210 and the display driver 220 to emit light from the pixel SP1, SP2, or SP3. To this end, a signal line and a power line may be provided on the circuit board 230.

[0085] The timing controller 240 may be mounted on the circuit board 230, and receive image data and a timing synchronization signal from a display driving system or a graphics device through a user connector provided on the circuit board 230. The timing controller 240 may generate digital video data by arranging the image data into a suitable pixel arrangement structure based on the timing synchronization signal, and may supply the generated digital video data to the display driver 220. The timing controller 240 may generate a data control signal and a gate control signal based on the timing synchronization signal. The timing controller 240 may control the data voltage supply timing of the display driver 220 based on the data control signal, and may control the gate signal supply timing of the gate driver 260 based on the gate control signal.

[0086] The power supply unit 250 may be disposed on the circuit board 230 to supply a power voltage to the flexible film 210 and the display driver 220. For example, the power supply unit 250 may generate a driving voltage or a high potential voltage and supply it to the first voltage line VDL, may generate a low potential voltage and supply it to the vertical voltage line VVSL, and may generate an initialization voltage and supply it to the initialization voltage line VIL.

[0087] The gate driver 260 may be disposed on the left and right sides of the non-display area NDA. The gate driver 260 may generate a gate signal based on a gate control signal supplied from the timing controller 240. The gate control signal may include a start signal, a clock signal, and a power voltage, but the present disclosure is not limited thereto. The gate driver 260 may supply the gate signal to the gate line GL according to a set order.

[0088] Figure 2 An arrangement of pixels and lines in a portion of a display device according to an embodiment is shown.

[0089] refer to Figure 2 , also refer to Figure 1 , the pixel circuits of the second pixel SP2, the first pixel SP1, and the third pixel SP3 may be sequentially arranged in the reverse direction of the second direction DR2, but the arrangement of the pixel circuits is not limited thereto.

[0090] Each of the first pixel SP1 , the second pixel SP2 , and the third pixel SP3 may be connected to a first voltage line VDL, an initialization voltage line VIL, a gate line GL, and a data line DL associated with a corresponding pixel.

[0091] The first voltage line VDL may extend in the second direction DR2. The first voltage line VDL may be disposed on the left side of the pixel circuit of the first pixel SP1, the pixel circuit of the second pixel SP2, and the pixel circuit of the third pixel SP3. The first voltage line VDL may supply a driving voltage or a high potential voltage to a transistor of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0092] The horizontal voltage line HVDL may extend in the first direction DR1. The k-th horizontal voltage line HVDL may be disposed in the k+1-th row ROW. k+1 (k is a positive integer) above the first gate line GL1 disposed in . The horizontal voltage line HVDL may be connected to the first voltage line VDL. The horizontal voltage line HVDL may receive a driving voltage or a high potential voltage from the first voltage line VDL.

[0093] The initialization voltage line VIL may extend in the second direction DR2. The initialization voltage line VIL may be disposed on the left side of an auxiliary line of the second gate line GL2, the auxiliary line branching from the second gate line GL2 in the second direction DR2. The initialization voltage line VIL may be disposed between the auxiliary line of the second gate line GL2 branching in the second direction DR2 and the vertical voltage line VVSL. The initialization voltage line VIL may supply an initialization voltage to a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The initialization voltage line VIL may receive a sensing signal from a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 to supply the sensing signal to the display driver 220.

[0094] The vertical voltage line VVSL may extend in the second direction DR2. The vertical voltage line VVSL may be disposed on the left side of the initialization voltage line VIL. The vertical voltage line VVSL may be connected between the power supply unit 250 and the second voltage line VSL. The vertical voltage line VVSL may supply a low potential voltage supplied from the power supply unit 250 to the second voltage line VSL.

[0095] The second voltage line VSL may extend in the first direction DR1. The k-th second voltage line VSL may be disposed in the k-th row ROW. k The second voltage line VSL may supply the low potential voltage received from the vertical voltage line VVSL to the light emitting element layers EML (see Figure 6).

[0096] The first gate line GL1 may extend in the first direction DR1. The first gate line GL1 may be disposed above the pixel circuit of the second pixel SP2. At least a portion of the first gate line GL1 may extend in a direction opposite to the second direction DR2. For example, the first gate line GL1 may include an auxiliary line that branches in a direction opposite to the second direction DR2 and extends immediately to the right of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The auxiliary line of the first gate line GL1 may be disposed on the right side of the pixel circuit of the first pixel SP1, the pixel circuit of the second pixel SP2, and the pixel circuit of the third pixel SP3. The first gate line GL1 may supply the first gate signal received from the gate driver 260 to the pixel circuit of the first pixel SP1, the pixel circuit of the second pixel SP2, and the pixel circuit of the third pixel SP3 through the auxiliary line extending in a direction opposite to the second direction DR2.

[0097] The second gate line GL2 may extend in the first direction DR1. The second gate line GL2 may be disposed below the pixel circuit of the third pixel SP3. At least a portion of the second gate line GL2 may extend in the second direction DR2. For example, the second gate line GL2 may include an auxiliary line that branches in the second direction DR2 and extends immediately to the left side of the first voltage line VDL. The auxiliary line of the second gate line GL2 may be disposed on the left side of the first voltage line VDL. The second gate line GL2 may supply the second gate signal received from the gate driver 260 to the pixel circuit of the first pixel SP1, the pixel circuit of the second pixel SP2, and the pixel circuit of the third pixel SP3 through the auxiliary line extending in the second direction DR2.

[0098] The data lines DL may extend in the second direction DR2. Each of the data lines DL may supply a data voltage to a pixel SP connected to the corresponding data line DL. The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3.

[0099] The first data line DL1 may extend in the second direction DR2. The first data line DL1 may be disposed on the right side of the auxiliary line of the first gate line GL1. The first data line DL1 may supply a data voltage received from the display driver 220 to a pixel circuit of the first pixel SP1.

[0100] The third data line DL3 may extend in the second direction DR2. The third data line DL3 may be disposed on the right side of the first data line DL1. The third data line DL3 may supply a data voltage received from the display driver 220 to a pixel circuit of the third pixel SP3.

[0101] The second data line DL2 may extend in the second direction DR2. The second data line DL2 may be disposed on the right of the third data line DL3. The second data line DL2 may supply a data voltage received from the display driver 220 to a pixel circuit of the second pixel SP2.

[0102] Figure 3 is an equivalent circuit diagram of a pixel according to one embodiment.

[0103] refer to Figure 3 , which can be Figure 2 The pixel shown in any one of the first pixel SP1, the second pixel SP2 and the third pixel SP3 shown in the figure can be connected to the first voltage line VDL, the data line DL, the initialization voltage line VIL, the first gate line GL1, the second gate line GL2 and the vertical voltage line VVSL related to the pixel. Therefore, each of the first pixel SP1, the second pixel SP2 and the third pixel SP3 may include a pixel circuit and a light emitting element ED. The pixel circuit of each of the first pixel SP1, the second pixel SP2 and the third pixel SP3 may include a first transistor ST1, a second transistor ST2 and a third transistor ST3 and a first capacitor C1.

[0104] The first transistor ST1 may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor ST1 may be connected to the first node N1, the drain electrode of the first transistor ST1 may be connected to the first voltage line VDL, and the source electrode of the first transistor ST1 may be connected to the second node N2. The first transistor ST1 may control a drain-source current (or a driving current) based on a data voltage applied to the gate electrode of the first transistor ST1. The first transistor ST1 may be a driving transistor for driving the light emitting element ED.

[0105] The light emitting element ED may emit light in response to a driving current. The amount of light emission or brightness generated by the light emitting element ED may be proportional to the magnitude of the driving current. The light emitting element ED may be an organic light emitting diode (OLED) having an organic light emitting layer, a quantum dot light emitting diode (LED) including a quantum dot light emitting layer, a micro LED, or an inorganic LED having an inorganic semiconductor.

[0106] A first electrode of the light emitting element ED may be connected to the second node N2, and a second electrode of the light emitting element ED may be connected to the vertical voltage line VVSL. The first electrode of the light emitting element ED may be connected to the source electrode of the first transistor ST1, the drain electrode of the third transistor ST3, and the first capacitor electrode of the first capacitor C1 through the second node N2.

[0107] The gate electrode of the second transistor ST2 may be connected to the first gate line GL1, the drain electrode of the second transistor ST2 may be connected to the data line DL, and the source electrode of the second transistor ST2 may be connected to the first node N1. The source electrode of the second transistor ST2 may be connected to the gate electrode of the first transistor ST1 and the second capacitor electrode of the first capacitor C1 through the first node N1. The second transistor ST2 may be turned on or off according to the first gate signal from the first gate line GL1. Therefore, the first gate signal from the first gate line GL1 may turn on the second transistor ST2 to electrically connect the data line DL to the first node N1, and the first node N1 is the gate electrode of the first transistor ST1 or is electrically connected to the gate electrode of the first transistor ST1. The second transistor ST2 may be a switching transistor for controlling a current flowing through the first transistor ST1 and the light emitting element ED.

[0108] The gate electrode of the third transistor ST3 may be connected to the second gate line GL2, the drain electrode of the third transistor ST3 may be connected to the second node N2, and the source electrode of the third transistor ST3 may be connected to the initialization voltage line VIL. The drain electrode of the third transistor ST3 may be connected to the source electrode of the first transistor ST1, the first capacitor electrode of the first capacitor C1, and the first electrode of the light emitting element ED through the second node N2. The third transistor ST3 may be turned on or off according to the second gate signal. Specifically, the third transistor ST3 may be turned on by the second gate signal from the second gate line GL2 to electrically connect the initialization voltage line VIL to the second node N2, and the second node N2 is the source electrode of the first transistor ST1 or is connected to the source electrode of the first transistor ST1. The third transistor ST3 may be turned on according to the second gate signal to supply the sensing signal to the initialization voltage line VIL. The third transistor ST3 may be a switching transistor for controlling the current flowing through the first transistor ST1 and the light emitting element ED.

[0109] Figure 4 A layout diagram of a portion of a display panel including pixels according to an embodiment is shown. Figure 5 is a cross-sectional view of a display panel according to a comparative example. Figure 6 is along Figure 4 A cross-sectional view taken along line X1-X1'. Figure 7 is along Figure 4 A cross-sectional view taken along line X2-X2' and line X3-X3'. Figure 8 is along Figure 4 A cross-sectional view taken along line X4-X4'. Fig. 9 is a plan view of a valley region according to one embodiment. Figure 4 The light emitting layer LEL is not shown in the layout diagram (see Figure 5) and the common electrode CME (see Figure 5 ).

[0110] Figure 4 FIG. 1 shows a layout diagram of a pixel SP including a first pixel SP1, a second pixel SP2, and a third pixel SP3. Figures 4 to 9 , since the cross sections of the first transistor ST1 of the first pixel SP1, the second pixel SP2, and the third pixel SP3 are similar to each other, the cross section of the first transistor ST1 of the third pixel SP3 is shown as a representative. In addition, since the cross sections of the second transistor ST2 of the first pixel SP1, the second pixel SP2, and the third pixel SP3 are similar to each other, the cross section of the second transistor ST2 of the third pixel SP3 is shown as a representative. Since the cross sections of the third transistor ST3 of the first pixel SP1, the second pixel SP2, and the third pixel SP3 are similar to each other, the cross section of the third transistor ST3 of the second pixel SP2 is shown as a representative.

[0111] Apart from Figure 3 In addition, refer to Figures 4 to 9 , the display panel may include a substrate 110 , a thin film transistor layer TFTL, and a light emitting element layer EML.

[0112] The substrate 110 may include a transparent material. For example, the substrate 110 may include a transparent insulating material such as glass or quartz. The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto and may include a plastic such as polyimide and may have a flexible property that allows it to be warped, bent, folded, or curled.

[0113] The thin film transistor layer TFTL may be disposed on the substrate 110. The thin film transistor layer TFTL may include a first metal layer MTL1 disposed on the substrate 110, a buffer layer BF covering the first metal layer MTL1, an active layer ACTL disposed on the buffer layer BF, a gate insulating layer GI covering the active layer ACTL, a second metal layer MTL2 disposed on the gate insulating layer GI, a passivation layer PV covering the second metal layer MTL2, and a via layer VIA covering the passivation layer PV.

[0114] The first metal layer MTL1 may include a vertical voltage line VVSL, an initialization voltage line VIL, a first voltage line VDL, a data line DL, and a first capacitor electrode CPE1.

[0115] The active layer ACTL may include first, second, and third drain electrodes DE1, DE2, and DE3, first, second, and third source electrodes SE1, SE2, and SE3, first, second, and third active regions ACT1, ACT2, and ACT3, and a second capacitor electrode CPE2.

[0116] The second metal layer MTL2 may include a horizontal voltage line HVDL, a first gate line GL1, a second gate line GL2, a second voltage line VSL, and a first gate electrode GE1, a second gate electrode GE2 and a third gate electrode GE3, a first connection electrode CE1, a second connection electrode CE2, a third connection electrode CE3, a fourth connection electrode CE4, a fifth connection electrode CE5, a sixth connection electrode CE6, a seventh connection electrode CE7, an eighth connection electrode CE8 and a ninth connection electrode CE9, and a first auxiliary electrode AUE1 and a second auxiliary electrode AUE2.

[0117] The buffer layer BF may be disposed on (eg, cover) the first metal layer MTL1. The buffer layer BF may be formed of a plurality of layers in which one or more inorganic layers of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

[0118] The gate insulating layer GI may be disposed on (eg, cover) the active layer ACTL. The gate insulating layer GI may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y )

[0119] The passivation layer PV may be disposed on the second metal layer MTL2 (eg, covering the second metal layer MTL2). The passivation layer PV may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. However, the passivation layer PV is not limited thereto and may be made of an organic insulating material such as polyimide (PI).

[0120] The via layer VIA may include an organic insulating material such as polyimide (PI), and may compensate for a stepped portion formed by a conductive layer disposed thereunder to planarize a top surface on which the light emitting element layer EML is formed.

[0121] like Figure 4 The pixel SP shown in FIG. 1 may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. The pixel circuits of the second pixel SP2, the first pixel SP1, and the third pixel SP3 may be arranged in the opposite direction of the second direction DR2, but the arrangement of the pixel circuits is not limited thereto.

[0122] The first voltage line VDL may extend in the second direction DR2. Figure 4In a plan view of FIG. 1 , the first voltage line VDL may be disposed on the left side of the pixel circuit of the first pixel SP1, the pixel circuit of the second pixel SP2, and the pixel circuit of the third pixel SP3. The first voltage line VDL may be disposed in the first metal layer MTL1 on the substrate 110. The first voltage line VDL may overlap the first connection electrode CE1 and the fourth connection electrode CE4 of the second metal layer MTL2.

[0123] The first connection electrode CE1 and the fourth connection electrode CE4 may extend in the first direction DR1 and the second direction DR2. The first connection electrode CE1 and the fourth connection electrode CE4 may be disposed in the second metal layer MTL2. The first connection electrode CE1 and the fourth connection electrode CE4 may be connected to the first voltage line VDL through a via hole. The first voltage line VDL may reduce line resistance by being connected to the first connection electrode CE1 and the fourth connection electrode CE4.

[0124] The first connection electrode CE1 may be connected to the first drain electrode DE1 of the first transistor ST1 of the second pixel SP2. Therefore, the first voltage line VDL may supply a driving voltage to the second pixel SP2 through the first connection electrode CE1.

[0125] The fourth connection electrode CE4 may be connected to the first drain electrode DE1 of the first transistor ST1 of each of the first pixel SP1 and the third pixel SP3. Therefore, the first voltage line VDL may supply a driving voltage to the first pixel SP1 and the third pixel SP3 through the fourth connection electrode CE4.

[0126] The first voltage line VDL may be connected to the horizontal voltage line HVDL to supply a driving voltage. The horizontal voltage line HVDL may extend in the first direction DR1. In a plan view, the horizontal voltage line HVDL may be disposed above the first gate line GL1 or below the second gate line GL2. The horizontal voltage line HVDL may be disposed in the second metal layer MTL2. The horizontal voltage line HVDL may be connected to the first voltage line VDL to receive a driving voltage.

[0127] The initialization voltage line VIL may extend in the second direction DR2. In a plan view, the initialization voltage line VIL may be disposed on the left side of the first voltage line VDL. The initialization voltage line VIL may be disposed in the first metal layer MTL1. The initialization voltage line VIL may overlap with the second auxiliary electrode AUE2 of the second metal layer MTL2 and may be electrically connected to the second auxiliary electrode AUE2. The initialization voltage line VIL may reduce line resistance by being connected to the second auxiliary electrode AUE2.

[0128] The second auxiliary electrode AUE2 may extend in the second direction DR2. The second auxiliary electrode AUE2 may be disposed in the second metal layer MTL2. The second auxiliary electrode AUE2 may be connected to the third source electrode SE3 of the third transistor ST3 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3. Therefore, the initialization voltage line VIL may supply an initialization voltage to the third transistor ST3 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 through the second auxiliary electrode AUE2, and may receive a sensing signal from the third transistor ST3 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0129] The vertical voltage line VVSL may extend in the second direction DR2. In a plan view, the vertical voltage line VVSL may be disposed on the left side of the initialization voltage line VIL. The vertical voltage line VVSL may be disposed in the first metal layer MTL1. The vertical voltage line VVSL may overlap the first auxiliary electrode AUE1 of the second metal layer MTL2.

[0130] The first auxiliary electrode AUE1 may extend in the second direction DR2. The first auxiliary electrode AUE1 may be disposed in the second metal layer MTL2. The first auxiliary electrode AUE1 may be connected to the vertical voltage line VVSL. The vertical voltage line VVSL may reduce line resistance by being connected to the first auxiliary electrode AUE1.

[0131] The first auxiliary electrode AUE1 may be connected to the common electrode auxiliary electrode VCE. Therefore, the vertical voltage line VVSL may supply a low potential voltage to the common electrode CME through the first auxiliary electrode AUE1 and the common electrode auxiliary electrode VCE.

[0132] The vertical voltage line VVSL may be connected to the second voltage line VSL to supply a low potential voltage to the second voltage line VSL. The second voltage line VSL may extend in the first direction DR1. In a plan view, the second voltage line VSL may be disposed above the first gate line GL1 or below the second gate line GL2. The second voltage line VSL may be disposed in the second metal layer MTL2. The second voltage line VSL may receive a low potential voltage from the vertical voltage line VVSL.

[0133] In a plan view, the first gate line GL1 may be disposed above the pixel circuit of the second pixel SP2. The first gate line GL1 may be disposed in the second metal layer MTL2. The first gate line GL1 may include a first auxiliary gate line BGL1 that branches and extends in the opposite direction of the second direction DR2 along the right sides of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0134] In a plan view, the first auxiliary gate line BGL1 may protrude from the first gate line GL1 in a reverse direction of the second direction DR2. In a plan view, the first auxiliary gate line BGL1 may be disposed on the right side of the pixel circuit of the first pixel SP1, the pixel circuit of the second pixel SP2, and the pixel circuit of the third pixel SP3. That is, in a plan view, the first auxiliary gate line BGL1 may be disposed between the first pixel SP1, the second pixel SP2, and the third pixel SP3 and the data line DL. The first gate line GL1 may supply a first gate signal to the second transistor ST2 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 through the first auxiliary gate line BGL1.

[0135] In a plan view, the second gate line GL2 may be disposed below the pixel circuit of the first pixel SP1 and the pixel circuit of the third pixel SP3. The second gate line GL2 may be disposed in the second metal layer MTL2. The second gate line GL2 may include a second auxiliary gate line BGL2 branched and extending in the second direction DR2 along the left side of the first voltage line VDL.

[0136] In a plan view, the second auxiliary gate line BGL2 may protrude from the second gate line GL2 in the second direction DR2. In a plan view, the second auxiliary gate line BGL2 may be disposed on the left side of the first voltage line VDL. That is, in a plan view, the second auxiliary gate line BGL2 may be disposed between the initialization voltage line VIL and the first voltage line VDL. The second gate line GL2 may supply a second gate signal to the third transistor ST3 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 through the second auxiliary gate line BGL2.

[0137] The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3. Each of the first data line DL1, the second data line DL2, and the third data line DL3 may extend in the second direction DR2.

[0138] In a plan view, the first data line DL1 may be disposed on the right side of the first auxiliary gate line BGL1. The first data line DL1 may be disposed in the first metal layer MTL1. The fifth connection electrode CE5 of the second metal layer MTL2 may electrically connect the first data line DL1 to the second drain electrode DE2 of the second transistor ST2 of the first pixel SP1. Therefore, the first data line DL1 may supply a data voltage to the second transistor ST2 of the first pixel SP1 through the fifth connection electrode CE5.

[0139] In a plan view, the third data line DL3 may be disposed on the right side of the first data line DL1. The third data line DL3 may be disposed in the first metal layer MTL1. The seventh connection electrode CE7 of the second metal layer MTL2 may electrically connect the third data line DL3 to the second drain electrode DE2 of the second transistor ST2 of the third pixel SP3. Therefore, the third data line DL3 may supply a data voltage to the second transistor ST2 of the third pixel SP3 through the seventh connection electrode CE7.

[0140] In a plan view, the second data line DL2 may be disposed on the right side of the third data line DL3. The second data line DL2 may be disposed in the first metal layer MTL1. The second connection electrode CE2 of the second metal layer MTL2 may electrically connect the second data line DL2 to the second drain electrode DE2 of the second transistor ST2 of the second pixel SP2. Therefore, the second data line DL2 may supply a data voltage to the second transistor ST2 of the second pixel SP2 through the second connection electrode CE2.

[0141] The pixel circuit of the first pixel SP1 may include first, second and third transistors ST1 , ST2 and ST3 , and a first capacitor C1 .

[0142] The first transistor ST1 of the first pixel SP1 may include a first active region ACT1 , a first gate electrode GE1 , a first drain electrode DE1 , and a first source electrode SE1 .

[0143] The first active region ACT1 of the first transistor ST1 may be disposed in the active layer ACTL and may overlap the first gate electrode GE1 of the first transistor ST1 .

[0144] The first gate electrode GE1 of the first transistor ST1 may be disposed in the second metal layer MTL2. The first gate electrode GE1 of the first transistor ST1 may be connected to the second capacitor electrode CPE2 of the first capacitor C1 of the first pixel SP1. The first gate electrode GE1 of the first transistor ST1 may be electrically connected to the second source electrode SE2 of the second transistor ST2 of the first pixel SP1 through the second capacitor electrode CPE2 of the first capacitor C1.

[0145] The first drain electrode DE1 and the first source electrode SE1 of the first transistor ST1 may be made conductive by heat treatment of the active layer ACTL. The first drain electrode DE1 and the first source electrode SE1 of the first transistor ST1 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0146] The first drain electrode DE1 of the first transistor ST1 of the first pixel SP1 may be electrically connected to the first voltage line VDL through the fourth connection electrode CE4. The fourth connection electrode CE4 may be connected to the first voltage line VDL. Therefore, the first drain electrode DE1 of the first transistor ST1 may receive a driving voltage from the first voltage line VDL through the fourth connection electrode CE4.

[0147] The first source electrode SE1 of the first transistor ST1 may be electrically connected to the third drain electrode DE3 of the third transistor ST3 of the first pixel SP1 , the first capacitor electrode CPE1 of the first capacitor C1 , and the light emitting element ED through the sixth connection electrode CE6 .

[0148] The first source electrode SE1 of the first transistor ST1 may be electrically connected to the light emitting element ED of the first pixel SP1 through the sixth connection electrode CE6. For example, the first source electrode SE1 of the first transistor ST1 may be electrically connected to the first pixel electrode PXR through the sixth connection electrode CE6. Therefore, the first source electrode SE1 of the first transistor ST1 may supply a driving current to the light emitting element ED through the first pixel electrode PXR.

[0149] The second transistor ST2 of the first pixel SP1 may include a second active area ACT2, a second gate electrode GE2, a second drain electrode DE2, and a second source electrode SE2.

[0150] The second active region ACT2 of the second transistor ST2 may be disposed in the active layer ACTL and may overlap the second gate electrode GE2 of the second transistor ST2 .

[0151] The second gate electrode GE2 of the second transistor ST2 may be disposed in the second metal layer MTL2. The second gate electrode GE2 of the second transistor ST2 may be a portion of the first auxiliary gate line BGL1.

[0152] The second drain electrode DE2 and the second source electrode SE2 of the second transistor ST2 may be made conductive by heat treatment of the active layer ACTL. The second drain electrode DE2 and the second source electrode SE2 of the second transistor ST2 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0153] The second drain electrode DE2 of the second transistor ST2 may be connected to the fifth connection electrode CE5 of the second metal layer MTL2. The second drain electrode DE2 of the second transistor ST2 may be electrically connected to the first data line DL1 through the fifth connection electrode CE5 of the second metal layer MTL2. Therefore, the first data line DL1 supplies a data voltage to the second transistor ST2 of the first pixel SP1 through the fifth connection electrode CE5.

[0154] The second source electrode SE2 of the second transistor ST2 may be electrically connected to the second capacitor electrode CPE2 of the first capacitor C1 of the first pixel SP1. The second capacitor electrode CPE2 may be connected to the first gate electrode GE1 of the first transistor ST1. Therefore, the second source electrode SE2 of the second transistor ST2 may supply the first gate voltage to the first transistor ST1 through the second capacitor electrode CPE2.

[0155] The third transistor ST3 of the first pixel SP1 may include a third active region ACT3 , a third gate electrode GE3 , a third drain electrode DE3 , and a third source electrode SE3 .

[0156] The third active region ACT3 of the third transistor ST3 may be disposed in the active layer ACTL and may overlap the third gate electrode GE3 of the third transistor ST3 .

[0157] The third gate electrode GE3 of the third transistor ST3 may be disposed in the second metal layer MTL2. The third gate electrode GE3 of the third transistor ST3 may be a portion of the second auxiliary gate line BGL2.

[0158] The third drain electrode DE3 and the third source electrode SE3 of the third transistor ST3 may be made conductive by heat treatment of the active layer ACTL. The third drain electrode DE3 and the third source electrode SE3 of the third transistor ST3 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0159] The third drain electrode DE3 of the third transistor ST3 may be connected to the sixth connection electrode CE6 of the second metal layer MTL2. The third drain electrode DE3 of the third transistor ST3 may be electrically connected to the first source electrode SE1 of the first transistor ST1, the first capacitor electrode CPE1 of the first capacitor C1, and the first pixel electrode PXR of the first pixel SP1 through the sixth connection electrode CE6.

[0160] The third source electrode SE3 of the third transistor ST3 may be connected to the second auxiliary electrode AUE2 of the second metal layer MTL2. The third source electrode SE3 of the third transistor ST3 may be electrically connected to the initialization voltage line VIL through the second auxiliary electrode AUE2. The third source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The third source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0161] The first capacitor C1 of the first pixel SP1 may include a first capacitor electrode CPE1 disposed in the first metal layer MTL1 and a second capacitor electrode CPE2 disposed in the active layer ACTL. The first capacitor electrode CPE1 may be connected to the first source electrode SE1 of the first transistor ST1, the third drain electrode DE3 of the third transistor ST3, and the first pixel electrode PXR of the first pixel SP1 through the sixth connection electrode CE6. The second capacitor electrode CPE2 may be connected to the first gate electrode GE1 of the first transistor ST1 and the second source electrode SE2 of the second transistor ST2.

[0162] The pixel circuit of the second pixel SP2 may include first, second, and third transistors ST1, ST2, and ST3, and a first capacitor C1.

[0163] The first transistor ST1 of the second pixel SP2 may include a first active area ACT1 of the second pixel SP2 , a first gate electrode GE1 , a first drain electrode DE1 , and a first source electrode SE1 .

[0164] The first active region ACT1 of the first transistor ST1 may be disposed in the active layer ACTL and may overlap the first gate electrode GE1 of the first transistor ST1 .

[0165] The first gate electrode GE1 of the first transistor ST1 may be disposed in the second metal layer MTL2. The first gate electrode GE1 of the first transistor ST1 may be connected to the second capacitor electrode CPE2 of the first capacitor C1 of the second pixel SP2. The first gate electrode GE1 of the first transistor ST1 may be electrically connected to the second source electrode SE2 of the second transistor ST2 of the second pixel SP2 through the second capacitor electrode CPE2 of the first capacitor C1.

[0166] The first drain electrode DE1 and the first source electrode SE1 of the first transistor ST1 may be made conductive by heat treatment of the active layer ACTL. The first drain electrode DE1 and the first source electrode SE1 of the first transistor ST1 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0167] The first drain electrode DE1 of the first transistor ST1 may be electrically connected to the first voltage line VDL through the first connection electrode CE1. The first connection electrode CE1 may be connected to the first voltage line VDL. Therefore, the first drain electrode DE1 of the first transistor ST1 may receive a driving voltage from the first voltage line VDL through the first connection electrode CE1.

[0168] The first source electrode SE1 of the first transistor ST1 may be electrically connected to the third drain electrode DE3 of the third transistor ST3 of the second pixel SP2 and the first capacitor electrode CPE1 of the first capacitor C1 through the third connection electrode CE3 .

[0169] The first source electrode SE1 of the first transistor ST1 may be electrically connected to the light emitting element ED of the second pixel SP2 through the third connection electrode CE3, the first capacitor electrode CPE1 of the first capacitor C1, and the ninth connection electrode CE9. For example, the first source electrode SE1 of the first transistor ST1 may be electrically connected to the second pixel electrode PXG through the third connection electrode CE3, the first capacitor electrode CPE1 of the first capacitor C1, and the ninth connection electrode CE9. Therefore, the first source electrode SE1 of the first transistor ST1 may supply a driving current to the light emitting element ED through the second pixel electrode PXG.

[0170] The second transistor ST2 of the second pixel SP2 may include a second active area ACT2, a second gate electrode GE2, a second drain electrode DE2, and a second source electrode SE2.

[0171] The second active region ACT2 of the second transistor ST2 may be disposed in the active layer ACTL and may overlap the second gate electrode GE2 of the second transistor ST2 .

[0172] The second gate electrode GE2 of the second transistor ST2 may be disposed in the second metal layer MTL2. The second gate electrode GE2 of the second transistor ST2 may be a portion of the first auxiliary gate line BGL1.

[0173] The second drain electrode DE2 and the second source electrode SE2 of the second transistor ST2 may be made conductive by heat treatment of the active layer ACTL. The second drain electrode DE2 and the second source electrode SE2 of the second transistor ST2 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0174] The second drain electrode DE2 of the second transistor ST2 may be connected to the second connection electrode CE2 of the second metal layer MTL2. The second drain electrode DE2 of the second transistor ST2 may be electrically connected to the second data line DL2 through the second connection electrode CE2 of the second metal layer MTL2. Therefore, the second data line DL2 supplies a data voltage to the second transistor ST2 of the second pixel SP2 through the second connection electrode CE2.

[0175] The second source electrode SE2 of the second transistor ST2 may be electrically connected to the first capacitor C1, and in particular, to the second capacitor electrode CPE2 formed in the active layer ACTL. The second capacitor electrode CPE2 may be connected to the first gate electrode GE1 of the first transistor ST1. Therefore, the second source electrode SE2 of the second transistor ST2 may supply the first gate voltage to the first transistor ST1 through the second capacitor electrode CPE2.

[0176] The third transistor ST3 of the second pixel SP2 may include a third active region ACT3 , a third gate electrode GE3 , a third drain electrode DE3 , and a third source electrode SE3 .

[0177] The third active region ACT3 of the third transistor ST3 may be disposed in the active layer ACTL and may overlap the third gate electrode GE3 of the third transistor ST3 .

[0178] The third gate electrode GE3 of the third transistor ST3 may be disposed in the second metal layer MTL2. The third gate electrode GE3 of the third transistor ST3 may be a portion of the second auxiliary gate line BGL2.

[0179] The third drain electrode DE3 and the third source electrode SE3 of the third transistor ST3 may be made conductive by heat treatment of the active layer ACTL. The third drain electrode DE3 and the third source electrode SE3 of the third transistor ST3 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0180] The third drain electrode DE3 of the third transistor ST3 may be connected to the third connection electrode CE3 of the second metal layer MTL2. The third drain electrode DE3 of the third transistor ST3 may be electrically connected to the first source electrode SE1 of the first transistor ST1 and the first capacitor electrode CPE1 of the first capacitor C1 through the third connection electrode CE3. The third drain electrode DE3 of the third transistor ST3 may be electrically connected to the second pixel electrode PXG through the third connection electrode CE3, the first capacitor electrode CPE1, and the ninth connection electrode CE9.

[0181] The third source electrode SE3 of the third transistor ST3 may be connected to the second auxiliary electrode AUE2 of the second metal layer MTL2. The third source electrode SE3 of the third transistor ST3 may be electrically connected to the initialization voltage line VIL through the second auxiliary electrode AUE2. The third source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The third source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0182] The first capacitor C1 of the second pixel SP2 may include a first capacitor electrode CPE1 disposed in the first metal layer MTL1 and a second capacitor electrode CPE2 disposed in the active layer ACTL. The first capacitor electrode CPE1 may be connected to the first source electrode SE1 of the first transistor ST1 and the third drain electrode DE3 of the third transistor ST3 through the third connection electrode CE3. The first capacitor electrode CPE1 may be connected to the second pixel electrode PXG of the second pixel SP2 through the ninth connection electrode CE9. The second capacitor electrode CPE2 may be connected to the first gate electrode GE1 of the first transistor ST1 and the second source electrode SE2 of the second transistor ST2.

[0183] The pixel circuit of the third pixel SP3 may include first, second and third transistors ST1, ST2 and ST3, and a first capacitor C1.

[0184] The first transistor ST1 of the third pixel SP3 may include a first active region ACT1 , a first gate electrode GE1 , a first drain electrode DE1 , and a first source electrode SE1 .

[0185] The first active region ACT1 of the first transistor ST1 may be disposed in the active layer ACTL and may overlap the first gate electrode GE1 of the first transistor ST1 .

[0186] The first gate electrode GE1 of the first transistor ST1 may be disposed in the second metal layer MTL2. The first gate electrode GE1 of the first transistor ST1 may be connected to the second capacitor electrode CPE2 of the first capacitor C1 of the third pixel SP3. The first gate electrode GE1 of the first transistor ST1 may be electrically connected to the second source electrode SE2 of the second transistor ST2 of the third pixel SP3 through the second capacitor electrode CPE2 of the first capacitor C1.

[0187] The first drain electrode DE1 and the first source electrode SE1 of the first transistor ST1 may be made conductive by heat treatment of the active layer ACTL. The first drain electrode DE1 and the first source electrode SE1 of the first transistor ST1 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0188] The first drain electrode DE1 of the first transistor ST1 may be electrically connected to the first voltage line VDL through the fourth connection electrode CE4. The fourth connection electrode CE4 may be connected to the first voltage line VDL. Therefore, the first drain electrode DE1 of the first transistor ST1 may receive a driving voltage from the first voltage line VDL through the fourth connection electrode CE4.

[0189] The first source electrode SE1 of the first transistor ST1 may be electrically connected to the third drain electrode DE3 of the third transistor ST3 of the third pixel SP3 , the first capacitor electrode CPE1 of the first capacitor C1 , and the light emitting element ED through the eighth connection electrode CE8 .

[0190] The first source electrode SE1 of the first transistor ST1 may be electrically connected to the light emitting element ED of the third pixel SP3 through the eighth connection electrode CE8. For example, the first source electrode SE1 of the first transistor ST1 may be electrically connected to the third pixel electrode PXB through the eighth connection electrode CE8. Therefore, the first source electrode SE1 of the first transistor ST1 may supply a driving current to the light emitting element ED through the third pixel electrode PXB.

[0191] The second transistor ST2 of the third pixel SP3 may include a second active area ACT2, a second gate electrode GE2, a second drain electrode DE2, and a second source electrode SE2.

[0192] The second active region ACT2 of the second transistor ST2 may be disposed in the active layer ACTL and may overlap the second gate electrode GE2 of the second transistor ST2 .

[0193] The second gate electrode GE2 of the second transistor ST2 may be disposed in the second metal layer MTL2. The second gate electrode GE2 of the second transistor ST2 may be a portion of the first auxiliary gate line BGL1.

[0194] The second drain electrode DE2 and the second source electrode SE2 of the second transistor ST2 may be made conductive by heat treatment of the active layer ACTL. The second drain electrode DE2 and the second source electrode SE2 of the second transistor ST2 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0195] The second drain electrode DE2 of the second transistor ST2 may be connected to the seventh connection electrode CE7 of the second metal layer MTL2. The second drain electrode DE2 of the second transistor ST2 may be electrically connected to the third data line DL3 through the seventh connection electrode CE7 of the second metal layer MTL2. Therefore, the third data line DL3 supplies a data voltage to the second transistor ST2 of the third pixel SP3 through the seventh connection electrode CE7.

[0196] The second source electrode SE2 of the second transistor ST2 may be electrically connected to the first capacitor C1, and in particular, to the second capacitor electrode CPE2 formed in the active layer ACTL. The second capacitor electrode CPE2 may be connected to the first gate electrode GE1 of the first transistor ST1. Therefore, the second source electrode SE2 of the second transistor ST2 may supply the first gate voltage to the first transistor ST1 through the second capacitor electrode CPE2.

[0197] The third transistor ST3 of the third pixel SP3 may include a third active region ACT3 , a third gate electrode GE3 , a third drain electrode DE3 , and a third source electrode SE3 .

[0198] The third active region ACT3 of the third transistor ST3 may be disposed in the active layer ACTL and may overlap the third gate electrode GE3 of the third transistor ST3 .

[0199] The third gate electrode GE3 of the third transistor ST3 may be disposed in the second metal layer MTL2. The third gate electrode GE3 of the third transistor ST3 may be a portion of the second auxiliary gate line BGL2.

[0200] The third drain electrode DE3 and the third source electrode SE3 of the third transistor ST3 may be made conductive by heat treatment of the active layer ACTL. The third drain electrode DE3 and the third source electrode SE3 of the third transistor ST3 may be conductive as an N-type semiconductor, but the present disclosure is not limited thereto.

[0201] The third drain electrode DE3 of the third transistor ST3 may be connected to the eighth connection electrode CE8 of the second metal layer MTL2. The third drain electrode DE3 of the third transistor ST3 may be electrically connected to the first source electrode SE1 of the first transistor ST1, the first capacitor electrode CPE1 of the first capacitor C1, and the third pixel electrode PXB of the third pixel SP3 through the eighth connection electrode CE8.

[0202] The third source electrode SE3 of the third transistor ST3 may be connected to the second auxiliary electrode AUE2 of the second metal layer MTL2. The third source electrode SE3 of the third transistor ST3 may be electrically connected to the initialization voltage line VIL through the second auxiliary electrode AUE2. The third source electrode SE3 of the third transistor ST3 may receive an initialization voltage from the initialization voltage line VIL. The third source electrode SE3 of the third transistor ST3 may supply a sensing signal to the initialization voltage line VIL.

[0203] The first capacitor C1 of the third pixel SP3 may include a first capacitor electrode CPE1 disposed in the first metal layer MTL1 and a second capacitor electrode CPE2 disposed in the active layer ACTL. The first capacitor electrode CPE1 may be connected to the first source electrode SE1 of the first transistor ST1, the third drain electrode DE3 of the third transistor ST3, and the third pixel electrode PXB of the third pixel SP3 through the eighth connection electrode CE8. The second capacitor electrode CPE2 may be connected to the first gate electrode GE1 of the first transistor ST1 and the second source electrode SE2 of the second transistor ST2.

[0204] like Figures 5 to 8 As shown in , the light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a third metal layer MTL3 disposed on the via layer VIA, a pixel defining layer PDL disposed on the third metal layer MTL3 and the via layer VIA, a light emitting layer LEL disposed on the third metal layer MTL3 and the pixel defining layer PDL, and a common electrode CME disposed on the light emitting layer LEL.

[0205] The third metal layer MTL3 may be disposed on the via layer VIA. The third metal layer MTL3 may include a pixel electrode PXE and a common electrode auxiliary electrode VCE. The pixel electrode PXE may include a first electrode (e.g., an anode electrode) of a light emitting diode. The pixel electrode PXE may include a first pixel electrode PXR of a first pixel SP1, a second pixel electrode PXG of a second pixel SP2, and a third pixel electrode PXB of a third pixel SP3.

[0206] The first pixel electrode PXR of the first pixel SP1 may be substantially disposed at the center and lower left end of the pixel SP. For example, the first pixel electrode PXR may overlap the initialization voltage line VIL, the first voltage line VDL, and the pixel circuit of the first pixel SP1 in the third direction DR3. The first pixel electrode PXR may extend in an oblique direction between the first direction DR1 and the second direction DR2.

[0207] The first pixel electrode PXR may be electrically connected to the first source electrode SE1 of the first transistor ST1 of the first pixel SP1 through the sixth connection electrode CE6 and a contact hole overlapping the sixth connection electrode CE6. The first pixel electrode PXR may receive a driving voltage from the first voltage line VDL through the first source electrode SE1 of the first transistor ST1 of the first pixel SP1.

[0208] In a plan view, the second pixel electrode PXG of the second pixel SP2 may be substantially disposed at the center and upper end of the pixel SP. For example, the second pixel electrode PXG may overlap the first voltage line VDL, the pixel circuit of the second pixel SP2, the first gate line GL1, and the second voltage line VSL in the third direction DR3.

[0209] The second pixel electrode PXG may be connected to the first source electrode SE1 of the first transistor ST1 of the second pixel SP2 through the ninth connection electrode CE9, the contact hole overlapped with the ninth connection electrode CE9, the first capacitor electrode CPE1, and the third connection electrode CE3. The second pixel electrode PXG may receive a driving voltage from the first voltage line VDL through the first source electrode SE1 of the first transistor ST1 of the second pixel SP2.

[0210] In a plan view, the third pixel electrode PXB of the third pixel SP3 may be disposed substantially at the center and the lower right end of the pixel SP. For example, the third pixel electrode PXB may overlap the data line DL and the pixel circuit of the third pixel SP3 in the third direction DR3.

[0211] The third pixel electrode PXB may receive a driving voltage from the first voltage line VDL through the first source electrode SE1 of the first transistor ST1 of the third pixel SP3 through the eighth connection electrode CE8 and a contact hole overlapping the eighth connection electrode CE8.

[0212] The common electrode auxiliary electrode VCE may be disposed substantially on the left side of the pixel SP in a plan view. The common electrode auxiliary electrode VCE may overlap the vertical voltage line VVSL in the third direction DR3.

[0213] The common electrode auxiliary electrode VCE may be connected to the first auxiliary electrode AUE1 through a contact hole. The common electrode auxiliary electrode VCE may receive a low potential voltage from the vertical voltage line VVSL through the first auxiliary electrode AUE1.

[0214] like Figures 5 to 8 The pixel defining layer PDL shown in the figure may be disposed on the via layer VIA of the thin film transistor layer TFTL and the third metal layer MTL3. The pixel defining layer PDL may electrically insulate the patterned third metal layer MTL3. The pixel defining layer PDL may include a plurality of opening portions. Some of the plurality of opening portions may expose a portion of the third metal layer MTL3. The pixel electrode PXE of the third metal layer MTL3 may contact the light emitting layer LEL through the plurality of opening portions.

[0215] The emission area LA may be defined by an opening portion of the pixel defining layer PDL. For example, the first emission area LA1 may be defined by an opening portion of the pixel defining layer PDL overlapping the first pixel electrode PXR, the second emission area LA2 may be defined by an opening portion of the pixel defining layer PDL overlapping the second pixel electrode PXG, and the third emission area LA3 may be defined by an opening portion of the pixel defining layer PDL overlapping the third pixel electrode PXB. The first emission area LA1, the second emission area LA2, and the third emission area LA3 may have sizes smaller than the size of the first pixel electrode PXR, the size of the second pixel electrode PXG, and the size of the third pixel electrode PXB, respectively.

[0216] In a plan view, the first emission area LA1 may be substantially disposed at the lower left end of the pixel SP. The first emission area LA1 may overlap a majority of the first pixel electrode PXR. In a plan view, the second emission area LA2 may be substantially disposed at the upper end of the center of the pixel SP. The second emission area LA2 may overlap a majority of the second pixel electrode PXG. In a plan view, the third emission area LA3 may be substantially disposed at the lower right end of the pixel SP. The third emission area LA3 may overlap a majority of the third pixel electrode PXB.

[0217] Each of the contact holes through which each of the first pixel electrode PXR, the second pixel electrode PXG, and the third pixel electrode PXB is electrically connected to the first source electrode SE1 of the first transistor ST1 of the associated pixel SP1, SP2, or SP3 may not overlap with the opening portion of the pixel defining layer PDL.

[0218] The light-emitting layer LEL may be disposed on the third metal layer MTL3 and the pixel defining layer PDL. In one embodiment, the light-emitting layer LEL may be disposed as a whole across the entire surface of the display area. The light-emitting layer LEL may be physically connected across the emission area LA and the pixel SP. The light-emitting layer LEL may be disposed across the emission area LA and the pixel SP. For example, the light-emitting layer LEL may be in direct contact with the pixel electrode PXE exposed by the pixel defining layer PDL, and may also be in direct contact with the side surface and the top surface of the pixel defining layer PDL. Therefore, for each of the emission areas LA1, LA2, and LA3, the wavelength of light emitted from the light-emitting layer LEL may be the same. For example, the light-emitting layer LEL of each of the emission areas LA1, LA2, and LA3 may emit blue light or ultraviolet light. In this case, the color control structure disposed above the light-emitting element layer EML may include a wavelength conversion layer to display the color of the pixel SP1, SP2, or SP3.

[0219] In another embodiment, the light emitting layer LEL may include regions of different materials spaced apart from each other for the emission regions LA1, LA2, and LA3 separated by the pixel defining layer PDL. In this case, for each of the emission regions LA1, LA2, and LA3, the wavelength of light emitted from the corresponding region of the light emitting layer LEL may be different.

[0220] The common electrode CME may be arranged on the light emitting layer LEL. The common electrode CME may be integrally arranged across the entire surface of the display area. The common electrode CME may be physically connected across the emission area LA and the pixel SP. The common electrode CME may be arranged across the emission area LA and the pixel SP. The common electrode CME may be a second electrode (e.g., a cathode electrode) of the light emitting diode.

[0221] The pixel electrode PXE, the light emitting layer LEL, and the common electrode CME may constitute a light emitting element (eg, OLED). Light emitted from the light emitting layer LEL may be emitted upward through the common electrode CME.

[0222] In some embodiments, a portion of the light emitted from the light emitting layer LEL may be emitted toward the thin film transistor layer TFTL. When the light emitted from the light emitting layer LEL is incident on the active layer ACTL of the first transistor ST1 serving as a driving transistor, the display device 1 (see Figure 1 ) may be degraded due to photo-induced degradation. Photo-induced degradation refers to a phenomenon in which an inherent characteristic curve between drain-source current (Ids) and gate voltage (Vg) of a transistor is shifted due to external light incident on the transistor, resulting in a change in the magnitude of a threshold voltage (Vth).

[0223] like Figure 5 and Figure 6 As shown in FIG. 1 , in the display device 1 according to the comparative embodiment and the exemplary embodiment, no other metal layer may be provided between the second metal layer MTL2 provided with the gate electrode of the transistor and the third metal layer MTL3 provided with the pixel electrode PXE. This arrangement of minimizing the number of stacks can improve process efficiency.

[0224] However, if Figure 5 As in the comparative embodiment shown in , as the height difference between the active layer ACTL and the third metal layer MTL3 decreases, among the light emitted from the light emitting layer LEL disposed on the first pixel electrode PXR of the first pixel SP1, some light L1' may be incident on the active layer ACTL of the first transistor ST1 of the third pixel SP3. As a result, light-induced degradation may occur in the first transistor ST1 of the third pixel SP3 due to the light L1' emitted from the first pixel SP1.

[0225] On the other hand, according to Figure 6 In the display device 1 of the embodiment, the via layer VIA may include a valley VAL to place the portion of the pixel electrode PXE extending into the valley VAL at a lower height, thereby blocking the light path and preventing light emitted from the light emitting layer LEL disposed on the pixel electrode PXE of the adjacent pixel from being incident on the transistor within its own pixel. Therefore, light-induced degradation of the transistor can be reduced or minimized.

[0226] For example, Figure 6 As shown in , the via layer VIA may include a peak CRS and a valley VAL. The peak CRS may be a portion of the via layer VIA where the thickness of the via layer VIA is the largest, and the valley VAL may be a portion of the via layer VIA where the thickness of the via layer VIA is the smallest. The via layer VIA may include an area (i.e., a valley area VALA) where the valley VAL is located. A slope may be set between the peak CRS and the valley VAL.

[0227] The thickness TH2 of the valley VAL may be less than the thickness TH1 of the peak CRS. For example, the thickness TH1 of the peak CRS may be 3 to 5 times the thickness TH2 of the valley VAL. The thickness TH1 of the peak CRS and the thickness TH2 of the valley VAL may mean the vertical distance from the top surface of the passivation layer PV to the top surface of the via layer VIA.

[0228] Most of the pixel electrode PXE may be disposed on the peak CRS of the via layer VIA. Figure 4 As shown in , the second pixel electrode PXG may not overlap the valley area VALA. A portion of the first pixel electrode PXR and a portion of the third pixel electrode PXB may overlap the valley area VALA.

[0229] By placing most of the area of ​​the pixel electrode PXE on the peak CRS of the via layer VIA, the capacitance of the first capacitor C1 of the first pixel SP1, the capacitance of the first capacitor C1 of the second pixel SP2, and the capacitance of the first capacitor C1 of the third pixel SP3 can be sufficiently ensured. For example, the first capacitor C1 of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 can overlap with the peak CRS in the third direction DR3. Since the first capacitor electrode CPE1 of the first capacitor C1 can be connected to the pixel electrode PXE through the connection electrodes CE6, CE8, and CE9, the via layer VIA overlapping the first capacitor C1 can be formed as the peak CRS to ensure sufficient capacitance.

[0230] At the same time, the portions of the first pixel electrode PXR and the third pixel electrode PXB overlapping with the valley area VALA may not overlap with the first emission area LA1 and the third emission area LA3, respectively. That is, the valley area VALA may not overlap with the first emission area LA1, the second emission area LA2, and the third emission area LA3. Therefore, the color difference phenomenon between adjacent pixels SP can be minimized. The color difference phenomenon means that incorrect light emission occurs due to a coupling phenomenon with a pixel circuit of an adjacent pixel.

[0231] One end of the third pixel electrode PXB facing the first pixel electrode PXR may be disposed on the valley VAL of the via layer VIA. That is, one end of the third pixel electrode PXB facing the first pixel electrode PXR may be disposed in the valley area VALA. Therefore, since one end of the third pixel electrode PXB extends to a height lower than that of the first pixel electrode PXR, light L1 emitted at a downward angle from the light emitting layer LEL disposed on the first pixel electrode PXR may be prevented from being incident on the active layer ACTL of the first transistor ST1 of the third pixel SP3. Therefore, light-induced degradation of the first transistor ST1 may be reduced or minimized.

[0232] Similarly, if Figure 8 As shown in , one end of the first pixel electrode PXR facing the second pixel electrode PXG may be disposed on the valley VAL of the via layer VIA. That is, one end of the first pixel electrode PXR facing the second pixel electrode PXG may extend into the valley area VALA and be disposed in the valley area VALA. Therefore, since one end of the first pixel electrode PXR is placed at a height lower than that of the second pixel electrode PXG, light L2 emitted downward from the light emitting layer LEL disposed on the second pixel electrode PXG may be prevented from being incident on the active layer ACTL of the first transistor ST1 of the first pixel SP1. Therefore, light-induced degradation of the first transistor ST1 may be reduced or minimized.

[0233] like Figure 4 and Fig. 9 As shown in , the valley area VALA may include a first area VALAa, a second area VALAb, and a third area VALAc.

[0234] The first area VALAa may be disposed between the first pixel electrode PXR and the third pixel electrode PXB. For example, in a plan view, the first area VALAa may be disposed between the first pixel electrode PXR and the first transistor ST1 of the third pixel SP3. The first area VALAa may overlap with an end of the third pixel electrode PXB facing the first pixel electrode PXR in the third direction DR3.

[0235] The first area VALAa may be disposed to surround at least a portion of the first transistor ST1 of the third pixel SP3 in a plan view. The first area VALAa may be disposed to surround a side of the first transistor ST1 of the third pixel SP3 facing the first pixel electrode PXR in a plan view.

[0236] The width W1a of the portion of the first area VALAa extending along the second direction DR2 in the first direction DR1 may be smaller than the width W1b of the portion of the first area VALAa extending along the first direction DR1 in the first direction DR1. The width W1b of the portion of the first area VALAa extending along the first direction DR1 in the first direction DR1 may be 3 to 5 times the width W1a of the portion of the first area VALAa extending along the second direction DR2 in the first direction DR1.

[0237] The second area VALAb may be disposed between the first pixel electrode PXR and the second pixel electrode PXG. For example, in a plan view, the second area VALAb may be disposed between the second pixel electrode PXG and the first transistor ST1 of the first pixel SP1. In a plan view, the second area VALAb may be disposed between the second pixel electrode PXG and a side of the first transistor ST1 of the first pixel SP1 facing the second pixel electrode PXG. The second area VALAb may overlap with an end of the first pixel electrode PXR facing the second pixel electrode PXG in a third direction DR3.

[0238] The third region VALAc may connect the first region VALAa to the second region VALAb. The third region VALAc may be disposed between the first pixel electrode PXR and the third pixel electrode PXB. For example, the third region VALAc may be disposed between the third pixel electrode PXB and the first transistor ST1 of the first pixel SP1. The third region VALAc may overlap with an end of the first pixel electrode PXR facing the third pixel electrode PXB in the third direction DR3.

[0239] The third area VALAc may be disposed to surround at least a portion of the first transistor ST1 of the first pixel SP1 in a plan view. The third area VALAc may be disposed to surround a side of the first transistor ST1 of the first pixel SP1 facing the third pixel electrode PXB in a plan view.

[0240] Hereinafter, some other embodiments of the display device will be described. Hereinafter, descriptions of components identical to those of the above-described embodiment denoted by the same reference numerals will be omitted or simplified, and differences among the embodiments will be mainly described.

[0241] Fig.10is a layout diagram of a portion of a display panel according to another embodiment. Fig.11 is along Fig.10 A cross-sectional view taken along line X5-X5'. Fig.12 yes Fig.10 Floor plan of the valley area in the layout.

[0242] Figures 10 to 12 Shown with the above reference Figure 4 The difference between the embodiments described above and the like is that the shape of the first area VALAa is different.

[0243] refer to Figures 10 to 12 , more specifically, Figures 10 to 12 The embodiment has a valley area VALA having a width W2a in the first direction DR1 of a portion of the first area VALAa extending along the second direction DR2, and the width W2a may be greater than that in the above reference. Fig. 9 In the embodiment described above, the portion of the first area VALAa extending along the second direction DR2 has a width W1a in the first direction DR1. Figures 10 to 12 , a width W2b of a portion of the first area VALAa extending along the first direction DR1 in the first direction DR1 may be 1.5 to 2 times a width W2a of a portion of the first area VALAa extending along the second direction DR2 in the first direction DR1.

[0244] The first area VALAa may overlap at least a portion of the first transistor ST1 of the third pixel SP3 in the third direction DR3. For example, the first area VALAa may overlap the first drain electrode DE1 of the first transistor ST1 of the third pixel SP3 in the third direction DR3.

[0245] Will Fig.11 Examples and Figure 6 Compared with the above reference Figure 6 Compared with the embodiments described in the above, more third pixel electrodes PXB may be arranged Fig.11 Therefore, the light L1 emitted from the light emitting layer LEL disposed on the first pixel electrode PXR at a downward angle can be further prevented from being incident on the active layer ACTL of the first transistor ST1 of the third pixel SP3. Therefore, the light-induced degradation of the first transistor ST1 can be further reduced or minimized.

[0246] Fig.13 is a layout diagram of a portion of a display panel according to another embodiment. Fig.14 is along Fig.13 A cross-sectional view taken along line X6-X6'. Fig.15 yes Fig.13A plan view of the valley region of an embodiment of the present invention.

[0247] Figures 13 to 15 The embodiment and the above reference Figure 4 and Fig.10 The main difference between the embodiments described above and the like is that the shape of the first area VALAa of the valley area VALA is different.

[0248] refer to Figures 13 to 15 , more specifically, if Fig.15 The first area VALAa shown in FIG. 4 may have a rectangular shape. The width W3 of the first area VALAa in the first direction DR1 may be constant in the second direction DR2. For example, the width W3 of the first area VALAa in the first direction DR1 may be the same as the width W1b of the portion of the first area VALAa extending along the first direction DR1 in the above-described embodiment (see FIG. 4 ). Fig. 9 ) and W2b (see Fig.12 )same.

[0249] like Fig.14 As shown in , the first area VALAa may overlap with at least a portion of the first transistor ST1 of the third pixel SP3 in the third direction DR3. For example, in a plan view (i.e., when viewed along the third direction DR3), the first area VALAa may overlap with the first drain electrode DE1, the first active area ACT1, and the first gate electrode GE1 of the first transistor ST1 of the third pixel SP3.

[0250] exist Figures 13 to 15 In the embodiment, with reference to the above Figure 6 and Fig.11 Compared with the embodiments described above, more third pixel electrodes PXB may be disposed on the valley VAL. Therefore, more third pixel electrodes PXB may be disposed at a lower level to block light L1 emitted at a downward angle from the light emitting layer LEL disposed on the first pixel electrode PXR, so that the light L1 may be further prevented from being incident on the active layer ACTL of the first transistor ST1 of the third pixel SP3. Therefore, light-induced degradation of the first transistor ST1 may be further reduced or minimized.

[0251] Fig.16 is a layout diagram of a portion of a display panel according to another embodiment. Fig.17 is along Fig.16 A cross-sectional view taken along line X7-X7'. Fig.18 yes Fig.16 A plan view of the valley region of an embodiment of the present invention.

[0252] Figures 16 to 18 The embodiment and the above reference Figure 4 , Fig.10 and Fig.13 The difference between the embodiments described in the examples is that: Fig.18 The valley area VALA shown in FIG. 4 further includes a fourth area VALAd. More specifically, the valley area VALA may further include a fourth area VALAd.

[0253] refer to Figures 16 to 18 In a plan view, the fourth area VALAd may protrude from the first area VALAa and the third area VALAc in a substantially oblique direction between the first direction DR1 and the second direction DR2. In a plan view, the fourth area VALAd may be disposed between the first pixel electrode PXR and the third pixel electrode PXB. For example, in a plan view, the fourth area VALAd may be disposed between the third pixel electrode PXB and the first transistor ST1 of the first pixel SP1.

[0254] The fourth area VALAd may be disposed to surround at least a portion of the first transistor ST1 of the first pixel SP1 in plan view. In particular, the fourth area VALAd may be disposed to surround a side of the first transistor ST1 of the first pixel SP1 facing the third pixel electrode PXB in plan view.

[0255] The fourth area VALAd may overlap the first capacitor C1 of the first pixel SP1 in a plan view (ie, when viewed along the third direction DR3). The shape of the fourth area VALAd may correspond to the shape of the end of the first capacitor C1 of the first pixel SP1 facing the third pixel electrode PXB in a plan view.

[0256] exist Figures 16 to 18 In the embodiment of the present invention, the first pixel electrode PXR may block the light L3 emitted at a downward angle from the light emitting layer LEL disposed on the third pixel electrode PXB, and may prevent the light L3 from being incident on the active layer ACTL of the first transistor ST1 of the first pixel SP1. Therefore, light-induced degradation of the first transistor ST1 may be reduced or minimized.

[0257] Fig.19 is a layout diagram of a portion of a display panel according to another embodiment. Fig. 20 is along Fig.19 A cross-sectional view taken along line X8-X8'.

[0258] Fig.19 and Fig. 20 The embodiment and the above reference Figure 4 , Fig.10 , Fig.13 and Fig.16The difference between the embodiments described in the examples is that the valley area VALA does not overlap with the end of the pixel electrode PXE, but overlaps with the gate electrode of the protected transistor and the portion of the pixel electrode covering the gate electrode. Fig. 20 In the specific example, the valley area VALA (see Fig.19 ) overlaps the first gate electrode GE1 of the first transistor ST1 of the third pixel SP3 and the first active area ACT1, and the third pixel electrode PXB extends into and passes through the valley area VALA, and one end of the third pixel electrode PXB returns to the peak CRS.

[0259] refer to Fig.19 and Fig. 20 , Fig.19 and Fig. 20 The valley area VALA can include Fig.19 The first valley area VALA1 and the second valley area VALA2 are shown in FIG.

[0260] The first valley area VALA1 may overlap the first gate electrode GE1 of the first transistor ST1 of the third pixel SP3 and the first active area ACT1. The first valley area VALA1 may not overlap an end portion of the third pixel electrode PXB.

[0261] The second valley area VALA2 may overlap the first gate electrode GE1 of the first transistor ST1 of the first pixel SP1 and the first active area ACT1. The second valley area VALA2 may not overlap the end of the first pixel electrode PXR.

[0262] like Fig. 20 As shown in , one end of the third pixel electrode PXB facing the first pixel electrode PXR may be positioned at the same height as the first pixel electrode PXR (i.e., positioned on the peak CRS of the via layer VIA). However, a portion of the third pixel electrode PXB overlapping with the first gate electrode GE1 of the first transistor ST1 of the third pixel SP3 may be positioned at a height lower than that of the first pixel electrode PXR (i.e., positioned on the valley VAL of the via layer VIA).

[0263] Fig. 20It is shown that light L4 emitted at a downward angle from the light emitting layer LEL disposed on the first pixel electrode PXR may be reflected by the fourth connection electrode CE4 of the second metal layer MTL2 and travel toward the bottom surface of the third pixel electrode PXB. The light L4 reflected by the fourth connection electrode CE4 may then be reflected from the inclined surface of the third pixel electrode PXB positioned on the slope between the peak CRS and the valley VAL of the via layer VIA. Then, the light reflected from the inclined surface may travel away from the first transistor ST1 of the third pixel SP3. Therefore, some of the light L4 emitted from the light emitting layer LEL disposed on the first pixel electrode PXR may be prevented from being incident on the active layer ACTL of the first transistor ST1 of the third pixel SP3. Therefore, the light-induced degradation of the first transistor ST1 may be reduced or minimized.

[0264] exist Fig. 20 , only the first valley area VALA1 is shown, but the same principle can be applied to the second valley area VALA2, so the illustration and description of the second valley area VALA2 will be omitted.

[0265] Fig.21 is a layout diagram of a display panel according to another embodiment. Fig. 22 is a layout diagram of a display panel according to another embodiment. Fig.21 and Fig. 22 An embodiment may be similar to Fig.19 and Fig. 20 , but as Fig.21 and Fig. 22 As shown in FIG. 1 , the width of the valley area VALA in the first direction DR1 and the second direction DR2 may be different. Fig.21 and Fig. 22 As shown in FIG. 1 , the width of the valley area VALA in the first direction DR1 and the second direction DR2 may be greater than Fig.19 The width of the valley area VALA in the first direction DR1 and the second direction DR2.

[0266] refer to Fig.21 and Fig. 22 In one embodiment, as the width of the valley area VALA in the first direction DR1 increases, the valley area VALA may also overlap the first drain electrode DE1 and the first source electrode SE1 of the first transistor ST1 of each of the first pixel SP1 and the third pixel SP3 in the third direction DR3.

[0267] In one embodiment, as the width of the valley area VALA in the second direction DR2 increases, the first valley area VALA1 may overlap the eighth connection electrode CE8 , and the second valley area VALA2 may overlap the sixth connection electrode CE6 .

[0268] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing from the principles of the present disclosure. Therefore, the disclosed embodiments of the present invention are used only in a general and descriptive sense, and not for a limiting purpose.

Claims

1. A display device, comprising a first pixel and a second pixel, in, The first pixel and the second pixel each include: a first transistor; a portion of a via layer disposed on the first transistor; and A portion of the first metal layer is disposed on the via layer, The first pixel also includes a first pixel electrode disposed in the first metal layer, the second pixel also includes a second pixel electrode disposed in the first metal layer, and the first pixel electrode has a first end facing the second pixel electrode and positioned at a height lower than that of the second pixel electrode.

2. The display device according to claim 1, in, The via layer includes peaks and valleys, The thickness of the peak is greater than the thickness of the valley, The first end is positioned on the valley, and The second pixel electrode is positioned on the peak.

3. The display device according to claim 2, in, The thickness of the peak is 3 to 5 times the thickness of the valley.

4. The display device according to claim 2, in, The via layer includes a valley region, the valley region being a region where the valley is located, and In a plan view, the valley region is disposed between the first transistor and the second pixel electrode of the first pixel.

5. The display device according to claim 4, further comprising a pixel defining layer disposed on the first metal layer, in, The pixel defining layer includes a plurality of opening portions overlapping at least a portion of the first pixel electrode and the second pixel electrode, and The plurality of opening portions do not overlap with the valley region.

6. The display device according to claim 5, in, The plurality of opening portions are disposed on the peaks.

7. The display device according to claim 4, in, The valley region is disposed to surround at least a portion of the first transistor of the first pixel in a plan view.

8. The display device according to claim 7, in, The valley region is disposed to surround one side of the first transistor of the first pixel, the one side facing the second pixel electrode, in a plan view.

9. The display device according to claim 4, further comprising a third pixel, in, The third pixel includes a third pixel electrode disposed in the first metal layer, and A second end portion, which is an end portion of the second pixel electrode facing the third pixel electrode, is positioned at a height lower than that of the third pixel electrode.

10. The display device according to claim 9, in, The valley area includes: a first region overlapping the first end; a second region overlapping the second end portion; and A third region connects the first region to the second region.

11. The display device according to claim 10, in, The first region is disposed to surround one side of the first transistor of the first pixel, the one side facing the second pixel electrode, in a plan view.

12. The display device according to claim 10, in, In a plan view, the second region is disposed between the third pixel electrode and one side of the first transistor of the second pixel, the one side facing the third pixel electrode.

13. The display device according to claim 10, in, The third region is disposed to surround one side of the first transistor of the second pixel, the one side facing the first pixel electrode, in a plan view.

14. The display device according to claim 10, in, The first region overlaps with the first transistor of the first pixel.

15. The display device according to claim 10, in, The valley region further includes a fourth region protruding from the third region, and In a plan view, the fourth region is disposed between the first pixel electrode and the first transistor of the second pixel.

16. The display device according to claim 2, in, Each of the first pixel and the second pixel further includes a first capacitor connected to the corresponding first transistor, and The first capacitor of each of the first pixel and the second pixel overlaps the corresponding peak.

17. The display device according to claim 1, in, In a thickness direction of the via layer, no other metal layer is disposed between the first metal layer and the first transistor of the first pixel.

18. The display device according to claim 1, in, Each of the first pixel and the second pixel further includes: a light-emitting layer, disposed on the first metal layer; and A second metal layer is disposed on the light emitting layer, The first transistor of each of the first pixel and the second pixel is a driving transistor configured to drive light emission of the light emitting layer.

19. A display device, comprising a first pixel and a second pixel, in, The first pixel and the second pixel each include: a first transistor; a portion of a via layer disposed on the first transistor; and A portion of the first metal layer is disposed on the via layer, The first pixel also includes a first pixel electrode disposed in the first metal layer, the second pixel also includes a second pixel electrode disposed in the first metal layer, and a portion of the first pixel electrode overlapping with the first transistor of the first pixel is positioned at a height lower than a height of the second pixel electrode.

20. The display device according to claim 19, in, A first end portion of the first pixel electrode facing the second pixel electrode is positioned at the same height as the second pixel electrode.

21. The display device according to claim 19, in, The via layer includes peaks and valleys, The thickness of the peak is greater than the thickness of the valley, The portion of the first pixel electrode overlapping the first transistor of the first pixel is positioned on the valley, and The second pixel electrode is positioned on the peak.

22. The display device according to claim 19, in, In a thickness direction of the via layer, no other metal layer is disposed between the first metal layer and the first transistor of the first pixel.

Images