Method and system for realizing automatic test of programmable logic array by using ATPG tool
Automated testing of FPGAs using ATPG tools addresses the inefficiencies of current methods by inserting virtual and real scan chains to generate and analyze test vectors, achieving efficient and precise fault detection.
Patent Information
- Application Number
- CN202411152880.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2024-12-13
AI Technical Summary
Current testing methods for field programmable gate arrays (FPGAs) require redeveloping test vectors for every function change, leading to high development workload and lack precise fault coverage, as function-based testing cannot provide exact fault coverage values.
Implement automated testing using ATPG tools by inserting a virtual scan chain and real scan chain into the FPGA, generating test vectors, and analyzing them to determine functional faults through the real scan chain.
Enables efficient and high-coverage automated testing of FPGAs without redeveloping test vectors, providing precise fault coverage and functional fault detection.
Smart Images
Figure CN119125839A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of field programmable logic array (FPGA) technology, and in particular to a method and system for implementing automated testing of a field programmable logic array using an ATPG tool. Background Art
[0002] Scan Chain and ATPG in DFT are both effective and widely used design technologies in modern integrated circuit design. However, due to the particularity of its design, field programmable gate arrays (FPGAs) cannot directly use this general technology. Currently, a function-based test method is used. For example, for each function, a corresponding test vector is developed and tested on the chip. The more complex the function, the more test vectors are required.
[0003] There are two flaws in the function-based testing method of programmable logic array FPGA:
[0004] 1. Test vectors are developed based on functions. If the functions of programmable arrays of different products change, the test vectors must be redeveloped, which results in a huge development workload.
[0005] 2. Unlike fault model-based ATPG, function-based test vectors cannot give exact fault coverage values.
[0006] This section is intended to provide a background or context to the embodiments of the present application as recited in the claims. The description herein is not admitted to be prior art as disclosed by virtue of its inclusion in this section. Summary of the invention
[0007] The purpose of this application is to provide a method and system for realizing automated testing of programmable logic arrays using ATPG tools, using the algorithm advantages of ATPG tools to generate complete test vectors, thereby realizing automated testing of programmable logic arrays.
[0008] The present application discloses a method for realizing automated testing of a programmable logic array using an ATPG tool, comprising:
[0009] Inserting a virtual scan chain, a combinational logic composed of a plurality of programmable points in a programmable logic array, and a real scan chain in an ATPG tool, wherein a plurality of outputs of the virtual scan chain correspond one-to-one to the plurality of programmable points and are respectively connected to the combinational logic;
[0010] Generate test vectors using the ATPG tool;
[0011] Analyzing the test vectors generated by the ATPG tool, extracting the test vectors corresponding to the virtual scan chain, and adding the test vectors to a portion of the downloaded code stream of the programmable logic array corresponding to the plurality of programmable points;
[0012] enabling the real scan chain, and inputting a test vector corresponding to the real scan chain into the real scan chain;
[0013] Turning off the real scan chain, capturing the output value of the combinational logic to the real scan chain; and
[0014] The real scan chain is enabled, an output value of the real scan chain is extracted, and whether the combinational logic has a functional fault is determined according to the output value of the real scan chain.
[0015] In a preferred embodiment, the real scan chain includes: n multiplexers and corresponding n triggers;
[0016] Each multiplexer is controlled by an enable signal, the output end of each multiplexer is respectively coupled to the data end of the corresponding trigger, an input end of each multiplexer is respectively coupled to an output of the combinational logic, another input end of the first multiplexer is coupled to the test vector corresponding to the real scan chain, and another input end of the second multiplexer to the nth multiplexer is respectively coupled to the output end of the first trigger to the n-1th trigger.
[0017] In a preferred example, the output terminal of the first trigger is also coupled to the combinational logic.
[0018] In a preferred example, the trigger is selected from one or more of the following groups: RS trigger, D trigger, and JK trigger.
[0019] In a preferred embodiment, the virtual scan chain includes: m multiplexers and corresponding m triggers;
[0020] Among them, each multiplexer is controlled by an enable signal, the output end of each multiplexer is respectively coupled to the data end of the corresponding trigger, the other input end of the first multiplexer is coupled to the test vector corresponding to the real scan chain, the other input ends of the second multiplexer to the nth multiplexer are respectively coupled to the output ends of the first trigger to the n-1th trigger, and the output end of each trigger is respectively coupled to the input of the combinational logic corresponding to the corresponding programmable point.
[0021] In a preferred example, the trigger is selected from one or more of the following groups: RS trigger, D trigger, and JK trigger.
[0022] In a preferred example, the programmable logic array includes a plurality of programmable points, and each programmable point includes a logic circuit.
[0023] The present application also discloses a system for implementing automated testing of a programmable logic array using an ATPG tool, comprising:
[0024] A test vector generation module, used for inserting a virtual scan chain, a combinational logic composed of a plurality of programmable points in a programmable logic array, and a real scan chain in an ATPG tool, wherein a plurality of outputs of the virtual scan chain correspond one-to-one to the plurality of programmable points and are respectively connected to the combinational logic, and generating a test vector using the ATPG tool;
[0025] A code stream generation module, configured to analyze the test vectors generated by the ATPG tool, extract the test vectors corresponding to the virtual scan chain, and add the test vectors to a portion of the downloaded code stream of the programmable logic array corresponding to the plurality of programmable points;
[0026] A fault analysis module is used to first enable the real scan chain to input the test vector corresponding to the real scan chain into the real scan chain, then disable the real scan chain to capture the output value of the combinational logic to the real scan chain, and enable the real scan chain again to extract the output value of the real scan chain and determine whether the combinational logic has a functional fault according to the output value of the real scan chain.
[0027] The present application also discloses a system for implementing automated testing of a programmable logic array using an ATPG tool, including:
[0028] a memory for storing computer executable instructions; and,
[0029] A processor, coupled to the memory, is configured to implement the steps in the method described above when executing the computer executable instructions.
[0030] The present application also discloses a computer-readable storage medium in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the steps in the method described above are implemented.
[0031] In the implementation manner of the present application, the algorithm advantages of the ATPG tool are used to generate complete test vectors, thereby realizing automated testing of the programmable logic array.
[0032] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 It is a flowchart of a method for realizing an automated testing of a programmable logic array using an ATPG tool according to the first embodiment of the present application.
[0034] Figure 2 is a schematic diagram of a programmable logic array circuit according to an embodiment of the present application.
[0035] Figure 3 It is a schematic diagram of the structure of an automated testing system for a programmable logic array using an ATPG tool according to the second embodiment of the present application. DETAILED DESCRIPTION
[0036] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0037] Description of some concepts:
[0038] Design for Test (DFT): DFT refers to the insertion of various hardware logics used to improve the testability (including controllability and observability) of the chip during the original chip design stage. Through this part of the logic, test vectors are generated to achieve the purpose of testing large-scale chips.
[0039] Scan Chain: Scan chain is a testability design implementation technology. It allows testers to control and observe the signal value of the internal trigger of the circuit from the outside by implanting a shift register.
[0040] Automatic Test Pattern Generation (ATPG): ATPG refers to the process of automatically generating test patterns used in semiconductor device testing. Test patterns are loaded into the device input pins in sequence, and the output signals are collected and compared with the budgeted test patterns to determine the test results.
[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0042] The first embodiment of the present application relates to a method for implementing automated testing of a programmable logic array using an ATPG tool, the process of which is as follows: Figure 1 As shown, the method comprises the following steps:
[0043] Step 101, inserting a virtual scan chain, a combinational logic composed of multiple programmable points in a programmable logic array, and a real scan chain into an ATPG tool, wherein multiple outputs of the virtual scan chain correspond to multiple programmable points one by one and are connected to the combinational logic respectively.
[0044] In one embodiment, the real scan chain includes n multiplexers and corresponding n triggers, wherein each multiplexer is controlled by an enable signal, an output end of each multiplexer is respectively coupled to a data end of a corresponding trigger, an input end of each multiplexer is respectively coupled to an output of a combinational logic, another input end of the first multiplexer is coupled to a test vector corresponding to the real scan chain, and another input end of the second multiplexer to the nth multiplexer is respectively coupled to an output end of the first trigger to the n-1th trigger.
[0045] In one embodiment, the output of the first flip-flop is further coupled to the combinational logic.
[0046] In one embodiment, the trigger of the real scan chain is selected from one or more of the following groups: RS trigger, D trigger, and JK trigger.
[0047] In one embodiment, the virtual scan chain includes m multiplexers and corresponding m triggers, wherein each multiplexer is controlled by an enable signal, the output end of each multiplexer is respectively coupled to the data end of the corresponding trigger, the other input end of the first multiplexer is coupled to the test vector corresponding to the real scan chain, the other input ends of the second multiplexer to the nth multiplexer are respectively coupled to the output ends of the first trigger to the n-1th trigger, and the output end of each trigger is respectively coupled to the input of the combinational logic corresponding to the corresponding programmable point.
[0048] In one embodiment, the trigger of the virtual scan chain is selected from one or more of the following groups: RS trigger, D trigger, JK trigger.
[0049] It should be understood that the virtual scan chain is only made before the circuit is input into the ATPG tool to replace the programmable points so that the ATPG tool can generate complete test vectors. However, there is no virtual scan chain in the actual circuit.
[0050] In one embodiment, the programmable logic array includes multiple programmable points (e.g., 3 or more), each of which includes a logic circuit. Each logic circuit obtains a corresponding value through an internal logic operation according to an external input. It should be understood that the programmable logic array may include multiple programmable points, and the multiple programmable points may constitute multiple different combinational logics.
[0051] Step 102: Generate test vectors using an ATPG tool.
[0052] Step 103 , analyzing the test vectors generated by the ATPG tool, extracting the test vectors corresponding to the virtual scan chain, and adding the test vectors to the partial download code stream of the programmable logic array corresponding to the plurality of programmable points.
[0053] Step 104 , enabling the real scan chain, and inputting the test vector corresponding to the real scan chain into the real scan chain.
[0054] Step 105 , closing the real scan chain, and capturing the output value of the combinational logic to the real scan chain.
[0055] Step 106 , enabling the real scan chain, extracting the output value of the real scan chain, and judging whether the combinational logic has a functional fault according to the output value of the real scan chain.
[0056] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.
[0057] In order to utilize the existing general DFT technology and tools to solve the shortcomings of the current FPGA programmable logic array testing methods, it is necessary to make some improvements to the test vector generation process of the FPGA programmable logic array. Without changing the original function of the programmable logic array, the advantages of the APTG tool can be fully utilized to generate efficient and high-coverage test vectors.
[0058] like Figure 2 As shown, the circuit of the programmable logic array can be abstracted as Figure 2 In the right box, Fuse0, Fuse1, and Fuse2 represent three different programmable points. The combinational logic function of the programmable logic array ( Figure 2 In the example above, the combination logic A is represented by "combinatorial logic A" and can actually be determined by the combination of the values of Fuse0, Fuse1, Fuse2 and the registers of the real scan chain. The sequential logic function is implemented by the registers in the right box. Defects in the manufacturing process will occur in the combination logic A and registers, resulting in functional failures. The ATPG tool generates various reasonable combinations of Fuse0, Fuse1, and Fuse2 through algorithms, and traverses various possible situations of the combination logic A. Any functional failure caused by a defect will be reflected in the registers in the right box. By transmitting the register values to the outside of the chip through the scan chain, defects and failures can be confirmed.
[0059] Although theoretically, the ATPG tool can generate all test vectors by analyzing the structure of combinational logic A through algorithms and generating various reasonable combinations of Fuse0, Fuse1, and Fuse2, the prerequisite is that the input ports of combinational logic A must be connected with scan chains (such as Figure 2 In this embodiment, the test vector is inserted before the ATPG tool is used to generate the test vector. Figure 2 In the "virtual scan chain" on the left, replace Fuse0, Fuse1, and Fuse2. After the test vector is generated, download the test vector to the fuse of the FPGA through the FPGA-specific download method for testing.
[0060] The specific test process is:
[0061] 1. Insert a virtual scan chain to replace the original fuse.
[0062] 2. Use ATPG tools to generate test vectors.
[0063] 3. Analyze the test vectors generated by the ATPG tool, extract the vectors that should have been loaded into the virtual scan chain, put them into the FPGA download code stream, and use the FPGA's unique download method to download these vectors to the corresponding fuse.
[0064] 4. Set scan_en to 1, turn on the shift function of the real scan chain, and move the vector that should be loaded into the real scan chain to the real scan chain through scan_in_real0.
[0065] 5. Set scan_en to 0 and capture the output of combinational logic A into the real scan chain.
[0066] 6. Set scan_en to 1, turn on the real scan chain, and move the value captured in the real scan chain to the outside of the chip through scan_out_real0 for inspection to determine whether the combinational logic A has any functional failure.
[0067] The second embodiment of the present application relates to a system for implementing automated testing of a programmable logic array using an ATPG tool, and its structure is as follows: Figure 2 As shown, the system for implementing automated testing of a programmable logic array using an ATPG tool includes a test vector generation module 201, a code stream generation module 202, and a fault analysis module 203. The test vector generation module 201 is used to insert a virtual scan chain, a combinational logic composed of multiple programmable points in a programmable logic array, and a real scan chain in the ATPG tool, wherein multiple outputs of the virtual scan chain correspond to multiple programmable points one by one and are respectively connected to the combinational logic, and use the ATPG tool to generate a test vector. The code stream generation module 202 is used to analyze the test vector generated by the ATPG tool, extract the test vector corresponding to the virtual scan chain, and add the test vector to the partially downloaded code stream of the programmable logic array corresponding to the multiple programmable points. The fault analysis module 203 is used to first enable the real scan chain to input the test vector corresponding to the real scan chain into the real scan chain, then turn off the real scan chain to capture the output value of the combinational logic to the real scan chain, and enable the real scan chain again to extract the output value of the real scan chain and judge whether the combinational logic has a functional fault according to the output value of the real scan chain.
[0068] The first implementation manner is a method implementation manner corresponding to the present implementation manner. The technical details in the first implementation manner can be applied to the present implementation manner, and the technical details in the present implementation manner can also be applied to the first implementation manner.
[0069] It should be noted that those skilled in the art should understand that the implementation functions of each module shown in the above-mentioned implementation method of the system for realizing the automated test of programmable logic arrays using ATPG tools can be understood by referring to the relevant description of the method for realizing the automated test of programmable logic arrays using ATPG tools. The functions of each module shown in the implementation method of the system for realizing the automated test of programmable logic arrays using ATPG tools can be realized by a program (executable instruction) running on a processor, or by a specific logic circuit. If the system for realizing the automated test of programmable logic arrays using ATPG tools in the embodiment of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM, Read Only Memory), a disk or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.
[0070] Accordingly, the present application also provides a computer-readable storage medium in which computer executable instructions are stored, and when the computer executable instructions are executed by the processor, the various method embodiments of the present application are implemented. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable storage media does not include temporary computer-readable media (transitory media), such as modulated data signals and carriers.
[0071] In addition, the embodiment of the present application also provides a system for implementing automated testing of programmable logic arrays using ATPG tools, which includes a memory for storing computer executable instructions, and a processor; the processor is used to implement the steps in the above-mentioned method implementations when executing the computer executable instructions in the memory. Among them, the processor can be a central processing unit (Central Processing Unit, referred to as "CPU"), or other general-purpose processors, digital signal processors (Digital Signal Processor, referred to as "DSP"), Application Specific Integrated Circuit (Application Specific Integrated Circuit, referred to as "ASIC"), etc. The aforementioned memory can be a read-only memory (read-only memory, referred to as "ROM"), a random access memory (random access memory, referred to as "RAM"), a flash memory (Flash), a hard disk or a solid-state hard disk, etc. The steps of the method disclosed in each embodiment of the present invention can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
[0072] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.
[0073] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.
[0074] In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Claims
1. A method for implementing automated testing of a programmable logic array using an ATPG tool, characterized in that: include: Inserting a virtual scan chain, a combinational logic composed of a plurality of programmable points in a programmable logic array, and a real scan chain in an ATPG tool, wherein a plurality of outputs of the virtual scan chain correspond one-to-one to the plurality of programmable points and are respectively connected to the combinational logic; Generate test vectors using the ATPG tool; Analyzing the test vectors generated by the ATPG tool, extracting the test vectors corresponding to the virtual scan chain, and adding the test vectors to a portion of the downloaded code stream of the programmable logic array corresponding to the plurality of programmable points; enabling the real scan chain, and inputting a test vector corresponding to the real scan chain into the real scan chain; Turning off the real scan chain, and capturing the output value of the combinational logic to the real scan chain; as well as The real scan chain is enabled, an output value of the real scan chain is extracted, and whether the combinational logic has a functional fault is determined according to the output value of the real scan chain.
2. The method for implementing automated testing of a programmable logic array using an ATPG tool as claimed in claim 1, wherein: The real scan chain includes: n multiplexers and corresponding n triggers; Each multiplexer is controlled by an enable signal, the output end of each multiplexer is respectively coupled to the data end of the corresponding trigger, an input end of each multiplexer is respectively coupled to an output of the combinational logic, another input end of the first multiplexer is coupled to the test vector corresponding to the real scan chain, and another input end of the second multiplexer to the nth multiplexer is respectively coupled to the output end of the first trigger to the n-1th trigger.
3. The method for implementing automated testing of a programmable logic array using an ATPG tool as claimed in claim 2, wherein: The output terminal of the first flip-flop is also coupled to the combinational logic.
4. The method for implementing automated testing of a programmable logic array using an ATPG tool as claimed in claim 2, wherein: The trigger is selected from one or more of the following groups: an RS trigger, a D trigger, and a JK trigger.
5. The method for implementing automated testing of a programmable logic array using an ATPG tool as claimed in claim 1, wherein: The virtual scan chain includes: m multiplexers and corresponding m triggers; Among them, each multiplexer is controlled by an enable signal, the output end of each multiplexer is respectively coupled to the data end of the corresponding trigger, the other input end of the first multiplexer is coupled to the test vector corresponding to the real scan chain, the other input ends of the second multiplexer to the nth multiplexer are respectively coupled to the output ends of the first trigger to the n-1th trigger, and the output end of each trigger is respectively coupled to the input of the combinational logic corresponding to the corresponding programmable point.
6. The method for implementing automated testing of a programmable logic array using an ATPG tool as claimed in claim 5, characterized in that: The trigger is selected from one or more of the following groups: an RS trigger, a D trigger, and a JK trigger.
7. The method for implementing automated testing of a programmable logic array using an ATPG tool as claimed in claim 1, wherein: The programmable logic array includes a plurality of programmable points, each of which includes a logic circuit.
8. A system for implementing automated testing of a programmable logic array using an ATPG tool, characterized in that: include: A test vector generation module, used for inserting a virtual scan chain, a combinational logic composed of a plurality of programmable points in a programmable logic array, and a real scan chain in an ATPG tool, wherein a plurality of outputs of the virtual scan chain correspond one-to-one to the plurality of programmable points and are respectively connected to the combinational logic, and generating a test vector using the ATPG tool; A code stream generation module, configured to analyze the test vectors generated by the ATPG tool, extract the test vectors corresponding to the virtual scan chain, and add the test vectors to a portion of the downloaded code stream of the programmable logic array corresponding to the plurality of programmable points; A fault analysis module is used to first enable the real scan chain to input the test vector corresponding to the real scan chain into the real scan chain, then disable the real scan chain to capture the output value of the combinational logic to the real scan chain, and enable the real scan chain again to extract the output value of the real scan chain and determine whether the combinational logic has a functional fault according to the output value of the real scan chain.
9. A system for implementing automated testing of a programmable logic array using an ATPG tool, characterized in that: include: A memory for storing computer executable instructions; as well as, A processor, coupled to the memory, configured to implement the steps of the method according to any one of claims 1 to 7 when executing the computer executable instructions.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the steps in the method according to any one of claims 1 to 7 are implemented.
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