A baseband processing board based on a single Beidou and a data processing method

Abstract

The present invention relates to a baseband processing board and a data processing method based on a single Beidou, which are implemented by an FPGA processing chip. The FPGA processing chip includes a programmable logic part, Core0, and Core1. The programmable logic part of the FPGA processing chip completes the acquisition and tracking of Beidou signals. Core1 is used for the acquisition and tracking control of baseband signals, and writes the generated navigation message and observables into the shared memory for Core0 to process. Core0 reads the conformal memory data, parses the navigation message and performs PVT solution, receives external control instructions, outputs NMEA and RTCM protocols, configures the acquisition and tracking parameters of Core1, receives RTCM data to achieve RTK positioning, and realizes system upgrade, data backup and recovery, and log storage. The present invention can more effectively extract navigation information and improve positioning efficiency by the cooperation of a dual-ARM core and a logic processing unit in the FPGA chip to complete signal processing.

Description

Technical Field

[0001] The present invention relates to the field of communications, and particularly to a baseband processing board based on a single Beidou satellite and a data processing method therefor. Background Art

[0002] Existing baseband processing boards generally focus on signal reception and processing of satellite systems, and usually adopt a scheme architecture of a general mainboard CPU + a dedicated PVT processing module; however, the existing technology fails to fully utilize the advantages of a single Beidou system, lacks specialized processing of single Beidou signals, and the overall performance and efficiency of the system are not high, and the power consumption and volume of a single board are relatively large. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art, and provide a baseband processing board based on a single Beidou satellite and a data processing method therefor, so as to solve the problems existing in the prior art.

[0004] The purpose of the present invention is achieved by the following technical solutions: A data processing method for a baseband processing board based on a single Beidou satellite, the method is implemented by an FPGA processing chip, and the FPGA processing chip includes a programmable logic part and two ARM cores, namely Core0 and Core1;

[0005] The programmable logic part of the FPGA processing chip completes the acquisition and tracking of Beidou signals;

[0006] Core1 is used for the acquisition and tracking control of baseband signals, and writes the generated navigation message and observables into a shared memory for Core0 to process;

[0007] Core0 reads the data in the conformal memory, parses the navigation message and performs PVT solution, and receives external control instructions, outputs protocols in NMEA, RTCM formats and other formats, configures the acquisition and tracking parameters of Core1 in the form of a shared memory, receives RTCM data to implement RTK positioning, and realizes system upgrade, data backup and recovery, and log storage.

[0008] The data processing process between Core0 and Core1 includes:

[0009] Core0 issues an acquisition command to Core1, Core1 enables the channel module, controls the pseudo-code generator to generate pseudo-code, and starts the acquisition module;

[0010] The programmable logic part completes signal search through the acquisition module for matched filtering and FFT, and at the same time Core0 maintains and refreshes the acquisition and tracking states of the channels;

[0011] The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler offset data, and completes the calculation of loop filter parameters and loop control. Then, the programmable logic part completes signal synchronization tracking through the tracking channel module's processing of the NCO of the signal code and the NCO of the signal carrier. At the same time, Core0 performs channel acquisition and maintenance and refresh of the tracking state;

[0012] After Core1 completes bit synchronization, frame synchronization, telemetry decoding and parsing, it performs subsequent data processing through Core0.

[0013] The subsequent data processing through Core0 includes:

[0014] Core0 obtains the telemetry sent by Core1, and at the same time obtains the pseudo-code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part, and then performs positioning, velocity measurement and timing operations;

[0015] Core0 sends the set local time to the programmable logic part. The programmable logic part completes internal time counting through the TIC module, generates an observation sampling interrupt signal for the tracking channel module, and at the same time Core0 performs data protocol framing and output.

[0016] A single Beidou baseband processing board includes an FPGA processing chip and its peripheral circuits connected thereto. The FPGA processing chip includes a programmable logic part and two ARM cores, Core0 and Core1;

[0017] The programmable logic part completes the acquisition and tracking of Beidou signals;

[0018] Core1 is used for the acquisition and tracking control of baseband signals, and writes the generated navigation telemetry and observables into the shared memory for Core0 to process;

[0019] Core0 reads the conformal memory data, performs navigation telemetry parsing and PVT solution, and receives external control instructions, outputs NMEA, RTCM protocols and other format protocols, configures the acquisition and tracking parameters of Core1 in the way of shared memory, receives RTCM data to achieve RTK positioning, and realizes system upgrade, data backup recovery and log storage.

[0020] The data processing process between Core0 and Core1 includes:

[0021] Core0 issues an acquisition command to Core1. Core1 activates the channel module, controls the pseudo-code generator to generate pseudo-code, and starts the acquisition module;

[0022] The programmable logic part completes signal search by matching filtering through the capture module and performing FFT. Meanwhile, Core0 maintains and refreshes the capture and tracking status of the channel.

[0023] The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler shift data, and completes the calculation of loop filter parameters and loop control. Then, the programmable logic part completes signal synchronization tracking through the NCO of the signal code and the NCO of the signal carrier in the tracking channel module. Meanwhile, Core0 maintains and refreshes the capture and tracking status of the channel.

[0024] After Core1 completes bit synchronization, frame synchronization, message decoding and parsing, subsequent data processing is carried out through Core0.

[0025] The subsequent data processing through Core0 includes:

[0026] Core0 obtains the message sent by Core1, and at the same time obtains the pseudo-code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part, and then performs positioning, speed measurement and timing operations.

[0027] Core0 sends the set local time to the programmable logic part. The programmable logic part completes internal time counting through the TIC module, generates an observable sampling interrupt signal to the tracking channel module, and at the same time Core0 performs data protocol framing and output.

[0028] The peripheral circuit includes a power supply part, a radio frequency part, an interface part, an RTC and a clock part connected to the FPGA processing chip; the interface part includes a network interface, a USB interface, and an RS422 / 232 interface.

[0029] The present invention has the following advantages: A baseband processing board and a data processing method based on a single Beidou satellite complete signal processing through the cooperation of a dual-ARM core + logic processing unit in the FPGA chip. Compared with traditional multi-satellite system receivers, the two cores in the ARM perform their respective duties, and cooperate with the FPGA logic part to complete various functions of the entire receiver, which can more effectively extract navigation information, improve positioning efficiency, and achieve more efficient and accurate signal processing capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic structural diagram of the baseband processing board of the present invention;

[0031] Figure 2 is a schematic flow diagram of the method of the present invention;

[0032] Figure 3 is a schematic circuit diagram of the radio frequency part;

[0033] Figure 4 It is a circuit schematic diagram of the clock part. Specific implementation manners

[0034] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of the present application, rather than all of them. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the protection scope of the present application claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application. The present invention will be further described below with reference to the accompanying drawings.

[0035] As Figure 1 shown, the baseband processing board of the present invention based on a single Beidou mainly includes a power supply part, a radio frequency part, an FPGA, an RTC (real-time clock), a network interface, a USB interface, a 422 / 232 interface and peripheral circuits, etc.; the Beidou satellite signals received by the antenna first pass through a low-noise amplifier, and then are distributed to 6 channels by a power divider device. After passing through a band-pass filter (SAW), they enter the radio frequency chip, and the radio frequency chip digitizes the signals and sends them to the FPGA to complete positioning and calculation; among them, the number of signal tracking channels is 256, supporting a single Beidou BDS. Each tracking channel can complete carrier tracking, pseudo-code tracking, and message demodulation of Beidou satellite signals, and provide raw observables for positioning and calculation.

[0036] Furthermore, in the FPGA processing chip, an SOC processing system is embedded for PVT and protocol processing, which includes two ARM Cortex-A9 processors, Core0 and Core1, both with an operating frequency of 800 MHz. The programmable logic (PL) part of the FPGA completes the acquisition and tracking of Beidou signals. Core1 is used for the acquisition and tracking control of baseband signals, and writes the generated navigation message and observables into the shared memory for Core0 to process. Core0 is equipped with a lightweight embedded operating system to implement a network protocol stack and a FAT file system. Core0 reads the data in the shared memory for the parsing of navigation messages and PVT calculation, and receives external control instructions, outputs protocols in NMEA, RTCM and other formats, configures the acquisition and tracking parameters of Core1 in the form of shared memory, receives RTCM data to implement RTK positioning, and realizes system upgrade, data backup and recovery, and log storage.

[0037] As Figure 2 shown, the data processing process between Core0 and Core1 includes:

[0038] Core0 sends a capture command to Core1. Core1 enables the channel module, controls the pseudo-code generator to generate pseudo-code, and starts the capture module;

[0039] The programmable logic part completes signal search through the capture module by matching filtering and performing FFT. At the same time, Core0 maintains and refreshes the capture and tracking status of the channel;

[0040] The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler offset data, and completes the calculation of loop filter parameters and loop control. Then, the programmable logic part completes signal synchronization tracking through the tracking channel module for the NCO of the signal code and the NCO (numerically controlled oscillator) of the signal carrier. At the same time, Core0 maintains and refreshes the capture and tracking status of the channel;

[0041] Core1 completes bit synchronization, frame synchronization, message decoding and parsing. Core0 obtains the message sent by Core1, and at the same time obtains the pseudo-code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part, and then performs positioning, velocity measurement and timing operations;

[0042] Core0 sends the set local time to the programmable logic part. The programmable logic part completes internal time counting through the TIC module, generates an observable sampling interrupt signal for the tracking channel module, and at the same time Core0 performs data protocol framing and output.

[0043] As Figure 3 shown, the Beidou signal first arrives at the antenna module. The weak satellite signal received by the antenna is amplified by the amplifier and sent to the power divider, and then the satellite signal is split through the filter. The six-way satellite signals split out respectively enter the RF chip A and the RF chip B. After down-conversion, amplification and analog-to-digital conversion inside the RF chip, the digital intermediate frequency is output.

[0044] As Figure 4 shown, the clock circuit is divided into RF clock and baseband clock. The RF clock is 10MHz and the baseband clock is 33.33MHz. The RF clock has an on-board clock and an external clock. When the FPGA detects the external clock input, it can control the CTRL to complete the clock switching.

[0045] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and improvements, and can be changed within the scope of the concept described herein through the above teachings or the techniques or knowledge in related fields. And the changes and alterations made by those skilled in the art that do not depart from the spirit and scope of the present invention shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A data processing method for a baseband processing board based on a single Beidou satellite, characterized in that: The method is implemented by an FPGA processing chip, which includes a programmable logic part and two ARM cores, Core0 and Core1; The programmable logic part of the FPGA processing chip completes the acquisition and tracking of Beidou signals; Core1 is used for the acquisition and tracking control of baseband signals, and writes the generated navigation message and observables into the shared memory for Core0 to process; Core0 reads the conformal memory data, parses the navigation message and performs PVT solution, and receives external control instructions, outputs NMEA, RTCM protocols and other format protocols, configures the acquisition and tracking parameters of Core1 in the way of shared memory, receives RTCM data to achieve RTK positioning, and realizes system upgrade, data backup recovery and log storage; The data processing process between Core0 and Core1 includes: Core0 issues an acquisition command to Core1, Core1 enables the channel module, controls the pseudo-code generator to generate pseudo-code, and starts the acquisition module; The programmable logic part completes signal search through the acquisition module for matched filtering and FFT. At the same time, Core0 maintains and refreshes the acquisition and tracking status of the channel; The programmable logic part judges whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler offset data, and completes the calculation of loop filter parameters and loop control. Then the programmable logic part completes signal synchronization tracking through the tracking channel module for the NCO of the signal code and the NCO of the signal carrier. At the same time, Core0 maintains and refreshes the acquisition and tracking status of the channel; After Core1 completes bit synchronization, frame synchronization, message decoding and parsing, it performs subsequent data processing through Core0; The subsequent data processing through Core0 includes: Core0 obtains the message sent by Core1, and at the same time obtains the pseudo-code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part, and then performs positioning, speed measurement and timing operations; Core0 sends the set local time to the programmable logic part. The programmable logic part completes the internal time count through the TIC module, generates an observable sampling interrupt signal to the tracking channel module, and at the same time Core0 performs data protocol framing and output.

2. A single Beidou baseband processing board, which includes an FPGA processing chip and its connected peripheral circuits, is characterized in that: The FPGA processing chip includes a programmable logic part and two ARM cores, Core0 and Core1; The programmable logic part completes the acquisition and tracking of Beidou signals; Core1 is used for the acquisition and tracking control of baseband signals, and writes the generated navigation message and observables into the shared memory for Core0 to process; Core0 reads the shared memory data, parses the navigation message and performs PVT solution, and receives external control instructions, outputs NMEA, RTCM protocols and other format protocols, configures the acquisition and tracking parameters of Core1 in the way of shared memory, receives RTCM data to achieve RTK positioning, and realizes system upgrade, data backup recovery and log storage; The data processing process between Core0 and Core1 includes: Core0 issues a capture command to Core1. Core1 enables the channel module, controls the pseudorandom code generator to generate pseudorandom code, and starts the capture module; The programmable logic part completes signal search through the capture module's matched filtering and FFT. Meanwhile, Core0 maintains and refreshes the capture and tracking status of the channel; The programmable logic part determines whether the search is successful. If successful, Core1 obtains the signal code phase data and Doppler shift data, and completes the calculation of loop filter parameters and loop control. Then, the programmable logic part completes signal synchronization tracking through the tracking channel module's processing of the NCO of the signal code and the NCO of the signal carrier. Meanwhile, Core0 maintains and refreshes the capture and tracking status of the channel; After Core1 completes bit synchronization, frame synchronization, message decoding and parsing, subsequent data processing is performed through Core0; The subsequent data processing through Core0 includes: Core0 obtains the message sent by Core1, and at the same time obtains the pseudorandom code NCO count, bit count, frame calculation and carrier NCO count sent by the programmable logic part, and then performs positioning, speed measurement and timing operations; Core0 sends the set local time to the programmable logic part. The programmable logic part completes internal time counting through the TIC module, generates an observation sampling interrupt signal for the tracking channel module, and at the same time Core0 performs data protocol framing and output.

3. A single Beidou baseband processing board according to claim 2, characterized in that: The peripheral circuit includes a power supply part, a radio frequency part, an interface part, an RTC and a clock part connected to the FPGA processing chip; the interface part includes a network interface, a USB interface, and an RS422 / 232 interface.

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