Semiconductor package

Abstract

There is provided a semiconductor package including: a package substrate; a connection substrate mounted on the package substrate and including a first conductive connection structure; a first integrated circuit device mounted on the package substrate; and a second integrated circuit device disposed on the connection substrate and the first integrated circuit device and including a first portion overlapping the first integrated circuit device and a second portion overlapping the connection substrate, where one of the first integrated circuit device and the second integrated circuit device includes a photonic integrated circuit device to which an optical fiber is attached, and the other of the first and second integrated circuit devices comprises an electronic integrated circuit device, and wherein the second integrated circuit device is electrically connected to the package substrate via the first conductive connection structure of the connection substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0075068 filed in the Korean Intellectual Property Office on June 12, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to semiconductor packages and, more particularly, to semiconductor packages including electronic integrated circuit devices and photonic integrated circuit devices. Background Art

[0004] With the rapid development of the electronics industry, electrical devices are required to have higher data transmission speeds. Recently, attempts have been made to apply photonic devices to electrical devices to achieve high data transmission speeds. For example, various studies are being conducted on co-packaged optical (CPO) packages including photonic integrated circuit (PIC) devices and electronic integrated circuit (EIC) devices to meet the needs of increasing communication speeds and reducing signal loss. Summary of the invention

[0005] The present disclosure provides a semiconductor package including an electronic integrated circuit device and a photonic integrated circuit device.

[0006] According to one aspect of the present disclosure, a semiconductor package is provided, comprising: a packaging substrate; a connecting substrate mounted on the packaging substrate and comprising a first conductive connection structure; a first integrated circuit device mounted on the packaging substrate; and a second integrated circuit device arranged on the connecting substrate and the first integrated circuit device and comprising a first portion overlapping with the first integrated circuit device and a second portion overlapping with the connecting substrate, wherein one of the first integrated circuit device and the second integrated circuit device comprises a photonic integrated circuit device to which an optical fiber is attached, and the other of the first integrated circuit device and the second integrated circuit device comprises an electronic integrated circuit device, and wherein the second integrated circuit device is electrically connected to the packaging substrate via the first conductive connection structure of the connecting substrate.

[0007] According to another aspect of the present disclosure, a semiconductor package is provided, comprising: a packaging substrate; a connecting substrate mounted on the packaging substrate and comprising a molded base layer and a plurality of molded through-electrodes penetrating the molded base layer; a photonic integrated circuit device mounted on the packaging substrate and configured to receive and receive optical signals via optical fibers; and an electronic integrated circuit device mounted on the photonic integrated circuit device and the connecting substrate and configured to process signals provided by the photonic integrated circuit device; wherein the electronic integrated circuit device is directly connected to the photonic integrated circuit device and the connecting substrate, and the electronic integrated circuit device is electrically connected to the packaging substrate via the plurality of molded through-electrodes.

[0008] According to another aspect of the present disclosure, a semiconductor package is provided, comprising: a packaging substrate; a connecting substrate mounted on the packaging substrate; a first integrated circuit device mounted on the packaging substrate; a second integrated circuit device disposed on the connecting substrate and the first integrated circuit device, the second integrated circuit device being directly connected to the first integrated circuit device and being electrically connected to the packaging substrate via the connecting substrate; and a third integrated circuit device mounted on the connecting substrate and being electrically connected to the second integrated circuit device via the connecting substrate, wherein one of the first integrated circuit device and the second integrated circuit device comprises a photonic integrated circuit device attached with an optical fiber, and the other of the first integrated circuit device and the second integrated circuit device comprises an electronic integrated circuit device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view of a semiconductor package according to some embodiments;

[0011] Figure 2 is a plan view of a first integrated circuit device and a connection substrate of a semiconductor package according to some embodiments;

[0012] Figure 3 is a plan view of a first integrated circuit device and a connection substrate of a semiconductor package according to some embodiments;

[0013] Figure 4 is an enlarged view of a junction region between a first integrated circuit device and a second integrated circuit device in a semiconductor package according to some embodiments;

[0014] Figure 5 is an enlarged view of a junction region between a connection substrate and a second integrated circuit device in a semiconductor package according to some embodiments;

[0015] Figure 6 is a cross-sectional view of a semiconductor package according to some embodiments;

[0016] Figure 7 is a cross-sectional view of a semiconductor package according to some embodiments;

[0017] Figure 8 is a cross-sectional view of a semiconductor package according to some embodiments;

[0018] Fig. 9 is a cross-sectional view of a semiconductor package according to some embodiments;

[0019] Fig.10is a cross-sectional view of a semiconductor package according to some embodiments;

[0020] FIG. 11A to FIG. 11E is a diagram for explaining a method of manufacturing a semiconductor package according to some embodiments; and

[0021] Fig. 12A and Fig. 12B is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and redundant descriptions thereof are omitted.

[0023] In the present disclosure, the vertical direction may be defined as the Z direction, and the horizontal direction may be defined as a direction perpendicular to the Z direction. The first horizontal direction and the second horizontal direction may be defined as directions intersecting each other. The first horizontal direction may be referred to as the X direction, and the second horizontal direction may be referred to as the Y direction. The horizontal width of a component may be referred to as its length in the horizontal direction, and the vertical level of a component may be referred to as its position in the vertical direction.

[0024] Figure 1 is a cross-sectional view of a semiconductor package 10 according to some embodiments.

[0025] refer to Figure 1 , the semiconductor package 10 includes a package substrate 510 , a first integrated circuit device 100 , a second integrated circuit device 200 , and a connection substrate 300 .

[0026] The semiconductor package 10 may include a photonic integrated circuit (PIC) device configured to transceive and process optical signals, and an electronic integrated circuit (EIC) device configured to process signals provided by the PIC device. The semiconductor package 10 may include a co-packaged optical (CPO) package in which the PIC device and the EIC device are packaged together. Any one of the first integrated circuit device 100 and the second integrated circuit device 200 may include a PIC device, and the other may include an EIC device.

[0027] The package substrate 510 may include, for example, a printed circuit board (PCB), a flexible substrate, or a tape substrate. The package substrate 510 includes a substrate base 511, a plurality of substrate upper pads 513 disposed in the upper surface of the substrate base 511, and a plurality of substrate lower pads 515 disposed in the lower surface of the substrate base 511. The substrate base 511 may include at least one material of phenolic resin, epoxy resin, and polyimide. Each substrate upper pad 513 and each substrate lower pad 515 may include a conductive material (e.g., copper). The external connection terminal 520 may be attached to each of the plurality of substrate lower pads 515.

[0028] The first integrated circuit device 100 may be mounted on a package substrate 510. For example, the first integrated circuit device 100 may be mounted on the package substrate 510 via a plurality of first chip connection bumps 411. Each of the first chip connection bumps 411 may include, for example, a solder bump.

[0029] The first integrated circuit device 100 includes a plurality of lower bump pads 181 disposed in its lower surface, and a plurality of first connection pads 110 disposed in its upper surface. Each lower bump pad 181 and each first connection pad 110 may include a conductive material (e.g., copper). Each first chip connection bump 411 may be disposed between a corresponding lower bump pad 181 among the plurality of lower bump pads 181 and a corresponding substrate pad 513 among the plurality of substrate upper pads 513. Electrical signals (e.g., input / output data signals, power supply signals, ground signals, etc.) may be transmitted between the first integrated circuit device 100 and the package substrate 510 via the plurality of first chip connection bumps 411.

[0030] The second integrated circuit device 200 may be stacked on the first integrated circuit device 100 in an offset stacking manner or a shifted stacking manner. A first portion of the second integrated circuit device 200 may vertically overlap with the first integrated circuit device 100 and may be attached to the first integrated circuit device 100. A second portion of the second integrated circuit device 200 may not vertically overlap with the first integrated circuit device 100 and protrude from one side surface of the first integrated circuit device 100 in a horizontal direction (e.g., in the X direction and / or the Y direction). In addition, the first integrated circuit device 100 may include a first portion of the first integrated circuit device 100 vertically overlapping with or covered with the second integrated circuit device 200, and a second portion of the first integrated circuit device 100 not vertically overlapping with or covered with the second integrated circuit device 200.

[0031] The second integrated circuit device 200 may be connected to the first integrated circuit device 100 without a connection medium such as a bump. In some embodiments, the second integrated circuit device 200 may be bonded to the first integrated circuit device 100 in a copper-to-copper direct bonding manner or a hybrid bonding manner. The second integrated circuit device 200 includes a plurality of second connection pads 210 disposed in a lower surface thereof. Some of the second connection pads 210 of the plurality of second connection pads 210 of the second integrated circuit device 200 may be directly connected to the first connection pads 110 of the first integrated circuit device 100. Between the first integrated circuit device 100 and the second integrated circuit device 200, electrical signals may be transmitted via the first connection pads 110 of the first integrated circuit device 100 and the second connection pads 210 of the second integrated circuit device 200.

[0032] The connection substrate 300 may be disposed between the second integrated circuit device 200 and the package substrate 510, and may be disposed on one side of the first integrated circuit device 100. The connection substrate 300 may completely or partially overlap with the second portion of the second integrated circuit device 200 in the vertical direction. The connection substrate 300 may provide an electrical signal path for transmitting electrical signals between the second integrated circuit device 200 and the package substrate 510. The connection substrate 300 may be mounted on the package substrate 510. For example, the connection substrate 300 may be mounted on the package substrate 510 via a plurality of second chip connection bumps 413. Each second chip connection bump 413 may include, for example, a solder bump.

[0033] The connection substrate 300 includes an insulating base layer 310 and a plurality of through electrodes 320 disposed in the insulating base layer 310 .

[0034] The insulating base layer 310 may include a base layer based on molding. The insulating base layer 310 may include, for example, a resin layer (e.g., epoxy resin), and an organic filler and / or an inorganic filler contained in the resin layer. For example, the insulating base layer 310 may be formed of an epoxy molding compound (EMC).

[0035] Each of the plurality of through electrodes 320 may extend from the lower surface of the insulating base layer 310 to the upper surface of the insulating base layer 310 to penetrate the insulating base layer 310. Each of the plurality of through electrodes 320 may include a molded through electrode that vertically penetrates the molded base layer. Each through electrode 320 may include a conductive material (e.g., copper). In some embodiments, the lower surface of each through electrode 320 may be coplanar with the lower surface of the insulating base layer 310, and the upper surface of each through electrode 320 may be coplanar with the upper surface of the insulating base layer 310. The lower surface of each through electrode 320 may be connected to a corresponding second chip connection bump 413 among the second chip connection bumps 413, and the upper surface of each through electrode 320 may be connected to a corresponding second connection pad 210 among the second connection pads 210 of the second integrated circuit device 200. Each through electrode 320 may be electrically connected to a corresponding substrate pad 513 among a plurality of substrate pads 513 via a corresponding second chip connection bump 413 among the plurality of second chip connection bumps 413. Between the second integrated circuit device 200 and the package substrate 510, electrical signals (e.g., input / output data signals, power supply signals, ground signals, etc.) may be transmitted via the plurality of through electrodes 320 and the plurality of second chip connection bumps 413. The plurality of through electrodes 320 may include a structure for electrical connection between the package substrate 510 and the second integrated circuit device 200, and in the present disclosure, the plurality of through electrodes 320 may be referred to as a first conductive connection structure.

[0036] In some embodiments, the first integrated circuit device 100 may include a PIC device connected to at least one optical fiber OF, and the second integrated circuit device 200 may include an EIC device. The PIC device may include, for example, a light source, a photonic waveguide, a filter, a coupler, etc. The PIC device may be configured to receive and transmit optical signals from and to an external device via the optical fiber OF, and may be configured to convert an electrical signal provided by the EIC device into an optical signal. Various signals (e.g., input / output data signals, power supply signals, ground signals, etc.) may be transmitted between the PIC device and the external device via the optical fiber OF. The EIC device may be configured to convert an optical signal provided by the PIC device into an electrical signal. Because the semiconductor package 10 includes a CPO package in which the PIC device and the EIC device are packaged together, high-speed data signal processing can be achieved with low power.

[0037] Figure 2 and Figure 3 are plan views of a first integrated circuit device 100 and a connection substrate 300 of a semiconductor package 10 according to some embodiments, respectively.

[0038] refer to Figure 2, the insulating base layer 310 of the connection substrate 300 may directly contact one side surface of the first integrated circuit device 100, and may continuously extend along one side surface of the first integrated circuit device 100. In some embodiments, the connection substrate 300 may also be spaced apart from the first integrated circuit device 100 in a horizontal direction (e.g., in the X direction and / or the Y direction).

[0039] refer to Figure 3 , the insulating base layer 310 of the connection substrate 300 may extend along the side surface of the first integrated circuit device 100 and may surround the first integrated circuit device 100. Because the side surface of the first integrated circuit device 100 is covered by the insulating base layer 310 of the connection substrate 300, the side surface of the first integrated circuit device 100 may not be exposed to the outside.

[0040] Figure 4 is an enlarged view of a junction region between a first integrated circuit device 100A and a second integrated circuit device 200A in a semiconductor package 10 according to some embodiments. Hereinafter, the above description is omitted or simplified.

[0041] refer to Figure 4 , the first integrated circuit device 100A includes a first semiconductor substrate 131 , a first semiconductor device layer 133 and a first bonding layer 120 .

[0042] The first semiconductor substrate 131 may include silicon (eg, crystalline silicon, polycrystalline silicon, or amorphous silicon). The first semiconductor substrate 131 includes an active surface 131F and an inactive surface opposite to each other. The active surface 131F of the first semiconductor substrate 131 may correspond to an upper surface of the first semiconductor substrate 131.

[0043] The first semiconductor device layer 133 may be disposed on the active surface 131F of the first semiconductor substrate 131. The first semiconductor device layer 133 may include a first front end of line (FEOL) structure formed on the active surface 131F of the first semiconductor substrate 131, and a first back end of line (BEOL) structure formed on the first FEOL structure. The first FEOL structure may include a first individual device formed in the first semiconductor substrate 131 and / or formed on the active surface 131F of the first semiconductor substrate 131. The first BEOL structure may include a distribution layer having a multi-layer structure.

[0044] The first bonding layer 120 may be disposed on the first semiconductor device layer 133 . The first bonding layer 120 includes a plurality of first connection pads 110 , and a first pad insulating layer 121 surrounding each of the plurality of first connection pads 110 .

[0045] The first pad insulating layer 121 may include oxide and / or nitride. For example, the first pad insulating layer 121 may include at least one of SiO, SiN, SiCN, SiCO, and a polymer material. The upper surface of the first pad insulating layer 121 may constitute the upper surface of the first integrated circuit device 100A.

[0046] A plurality of first connection pads 110 may be arranged at substantially the same vertical level as each other. The upper surfaces of the plurality of first connection pads 110 may constitute the upper surface of the first integrated circuit device 100A. Each first connection pad 110 may include a metal material (e.g., copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or gold (Au)).

[0047] The second integrated circuit device 200A includes a second semiconductor substrate 231 , a second semiconductor device layer 233 , and a second bonding layer 220 .

[0048] The second semiconductor substrate 231 includes an active surface 231F and an inactive surface opposite thereto. The active surface 231F of the second semiconductor substrate 231 may correspond to a lower surface of the second semiconductor substrate 231. The material of the second semiconductor substrate 231 may be the same as or similar to that of the first semiconductor substrate 131.

[0049] The second semiconductor device layer 233 may be disposed below the active surface 231F of the second semiconductor substrate 231. The second semiconductor device layer 233 may include a second FEOL structure formed below the active surface 231F of the second semiconductor substrate 231, and a second BEOL structure formed below the second FEOL structure. The second FEOL structure may include a second separate device formed in the second semiconductor substrate 231 and / or formed on the active surface 231F of the second semiconductor substrate 231. The second BEOL structure may include a distribution layer having a multi-layer structure.

[0050] The second bonding layer 220 may be disposed under the second semiconductor device layer 233 and may directly contact the first bonding layer 120 of the first integrated circuit device 100A. The second bonding layer 220 includes a plurality of second connection pads 210 and a second pad insulating layer 221 surrounding each of the plurality of second connection pads 210.

[0051] The second pad insulating layer 221 may include oxide and / or nitride. For example, the second pad insulating layer 221 may include at least one of SiO, SiN, SiCN, SiCO and a polymer material. The lower surface of the second pad insulating layer 221 may constitute the lower surface of the second integrated circuit device 200A.

[0052] A plurality of second connection pads 210 may be arranged at substantially the same vertical level as each other. The lower surface of the plurality of second connection pads 210 may constitute the lower surface of the second integrated circuit device 200A. Each second connection pad 210 may include a metal material (e.g., copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or gold (Au)).

[0053] The first integrated circuit device 100A can be bonded to the second integrated circuit device 200A by using a hybrid bonding process. The upper surface of the first pad insulating layer 121 and the lower surface of the second pad insulating layer 221 can be bonded to each other, and the upper surfaces of the plurality of first connection pads 110 can be bonded to the lower surfaces of the plurality of second connection pads 210, respectively. In some embodiments, the material of the first pad insulating layer 121 can be the same as the material of the second pad insulating layer 221. For example, the first pad insulating layer 121 and the second pad insulating layer 221 can include silicon oxide. In some embodiments, the silicon oxide layer of the first pad insulating layer 121 can directly contact the silicon oxide layer of the second pad insulating layer 221. For the bonding between the first integrated circuit device 100A and the second integrated circuit device 200A, the upper surfaces of the first pad insulating layer 121 and the second pad insulating layer 221 can have a bonding force suitable for bonding by using a plasma process and / or a wet process. The plurality of first connection pads 110 and the plurality of second connection pads 210 can include the same metal (e.g., copper).

[0054] Figure 5 is an enlarged view of a bonding region between a connection substrate 300A and a second integrated circuit device 200A in a semiconductor package 10 according to some embodiments. Hereinafter, the above description is omitted or simplified.

[0055] refer to Figure 5 , the connection substrate 300A includes a third bonding layer 330 disposed on the insulating base layer 310 . The third bonding layer 330 includes a plurality of third connection pads 331 , and a third pad insulating layer 333 surrounding each of the plurality of third connection pads 331 .

[0056] The third pad insulating layer 333 may include oxide and / or nitride. For example, the third pad insulating layer 333 may include at least one of SiO, SiN, SiCN, SiCO and a polymer material. The upper surface of the third pad insulating layer 333 may constitute the upper surface of the third integrated circuit device 400.

[0057] The plurality of third connection pads 331 may be at the same vertical level as each other. Each third connection pad 331 may be connected to the through electrode 320. The upper surface of the plurality of third connection pads 331 may constitute the upper surface of the third integrated circuit device 400. Each third connection pad 331 may include a metal material (e.g., Cu, Al, W, Ag, or Au).

[0058] The connection substrate 300A can be bonded to the second integrated circuit device 200A by using hybrid bonding. The upper surface of the third pad insulating layer 333 and the lower surface of the second pad insulating layer 221 can be bonded to each other, and the upper surfaces of the plurality of third connection pads 331 can be bonded to the lower surfaces of the plurality of second connection pads 210, respectively. In some embodiments, the material of the third pad insulating layer 333 can be the same as the material of the second pad insulating layer 221. For example, the third pad insulating layer 333 and the second pad insulating layer 221 can include silicon oxide. In some embodiments, the silicon oxide layer of the third pad insulating layer 333 can directly contact the silicon oxide layer of the second pad insulating layer 221. For the bonding between the connection substrate 300A and the second integrated circuit device 200A, the upper surface of the third pad insulating layer 333 and the lower surface of the second pad insulating layer 221 can have a bonding force suitable for bonding by using plasma treatment and / or wet treatment processes. The plurality of third connection pads 331 and the plurality of second connection pads 210 can include the same metal (e.g., copper).

[0059] Figure 6 is a cross-sectional view of a semiconductor package 10A according to some embodiments. Figure 6 The semiconductor package 10A shown in FIG. Figure 1 Differences in the semiconductor package 10 are described.

[0060] refer to Figure 6 , the semiconductor package 10A includes a package substrate 510 , a first integrated circuit device 100 , a second integrated circuit device 200 , a connection substrate 300B, and a third integrated circuit device 400 .

[0061] The second integrated circuit device 200 and the third integrated circuit device 400 can be mounted on the connection substrate 300B, and can be spaced apart from each other in the horizontal direction (e.g., in the X direction and / or the Y direction) on the connection substrate 300B. The second integrated circuit device 200 can be mounted on the connection substrate 300B via the third chip connection bump 421, and the third integrated circuit device 400 can be mounted on the connection substrate 300B via the fourth chip connection bump 423 attached to the pad 410 on its lower surface. The second integrated circuit device 200 and the third integrated circuit device 400 can be electrically connected to each other via the connection substrate 300B. The third integrated circuit device 400 may include an application-specific integrated circuit (ASIC) device, a memory device, a logic device, and / or a server. In the present disclosure, the connection substrate 300B may also be referred to as an interposer.

[0062] The connection substrate 300B includes a base layer 341 , a plurality of through electrodes 343 , a lower conductive pad 345 , and a redistribution structure 350 .

[0063] The base layer 341 may include a silicon-based base layer. The base layer 341 may include silicon (Si) (eg, crystalline silicon, polycrystalline silicon, or amorphous silicon). The base layer 341 may generally have a plate shape, and an upper surface and an lower surface facing each other.

[0064] The redistribution structure 350 may be disposed on an upper surface of the base layer 341. The redistribution structure 350 includes a redistribution insulation layer 351 covering the upper surface of the base layer 341, and a conductive redistribution pattern 353 covered by the redistribution insulation layer 351.

[0065] In some embodiments, the redistribution insulating layer 351 may include an organic insulating material. For example, the redistribution insulating layer 351 may include a photo-imageable dielectric (PID) such as polyimide. In some embodiments, the redistribution insulating layer 351 may include an inorganic insulating material. For example, the redistribution insulating layer 351 may include at least one of silicon oxide and silicon nitride.

[0066] The conductive redistribution pattern 353 may include a plurality of conductive layers at different levels in the redistribution insulating layer 351 to form a multilayer structure, and conductive vias extending in the vertical direction (Z direction) within the redistribution insulating layer 351 to connect the plurality of conductive layers. For example, the conductive redistribution pattern 353 may include at least one metal of W, Al, and Cu. The conductive redistribution pattern 353 may include a pad to which a plurality of third chip connection bumps 421 are attached, and a pad to which a plurality of fourth chip connection bumps 423 are attached. In addition, the conductive redistribution pattern 353 may include a second conductive connection structure configured to transmit electrical signals between the second integrated circuit device 200 and the third integrated circuit device 400.

[0067] The lower conductive pad 345 may be disposed on the lower surface of the base layer 341. The lower conductive pad 345 may be connected to the substrate on-pad 513 of the package substrate 510 via the second chip connection bump 413. The lower conductive pad 345 may include at least one metal of W, Al, and Cu.

[0068] The plurality of through electrodes 343 may be configured to be electrically connected between the conductive redistribution pattern 353 of the redistribution structure 350 and the lower conductive pad 345. Each through electrode 343 may extend from the upper surface of the base layer 341 to the lower surface of the base layer 341, and penetrate the base layer 341 in the vertical direction (Z direction). The upper end of each through electrode 343 may be connected to the conductive redistribution pattern 353 of the redistribution structure 350, and the lower end of each through electrode 343 may be connected to the lower conductive pad 345 corresponding thereto.

[0069] For example, each penetration electrode 343 may include a columnar conductive plug penetrating the base layer 341, and a cylindrical conductive barrier layer surrounding the sidewall of the conductive plug. A via insulating layer may be provided between the base layer 341 and each penetration electrode 343. The via insulating layer may include an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination thereof. At least one of the plurality of penetration electrodes 343 may constitute a first conductive connection structure electrically connected between the package substrate 510 and the second integrated circuit device 200 together with the conductive redistribution pattern 353. In addition, at least one penetration electrode 343 among the plurality of penetration electrodes 343 may electrically connect the third integrated circuit device 400 to the package substrate 510 together with the conductive redistribution pattern 353.

[0070] In some embodiments, the first integrated circuit device 100 may include a PIC device connected to at least one optical fiber OF, and the second integrated circuit device 200 may include an EIC device. In some embodiments, the second integrated circuit device 200 may include a PIC device connected to at least one optical fiber OF, and the first integrated circuit device 100 may include an EIC device.

[0071] Figure 7 is a cross-sectional view of a semiconductor package 10B according to some embodiments. Figure 7 The semiconductor package 10B shown in FIG. Figure 6 The differences of the semiconductor package 10A are described.

[0072] refer to Figure 7In the semiconductor package 10B, the second integrated circuit device 200 and the third integrated circuit device 400 may be mounted on a connection substrate 300C and may be electrically connected to each other via the connection substrate 300C. The connection substrate 300C includes an insulating base layer 361 and a conductive distribution pattern 363 disposed in the insulating base layer 361. In some embodiments, the connection substrate 300C may include passive devices such as capacitors. In the present disclosure, the connection substrate 300C may be referred to as a redistribution interposer.

[0073] The insulating base layer 361 may include an organic-based base layer. The insulating base layer 361 may include a plurality of insulating layers stacked vertically. The insulating base layer 361 may include a PID such as polyimide.

[0074] The conductive distribution pattern 363 may include a plurality of conductive layers at different levels in the insulating base layer 361 to form a multilayer structure, and conductive vias extending in a vertical direction (Z direction) to connect the plurality of conductive layers to each other in the insulating base layer 361. For example, the conductive distribution pattern 363 may include at least one metal of W, Al, and Cu.

[0075] The conductive distribution pattern 363 may include a first conductive connection structure electrically connected between the σth integrated circuit device 200 and the packaging substrate 510, a second conductive connection structure electrically connected between the second integrated circuit device 200 and the third integrated circuit device 400, and a third conductive connection structure electrically connected between the third integrated circuit device 400 and the packaging substrate 510, a pad to which a plurality of third chip connection bumps 421 are attached, a pad to which a plurality of fourth chip connection bumps 423 are attached, and a pad to which a plurality of second chip connection bumps 413 are attached.

[0076] Figure 8 is a cross-sectional view of a semiconductor package 10C according to some embodiments. Figure 8 The semiconductor package 10C shown here focuses on the reference Figure 6 The differences of the semiconductor package 10A are described.

[0077] refer to Figure 8 In the semiconductor package 10C, the second integrated circuit device 200 and the third integrated circuit device 400 may be mounted on a connection substrate 300D and may be electrically connected to each other via the connection substrate 300D. The connection substrate 300D includes an insulating base layer 371, a conductive distribution pattern 373 disposed in the insulating base layer 371, and a bridge chip 380 disposed in the insulating base layer 371. In some embodiments, the connection substrate 300D may include passive devices such as capacitors.

[0078] The insulating base layer 371 may include an organic insulating material and / or an inorganic insulating material. The conductive distribution pattern 373 may include a plurality of conductive layers at different levels in the insulating base layer 371 to form a multilayer structure, and may include conductive vias extending in the vertical direction (Z direction) in the insulating base layer 371 to connect the plurality of conductive layers to each other. For example, the conductive distribution pattern 373 may include at least one metal of W, Al, and Cu. The conductive distribution pattern 373 may include a first conductive connection structure electrically connected between the second integrated circuit device 200 and the package substrate 510, a third conductive connection structure electrically connected between the third integrated circuit device 400 and the package substrate 510, a pad to which a plurality of fourth chip connection bumps 423 are attached, and a pad to which a plurality of second chip connection bumps 413 are attached.

[0079] The bridge chip 380 may be accommodated in the recess of the insulating base layer 371. The bridge chip 380 includes a bridge distribution pattern 381 configured to electrically connect between the second integrated circuit device 200 and the third integrated circuit device 400. In the present disclosure, the bridge distribution pattern 381 of the bridge chip 380 may be referred to as a second conductive connection structure.

[0080] Fig. 9 is a cross-sectional view of a semiconductor package 10D according to some embodiments. Fig. 9 The semiconductor package 10D shown here focuses on the reference Figure 1 Differences in the semiconductor package 10 are described.

[0081] refer to Fig. 9 , in the semiconductor package 10D, the first integrated circuit device 100 may include an EIC device, and the second integrated circuit device 200 may include a PIC device. The optical fiber OF may be connected to the second integrated circuit device 200. The second integrated circuit device 200 may be configured to transmit and receive various signals from and to an external device via the optical fiber OF, and may be configured to transmit and receive signals from and to a package substrate 510 via a connection substrate 300. The first integrated circuit device 100 may be bonded to the second integrated circuit device 200 by using copper-to-copper direct bonding or hybrid bonding, and may be configured to convert an optical signal transmitted by the second integrated circuit device 200 into an electrical signal.

[0082] Fig.10 is a cross-sectional view of a semiconductor package 10E according to some embodiments. Fig.10 The semiconductor package 10E shown here focuses on the reference Fig. 9 The differences of the semiconductor package 10D are described.

[0083] refer to Fig.10In the semiconductor package 10E, the first integrated circuit device 100B may include an EIC device, and the second integrated circuit device 200 may include a PIC device. The first integrated circuit device 100B includes a plurality of through electrodes 183. Each through electrode 183 may have a columnar shape extending in a vertical direction (Z direction) in the first integrated circuit device 100B. Each through electrode 183 may vertically penetrate at least one first semiconductor substrate (see Figure 4 131 in the figure). Each through electrode 183 can be electrically connected between a corresponding lower bump pad 181 among the plurality of lower bump pads 181 and a corresponding first connection pad 110 among the plurality of first connection pads 110. The second integrated circuit device 200 can be electrically connected to the package substrate 510 and / or the first integrated circuit device 100B via the plurality of through electrodes 183. In addition, the first separate device provided in the first integrated circuit device 100B can be electrically connected to the package substrate 510 via the plurality of through electrodes 183.

[0084] The first integrated circuit device 100B and the second integrated circuit device 200 may be bonded to each other by using hybrid bonding. Figure 4 Similar to the description given, each first connection pad 110 can be directly connected to the second connection pad 210. Figure 4 Similar to the description given, the first integrated circuit device 100B may include a first pad insulation layer surrounding a plurality of first connecting pads 110, the second integrated circuit device 200 may include a second pad insulation layer surrounding a plurality of second connecting pads 210, and the first pad insulation layer of the first integrated circuit device 100B may be directly connected to the second pad insulation layer of the second integrated circuit device 200.

[0085] like Fig.10 As shown, the horizontal width of the first integrated circuit device 100B may be the same as the horizontal width of the second integrated circuit device 200. In some embodiments, the horizontal width of the first integrated circuit device 100B may be greater than the horizontal width of the second integrated circuit device 200, and a portion of the first integrated circuit device 100B may not be covered by the second integrated circuit device 200. In some embodiments, the horizontal width of the first integrated circuit device 100B may be less than the horizontal width of the second integrated circuit device 200, and a portion of the second integrated circuit device 200 may not vertically overlap with the first integrated circuit device 100B.

[0086] FIG. 11A to FIG. 11E is a diagram for explaining a method of manufacturing a semiconductor package 10 according to some embodiments. FIG. 11A to FIG. 11E To describe manufacturing Figure 1A method of semiconductor packaging 10 is shown.

[0087] Fig.11A is a plan view of a first structure S1 including a plurality of first integrated circuit devices 100, and Fig. 11B is a plan view of a second structure S2 including a plurality of second integrated circuit devices 200 .

[0088] refer to Fig.11A and Fig. 11B The method of manufacturing the semiconductor package 10 may include: preparing a first structure S1 and a second structure S2 respectively.

[0089] refer to Fig.11A , the first structure S1 may surround the plurality of first integrated circuit devices 100, the plurality of through electrodes 320, and the mold layer MD. The mold layer MD may surround the plurality of first integrated circuit devices 100 and the plurality of through electrodes 320. In the first structure S1, each of the plurality of first integrated circuit devices 100 may be aligned with any one of the first reference lines RL1 parallel to the second horizontal direction (e.g., the Y direction). For example, one edge of each first integrated circuit device 100 may be aligned with any one of the first reference lines RL1.

[0090] Forming the first structure S1 may include: arranging a plurality of first integrated circuit devices 100 on a carrier substrate, forming a plurality of through electrodes 320 on the carrier substrate, and forming a mold layer MD on the carrier substrate surrounding the plurality of first integrated circuit devices 100 and the plurality of through electrodes 320. The mold layer MD may be formed of, for example, EMC. The first structure S1 may be referred to as a reconstructed structure.

[0091] The first structure S1 includes a plurality of first unit regions UT1 arranged in a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction). The plurality of first unit regions UT1 may be separated from each other by using a subsequent cutting process. Each first unit region UT1 includes one first integrated circuit device 100, a plurality of through electrodes 320, and an insulating base layer 310 surrounding one first integrated circuit device 100 and the plurality of through electrodes 320. The insulating base layer 310 includes a portion of the mold layer MD.

[0092] refer to Fig. 11B, the second structure S2 includes a plurality of second integrated circuit devices 200 formed on a substrate such as a wafer. In the second structure S2, each of the plurality of second integrated circuit devices 200 may be aligned with any one of the second reference lines RL2 parallel to the second horizontal direction (e.g., the Y direction). For example, one edge of each second integrated circuit device 200 may be aligned with any one of the second reference lines RL2. Each second reference line RL2 may be spaced apart from one of the first reference lines RL1 defined relative to the first structure S1 by a constant offset distance DD in the first horizontal direction (e.g., the X direction).

[0093] The second structure S2 includes a plurality of second unit regions UT2 arranged in a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction). The plurality of second unit regions UT2 may be separated from each other by using a subsequent cutting process. Each second unit region UT2 includes a second integrated circuit device 200 and a dummy structure 291. Each second unit region UT2 and each first unit region UT1 may have the same size in a horizontal direction (e.g., X direction and / or Y direction).

[0094] Combination Fig.11A and Fig. 11B For reference Fig. 11C The method of manufacturing the semiconductor package 10 may include forming a bonding structure BS1, wherein, among the first structure S1 and the second structure S2, a lower structure LS corresponding to the first unit region UT1 of the first structure S1 is bonded to an upper structure US corresponding to the second unit region UT2 of the second structure S2.

[0095] In some embodiments, forming the bonding structure BS1 may include bonding the first structure S1 and the second structure S2 to each other, and separating the third structure into a plurality of bonding structures BS1 by performing a cutting process on the third structure generated by bonding the first structure S1 and the second structure S2 to each other. For example, bonding the first structure S1 and the second structure S2 to each other may be performed by using a hybrid bonding process. When the first structure S1 and the second structure S2 are bonded to each other, the plurality of first unit regions UT1 of the first structure S1 may be aligned and bonded with the plurality of second unit regions UT2 of the second structure S2, respectively.

[0096] and Fig. 11C Reference together Fig.11D , the dummy structure 291 may be removed from the upper structure US so that a portion of the upper surface of the first integrated circuit device 100 is exposed.

[0097] refer to Fig.11E, the bonding structure BS1 may be mounted on the package substrate 510 . The bonding structure BS1 may be mounted on the package substrate 510 via a plurality of first chip connection bumps 411 and a plurality of second chip connection bumps 413 .

[0098] refer to Figure 1 and Fig.11E , after mounting the bonding structure BS1 on the package substrate 510 , the optical fiber OF may be connected to the first integrated circuit device 100 .

[0099] In some embodiments, forming Fig.11D The illustrated bonding structure BS1 may include: Fig. 11B The second structure S2 in the embodiment of the present invention is subjected to a cutting process to form a plurality of second integrated circuit devices 200 from the second structure S2, and the second integrated circuit devices 200 are bonded to Fig.11A and performing a cutting process on a fourth structure generated by bonding the plurality of second integrated circuit devices 200 to the first structure S1 to separate the fourth structure into a plurality of bonded structures BS1.

[0100] In some embodiments, forming Fig.11D The illustrated bonding structure BS1 may include: Fig.11A The first structure S1 is cut into a plurality of first unit regions UT1 by performing a cutting process. Fig. 11B A cutting process is performed on the second structure S2 to form a plurality of second integrated circuit devices 200 from the second structure S2 , and a bonding structure BS1 is formed by bonding each first unit region UT1 to each second integrated circuit device 200 .

[0101] Fig. 12A and Fig. 12B is a cross-sectional view showing a method of manufacturing a semiconductor package 10A according to some embodiments. Fig. 12A and Fig. 12B To describe manufacturing Figure 6 A method of semiconductor package 10A is shown.

[0102] refer to Fig. 12A , a first integrated circuit device 100 and a second integrated circuit device 200 may be prepared and may be bonded to each other. The first integrated circuit device 100 and the second integrated circuit device 200 may be bonded to each other by using, for example, a copper-to-copper direct bonding or a hybrid bonding process.

[0103] refer to Fig. 12B , the connection substrate 300 may be mounted on the packaging substrate 510, and the Fig. 12AThe bonding structure BS2 in the package substrate 510 is mounted on the package substrate 510 and the connection substrate 300. The first integrated circuit device 100 of the bonding structure BS2 can be attached to the package substrate 510 via a plurality of first chip connection bumps 411, and the second integrated circuit device 200 of the bonding structure BS2 can be attached to the connection substrate 300 via a plurality of third chip connection bumps 421. Next, the third integrated circuit device 400 can be mounted on the connection substrate 300. The third integrated circuit device 400 can be attached to the connection substrate 300 via a plurality of third chip connection bumps 421.

[0104] refer to Figure 6 , after the third integrated circuit device 400 is mounted on the connection substrate 300 , the optical fiber OF may be connected to the first integrated circuit device 100 .

[0105] According to some embodiments of the present disclosure, since the semiconductor package includes a CPO package in which a PIC device and an EIC device are packaged together, high-speed data signal processing may be achieved with low power.

[0106] According to some embodiments of the present disclosure, since other integrated circuit devices such as ASIC devices can be packaged together with PIC devices and EIC devices by using a connection substrate, a semiconductor package in which various types of devices are integrated in a relatively small footprint can be provided.

[0107] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of possible protection. In a single embodiment, specific features described in the context of independent embodiments in the present disclosure can also be implemented in combination. On the contrary, different features described in a single implementation context can also be implemented in multiple embodiments separately, or in appropriate sub-combinations. In addition, although features can be described above as working in certain combinations and even initially claimed as such, one or more features from the combination can be deleted from the combination in some cases, and the combination can be directed to sub-combinations or variations of sub-combinations.

[0108] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, include: Package substrate; A connection substrate, mounted on the packaging substrate, the connection substrate comprising a first conductive connection structure; A first integrated circuit device mounted on the packaging substrate; as well as a second integrated circuit device disposed on the connection substrate and the first integrated circuit device, the second integrated circuit device comprising a first portion overlapping the first integrated circuit device and a second portion overlapping the connection substrate, wherein one of the first integrated circuit device and the second integrated circuit device comprises a photonic integrated circuit device with an optical fiber attached, and the other of the first integrated circuit device and the second integrated circuit device comprises an electronic integrated circuit device, and Wherein, the second integrated circuit device is electrically connected to the packaging substrate via the first conductive connection structure of the connection substrate.

2. The semiconductor package according to claim 1, in, The first integrated circuit device includes a plurality of first connection pads disposed on an upper surface of the first integrated circuit device, The second integrated circuit device includes a plurality of second connection pads disposed on a lower surface of the second integrated circuit device, and The plurality of first connection pads are directly and respectively bonded to the plurality of second connection pads.

3. The semiconductor package according to claim 2, in, The first integrated circuit device includes a first pad insulating layer surrounding the plurality of first connection pads, wherein the second integrated circuit device comprises a second pad insulating layer surrounding the plurality of second connection pads, and Wherein, the first pad insulating layer is directly bonded to the second pad insulating layer.

4. The semiconductor package according to claim 3, in, Each of the first pad insulating layer and the second pad insulating layer includes silicon oxide.

5. The semiconductor package according to claim 1, in, The connection substrate comprises an insulating base layer, wherein the insulating base layer comprises a molding-based base layer, and wherein the first conductive connection structure of the connection substrate penetrates the molding-based base layer and includes a plurality of through electrodes, and The plurality of through-electrodes include a plurality of molded through-electrodes, and the plurality of molded through-electrodes are configured to electrically connect the second integrated circuit device and the packaging substrate.

6. The semiconductor package according to claim 5, in, The first integrated circuit device includes a plurality of first connection pads disposed on an upper surface of the first integrated circuit device, and a first pad insulating layer surrounding the plurality of first connection pads. The second integrated circuit device includes a plurality of second connection pads disposed on a lower surface of the second integrated circuit device, and a second pad insulating layer surrounding the plurality of second connection pads. wherein the connection substrate comprises a plurality of third connection pads respectively connected to the plurality of molded through electrodes, and a third pad insulating layer surrounding the plurality of third connection pads, wherein some of the plurality of second connection pads are directly and respectively bonded to the plurality of first connection pads, wherein other second connection pads among the plurality of second connection pads are directly and respectively bonded to the plurality of third connection pads, and Wherein, each of the first pad insulating layer and the third pad insulating layer is directly bonded to the second pad insulating layer.

7. The semiconductor package according to claim 5, in, The molding-based substrate layer is directly connected to a side surface of the first integrated circuit device.

8. The semiconductor package according to claim 7, in, The molding-based substrate layer surrounds the first integrated circuit device. 9 . The semiconductor package according to claim 1 , further comprising a third integrated circuit device mounted on the connection substrate and electrically connected to the second integrated circuit device via the connection substrate.

10. The semiconductor package according to claim 9, in, The connection substrate includes a silicon-based base layer, and The first conductive connection structure of the connection substrate includes a plurality of through electrodes penetrating the silicon-based base layer.

11. The semiconductor package according to claim 9, in, The connection substrate includes an insulating base layer, and The first conductive connection structure of the connection substrate includes a plurality of redistribution patterns in the insulating base layer.

12. The semiconductor package according to claim 9, in, The connection substrate further includes an insulating base layer and a bridge chip in the insulating base layer, and The bridge chip includes a bridge distribution pattern that electrically connects the second integrated circuit device to the third integrated circuit device.

13. The semiconductor package according to claim 1, in, The first integrated circuit device comprises a photonic integrated circuit device and the second integrated circuit device comprises an electronic integrated circuit device.

14. The semiconductor package according to claim 1, in, The first integrated circuit device comprises an electronic integrated circuit device and the second integrated circuit device comprises a photonic integrated circuit device.

15. A semiconductor package, include: Package substrate; a connection substrate mounted on the packaging substrate, the connection substrate comprising a mold-based base layer and a plurality of mold-through electrodes penetrating the mold-based base layer; a photonic integrated circuit device mounted on the packaging substrate and configured to transmit and receive optical signals via an optical fiber; and an electronic integrated circuit device mounted on the photonic integrated circuit device and the connection substrate and configured to process signals provided by the photonic integrated circuit device, wherein the electronic integrated circuit device is directly connected to the photonic integrated circuit device and the connection substrate, and The electronic integrated circuit device is electrically connected to the packaging substrate via the plurality of molded through-electrodes.

16. The semiconductor package according to claim 15, in, The photonic integrated circuit device comprises a plurality of first connection pads disposed on an upper surface of the photonic integrated circuit device, and a first pad insulating layer surrounding the plurality of first connection pads. The electronic integrated circuit device comprises a plurality of second connection pads arranged on the lower surface of the electronic integrated circuit device, and a second pad insulation layer surrounding the plurality of second connection pads. wherein the connection substrate comprises a plurality of third connection pads connected to the plurality of molded through electrodes, and a third pad insulating layer surrounding the plurality of third connection pads, wherein one or more of the plurality of second connection pads are directly and respectively bonded to the plurality of first connection pads, wherein other second connection pads among the plurality of second connection pads that are different from the one or more second connection pads are directly and respectively bonded to the plurality of third connection pads, and Wherein, each of the first pad insulating layer and the third pad insulating layer is directly bonded to the second pad insulating layer.

17. The semiconductor package according to claim 16, in, Each of the first pad insulating layer, the second pad insulating layer, and the third pad insulating layer includes silicon oxide.

18. A semiconductor package, include: Package substrate; A connection substrate mounted on the packaging substrate; A first integrated circuit device mounted on the packaging substrate; a second integrated circuit device disposed on the connection substrate and the first integrated circuit device, wherein the second integrated circuit device is directly connected to the first integrated circuit device and is electrically connected to the packaging substrate via the connection substrate; and a third integrated circuit device mounted on the connection substrate and electrically connected to the second integrated circuit device via the connection substrate, wherein one of the first integrated circuit device and the second integrated circuit device comprises a photonic integrated circuit device with an optical fiber attached, and the other of the first integrated circuit device and the second integrated circuit device comprises an electronic integrated circuit device.

19. The semiconductor package according to claim 18, in, The connection substrate further comprises: Silicon-based substrate layer; A plurality of through electrodes penetrating the silicon-based substrate layer; and a redistribution structure disposed on the silicon-based substrate layer, the redistribution structure comprising a plurality of redistribution patterns electrically connected to the plurality of through electrodes, wherein the second integrated circuit device is electrically connected to the package substrate via at least one of the plurality of through electrodes, and Wherein, the second integrated circuit device is electrically connected to the third integrated circuit device via the plurality of redistribution patterns.

20. The semiconductor package according to claim 18, in, The connection substrate comprises: an insulating base layer; and a plurality of redistribution patterns disposed in the insulating base layer, and Wherein, the second integrated circuit device is electrically connected to each of the package substrate and the third integrated circuit device via the redistribution pattern.

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