Display panel

Abstract

The display panel comprises a plurality of data lines, a plurality of scanning lines, a plurality of pixel structures, a wire, a first conductive pattern and a first spacer. Each pixel structure is electrically connected to a corresponding data line and a corresponding scanning line. The pixel structures are arranged into a plurality of pixel columns and a plurality of pixel rows. The pixel rows include an (n-1) th pixel row, an nth pixel row and an (n + 1) th pixel row which are arranged in order in the first direction. The pixel structure of the nth pixel row and the pixel structure of the (n + 1) th pixel row are electrically connected to the same data line. The pixel columns include an mth pixel column and an (m + 1) th pixel column arranged in order in the second direction. The pixel structure of the nth pixel row and the mth pixel column and the pixel structure of the (n + 1) th pixel row and the (m + 1) th pixel column are electrically connected to two adjacent scanning lines respectively. In a top view of the display panel, the conductive line is located between the (n-1) th pixel row and the nth pixel row. The first conductive pattern is directly connected to the conductive line. In a top view of the display panel, the first spacer overlaps the first conductive pattern.

Description

Technical Field

[0001] The present invention relates to an optoelectronic device, and in particular to a display panel. Background Art

[0002] In recent years, people's demand for high-resolution display panels has gradually increased. However, when the resolution of the display panel increases, it means that the pixel size in the display panel must be reduced, thus testing whether the process capability meets more stringent design rules. In order to reduce the load of the process machine and increase the feasibility of the process, designing an appropriate pixel layout has become an important issue.

[0003] Generally speaking, a display panel includes a pixel array substrate, a color filter substrate, a display medium, and a spacer for maintaining a cell gap, wherein the spacer must stand on a platform of the pixel array substrate. However, when the resolution increases, the platform will occupy too much layout area, affecting the aperture ratio of the display panel. Summary of the invention

[0004] The invention provides a display panel with a high aperture ratio.

[0005] A display panel according to an embodiment of the present invention comprises a first substrate, a plurality of data lines, a plurality of scan lines, a plurality of pixel structures, a conductive line, a first conductive pattern, a second substrate, a first spacer and a display medium. A plurality of data lines are arranged on the first substrate and arranged in a first direction. A plurality of scan lines are arranged on the first substrate and arranged in a second direction. The first direction and the second direction are interlaced. A plurality of pixel structures are arranged on the first substrate. Each pixel structure is electrically connected to a corresponding data line and a corresponding scan line. A plurality of pixel structures are arranged into a plurality of pixel columns and a plurality of pixel rows. A plurality of pixel structures of each pixel column are arranged in the first direction. A plurality of pixel structures of each pixel row are arranged in the second direction. A plurality of pixel rows include the n-1th pixel row, the nth pixel row and the n+1th pixel row arranged in sequence in the first direction. A plurality of pixel structures of the nth pixel row and a plurality of pixel structures of the n+1th pixel row are electrically connected to the same data line. A plurality of pixel columns include the mth pixel column and the m+1th pixel column arranged in sequence in the second direction. A pixel structure of the nth pixel row and the mth pixel column and a pixel structure of the n+1th pixel row and the m+1th pixel column are respectively electrically connected to two adjacent scan lines of the plurality of scan lines. n and m are positive integers greater than or equal to 1. The wire is disposed on the first substrate. In a top view of the display panel, the wire is located between the n-1th pixel row and the nth pixel row. The first conductive pattern is directly connected to the wire. In a top view of the display panel, the first conductive pattern is located between the mth pixel column and the m+1th pixel column. The second substrate is disposed opposite to the first substrate. The first spacer is disposed on the second substrate. In a top view of the display panel, the first spacer overlaps with the first conductive pattern. The display medium is disposed between the first substrate and the second substrate.

[0006] A display panel according to another embodiment of the present invention includes a first substrate, a plurality of data lines, a plurality of scan lines, a plurality of adapter lines, a plurality of pixel structures, a first conductive pattern, a second substrate, a first spacer and a display medium. A plurality of data lines are arranged on the first substrate and arranged in a first direction. A plurality of scan lines are arranged on the first substrate and arranged in a second direction. The first direction and the second direction are interlaced. A plurality of adapter lines are arranged on the first substrate and arranged in the first direction. A plurality of adapter lines are electrically connected to a plurality of scan lines, respectively. A plurality of pixel structures are arranged on the first substrate. Each pixel structure is electrically connected to a corresponding data line and a corresponding scan line. A plurality of pixel structures are arranged in a plurality of pixel columns and a plurality of pixel rows. A plurality of pixel structures of each pixel column are arranged in the first direction. A plurality of pixel structures of each pixel row are arranged in the second direction. A plurality of pixel rows include an n-1th pixel row, an nth pixel row and an n+1th pixel row arranged in sequence in the first direction. A plurality of pixel structures of the nth pixel row and a plurality of pixel structures of the n+1th pixel row are electrically connected to the same data line. The plurality of pixel columns include an m-th pixel column and an m+1-th pixel column arranged in sequence in a second direction. A pixel structure of the n-th pixel row and the m-th pixel column and a pixel structure of the n+1-th pixel row and the m+1-th pixel column are electrically connected to two adjacent scan lines of the plurality of scan lines, respectively. n and m are positive integers greater than or equal to 1. The plurality of adapters include a first adapter. In a top view of the display panel, the first adapter is located between the n-1-th pixel row and the n-th pixel row, and the first conductive pattern is directly connected to the first adapter. The second substrate is disposed opposite to the first substrate. The first spacer is disposed on the second substrate. In a top view of the display panel, the first spacer overlaps with the first conductive pattern. The display medium is disposed between the first substrate and the second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a top and perspective schematic diagram of a display panel according to an embodiment of the present invention.

[0008] Figure 2 FIG. 1 is a partial enlarged schematic diagram of a display panel according to an embodiment of the present invention.

[0009] Figure 3 FIG. 4 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention.

[0010] Figure 4 FIG. 1 is a top and perspective schematic diagram of a display panel according to another embodiment of the present invention.

[0011] Figure 5 FIG. 1 is a partial enlarged schematic diagram of a display panel according to another embodiment of the present invention.

[0012] Figure 6FIG. 1 is a partial enlarged schematic diagram of a display panel according to another embodiment of the present invention.

[0013] Figure 7 FIG. 4 is a cross-sectional schematic diagram of a display panel according to another embodiment of the present invention.

[0014] Description of reference numerals:

[0015] 10, 10A: Display panel

[0016] 100, 100A: Pixel array substrate

[0017] 110: First substrate

[0018] 120: Pixel electrode

[0019] 130: Common electrode

[0020] 140, 170, 196: Insulation layer

[0021] 150, 150A: first conductive pattern

[0022] 150a, 160a, 180a, 192a, 194a: Edge

[0023] 160, 160A: second conductive pattern

[0024] 172, 196a: Contact window

[0025] 180: Bridge pattern

[0026] 192: First auxiliary pattern

[0027] 194: Second auxiliary pattern

[0028] 200: Opposite substrate

[0029] 210: Second substrate

[0030] 300: Display medium

[0031] A1, A2, A3: Local

[0032] C, Cn-3, Cn-2, Cn-1, Cn, Cn+1: pixel row

[0033] DL: Data Line

[0034] DML: Wire

[0035] d1: first direction

[0036] d2: second direction

[0037] d3: third direction

[0038] g: gap

[0039] H1: First height

[0040] H2: Second height

[0041] P: Touch sensor pad

[0042] PS1: The first interstitial

[0043] PS2: Second gap

[0044] R, Rm, Rm+1: pixel columns

[0045] SL: Scan Line

[0046] SPX: Pixel Structure

[0047] s:slit

[0048] T: Thin Film Transistor

[0049] Ta: The first end

[0050] Tb: Second end

[0051] Tc: Control terminal

[0052] Td: Semiconductor pattern

[0053] TGP, TGP1, TGP2: Adapter cable

[0054] TL: Touch signal line

[0055] I-I', II-II', III-III', IV-IV', V-V', VI-VI: line segments DETAILED DESCRIPTION

[0056] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0057] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may refer to the presence of other elements between two elements.

[0058] As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately", or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical property, etching property or other property, and can apply to all properties without a single standard deviation.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0060] Figure 1 FIG. 1 is a top and perspective schematic diagram of a display panel according to an embodiment of the present invention. Figure 2 FIG. 1 is a partial enlarged schematic diagram of a display panel according to an embodiment of the present invention. Figure 2 correspond Figure 1 Local A1. Figure 3 FIG. 4 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention. Figure 3 correspond Figure 2 The line segments I-I', II-II' and III-III'.

[0061] Please refer to Figure 1 , Figure 2 and Figure 3 The display panel 10 includes a pixel array substrate 100. The pixel array substrate 100 includes a first substrate 110. For example, in some embodiments, the material of the first substrate 110 may be glass, quartz, organic polymer, or opaque / reflective material (e.g., wafer, ceramic, or other applicable materials), or other applicable materials, but the present invention is not limited thereto.

[0062] The pixel array substrate 100 further includes a plurality of data lines DL and a plurality of scan lines SL, which are disposed on the first substrate 110. The plurality of data lines DL are arranged in a first direction d1. The plurality of scan lines SL are arranged in a second direction d2. The first direction d1 and the second direction d2 are interlaced. In some embodiments, the first direction d1 and the second direction d2 may be perpendicular, but the present invention is not limited thereto. For example, in some embodiments, the scan lines SL may belong to a first metal layer, the data lines DL may belong to a second metal layer, and the first metal layer is located between the second metal layer and the first substrate 110, but the present invention is not limited thereto.

[0063] The pixel array substrate 100 further includes a plurality of pixel structures SPX disposed on the first substrate 110. Each pixel structure SPX is electrically connected to a corresponding data line DL and a corresponding scan line SL. In some embodiments, each pixel structure SPX includes a thin film transistor T and a pixel electrode 120. The thin film transistor T has a first end Ta, a second end Tb, a control end Tc, and a semiconductor pattern Td. The first end Ta and the second end Tb are electrically connected to two regions of the semiconductor pattern Td, respectively. The first end Ta is electrically connected to a corresponding data line DL, the control end Tc is electrically connected to a corresponding scan line SL, and the second end Tb is electrically connected to the pixel electrode 120. For example, in some embodiments, the control end Tc of the thin film transistor T may belong to the first metal layer, and the first end Ta and the second end Tb of the thin film transistor T may belong to the second metal layer, but the present invention is not limited thereto.

[0064] In some embodiments, each pixel structure SPX further includes a common electrode 130, wherein the potential difference between the pixel electrode 120 and the common electrode 130 is used to drive the display medium 300. For example, in some embodiments, the pixel array substrate 100 further includes an insulating layer 140 disposed on the first substrate 110, the insulating layer 140 is disposed between the pixel electrode 120 and the common electrode 130, one of the pixel electrode 120 and the common electrode 130 has a plurality of slits s, and the other of the pixel electrode 120 and the common electrode 130 overlaps the plurality of slits s, but the present invention is not limited thereto. In some embodiments, the common electrode 130 may selectively belong to the first transparent conductive layer, the pixel electrode 120 may selectively belong to the second transparent conductive layer, the first transparent conductive layer is located between the second transparent conductive layer and the first substrate 110, but the present invention is not limited thereto.

[0065] The plurality of pixel structures SPX are arranged into a plurality of pixel columns R and a plurality of pixel rows C. The plurality of pixel structures SPX of each pixel column R are arranged in a first direction d1 , and the plurality of pixel structures SPX of each pixel row C are arranged in a second direction d2 .

[0066] The plurality of pixel rows C include an n-th pixel row Cn and an n+1-th pixel row Cn+1 arranged in sequence in the first direction d1, where n is a positive integer greater than or equal to 1. The plurality of pixel structures SPX of the n-th pixel row Cn and the plurality of pixel structures SPX of the n+1-th pixel row Cn+1 are electrically connected to the same data line DL. In some embodiments, the plurality of pixel rows C also include an n-2-th pixel row Cn-2 and an n-1-th pixel row Cn-1, the n-2-th pixel row Cn-2, the n-1-th pixel row Cn-1, the n-th pixel row Cn and the n+1-th pixel row Cn+1 are arranged in sequence in the first direction d1, and the plurality of pixel structures SPX of the n-2-th pixel row Cn-2 and the plurality of pixel structures SPX of the n-1-th pixel row Cn-1 are electrically connected to another data line DL.

[0067] The plurality of pixel columns R include an m-th pixel column Rm and an m+1-th pixel column Rm+1 sequentially arranged in the second direction d2, where m is a positive integer greater than or equal to 1. A pixel structure SPX of the n-th pixel row Cn and the m-th pixel column Rm and a pixel structure SPX of the n+1-th pixel row Cn+1 and the m+1-th pixel column Rm+1 are electrically connected to two adjacent scan lines SL of the plurality of scan lines SL, respectively.

[0068] The pixel array substrate 100 further includes a conductive line DML disposed on the first substrate 110. In the top view of the display panel 10, the conductive line DML is located between the n-1th pixel row Cn-1 and the nth pixel row Cn. In some embodiments, the conductive line DML may selectively belong to the second metal layer, but the present invention is not limited thereto.

[0069] In some embodiments, the plurality of common electrodes 130 of the plurality of pixel structures SPX may be connected to form a touch sensing pad P. In some embodiments, the pixel array substrate 100 may further include a touch signal line TL disposed on the first substrate 110 and electrically connected to the touch sensing pad P. In some embodiments, the plurality of pixel rows C further include an n-3 th pixel row Cn-3, the n-3 th pixel row Cn-3, the n-2 th pixel row Cn-2, the n-1 th pixel row Cn-1, the n th pixel row Cn, and the n+1 th pixel row Cn+1 are sequentially arranged in the first direction d1; in a top view of the display panel 10, the touch signal line TL may be disposed between the n-3 th pixel row Cn-3 and the n-2 th pixel row Cn-2. In some embodiments, the touch signal line TL may selectively belong to the second metal layer, but the present invention is not limited thereto.

[0070] In some embodiments, the display panel 10 further includes another touch signal line (not shown); in the top view of the display panel 10, the another touch signal line and the wire DML may be located between the n-1th pixel row Cn-1 and the nth pixel row Cn and disconnected from each other. That is, in some embodiments, the wire DML may selectively be a pseudo touch signal line, but the present invention is not limited thereto. In some embodiments, the wire DML may be floating, but the present invention is not limited thereto.

[0071] The pixel array substrate 100 also includes a first conductive pattern 150. In the top view of the display panel 10, the first conductive pattern 150 is located between the mth pixel column Rm and the m+1th pixel column Rm+1. The first conductive pattern 150 is directly connected to the wire DML. That is, the first conductive pattern 150 and the wire DML belong to the same film layer and are electrically connected to each other. In some embodiments, at least one of the first end Ta, the second end Tb and the control end Tc of the thin film transistor T and the first conductive pattern 150 may belong to the same film layer. For example, in some embodiments, the first conductive pattern 150 may belong to the same film layer as the first end Ta and the second end Tb of the thin film transistor T, but the present invention is not limited thereto. In some embodiments, the first conductive pattern 150 may be selectively floating, but the present invention is not limited thereto.

[0072] In some embodiments, the pixel array substrate 100 further includes a second conductive pattern 160, which is directly connected to the touch signal line TL. In some embodiments, in a top view of the display panel 10, the second conductive pattern 160 may be located between two adjacent scan lines SL. In some embodiments, at least one of the first end Ta, the second end Tb, and the control end Tc of the thin film transistor T and the second conductive pattern 160 may belong to the same film layer. For example, in some embodiments, the second conductive pattern 160 may belong to the same film layer as the first end Ta and the second end Tb of the thin film transistor T, but the present invention is not limited thereto.

[0073] The display panel 10 further includes an opposing substrate 200. The opposing substrate 200 includes a second substrate 210 and a first spacer PS1. The second substrate 210 is disposed opposite to the first substrate 110. The first spacer PS1 is disposed on the second substrate 210. In some embodiments, the first spacer PS1 of the opposing substrate 200 may abut against the pixel array substrate 100. In other words, the first spacer PS1 may be a main spacer of the display panel 10. In a top view of the display panel 10, the first spacer PS1 overlaps with the first conductive pattern 150. In some embodiments, in a top view of the display panel 10, the first spacer PS1 is located within the first conductive pattern 150. In some embodiments, the second substrate 210 may selectively be a color filter substrate, but the present invention is not limited thereto.

[0074] In some embodiments, the counter substrate 200 may further include a second spacer PS2 disposed on the second substrate 210. The third direction d3 is perpendicular to the second substrate 210. The first spacer PS1 and the second spacer PS2 have a first height H1 and a second height H2 in the third direction d3, respectively, and the first height H1 is greater than the second height H2. When the display panel 10 is not pressed, the second spacer PS2 and the pixel array substrate 100 may maintain a gap g. In other words, the second spacer PS2 may be a sub-spacer of the display panel 10. In some embodiments, in a top view of the display panel 10, the second spacer PS2 overlaps with the second conductive pattern 160. In some embodiments, in a top view of the display panel 10, the second spacer PS2 is located within the second conductive pattern 160.

[0075] In some embodiments, the pixel array substrate 100 further includes an insulating layer 170, and the insulating layer 170 is disposed between the touch sensing pad P and the touch signal line TL, wherein the touch sensing pad P is electrically connected to the second conductive pattern 160 through a contact window 172 of the insulating layer 170. In some embodiments, the second spacer PS2 may selectively overlap with the contact window 172, but the present invention is not limited thereto.

[0076] In some embodiments, the pixel array substrate 100 further includes a bridge pattern 180 electrically connecting the touch sensing pad P and the second conductive pattern 160. In a top view of the display panel 10, at least a portion of an edge 180a of the bridge pattern 180 substantially overlaps with at least a portion of an edge 160a of the second conductive pattern 160. More specifically, in a top view of the display panel 10, at least a portion of an edge 180a of the bridge pattern 180 substantially overlaps with at least a portion of an edge 160a of the second conductive pattern 160. In some embodiments, the bridge pattern 180 may selectively belong to the same second transparent conductive layer as the pixel electrode 120, but the present invention is not limited thereto.

[0077] The display panel 10 further includes a display medium 300 disposed between the first substrate 110 of the pixel array substrate 100 and the second substrate 210 of the opposite substrate 200. In some embodiments, the display medium 300 may be a liquid crystal layer, but the present invention is not limited thereto.

[0078] It is worth noting that the first conductive pattern 150 is used as a platform for carrying the first spacer PS1. Directly connecting the first conductive pattern 150 to the conductive line DML can save layout space and increase the aperture ratio. In some embodiments, the second conductive pattern 160 is used as a platform overlapping with the second spacer PS2. Directly connecting the second conductive pattern 160 to the touch signal line TL can further save layout space and increase the aperture ratio.

[0079] It must be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0080] Figure 4 FIG. 4 is a top and perspective schematic diagram of a display panel according to another embodiment of the present invention. Figure 5 FIG. 1 is a partial enlarged schematic diagram of a display panel according to another embodiment of the present invention. Figure 5 correspond Figure 4 Part A2. Figure 6 FIG. 1 is a partial enlarged schematic diagram of a display panel according to another embodiment of the present invention. Figure 6 correspond Figure 4 Part A3. Figure 7 FIG. 4 is a cross-sectional schematic diagram of a display panel according to another embodiment of the present invention. Figure 7 correspond Figure 5 The line segments IV-IV' and V-V' and Figure 6 The line segment VI-VI'.

[0081] Please refer to Figures 4 to 7 , the display panel 10A includes a pixel array substrate 100A. The pixel array substrate 100A includes a first substrate 110. The pixel array substrate 100A also includes a plurality of data lines DL and a plurality of scan lines SL, which are disposed on the first substrate 110. The plurality of data lines DL are arranged in a first direction d1. The plurality of scan lines SL are arranged in a second direction d2. The first direction d1 is interlaced with the second direction d2. The pixel array substrate 100A also includes a plurality of transfer lines TGP, which are disposed on the first substrate 110 and arranged in the first direction d1. The plurality of transfer lines TGP are electrically connected to the plurality of scan lines SL, respectively. In some embodiments, the transfer lines TGP may selectively belong to the second metal layer, but the present invention is not limited thereto.

[0082] The pixel array substrate 100A further includes a plurality of pixel structures SPX disposed on the first substrate 110. Each pixel structure SPX is electrically connected to a corresponding data line DL and a corresponding scan line SL. The plurality of pixel structures SPX are arranged into a plurality of pixel columns R and a plurality of pixel rows C. The plurality of pixel structures SPX of each pixel column R are arranged in a first direction d1. The plurality of pixel structures SPX of each pixel row C are arranged in a second direction d2. The plurality of pixel rows C include an nth pixel row Cn and an n+1th pixel row Cn+1 arranged in sequence in the first direction d1, wherein n is a positive integer greater than or equal to 1. The plurality of pixel structures SPX of the nth pixel row Cn and the plurality of pixel structures SPX of the n+1th pixel row Cn+1 are electrically connected to the same data line DL. The plurality of pixel columns R include an mth pixel column Rm and an m+1th pixel column Rm+1 arranged in sequence in the second direction d2, wherein m is a positive integer greater than or equal to 1. A pixel structure SPX of the nth pixel row Cn and the mth pixel column Rm and a pixel structure SPX of the n+1th pixel row Cn+1 and the m+1th pixel column Rm+1 are electrically connected to two adjacent scan lines SL of the plurality of scan lines SL, respectively.

[0083] The pixel array substrate 100A further includes a first conductive pattern 150A. The plurality of transfer lines TGP include a first transfer line TGP1. In a top view of the display panel 10A, the first transfer line TGP1 is located between the n-1th pixel row Cn-1 and the nth pixel row Cn, and the first conductive pattern 150A is directly connected to the first transfer line TGP1.

[0084] The display panel 10 further includes an opposing substrate 200. The opposing substrate 200 includes a second substrate 210 and a first spacer PS1. The second substrate 210 is disposed opposite to the first substrate 110. The first spacer PS1 is disposed on the second substrate 210. The display panel 10A further includes a display medium 300, which is disposed between the first substrate 110 of the pixel array substrate 100 and the second substrate 210 of the opposing substrate 200. In the top view of the display panel 10A, the first spacer PS1 overlaps with the first conductive pattern 150A. In some embodiments, in the top view of the display panel 10A, the first spacer PS1 is located within the first conductive pattern 150A. In some embodiments, at least one of the first end Ta, the second end Tb, and the control end Tc of the thin film transistor T and the first conductive pattern 150A may belong to the same film layer. For example, in some embodiments, the first conductive pattern 150A may belong to the same film layer as the first end Ta and the second end Tb of the thin film transistor T, but the present invention is not limited thereto. In some embodiments, the first conductive pattern 150A may selectively belong to the second metal layer, but the invention is not limited thereto.

[0085] In some embodiments, the pixel array substrate 100A may further selectively include a first auxiliary pattern 192, which is directly connected to a corresponding scan line SL. For example, in some embodiments, the first auxiliary pattern 192 may belong to the same film layer as the control terminal Tc of the thin film transistor T, but the present invention is not limited thereto. In some embodiments, in a top view of the display panel 10A, at least a portion of an edge 150a of the first conductive pattern 150A substantially overlaps with at least a portion of an edge 192a of the first auxiliary pattern 192. Further, in some embodiments, in a top view of the display panel 10A, at least a portion of an edge 150a of the first conductive pattern 150A substantially overlaps with at least a portion of an edge 192a of the first auxiliary pattern 192. In some embodiments, the first auxiliary pattern 192 may selectively belong to the first metal layer, but the present invention is not limited thereto.

[0086] In some embodiments, the plurality of transfer lines TGP further include a second transfer line TGP2. In some embodiments, in a top view of the display panel 10A, the second transfer line TGP2 is, for example, located between the n-3th pixel row Cn-3 and the n-2th pixel row Cn-2, but the present invention is not limited thereto. In some embodiments, the pixel array substrate 100A further includes a second conductive pattern 160A, which is directly connected to the second transfer line TGP2. In some embodiments, the counter substrate 200 may further include a second spacer PS2 disposed on the second substrate 210. The third direction d3 is perpendicular to the second substrate 210. The first spacer PS1 and the second spacer PS2 have a first height H1 and a second height H2, respectively, in the third direction d3, and the first height H1 is greater than the second height H2. In some embodiments, in a top view of the display panel 10A, the second spacer PS2 overlaps with the second conductive pattern 160A. In some embodiments, in a top view of the display panel 10A, the second spacer PS2 is located within the second conductive pattern 160A. In some embodiments, the second conductive pattern 160A may selectively belong to the second metal layer, but the invention is not limited thereto.

[0087] In some embodiments, the pixel array substrate 100A further includes an insulating layer 196 disposed between the transfer line TGP and the scan line SL, wherein the second transfer line TGP2 is electrically connected to a corresponding scan line SL through a contact window 196a of the insulating layer 196. In some embodiments, in a top view of the display panel 10A, the second spacer PS2 may selectively overlap with the contact window 196a. In some embodiments, the insulating layer 196 may be a gate insulating layer between the control terminal Tc of the thin film transistor T and the semiconductor pattern Td, but the present invention is not limited thereto.

[0088] In some embodiments, the pixel array substrate 100A may further selectively include a second auxiliary pattern 194, which is directly connected to the corresponding scan line SL. In the top view of the display panel 10A, at least a portion of the edge 160a of the second conductive pattern 160A substantially overlaps with at least a portion of the edge 194a of the second auxiliary pattern 194. More specifically, in the top view of the display panel 10A, at least a portion of the edge 160a of the second conductive pattern 160A substantially overlaps with at least a portion of the edge 194a of the second auxiliary pattern 194.

[0089] Similarly, the first conductive pattern 150A is used as a platform for carrying the first spacer PS1. The first conductive pattern 150A is directly connected to the patch cord TGP, which can save layout space and increase the aperture ratio. In some embodiments, the second conductive pattern 160A is used as a platform overlapping the second spacer PS2. The second conductive pattern 160A is directly connected to the patch cord TGP, which can further save layout space and increase the aperture ratio.

Claims

1. A display panel, comprising: a first substrate; A plurality of data lines are disposed on the first substrate and arranged in a first direction; A plurality of scanning lines are disposed on the first substrate and arranged in a second direction, wherein the first direction is staggered with the second direction; A plurality of pixel structures are disposed on the first substrate, wherein each of the pixel structures is electrically connected to a corresponding data line and a corresponding scan line, the pixel structures are arranged into a plurality of pixel columns and a plurality of pixel rows, the plurality of pixel structures of each pixel column are arranged in the first direction, the plurality of pixel structures of each pixel row are arranged in the second direction, the pixel rows include an n-1th pixel row, an nth pixel row and an n+1th pixel row sequentially arranged in the first direction, the pixel structures of the nth pixel row and the pixel structures of the n+1th pixel row are electrically connected to the same data line, the pixel columns include an mth pixel row and an m+1th pixel column sequentially arranged in the second direction, a pixel structure of the nth pixel row and the mth pixel column and a pixel structure of the n+1th pixel row and the m+1th pixel column are electrically connected to two adjacent scan lines among the scan lines, respectively, and n and m are positive integers greater than or equal to 1; A conductive line is disposed on the first substrate, wherein in a top view of the display panel, the conductive line is located between the n-1th pixel row and the nth pixel row; a first conductive pattern directly connected to the conductive line, wherein in a top view of the display panel, the first conductive pattern is located between the m-th pixel row and the (m+1)-th pixel row; a second substrate, disposed opposite to the first substrate; a first spacer disposed on the second substrate, wherein in a top view of the display panel, the first spacer overlaps with the first conductive pattern; and A display medium is disposed between the first substrate and the second substrate.

2. A display panel as described in claim 1, wherein each pixel structure includes a thin film transistor and a pixel electrode, the thin film transistor has a first end, a second end and a control end, the first end is electrically connected to a corresponding data line, the control end is electrically connected to a corresponding scan line, the second end is electrically connected to the pixel electrode, and at least one of the first end, the second end and the control end belongs to the same film layer as the first conductive pattern. 3 . The display panel as claimed in claim 1 , wherein the conductive line and the first conductive pattern are floating.

4. The display panel as claimed in claim 1, wherein each of the pixel structures comprises a thin film transistor, a pixel electrode and a common electrode, the thin film transistor has a first end, a second end and a control end, the first end is electrically connected to a corresponding data line, the control end is electrically connected to a corresponding scan line, the second end is electrically connected to the pixel electrode, a plurality of common electrodes of the pixel structures are connected to form a touch sensing pad, and the display panel further comprises: A touch signal line is disposed on the first substrate and electrically connected to the touch sensing pad; a second conductive pattern directly connected to the touch signal line; as well as A second spacer is disposed on the second substrate, wherein a third direction is perpendicular to the second substrate, the first spacer and the second spacer have a first height and a second height respectively in the third direction, and the first height is greater than the second height; In a top view of the display panel, the second spacer overlaps with the second conductive pattern.

5. The display panel according to claim 4, further comprising: an insulating layer disposed between the touch sensing pad and the touch signal line, wherein the touch sensing pad is electrically connected to the second conductive pattern through a contact window of the insulating layer; In a top view of the display panel, the second spacer overlaps with the contact window.

6. The display panel according to claim 4, further comprising: a bridge pattern electrically connecting the touch sensing pad and the second conductive pattern; In a top view of the display panel, at least a portion of an edge of the bridge pattern substantially overlaps with at least a portion of an edge of the second conductive pattern.

7. A display panel, comprising: a first substrate; A plurality of data lines are disposed on the first substrate and arranged in a first direction; A plurality of scanning lines are disposed on the first substrate and arranged in a second direction, wherein the first direction is staggered with the second direction; A plurality of transfer lines are disposed on the first substrate and arranged in the first direction, wherein the transfer lines are electrically connected to the scan lines respectively; A plurality of pixel structures are disposed on the first substrate, wherein each of the pixel structures is electrically connected to a corresponding data line and a corresponding scan line, the pixel structures are arranged into a plurality of pixel columns and a plurality of pixel rows, the plurality of pixel structures of each pixel column are arranged in the first direction, the plurality of pixel structures of each pixel row are arranged in the second direction, the pixel rows include an n-1th pixel row, an nth pixel row and an n+1th pixel row sequentially arranged in the first direction, the pixel structures of the nth pixel row and the pixel structures of the n+1th pixel row are electrically connected to the same data line, the pixel columns include an mth pixel row and an m+1th pixel row sequentially arranged in the second direction, a pixel structure of the nth pixel row and the mth pixel row and a pixel structure of the n+1th pixel row and the m+1th pixel row are electrically connected to two adjacent scan lines among the scan lines, respectively, and n and m are positive integers greater than or equal to 1; a first conductive pattern, wherein the plurality of transfer lines include a first transfer line, in a top view of the display panel, the first transfer line is located between the n-1th pixel row and the nth pixel row, and the first conductive pattern is directly connected to the first transfer line; a second substrate, disposed opposite to the first substrate; a first spacer disposed on the second substrate, wherein in a top view of the display panel, the first spacer overlaps with the first conductive pattern; and A display medium is disposed between the first substrate and the second substrate.

8. A display panel as described in claim 7, wherein each pixel structure includes a thin film transistor and a pixel electrode, the thin film transistor has a first end, a second end and a control end, the first end is electrically connected to a corresponding data line, the control end is electrically connected to a corresponding scan line, the second end is electrically connected to the pixel electrode, and at least one of the first end, the second end and the control end belongs to the same film layer as the first conductive pattern.

9. The display panel according to claim 7, further comprising: a first auxiliary pattern directly connected to a corresponding scan line; In a top view of the display panel, at least a portion of an edge of the first conductive pattern substantially overlaps with at least a portion of an edge of the first auxiliary pattern.

10. The display panel as claimed in claim 7, wherein the plurality of adapters further comprise a second adapter, and the display panel further comprises: A second conductive pattern directly connected to the second transfer line; as well as A second spacer is disposed on the second substrate, wherein a third direction is perpendicular to the second substrate, the first spacer and the second spacer have a first height and a second height respectively in the third direction, and the first height is greater than the second height; In a top view of the display panel, the second spacer overlaps with the second conductive pattern.

11. The display panel according to claim 10, further comprising: an insulating layer disposed between the transfer lines and the scan lines, wherein the second transfer line is electrically connected to a corresponding scan line through a contact window of the insulating layer; In a top view of the display panel, the second spacer overlaps with the contact window.

12. The display panel according to claim 10, further comprising: a second auxiliary pattern directly connected to another corresponding scan line; In a top view of the display panel, at least a portion of an edge of the second conductive pattern substantially overlaps with at least a portion of an edge of the second auxiliary pattern.

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