PLC instruction library building method and device, equipment and storage medium

Abstract

The invention discloses a PLC (Programmable Logic Controller) instruction library building method, device and equipment and a storage medium, which are applied to the technical field of engineering, and if a to-be-verified PLC instruction does not have the same function as any logic unit in target hardware description language programming software and is not realized through a basic logic unit combination in the target hardware description language programming software, the PLC instruction library is established. Determining the PLC instruction to be verified as a target PLC instruction; constructing a PLC instruction library based on the target PLC instructions, and determining hardware description language codes of the target PLC instructions in the PLC instruction library; and packaging the PLC instruction library to the target hardware description language programming software based on the hardware description language code of each target PLC instruction. According to the method, the PLC instruction library is constructed based on the hardware description language, and the instruction is packaged in the FPGA hardware language programming software, so that the corresponding hardware description language does not need to be manually rewritten, and the deployment efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of engineering technology, and in particular to a method, device, equipment and computer-readable storage medium for building a PLC instruction library. Background Art

[0002] FPGA (Field Programmable Gate Array) is a popular control chip in the current market. More and more manufacturers want to use FPGA to develop digital systems independently to achieve technological autonomy. One of the development directions is to use FPGA to replace PLC (Programmable Logic Controller) controllers with its excellent scalability. In the existing technology, if you want to deploy PLC instructions in FPGA, you need to write the corresponding hardware description language according to the PLC instructions, and then deploy the hardware description language in FPGA. However, each deployment requires rewriting the hardware description language, which is inefficient. Summary of the invention

[0003] The purpose of the present invention is to provide a method, device, equipment and computer-readable storage medium for building a PLC instruction library, which are applied to the field of industrial technology. The method constructs a PLC instruction library based on a hardware description language code, and encapsulates the instructions in an FPGA hardware language programming software. By calling the PLC instruction library, the deployment of PLC instructions on the FPGA can be realized without manually rewriting the corresponding hardware description language code, thereby improving the deployment efficiency.

[0004] In order to solve the above technical problems, the present invention provides a method for building a PLC instruction library, comprising:

[0005] Determining a first PLC instruction to be verified from the PLC instructions;

[0006] If the first PLC instruction to be verified is not the same as the function of any logic unit in the target hardware description language programming software, determining the first PLC instruction to be verified as the second PLC instruction to be verified;

[0007] If the function of the second PLC instruction to be verified is not implemented by the combination of basic logic units in the target hardware description language programming software, determining the second PLC instruction to be verified as the target PLC instruction;

[0008] Building a PLC instruction library based on the target PLC instruction, and determining a hardware description language code of each of the target PLC instructions in the PLC instruction library;

[0009] The PLC instruction library is encapsulated into the target hardware description language programming software based on the hardware description language code of each target PLC instruction.

[0010] Optionally, determining a first PLC instruction to be verified from the PLC instructions includes:

[0011] Obtain the usage statistics of each PLC instruction in the PLC programming software and determine the threshold number of times;

[0012] The PLC instruction whose usage statistics times are greater than the threshold times is determined as the first PLC instruction to be verified.

[0013] Optionally, determining a first PLC instruction to be verified from the PLC instructions includes:

[0014] Instruction selection information is obtained, and the first instruction to be verified is determined from each of the PLC instructions of the PLC programming software based on the instruction selection information.

[0015] Optionally, encapsulating the PLC instruction library into the target hardware description language programming software based on the hardware description language code of each target PLC instruction includes:

[0016] The PLC instruction library is encapsulated into Quartus programming software based on the Verilog hardware description language code of each target PLC instruction.

[0017] Optionally, encapsulating the PLC instruction library into the target hardware description language programming software based on the hardware description language code of each target PLC instruction includes:

[0018] Performing simulation verification in the target hardware description language programming software based on the hardware description language code of each target PLC instruction;

[0019] The target PLC instructions in the PLC instruction library that have passed the simulation verification are encapsulated into the target hardware description language programming software.

[0020] Optionally, the target PLC instructions include: scanning signal rising edge instructions, scanning detection falling edge instructions, generating pulse instructions with customizable width, output on delay instructions, output off delay instructions, custom adjustable counter instructions, multipliers with one decimal place, and dividers with one decimal place.

[0021] Optionally, the basic logic unit includes: an addition logic unit, a subtraction logic unit, a comparison logic unit, an AND gate logic unit, an OR gate logic unit, a NOT gate logic unit and an XOR gate logic unit.

[0022] In order to solve the above technical problems, the present invention provides a PLC instruction library building device, comprising:

[0023] A first module is used to determine a first PLC instruction to be verified from the PLC instructions;

[0024] A second module is used to determine the first PLC instruction to be verified as a second PLC instruction to be verified if the first PLC instruction to be verified is not the same as the function of any logic unit in the target hardware description language programming software;

[0025] A third module is used to determine the second PLC instruction to be verified as a target PLC instruction if the function of the second PLC instruction to be verified is not implemented by the combination of basic logic units in the target hardware description language programming software;

[0026] A fourth module is used to construct a PLC instruction library based on the target PLC instruction, and determine the hardware description language code of each target PLC instruction in the PLC instruction library;

[0027] The fifth module is used to encapsulate the PLC instruction library into the target hardware description language programming software based on the hardware description language code of each target PLC instruction.

[0028] In order to solve the above technical problems, the present invention provides an electronic device, comprising:

[0029] Memory, for storing computer programs;

[0030] A processor is used to implement the above-mentioned PLC instruction library building method when executing the computer program.

[0031] In order to solve the above technical problems, the present invention provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the above-mentioned PLC instruction library building method is implemented.

[0032] It can be seen that the method of the present invention determines the first PLC instruction to be verified from the PLC instruction; if the first PLC instruction to be verified is not the same as the function of any logic unit in the target hardware description language programming software, the first PLC instruction to be verified is determined as the second PLC instruction to be verified; if the second PLC instruction to be verified is not composed of the basic logic units in the target hardware description language programming software, the second PLC instruction to be verified is determined as the target PLC instruction; a PLC instruction library is constructed based on the target PLC instruction, and the hardware description language code of each target PLC instruction in the PLC instruction library is determined; based on the hardware description language code of each target PLC instruction, the PLC instruction library is encapsulated into the target hardware description language programming software. A PLC instruction library is constructed based on the hardware description language code, and the instruction is encapsulated in the FPGA hardware language programming software. By calling the PLC instruction library, the deployment of the PLC instruction on the FPGA can be realized, without manually rewriting the corresponding hardware description language code, thereby improving the deployment efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0034] Figure 1 A flow chart of a method for building a PLC instruction library provided by an embodiment of the present invention;

[0035] Figure 2 A structural block diagram of a PLC instruction library building device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] FPGA is a popular control chip in the current market. More and more manufacturers want to use FPGA to develop digital systems independently to achieve technical autonomy. Among them, the excellent scalability of FPGA is used to replace PLC controllers, which is one of the development directions. In the process of deploying PLC instructions in FPGA, the prior art needs to convert PLC instructions into hardware description language codes by manual coding. The PLC instructions need to be re-encoded during each deployment process. The repetitive work leads to low efficiency, and manual coding is prone to errors. The purpose of the present invention is to focus on the hardware description language itself, use the hardware description language to establish a basic instruction library of PLC, and provide basic instructions for developers to develop digital systems. The instructions in the instruction library can include common categories such as bit logic operations, timer operations, counter operations, and mathematical functions. Developers can directly use these instructions to develop digital systems, improve the development efficiency of digital systems, especially in the field of digital systems. Improve the development efficiency of FPGA controllers to replace PLC controllers and reduce the error rate.

[0038] The following combination Figure 1 , Figure 1 A flowchart of a method for building a PLC instruction library provided by an embodiment of the present invention, the method may include:

[0039] S101: Determine a first PLC instruction to be verified from PLC instructions.

[0040] The PLC instructions in this embodiment may be instructions in the PLC programming software. In this embodiment, the first PLC instruction to be verified may be determined from the PLC instructions. The first PLC instruction to be verified is the PLC instruction that needs to be converted into code, i.e., packaged and stored. Since there are many PLC instructions in the actual engineering field, if all PLC instructions are converted into code and packaged and stored, a huge workload will be generated. Therefore, in this embodiment, the first PLC instruction to be verified may be determined from the PLC instructions.

[0041] This embodiment does not limit the specific method of determining the first PLC instruction to be verified from the PLC instructions. Generally, a commonly used PLC instruction in the PLC instructions can be determined as the first PLC instruction to be verified.

[0042] Specifically, this embodiment can obtain the usage statistics of each PLC instruction in the PLC programming software, determine the threshold number of times, and determine the PLC instruction whose usage statistics are greater than the threshold number of times as the first PLC instruction to be verified. This embodiment does not limit the specific type of PLC programming software, which can be selected from actual engineering applications. This embodiment also does not limit the specific value of the threshold number of times, which can be set based on actual applications.

[0043] In addition to determining the commonly used PLC instructions as the first PLC instructions to be verified, this embodiment can also determine the first PLC instruction to be verified from the PLC instructions in a selected manner, that is, this embodiment can obtain instruction selection information, and determine the first instruction to be verified from each PLC instruction of the PLC programming software based on the instruction selection information.

[0044] In this embodiment, the instruction selection information includes information of the selected first instruction to be verified. Based on the instruction selection information, the first instruction to be verified can be determined from various PLC instructions of the PLC programming software. This embodiment does not limit the method of issuing the instruction selection information, and it can be set based on actual engineering applications.

[0045] In this embodiment, the first PLC instruction to be verified can be determined by any combination of the above two methods, that is, obtaining the usage statistics of each PLC instruction in the PLC programming software and determining the threshold number; determining the PLC instruction whose usage statistics are greater than the threshold number as the first PLC instruction to be verified, and / or obtaining instruction selection information, and determining the first instruction to be verified from the PLC instructions in the PLC programming software based on the instruction selection information.

[0046] S102: If the first PLC instruction to be verified is not the same as the function of any logic unit in the target hardware description language programming software, the first PLC instruction to be verified is determined as the second PLC instruction to be verified.

[0047] In this embodiment, after determining the first PLC instruction to be verified, it is necessary to verify the first PLC instruction to be verified to determine that the PLC instruction library finally constructed meets the requirements.

[0048] This embodiment does not limit the specific method of instruction verification. In order to avoid conflicts between the packaged PLC instructions and the existing logic unit functions in the target hardware description language programming software, which leads to waste of workload, this embodiment can verify the first PLC instruction to be verified to determine whether its function conflicts with the existing logic unit functions in the target hardware description language programming software. If the first PLC instruction to be verified is not the same as the function of any logic unit in the target hardware description language programming software, the first PLC instruction to be verified is determined as the second PLC instruction to be verified.

[0049] The target hardware description language programming software in this embodiment is a hardware description language programming software that deploys a PLC instruction library. This embodiment does not limit the specific type of the target hardware description language programming software, which can be selected based on actual applications. The existing logic units in the target hardware description language programming software are pre-deployed or built-in units.

[0050] This embodiment can also add a reminder function for verification failure. If the first PLC instruction to be verified has the same function as any logic unit in the target hardware description language programming software, this embodiment can generate instruction conflict information to remind the user that the first PLC instruction to be verified has not passed the verification.

[0051] S103: If the function of the second PLC instruction to be verified is not implemented by the combination of basic logic units in the target hardware description language programming software, the second PLC instruction to be verified is determined as the target PLC instruction.

[0052] After obtaining the second PLC to be verified, this embodiment can further verify the second PLC instruction to be verified. Generally, the hardware description language programming software contains multiple basic logic units. If the function of the PLC instruction can be completely realized by the basic logic combination, then the PLC instruction does not need to be encapsulated into the target hardware description language programming software.

[0053] That is, if the function of the second PLC instruction to be verified is not implemented by the combination of basic logic units in the target hardware description language programming software, the second PLC instruction to be verified is determined as the target PLC instruction. The target PLC instruction in this embodiment is the instruction that is finally packaged and stored.

[0054] This embodiment can also add a reminder function for verification failure. If the second PLC instruction to be verified can be composed entirely of basic logic units in the target hardware description language programming software, this embodiment can generate instruction conflict information to remind the user that the first PLC instruction to be verified has not passed the verification.

[0055] This embodiment limits the specific types of basic logic units, which can be set based on actual applications. Generally, the types of basic logic units can be addition logic units, subtraction logic units, comparison logic units, AND gate logic units, OR gate logic units, NOT gate logic units and XOR gate logic units.

[0056] S104: constructing a PLC instruction library based on the target PLC instruction, and determining the hardware description language code of each target PLC instruction in the PLC instruction library.

[0057] This embodiment can build a PLC instruction library based on the target PLC instruction, and determine the hardware description language code of each target PLC instruction in the PLC instruction library. This embodiment does not limit the specific type of the hardware description language code, and needs to correspond to the target hardware description language programming software, that is, the hardware description language used to describe each target PLC instruction in this embodiment needs to be a language recognizable by the target hardware description language programming software. Generally, the hardware description language can be Verilog language, and the target hardware description language programming software can be Quartus programming software, which can be selected based on actual applications.

[0058] This embodiment does not limit the specific method of determining the hardware description language code of each target PLC instruction in the PLC instruction library. Generally, the hardware description language code of each target PLC instruction written manually can be obtained.

[0059] S105: Encapsulating the PLC instruction library into the target hardware description language programming software based on the hardware description language code of each target PLC instruction.

[0060] This embodiment can encapsulate the PLC instruction library into the target hardware description language programming software based on the hardware description language code of each target PLC instruction to complete the construction of the PLC instruction library, such as encapsulating the PLC instruction library into Quartus programming software (a circuit design software) based on the Verilog (a hardware description language) logic code of each target PLC instruction.

[0061] After the PLC instruction library is built, the function of the PLC instruction can be implemented by calling the logic unit corresponding to the PLC instruction in the PLC instruction library. In this embodiment, each logic unit can be used by dragging and dropping in a graphical manner, or can be called through a port. The specific settings can be based on the actual application.

[0062] In actual applications, after user screening, this embodiment can use the scan signal rising edge instruction (P_TRIG), scan detection falling edge instruction (N_TRIG), generate pulse instruction with customizable width (TP), output on delay instruction (TON_PT), output off delay instruction (TOF), custom adjustable counter instruction (CTU), one-digit decimal multiplier (MUL) and one-digit decimal divider (DIV) in PLC instructions as target PLC instructions, and encapsulate the above instructions into the target hardware description language programming software.

[0063] Specifically, the function of the scan signal rising edge instruction is to detect the rising edge of the input. When the input signal changes from 0 to 1, it is necessary not only to capture this time period, but also to express it in the output. That is, when the input changes from 0 to 1, the output also changes from 0 to 1.

[0064] The scan detection falling edge instruction detects the falling edge of the input. When the input signal changes from 0 to 1, it is necessary not only to capture this time period, but also to show it in the output. That is, when the input changes from 1 to 0, the output also changes from 0 to 1.

[0065] The function of generating a pulse instruction with customizable width is that whenever the input generates a rising edge, the output generates a pulse of a preset width (usually 320ns) in real time, and the pulse width is adjustable, that is, when the input signal changes from 0 to 1, the output also changes from 0 to 1, and the output changes from 1 to 0 after a delay.

[0066] The function of the output on-delay instruction is that when the output is maintained for a preset time, the output follows the input, that is, when the input signal changes from 0 to 1 and remains for a preset time, the output will change from 0 to 1, and when the input changes from 1 to 0, the output is 0.

[0067] The function of the output shutdown delay instruction is that when the input is a rising edge, the output is a rising edge. When the input becomes a falling edge, the output will fall after a period of time. The time is custom adjusted. That is, when the input signal changes from 0 to 1, the output changes from 0 to 1. When the input changes from 1 to 0 and remains for a period of time, the output is 0.

[0068] The function of the custom-adjusted counter instruction is to record the number of rising edges of the input. The total count can be compared with a custom quantity, that is, when the input port CU generates a rising edge, the output port CV increases by 1. The output port CV records the total number of port pulses of the input port CU. The output port CV is reset by the input port R. When the output port CV is greater than the digital value of the input port PV, the output port Q changes from 0 to 1, otherwise it is 0, where CU, CV, R, PV and Q are counter ports.

[0069] Since the multiplication and division symbols of some domestically produced FPGAs are not convenient to use, the present embodiment adds multiplication and division instructions to the PLC instruction library.

[0070] The function of the multiplier with one decimal place is to multiply two inputs with one decimal place and keep one decimal place and store it in the output.

[0071] The function of the one-digit decimal divider is to divide two inputs with one-digit decimals and retain one decimal place and store it in the output.

[0072] In this embodiment, the clock cycle can be set based on the actual application, generally 20ns, the reset key is valid when the high level is maintained, and the low level reset is invalid. Since when the input generates a rising edge, it needs to be recorded when the clock rising edge arrives, so there is a delay in the output. This embodiment does not limit the delay time threshold, and the general delay time is not greater than 20ns.

[0073] Based on the above embodiments, the method of the present invention constructs a PLC instruction library based on the hardware description language code, and encapsulates the instructions in the FPGA hardware language programming software. By calling the PLC instruction library, the deployment of PLC instructions on the FPGA can be realized without manually rewriting the corresponding hardware description language code, thereby improving the deployment efficiency.

[0074] The following combination Figure 2 , Figure 2 A structural frame of a PLC instruction library building device provided by an embodiment of the present invention, the device may include:

[0075] The first module 100 is used to determine a first PLC instruction to be verified from the PLC instructions;

[0076] The second module 200 is used to determine the first PLC instruction to be verified as a second PLC instruction to be verified if the first PLC instruction to be verified is not the same as the function of any logic unit in the target hardware description language programming software;

[0077] The third module 300 is used to determine the second PLC instruction to be verified as a target PLC instruction if the function of the second PLC instruction to be verified is not implemented by the combination of basic logic units in the target hardware description language programming software;

[0078] The fourth module 400 is used to construct a PLC instruction library based on the target PLC instruction, and determine the logic code of each target PLC instruction in the PLC instruction library;

[0079] The fifth module 500 is used to encapsulate the PLC instruction library into the target hardware description language programming software based on the logic code of each target PLC instruction.

[0080] Based on the above embodiments, the method of the present invention constructs a PLC instruction library based on the hardware description language code, and encapsulates the instructions in the FPGA hardware language programming software. By calling the PLC instruction library, the deployment of PLC instructions on the FPGA can be realized without manually rewriting the corresponding hardware description language code, thereby improving the deployment efficiency.

[0081] Based on the above embodiment, the first module 100 may include:

[0082] The first unit is used to obtain the usage statistics of each PLC instruction in the PLC programming software and determine the threshold number of times;

[0083] The second unit is used to determine the PLC instruction whose usage statistics times are greater than the threshold times as the first PLC instruction to be verified.

[0084] Based on the above embodiments, the first module 100 may include:

[0085] The third unit is used to obtain instruction selection information, and determine the first instruction to be verified from each of the PLC instructions of the PLC programming software based on the instruction selection information.

[0086] Based on the above embodiments, the fifth module 500 may include:

[0087] The fourth unit is used to encapsulate the PLC instruction library into Quartus programming software based on the Verilog logic code of each target PLC instruction.

[0088] Based on the above embodiments, the fifth module 500 may include:

[0089] A fifth unit is used for performing simulation verification in the target hardware description language programming software based on the logic code of each target PLC instruction;

[0090] The sixth unit is used to encapsulate the target PLC instructions in the PLC instruction library that have passed the simulation verification into the target hardware description language programming software.

[0091] Based on the above embodiments, the target PLC instructions may include: scanning signal rising edge instructions, scanning detection falling edge instructions, generating pulse instructions with customizable width, output on delay instructions, output off delay instructions, custom adjustable counter instructions, multipliers with one decimal place, and dividers with one decimal place.

[0092] Based on the above embodiments, the basic logic unit may include: an addition logic unit, a subtraction logic unit, a comparison logic unit, an AND gate logic unit, an OR gate logic unit, a NOT gate logic unit and an XOR gate logic unit.

[0093] Based on the above embodiments, the present invention further provides an electronic device, which may include a memory and a processor, wherein the memory stores a computer program, and when the processor calls the computer program in the memory, the steps provided in the above embodiments may be implemented. Of course, the device may also include various necessary network interfaces, power supplies, and other components.

[0094] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by an execution terminal or a processor, the method provided in the embodiment of the present invention can be implemented; the storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0095] In this article, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. A method for building a PLC instruction library, It is characterized in that include: Determining a first PLC instruction to be verified from the PLC instructions; If the first PLC instruction to be verified is not the same as the function of any logic unit in the target hardware description language programming software, determining the first PLC instruction to be verified as the second PLC instruction to be verified; If the function of the second PLC instruction to be verified is not implemented by the combination of basic logic units in the target hardware description language programming software, determining the second PLC instruction to be verified as the target PLC instruction; Building a PLC instruction library based on the target PLC instruction, and determining a hardware description language code of each of the target PLC instructions in the PLC instruction library; The PLC instruction library is encapsulated into the target hardware description language programming software based on the hardware description language code of each target PLC instruction.

2. According to the PLC instruction library construction method of claim 1, It is characterized in that The step of determining a first PLC instruction to be verified from the PLC instructions comprises: Obtain the usage statistics of each PLC instruction in the PLC programming software and determine the threshold number of times; The PLC instruction whose usage statistics times are greater than the threshold times is determined as the first PLC instruction to be verified.

3. According to the PLC instruction library construction method of claim 1, It is characterized in that The step of determining a first PLC instruction to be verified from the PLC instructions comprises: Instruction selection information is obtained, and the first instruction to be verified is determined from each of the PLC instructions of the PLC programming software based on the instruction selection information.

4. According to the PLC instruction library construction method of claim 1, It is characterized in that The hardware description language code based on each of the target PLC instructions encapsulates the PLC instruction library into the target hardware description language programming software, including: The PLC instruction library is encapsulated into Quartus programming software based on the Verilog hardware description language code of each target PLC instruction.

5. According to the PLC instruction library construction method of claim 1, It is characterized in that The hardware description language code based on each of the target PLC instructions encapsulates the PLC instruction library into the target hardware description language programming software, including: Performing simulation verification in the target hardware description language programming software based on the hardware description language code of each target PLC instruction; The target PLC instructions in the PLC instruction library that have passed the simulation verification are encapsulated into the target hardware description language programming software.

6. According to the method for building a PLC instruction library as claimed in claim 1, It is characterized in that The target PLC instructions include: scanning signal rising edge instructions, scanning detection falling edge instructions, generating pulse instructions with customizable width, output on delay instructions, output off delay instructions, custom adjustable counter instructions, multipliers with one decimal place, and dividers with one decimal place.

7. According to the method for building a PLC instruction library as claimed in claim 1, It is characterized in that The basic logic unit includes: an addition logic unit, a subtraction logic unit, a comparison logic unit, an AND gate logic unit, an OR gate logic unit, a NOT gate logic unit and an XOR gate logic unit.

8. A PLC instruction library building device, It is characterized in that include: A first module is used to determine a first PLC instruction to be verified from the PLC instructions; A second module is used to determine the first PLC instruction to be verified as a second PLC instruction to be verified if the first PLC instruction to be verified is not the same as the function of any logic unit in the target hardware description language programming software; A third module is used to determine the second PLC instruction to be verified as a target PLC instruction if the function of the second PLC instruction to be verified is not implemented by the combination of basic logic units in the target hardware description language programming software; A fourth module is used to construct a PLC instruction library based on the target PLC instruction, and determine the hardware description language code of each target PLC instruction in the PLC instruction library; The fifth module is used to encapsulate the PLC instruction library into the target hardware description language programming software based on the hardware description language code of each target PLC instruction.

9. An electronic device, It is characterized in that include: Memory, for storing computer programs; A processor, used to implement the PLC instruction library building method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the method for building a PLC instruction library as described in any one of claims 1 to 7 is implemented.

Images