Instruction acquisition method, central processing unit, equipment, medium and program product

Abstract

The invention discloses an instruction acquisition method, a central processing unit, equipment, a medium and a program product, and belongs to the field of processors, the method comprises the following steps: acquiring a main path predicted for each branch instruction; determining the confidence degree classification of the main path corresponding to each branch instruction based on the size between the historical error prediction number of the main path of the same branch instruction and the confidence degree threshold; a confidence coefficient classification proportion is determined, the confidence coefficient classification proportion is the proportion of the branch instruction corresponding to the first classification in the total instruction, and the first classification is the confidence coefficient classification with the historical error prediction number larger than a confidence coefficient threshold; and taking the confidence coefficient classification proportion as an expected proportion as a control target, and adjusting a confidence coefficient threshold. By dynamically adjusting the confidence coefficient threshold, the problem that the proportion of the first branch instruction in the total instruction is too large due to the fact that the fixed threshold is too small for different load programs can be avoided, and the first branch instruction is the branch instruction corresponding to the main path with the confidence coefficient classification being the first classification.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of processors, and in particular to an instruction acquisition method, a central processing unit, a device, a medium, and a program product. Background Art

[0002] In the design of the central processing unit (CPU), the branch predictor in the CPU is used to predict the subsequent execution path of the branch instruction, and the subsequent execution path of the branch instruction corresponds to the next instruction of the branch instruction. The instruction cache in the CPU is used to cache the next instruction of the branch instruction in advance, so that the CPU can quickly obtain it from the instruction cache when executing the next instruction.

[0003] In the related art, the concept of confidence classification is introduced. The confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path. The branch instruction corresponds to two candidate subsequent execution paths. The main path is the path predicted to be executed in the two subsequent execution paths, and the secondary path is a subsequent execution path different from the main path. The confidence classification includes a first classification and a second classification. The related art determines the confidence classification based on whether the value of the counter in the branch predictor is greater than a fixed threshold. In the first classification, the first cache method is used, and the first cache method is based on the address of the main path or the address of the secondary path. In the second classification, the second cache method is used, and the second cache method is based on the address of the main path. The instruction cache instruction.

[0004] However, the total instructions of a program include branch instructions and other instructions. When the total number of instructions is fixed, the related technology may face a load program including different numbers of branch instructions. Due to the large number of branch instructions and the small fixed threshold, the number of first branch instructions may account for too large a proportion of the total number of instructions. The first branch instruction is the branch instruction corresponding to the main path with the first confidence classification. In this case, there will be too many instructions cached and insufficient space for the instruction cache. Summary of the invention

[0005] The present application provides an instruction acquisition method, a central processing unit, a device, a medium and a program product, and the technical solution at least includes:

[0006] According to one aspect of an embodiment of the present application, there is provided an instruction acquisition method, the method comprising:

[0007] Obtain the main path predicted for each branch instruction. Each branch instruction corresponds to two candidate subsequent execution paths. The main path is the path predicted to be executed in the two subsequent execution paths.

[0008] Based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold, the confidence classification of the main path corresponding to each branch instruction is determined, and the confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path;

[0009] Determine a confidence classification ratio, where the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is a confidence classification whose number of historical mispredictions is greater than a confidence threshold;

[0010] The confidence classification ratio is taken as the expected ratio as the control target, and the confidence threshold is adjusted.

[0011] According to another aspect of an embodiment of the present application, a central processing unit is provided, the central processing unit comprising:

[0012] A branch predictor is used to obtain a main path predicted for each branch instruction. Each branch instruction corresponds to two candidate subsequent execution paths. The main path is the path predicted to be executed in the two subsequent execution paths.

[0013] A branch predictor, for determining a confidence classification of a main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and a confidence threshold, wherein the confidence classification is used to indicate a probability classification of the accuracy of the prediction of the main path;

[0014] A branch predictor, used to determine a confidence classification ratio, where the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, the first classification being a confidence classification for which the number of historical mispredictions is greater than a confidence threshold;

[0015] The branch predictor is used to adjust the confidence threshold by taking the confidence classification ratio as the expected ratio as a control target.

[0016] According to another aspect of an embodiment of the present application, a computer device is provided, comprising: a processor and a memory, wherein at least one program is stored in the memory; the processor is used to execute at least one program in the memory to implement the above-mentioned instruction acquisition method.

[0017] According to another aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a processor to implement the above-mentioned instruction acquisition method.

[0018] According to another aspect of an embodiment of the present application, a computer program product or a computer program is provided, which includes computer instructions, the computer instructions are stored in a computer-readable storage medium, a processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the instruction acquisition method as described above.

[0019] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0020] The method obtains a main path predicted for each branch instruction, each branch instruction corresponds to two candidate subsequent execution paths, and the main path is a path predicted to be executed in the two subsequent execution paths; based on the size between the number of historical erroneous predictions of the main path of the same branch instruction and the confidence threshold, the confidence classification of the main path corresponding to each branch instruction is determined, and the confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path; the confidence classification ratio is determined, and the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is the confidence classification with the number of historical erroneous predictions greater than the confidence threshold; the confidence threshold is adjusted with the confidence classification ratio as the expected ratio as the control target, so as to avoid or reduce the problem that the fixed threshold is too small for different load programs, thereby causing the first branch instruction to account for too large a proportion of the total instructions, and the first branch instruction is the branch instruction corresponding to the main path with the confidence classification of the first classification. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram of a CPU provided by an exemplary embodiment of the present application is shown;

[0023] Figure 2 A schematic diagram of an instruction acquisition system provided by an exemplary embodiment of the present application is shown;

[0024] Figure 3 A flowchart of an instruction acquisition method provided by an exemplary embodiment of the present application is shown;

[0025] Figure 4 A flowchart of an instruction acquisition method provided by an exemplary embodiment of the present application is shown;

[0026] Figure 5 A flowchart of an instruction acquisition method provided by an exemplary embodiment of the present application is shown;

[0027] Figure 6 It is a structural block diagram of a computer device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0029] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0030] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0031] It should be noted that the object information (including but not limited to object device information, object personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the object or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0032] It should be understood that, although the terms first, second, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0033] The terminal devices involved in the embodiments of the present application include but are not limited to mobile phones, computers, intelligent voice interaction devices, smart home appliances, vehicle terminals, aircraft, etc. The embodiments of the present application can be applied to various scenarios, including but not limited to cloud technology, artificial intelligence, smart transportation, assisted driving, etc.

[0034] First, the relevant contents of this application are introduced:

[0035] Central Processing Unit (CPU): It is one of the main devices of electronic computers and the core component of computers. The main function of CPU is to interpret computer instructions and process data in computer software. CPU is the core component of the computer responsible for reading instructions, decoding instructions and executing instructions.

[0036] Instruction fetch: Instruction fetch is when the CPU gets the next instruction to be executed from the instruction cache. During execution, the CPU needs to fetch the instruction from the instruction cache and then execute it.

[0037] Hit instruction: means that when the CPU needs to obtain a certain instruction, since the instruction or the address corresponding to the instruction has been stored in the instruction cache, the instruction can be found. Finding the instruction means the instruction is hit, and not finding the instruction means the instruction is missed.

[0038] Branch instruction: A type of instruction in a computer program that is used to change the flow of execution during the execution of a computer program. A branch instruction determines the next step in the execution of a computer program based on whether a certain condition is met or not.

[0039] Prediction of branch instructions: Prediction of branch instructions refers to the CPU predicting the subsequent execution path when executing a branch instruction. The prediction of branch instructions is usually divided into two results: jump (taken) and not jump (not taken). If the prediction result is a jump, the CPU believes that the branch instruction will be executed and will jump to the target address to continue execution; if the prediction result is not a jump, the CPU believes that the branch instruction will not be executed and will continue to execute the next instruction of the branch instruction.

[0040] Main path / secondary path: A branch instruction corresponds to two candidate subsequent execution paths. The main path is the path predicted to be executed among the two subsequent execution paths, and the secondary path is a subsequent execution path different from the main path.

[0041] Confidence classification: Confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path, including a first classification and a second classification. For example, the first classification indicates that the possibility of the accuracy of the prediction of the main path is low, and the second classification indicates that the possibility of the accuracy of the prediction of the main path is high.

[0042] Artificial Intelligence (AI): It is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that machines have the functions of perception, reasoning and decision-making.

[0043] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. Basic artificial intelligence technologies generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, pre-trained models are also called large models and basic models. After fine-tuning, they can be widely used in downstream tasks in various major directions of artificial intelligence. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0044] With the research and advancement of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, driverless cars, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence-generated content, conversational interaction, smart medical care, smart customer service, game AI, etc. With the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0045] In the design of the CPU, the branch predictor in the CPU is used to predict the subsequent execution path of the branch instruction, and the subsequent execution path of the branch instruction corresponds to the next instruction of the branch instruction. The instruction cache in the CPU is used to obtain and store the next instruction of the branch instruction in advance, so that it can be quickly read from the instruction cache when executing the next instruction. If the CPU finds that there is an error in the subsequent execution path of the predicted branch instruction, it will clear the instruction and re-fetch (re-fetch the next instruction to be executed). Re-fetching requires obtaining instructions from a cache in the CPU that is lower than the instruction cache, or even from memory outside the CPU, which will reduce the efficiency of obtaining instructions and affect the performance of the CPU.

[0046] In the related art, when the execution path of a branch instruction is predicted by a branch predictor in a CPU, since the branch instruction corresponds to two candidate subsequent execution paths, the address of the predicted execution path (main path) is used as the prefetch address of the main path, the prefetch address of the main path is stored in the instruction cache, and the address of the subsequent execution path (secondary path) different from the main path is used as the prefetch address of the secondary path, and the prefetch address of the secondary path is stored in the instruction cache. The instruction cache obtains the corresponding instructions according to the prefetch address of the main path and the prefetch address of the secondary path. When the CPU re-fetches the instruction, it obtains the instruction corresponding to the prefetch address of the secondary path from the instruction cache to improve this problem. The confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path. The confidence classification includes a first classification and a second classification. The first classification indicates that the possibility of the accuracy of the prediction of the main path is low, and the second classification indicates that the possibility of the accuracy of the prediction of the main path is high. The related technology determines the confidence classification based on whether the value of the counter in the branch predictor is greater than a fixed threshold. Each counter is used to count the number of historical correct predictions of a single branch instruction. For example, when the value of the counter is greater than the fixed threshold, the confidence classification is the second classification. When the value of the counter is less than or equal to the fixed threshold, the confidence classification is the first classification.

[0047] In the related art, there are two methods for expressing confidence classification:

[0048] Method 1: Represent confidence classification according to the numerical value of the counter in the branch predictor.

[0049] The counter is used to count the number of historical correct predictions of branch instructions. The confidence classification of the branch instruction is confirmed by judging whether the value of the counter is greater than a fixed threshold. If the value of the counter is less than or equal to the fixed threshold, it indicates that the confidence classification is the first classification.

[0050] Method 2: Confidence classification is expressed by calculating the misprediction rate of branch instructions.

[0051] The error prediction rate is obtained by counting the number of historical mispredictions of branch instructions using an error counter, counting the number of historical correct predictions of branch instructions using a correct counter, and then dividing the value of the error counter by the sum of the values ​​of the error counter and the correct counter. The error prediction rate is compared with a fixed prediction rate threshold. If the error prediction rate is greater than the fixed prediction rate threshold, it indicates that the confidence classification is the first classification.

[0052] However, the total instructions of the program include branch instructions and other instructions. When the total number of instructions is fixed, the related technology faces a load program including different numbers of branch instructions. Since the confidence classification is determined according to a fixed threshold, it may happen that due to the large number of branch instructions and the small fixed threshold, the number of first branch instructions accounts for too large a proportion of the total number of instructions. The first branch instruction is the branch instruction corresponding to the main path with the confidence classification of the first classification. For example, the first load program includes 10 branch instructions, and the second load program includes 50 branch instructions. Assuming that the fixed threshold value is 3, there are 4 branch instructions corresponding to the main path with the confidence classification of the first classification in the first load program, then there are 4 instructions corresponding to the prefetch address of the prefetched secondary path, and there are 20 branch instructions corresponding to the main path with the confidence classification of the first classification in the second load program, then there are 20 instructions corresponding to the prefetch address of the prefetched secondary path. Compared with the first load program, the number of first branch instructions in the second load program accounts for a larger proportion of the total number of instructions, and the number of instructions corresponding to the prefetch address of the prefetched secondary path is also larger, which affects the performance of the CPU.

[0053] In order to solve the above problems, an embodiment of the present application provides an instruction acquisition method, which can be applied to a processor, such as a CPU in a server or a terminal device. The server can be an independent physical server, or a server cluster or a distributed system composed of multiple physical servers, but is not limited thereto. The terminal device can be an electronic device such as a personal computer (PC), a mobile phone, a tablet computer, a vehicle terminal (vehicle computer), a wearable device, etc.

[0054] Figure 1 A schematic diagram of a CPU 100 provided by an exemplary embodiment of the present application is shown, and the CPU 100 includes at least one of the following: a branch predictor 110 , an address selector 120 , an instruction fetch queue 130 , a prefetch queue 140 , a first cache 150 , a second cache 160 , and a third cache 170 .

[0055] The subsequent execution path of the branch instruction is predicted by the branch predictor 110 to obtain the prediction result of the branch instruction. The branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed in the two subsequent execution paths. The prediction result of the branch instruction carries the address of the main path. The branch predictor 110 sends the address of the main path to the instruction fetch queue 130, which is used to temporarily store the address of the main path. When it is not the turn to execute the branch instruction, the instruction fetch queue 130 sends the address of the main path as the pre-fetch address of the main path to the first cache 150, which can be called an instruction cache.

[0056] In some embodiments, the prediction result of the branch instruction also carries the confidence classification of the main path. When the confidence classification of the main path is the first classification, the address of the subsequent execution path different from the main path needs to be selected by the address selector 120 as the address of the secondary path and sent to the prefetch queue 140. The prefetch queue 140 can be called a secondary path prefetch queue, which is used to temporarily store the address of the secondary path. When it is not the turn to execute the branch instruction, the prefetch queue 140 sends the address of the secondary path as the prefetch address of the secondary path to the first cache 150. In the embodiment of the present application, the confidence classification is referred to as confidence, which is used to indicate the possibility classification of the accuracy of the prediction of the main path. The confidence classification includes a first classification and a second classification. The first classification indicates that the possibility of the accuracy of the prediction of the main path is low (low confidence), and the second classification indicates that the possibility of the accuracy of the prediction of the main path is high (high confidence).

[0057] In some embodiments, the instruction fetch queue 130 and the prefetch queue 140 send instruction requests to the corresponding caches respectively, and the instruction requests include at least one of: instruction fetch requests, main path prefetch requests, and secondary path prefetch requests. For example, the instruction fetch queue 130 sends the instruction fetch request to the first cache 150 and the second cache 160, the instruction fetch queue 130 sends the main path prefetch request to the first cache 150, and the prefetch queue 140 sends the secondary path prefetch request to the first cache 150. The main path prefetch request is used to request to prefetch the instruction corresponding to the prefetch address of the main path, and the secondary path prefetch request is used to request to prefetch the instruction corresponding to the prefetch address of the secondary path. The three instruction requests carry corresponding request addresses respectively, and the first cache 150 determines whether the instruction request hits by comparing the request address with the address stored in the first cache 150. When the request address matches the stored address, the instruction request hits; when the request address does not match the stored address, the instruction request misses.

[0058] In some embodiments, for a missed instruction request, it is necessary to request to obtain the instruction from the third cache 170. The missed instruction request includes at least one of: an instruction fetch request, a primary path prefetch request, and a secondary path prefetch request. The third cache 170 is a lower-level cache of the first cache 150, for example, a cache lower than the instruction cache.

[0059] Based on the missed instruction request, the third cache 170 returns the corresponding instruction to the first cache 150 or the second cache 160. The instruction includes at least one of the following: the instruction that needs to be executed currently, the instruction of the main path (the instruction corresponding to the prefetch address of the main path), and the instruction of the secondary path (the instruction corresponding to the prefetch address of the secondary path). For example, the third cache 170 returns the instruction that needs to be executed currently or the instruction of the main path to the first cache 150, and returns the instruction of the secondary path to the second cache 160.

[0060] Figure 2A schematic diagram of an instruction acquisition system 200 provided by an exemplary embodiment of the present application is shown. In some embodiments, when the CPU does not include other caches except the first cache 150 and the second cache 160, for a missed instruction request, it is necessary to request to obtain the instruction from the memory 210. The missed instruction request includes: at least one of an instruction fetch request, a primary path prefetch request, and a secondary path prefetch request.

[0061] Based on the missed instruction request, the memory 210 returns the corresponding instruction to the first cache 150 or the second cache 160. The instruction includes at least one of the following: the instruction that needs to be executed currently, the instruction of the main path (the instruction corresponding to the prefetch address of the main path), and the instruction of the secondary path (the instruction corresponding to the prefetch address of the secondary path). For example, the memory 210 returns the instruction that needs to be executed currently or the instruction of the main path to the first cache 150, and returns the instruction of the secondary path to the second cache 160.

[0062] In some embodiments, when the instruction fetch request hits an instruction in the second cache 160 , ie, an instruction of the secondary path, the second cache 160 stores the instruction of the secondary path in the first cache 150 .

[0063] In some embodiments, the branch predictor 110 includes a first storage unit 112, such as a branch target buffer (Branch Target Buffer, BTB), and the first storage unit 112 is a storage unit for storing branch prediction information, and the branch prediction information includes a confidence classification of the main path. The first storage unit 112 includes multiple items (multiple branch prediction information), and each item corresponds to a counter. Taking the counter as a saturated counter as an example, the number of bits occupied by the saturated counter is small, for example, 3 bits. When the branch predictor predicts an error, the value of the saturated counter of the corresponding item will be increased by 1, and the saturated counter will no longer increase after it is saturated (equal to 7 in the case of 3 bits).

[0064] In order to extend the use time of the saturated counter, when the total number of branch instruction mispredictions reaches a certain threshold, the values ​​of the saturated counters corresponding to all items are reduced by 1. For example, when the total number of branch instruction mispredictions reaches 32 times, the values ​​of the saturated counters corresponding to all items are reduced by 1. When the value of the saturated counter is 0, it will no longer decrease.

[0065] When the branch predictor 110 makes a prediction, if an item in the first storage unit 112 is hit, it is determined whether the value of the saturation counter corresponding to the hit item is greater than a preset confidence threshold. If it is greater than the confidence threshold, the confidence classification of the item is marked as the first classification (low confidence); if it is less than or equal to the confidence threshold, the confidence classification of the item is marked as the second classification (high confidence). For example, the confidence classification is represented by 1 bit, and when the bit value is 1, it indicates low confidence, and when the bit value is 0, it indicates high confidence; or when the bit value is 1, it indicates high confidence, and when the bit value is 0, it indicates low confidence, and the embodiment of the present application is not limited to this.

[0066] In some embodiments, the confidence threshold is dynamically adjusted for load programs including different numbers of branch instructions.

[0067] For different branch instructions, the confidence classification ratio is compared with the expected ratio. The confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions. For example, when the total number of instructions is 1000, a 10-bit threshold counter is used to accumulate and count the number of branch instructions whose confidence classification is the first classification. The confidence classification ratio is the ratio of the value of the threshold counter to the total number of instructions. The expected ratio represents the expected confidence classification ratio.

[0068] When the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased; when the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered.

[0069] In some embodiments, the confidence threshold may be changed based on a predetermined step size, or based on a dynamic step size determined by the difference between the confidence classification ratio and the expected ratio. For example, if the confidence classification ratio is greater than the expected ratio, the value of the confidence threshold is increased by 1, otherwise the value of the confidence threshold is decreased by 1. For example, when the expected ratio is 15%, the initial confidence threshold value is 4, and the total number of instructions is 1000, the value of the threshold counter is 100, and the confidence classification ratio is 10%, which is less than 15%, so the value of the confidence threshold is adjusted to 3.

[0070] The counter used to represent the confidence threshold is also a saturated counter. When occupying 3 bits, the saturated counter will not decrease after the value is 0, and will not increase after saturation (the value is 7).

[0071] In summary, the method provided in this embodiment can avoid or reduce the problem that the fixed confidence threshold is too large or too small for different load programs, thereby causing the number of first branch instructions to account for an unreasonable proportion of the total number of instructions, by taking the confidence classification ratio as the expected ratio as the control target and adjusting the confidence threshold. The first branch instruction is a branch instruction corresponding to the main path of the first classification;

[0072] The method provided in this embodiment also adds a second cache for storing instructions corresponding to the prefetch address of the secondary path. When an instruction fetch request hits the instruction corresponding to the prefetch address of the secondary path, the instruction corresponding to the prefetch address of the secondary path is stored in the first cache, thereby avoiding overwriting of the instructions in the first cache.

[0073] Figure 3 A flowchart of an instruction acquisition method provided by an exemplary embodiment of the present application is shown. The method is executed by a CPU and includes:

[0074] Step 310: Get the main path predicted for each branch instruction.

[0075] In some embodiments, each branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed in the two subsequent execution paths. For example, the subsequent execution paths are other instructions and the next instruction in sequence. When the path predicted to execute the branch instruction is to jump to other instructions, the main path is the other instructions; when the path predicted to execute the branch instruction is not to jump and continue to execute the next instruction in sequence, the main path is the next instruction in sequence.

[0076] Step 320: Determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold.

[0077] In some embodiments, the confidence threshold is a dynamically adjusted threshold value.

[0078] In some embodiments, the confidence classification is used to indicate the possibility classification of the prediction accuracy of the main path. The confidence classification may also be referred to as prediction confidence, or simply confidence, and includes a first classification and a second classification. For example, when the confidence classification is the first classification, it indicates that the possibility of the prediction accuracy of the main path is low, that is, the confidence classification is low; when the confidence classification of the main path is the second classification, it indicates that the possibility of the prediction accuracy of the main path is high, that is, the confidence classification is high.

[0079] Step 330: Determine the confidence classification ratio.

[0080] In some embodiments, the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is a confidence classification in which the number of historical mispredictions is greater than the confidence threshold.

[0081] In some embodiments, the CPU includes a first storage unit, the first storage unit is used to store branch prediction information corresponding to the main path, each branch prediction information corresponds to a prediction counter, and the prediction counter is used to indicate the number of historical mispredictions corresponding to the branch prediction information;

[0082] In the case where the value of the prediction counter is greater than the confidence threshold, the confidence classification is the first classification;

[0083] In case the value of the prediction counter is less than or equal to the confidence threshold, the confidence classification is the second classification.

[0084] Step 340: Taking the confidence classification ratio as the expected ratio as the control target, adjust the confidence threshold.

[0085] In some embodiments, the expected ratio is a preset confidence classification ratio, which is used to represent an expected relatively stable confidence classification ratio.

[0086] For different load programs, if the fixed confidence threshold is too small, the confidence classification ratio will be too large, which will lead to too many pre-fetched instructions and insufficient instruction cache space for storing instructions; if the fixed confidence threshold is too large, the confidence classification ratio will be too small, which will lead to too few pre-fetched instructions. When the CPU needs to obtain instructions, it may not be able to quickly find instructions in the instruction cache, wasting instruction cache space. By adjusting the confidence threshold, such problems can be avoided or reduced.

[0087] To sum up, the method provided in this embodiment adjusts the confidence threshold by taking the confidence classification ratio as the expected ratio as the control target, so as to avoid or reduce the problem that the fixed confidence threshold is too large or too small for different load programs, thereby causing the number of first branch instructions to account for an unreasonable ratio of the total number of instructions. The first branch instruction is a branch instruction corresponding to the main path of the first confidence classification.

[0088] In some embodiments, when the confidence classification ratio is greater than or less than the expected ratio, the confidence threshold is adjusted. Figure 4 A flowchart of an instruction acquisition method provided by an exemplary embodiment of the present application is shown. The method is executed by a CPU and includes:

[0089] Step 310: Get the main path predicted for each branch instruction.

[0090] In some embodiments, each branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed in the two subsequent execution paths. For example, the subsequent execution paths are other instructions and the next instruction in sequence. When the path predicted to execute the branch instruction is to jump to other instructions, the main path is the other instructions; when the path predicted to execute the branch instruction is not to jump and continue to execute the next instruction in sequence, the main path is the next instruction in sequence.

[0091] Step 320: Determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold.

[0092] In some embodiments, the confidence threshold is a dynamically adjusted threshold value.

[0093] In some embodiments, the confidence classification is used to indicate the possibility classification of the prediction accuracy of the main path. The confidence classification may also be referred to as prediction confidence, or simply confidence, and includes a first classification and a second classification. For example, when the confidence classification is the first classification, it indicates that the possibility of the prediction accuracy of the main path is low, that is, the confidence classification is low; when the confidence classification of the main path is the second classification, it indicates that the possibility of the prediction accuracy of the main path is high, that is, the confidence classification is high.

[0094] Step 330: Determine the confidence classification ratio.

[0095] In some embodiments, the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is a confidence classification in which the number of historical mispredictions is greater than the confidence threshold.

[0096] In some embodiments, the CPU includes a first storage unit, the first storage unit is used to store branch prediction information corresponding to the main path, each branch prediction information corresponds to a prediction counter, and the prediction counter is used to indicate the number of historical mispredictions corresponding to the branch prediction information;

[0097] In the case where the value of the prediction counter is greater than the confidence threshold, the confidence classification is the first classification;

[0098] In case the value of the prediction counter is less than or equal to the confidence threshold, the confidence classification is the second classification.

[0099] Step 342: When the confidence classification ratio is less than the expected ratio, lower the confidence threshold.

[0100] When the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered based on a predetermined step size, or the confidence threshold is lowered based on a dynamic step size determined based on the difference between the confidence classification ratio and the expected ratio.

[0101] like Figure 1 As shown, the branch predictor 110 is used to adjust the confidence threshold. The branch predictor 110 includes a first storage unit 112. The first storage unit 112 is a storage unit for storing branch prediction information. The branch prediction information includes the confidence classification of the main path. The first storage unit 112 includes multiple items (multiple branch prediction information), and each item corresponds to a counter. Taking the counter as a saturated counter as an example, the number of bits occupied by the saturated counter is small, for example, 3 bits. When the branch predictor predicts an error, the value of the saturated counter of the corresponding item will be increased by 1. When the saturated counter is saturated (equal to 7 in the case of 3 bits), it will no longer increase.

[0102] When the branch predictor 110 makes a prediction, if an item in the first storage unit 112 is hit, it is determined whether the value of the saturation counter corresponding to the hit item is greater than a preset confidence threshold. If it is greater than the confidence threshold, the confidence classification of the item is marked as the first classification (low confidence); if it is less than or equal to the confidence threshold, the confidence classification of the item is marked as the second classification (high confidence). For example, the confidence classification is represented by 1 bit, and when the bit value is 1, it indicates low confidence, and when the bit value is 0, it indicates high confidence; or when the bit value is 1, it indicates high confidence, and when the bit value is 0, it indicates low confidence, and the embodiment of the present application is not limited to this.

[0103] For different branch instructions, the confidence classification ratio is compared with the expected ratio. The confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions. For example, when the total number of instructions is 1000, a 10-bit threshold counter is used to accumulate and count the number of branch instructions whose confidence classification is the first classification. The confidence classification ratio is the ratio of the value of the threshold counter to the total number of instructions. The expected ratio represents the expected confidence classification ratio.

[0104] When the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased; when the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered.

[0105] In some embodiments, the confidence threshold may be changed based on a predetermined step size, and the predetermined step size is taken as 1 for example. If the confidence classification ratio is greater than the expected ratio, the value of the confidence threshold is increased by 1, otherwise the value of the confidence threshold is decreased by 1. For example, when the expected ratio is 15%, the initial confidence threshold value is 4, and the total number of instructions is 1000, the value of the threshold counter is 100, and the confidence classification ratio is 10%, which is less than 15%, so the value of the confidence threshold is adjusted to 3.

[0106] In some embodiments, the confidence threshold can be changed based on a dynamic step size determined by the difference between the confidence classification ratio and the expected ratio. For example, when the expected ratio is 15%, the initial confidence threshold value is 5, and the total number of instructions is 1000, the value of the threshold counter is 100, and the confidence classification ratio is 10%, which is less than 15%, so the value of the confidence threshold is adjusted to 3, so that when the total number of instructions is 1000, the value of the threshold counter is 150, and the confidence classification ratio is 15%.

[0107] Step 344: When the confidence classification ratio is greater than the expected ratio, increase the confidence threshold.

[0108] In some embodiments, when the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased based on a predetermined step size, or the confidence threshold is increased based on a dynamic step size determined based on the difference between the confidence classification ratio and the expected ratio.

[0109] The principle of increasing the confidence threshold is the same as the principle of decreasing the confidence threshold. For specific implementation details, refer to step 342 and will not be repeated here.

[0110] To summarize, the method provided in this embodiment adjusts the confidence threshold by taking the confidence classification ratio as the expected ratio as the control target, for example, adjusting the confidence threshold according to a predetermined step size or a dynamic step size determined by the difference between the confidence classification ratio and the expected ratio. This can avoid or reduce the problem that the fixed confidence threshold is too large or too small for different load programs, thereby resulting in an unreasonable ratio of the number of first branch instructions to the total number of instructions. The first branch instruction is a branch instruction corresponding to the main path of the first confidence classification.

[0111] In some embodiments, when the confidence classification is different, the cache method used is also different. Figure 5 A flowchart of an instruction acquisition method provided by an exemplary embodiment of the present application is shown. The method is executed by a CPU and includes:

[0112] Step 310: Get the main path predicted for each branch instruction.

[0113] In some embodiments, each branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed in the two subsequent execution paths. For example, the subsequent execution paths are other instructions and the next instruction in sequence. When the path predicted to execute the branch instruction is to jump to other instructions, the main path is the other instructions; when the path predicted to execute the branch instruction is not to jump and continue to execute the next instruction in sequence, the main path is the next instruction in sequence.

[0114] Step 320: Determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold.

[0115] In some embodiments, the confidence threshold is a dynamically adjusted threshold value.

[0116] In some embodiments, the confidence classification is used to indicate the possibility classification of the prediction accuracy of the main path. The confidence classification may also be referred to as prediction confidence, or simply confidence, and includes a first classification and a second classification. For example, when the confidence classification is the first classification, it indicates that the possibility of the prediction accuracy of the main path is low, that is, the confidence classification is low; when the confidence classification of the main path is the second classification, it indicates that the possibility of the prediction accuracy of the main path is high, that is, the confidence classification is high.

[0117] Step 322: Get instruction request.

[0118] In some embodiments, the instruction request includes at least one of the following: an instruction fetch request; a primary path prefetch request; a secondary path prefetch request.

[0119] Among them, the instruction fetch request is used to request to obtain the instructions to be executed; the main path prefetch request is used to request to prefetch the instructions of the main path, and the instructions of the main path are the instructions corresponding to the prefetch address of the main path; the secondary path prefetch request is used to request to prefetch the instructions of the secondary path, and the instructions of the secondary path are the instructions corresponding to the prefetch address of the secondary path.

[0120] Step 3242: When the confidence classification is the first classification, the first caching method is adopted.

[0121] In some embodiments, the CPU includes a first cache, the first cache is used to store the pre-fetch address of the main path and the pre-fetch address of the secondary path, the pre-fetch address of the main path is the address of the main path, the pre-fetch address of the secondary path is the address of a subsequent execution path different from the main path, the confidence classification includes a first classification and a second classification, the second classification is a confidence classification with a historical number of wrong predictions less than or equal to a confidence threshold. The first cache is also used to store instructions corresponding to the pre-fetch address of the main path and instructions corresponding to the pre-fetch address of the secondary path.

[0122] In some embodiments, the instruction request includes a main path prefetch request or a secondary path prefetch request, and the first caching method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path, the instruction of the main path is the instruction corresponding to the prefetch address of the main path; or, based on the hit situation of the secondary path prefetch request and the prefetch address of the secondary path, obtaining the instruction of the secondary path, the instruction of the secondary path is the instruction corresponding to the prefetch address of the secondary path.

[0123] Instructions for the main path:

[0124] In some embodiments, the CPU further includes a third cache, which is a lower level cache of the first cache. Based on the hit of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path includes:

[0125] When the main path prefetch request hits the prefetch address of the main path, obtaining the instruction of the main path in the first cache;

[0126] In the case that the main path prefetch request does not hit the prefetch address of the main path, the first cache sends the main path prefetch request to the third cache, and the third cache stores the instruction of the main path into the first cache.

[0127] In some embodiments, if the primary path prefetch request hits the prefetch address of the secondary path, fetching the instruction of the primary path in the first cache;

[0128] In the case that the primary path prefetch request does not hit the prefetch address of the secondary path, the first cache sends the primary path prefetch request to the third cache, and the third cache stores the instruction of the primary path into the first cache.

[0129] In some embodiments, when the main path prefetch request hits the address of the instruction fetch request, the main path instruction is obtained in the first cache;

[0130] In the case that the main path prefetch request does not hit the address of the instruction fetch request, the first cache sends the main path prefetch request to the third cache, and the third cache stores the instruction of the main path into the first cache.

[0131] like Figure 1 As shown, the instruction fetch queue 130 and the prefetch queue 140 send instruction requests to the corresponding caches respectively, and the instruction requests include: at least one of an instruction fetch request, a main path prefetch request, and a secondary path prefetch request. For example, the instruction fetch queue 130 sends the instruction fetch request to the first cache 150 and the second cache 160, the instruction fetch queue 130 sends the main path prefetch request to the first cache 150, and the prefetch queue 140 sends the secondary path prefetch request to the first cache 150. The main path prefetch request is used to request to prefetch the instruction corresponding to the prefetch address of the main path, and the secondary path prefetch request is used to request to prefetch the instruction corresponding to the prefetch address of the secondary path. The three instruction requests carry corresponding request addresses respectively, and the first cache 150 determines whether the instruction request hits by comparing the request address with the address stored in the first cache 150. When the request address matches the stored address, the instruction request hits; when the request address does not match the stored address, the instruction request misses.

[0132] For a missed instruction request, it is necessary to request to obtain the instruction from the third cache. The missed instruction request includes at least one of: an instruction fetch request, a primary path prefetch request, and a secondary path prefetch request. The third cache is a lower-level cache of the first cache, for example, a cache lower than the instruction cache. Optionally, for a missed instruction request, it is necessary to request to obtain the instruction from the memory.

[0133] Based on the missed instruction request, the third cache returns the corresponding instruction. After the third cache returns the corresponding instruction, different instructions are stored in the corresponding memory respectively. The instruction includes at least one of the following: instruction fetch result, main path prefetch result, and secondary path prefetch result. Among them, the instruction fetch result includes the instruction currently required to be executed, the main path prefetch result includes the instruction of the main path (the instruction corresponding to the prefetch address of the main path), and the secondary path prefetch result includes the instruction of the secondary path (the instruction corresponding to the prefetch address of the secondary path). For example, the third cache stores the instruction of the main path in the first cache.

[0134] In some embodiments, when the CPU is just started, there is no address or instruction stored in the first cache. 1. Taking other instructions A, branch instruction B, other instructions C, and other instructions D in order as an example, when other instruction A needs to be executed, the instruction fetch queue will send a first instruction fetch request to the first cache. The first instruction fetch request carries the address of other instruction A. If there is no hit, the first cache stores the address of other instruction A and sends the first instruction fetch request to the third cache. After a hit, other instruction A is returned to the first cache;

[0135] 2. The instruction fetch queue sends a first main path prefetch request, which carries the address of the main path of branch instruction B, to the first cache. If there is no hit, the first cache stores the address of the main path and sends the first main path prefetch request to the third cache. After a hit, the instruction corresponding to the address of the main path is returned to the first cache.

[0136] 3. The instruction fetch queue sends a second main path prefetch request, which carries the address of other instruction C and is sent to the first cache. If there is no hit, the first cache stores the address of other instruction C and sends the second main path prefetch request to the third cache. If there is a hit, the instruction corresponding to the address of other instruction C is returned to the first cache.

[0137] 4. The instruction fetch queue sends a third main path prefetch request, which carries the address of other instruction D, to the first cache. If there is no hit, the first cache stores the address of other instruction D and sends the third main path prefetch request to the third cache. If there is a hit, the instruction corresponding to the address of other instruction D is returned to the first cache.

[0138] 5. When the instruction fetch queue sends a main path prefetch request, the CPU continues to execute instructions. When the CPU executes branch instruction B, the instruction fetch queue sends a second instruction fetch request to the first cache. The second instruction fetch request carries the address of the main path of branch instruction B, hits the address of the main path of branch instruction B in the first cache, and executes the main path of branch instruction B, for example, jumping to other instruction D.

[0139] 6. When the CPU executes other instructions D, the instruction fetch queue sends a third instruction fetch request to the first cache. The third instruction fetch request carries the address of other instructions D, hits the address of other instructions D in the first cache, and obtains other instructions D.

[0140] 7. The instruction fetch queue continues to send main path prefetch requests. If the subsequent main path prefetch requests carry the address of other instruction A, the address of the main path of branch instruction B, the address of other instruction C, and the address of other instruction D, the main path prefetch request can hit and directly obtain the corresponding instruction from the first cache without going to the third cache to obtain the corresponding instruction.

[0141] Instructions for the secondary path:

[0142] In some embodiments, the CPU further includes: a second cache and a third cache, wherein the third cache is a lower level cache of the first cache. Based on the hit of the secondary path prefetch request and the prefetch address of the secondary path, obtaining the instruction of the secondary path includes:

[0143] In the case where the secondary path prefetch request hits the prefetch address of the secondary path, the first cache obtains the instruction of the secondary path;

[0144] In the case that the secondary path prefetch request does not hit the prefetch address of the secondary path, the first cache sends the secondary path prefetch request to the third cache, and the third cache stores the instruction of the secondary path into the second cache.

[0145] In some embodiments, if the secondary path prefetch request hits the prefetch address of the primary path, the first cache obtains the instruction of the secondary path;

[0146] In the case that the secondary path prefetch request does not hit the prefetch address of the primary path, the first cache sends the secondary path prefetch request to the third cache, and the third cache stores the instruction of the secondary path into the second cache.

[0147] In some embodiments, when the secondary path prefetch request hits the address of the instruction fetch request, the first cache obtains the instruction of the secondary path;

[0148] In the case that the secondary path prefetch request does not hit the address of the instruction fetch request, the first cache sends the secondary path prefetch request to the third cache, and the third cache stores the instruction of the secondary path into the second cache.

[0149] like Figure 1 As shown, the instruction fetch queue 130 and the prefetch queue 140 send instruction requests to the corresponding caches respectively, and the instruction requests include: at least one of an instruction fetch request, a main path prefetch request, and a secondary path prefetch request. For example, the instruction fetch queue 130 sends the instruction fetch request to the first cache 150 and the second cache 160, the instruction fetch queue 130 sends the main path prefetch request to the first cache 150, and the prefetch queue 140 sends the secondary path prefetch request to the first cache 150. The main path prefetch request is used to request to prefetch the instruction corresponding to the prefetch address of the main path, and the secondary path prefetch request is used to request to prefetch the instruction corresponding to the prefetch address of the secondary path. The three instruction requests carry corresponding request addresses respectively, and the first cache 150 determines whether the instruction request hits by comparing the request address with the address stored in the first cache 150. When the request address matches the stored address, the instruction request hits; when the request address does not match the stored address, the instruction request misses.

[0150] For a missed instruction request, it is necessary to request to obtain the instruction from the third cache. The missed instruction request includes at least one of: an instruction fetch request, a primary path prefetch request, and a secondary path prefetch request. The third cache is a lower-level cache of the first cache, for example, a cache lower than the instruction cache. Optionally, for a missed instruction request, it is necessary to request to obtain the instruction from the memory.

[0151] Based on the missed instruction request, the third cache returns the corresponding instruction. After the third cache returns the corresponding instruction, different instructions are stored in the corresponding memory respectively. The instruction includes at least one of the following: instruction fetch result, main path prefetch result, and secondary path prefetch result. Among them, the instruction fetch result includes the instruction currently required to be executed, the main path prefetch result includes the instruction of the main path (the instruction corresponding to the prefetch address of the main path), and the secondary path prefetch result includes the instruction of the secondary path (the instruction corresponding to the prefetch address of the secondary path). For example, the third cache stores the instruction of the main path in the first cache and the instruction of the secondary path in the second cache.

[0152] In some embodiments, the instruction request further includes an instruction fetch request. When the instruction fetch request hits an instruction of the secondary path in the second cache, the second cache stores the instruction of the secondary path into the first cache.

[0153] In the related art, the instructions of the secondary path are directly stored in the first cache, which may cause the currently executed instructions or other stored instructions to be replaced, thereby causing the instructions in the first cache to be overwritten. By first storing the instructions corresponding to the prefetch address of the secondary path in the second cache, and then storing the instructions corresponding to the prefetch address of the secondary path in the first cache when the instruction fetch request hits the instructions corresponding to the prefetch address of the secondary path, it is possible to avoid overwriting the instructions in the first cache.

[0154] Step 3244: When the confidence classification is the second classification, the second caching method is adopted.

[0155] In some embodiments, the second cache mode includes: obtaining the instruction of the main path based on the hit condition of the main path prefetch request and the prefetch address of the main path.

[0156] The second cache method is the same as the part for the instructions of the main path in step 3242. For specific implementation details, please refer to step 3242 and will not be repeated here.

[0157] Step 330: Determine the confidence classification ratio.

[0158] In some embodiments, the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is a confidence classification in which the number of historical mispredictions is greater than the confidence threshold.

[0159] In some embodiments, the CPU includes a first storage unit, the first storage unit is used to store branch prediction information corresponding to the main path, each branch prediction information corresponds to a prediction counter, and the prediction counter is used to indicate the number of historical mispredictions corresponding to the branch prediction information;

[0160] In the case where the value of the prediction counter is greater than the confidence threshold, the confidence classification is the first classification;

[0161] In case the value of the prediction counter is less than or equal to the confidence threshold, the confidence classification is the second classification.

[0162] Step 340: Taking the confidence classification ratio as the expected ratio as the control target, adjust the confidence threshold.

[0163] In some embodiments, the expected ratio is a preset confidence classification ratio, which is used to represent an expected relatively stable confidence classification ratio.

[0164] For different load programs, if the fixed confidence threshold is too small, the confidence classification ratio will be too large, which will lead to too many pre-fetched instructions and insufficient instruction cache space for storing instructions; if the fixed confidence threshold is too large, the confidence classification ratio will be too small, which will lead to too few pre-fetched instructions. When the CPU needs to obtain instructions, it may not be able to quickly find instructions in the instruction cache, wasting instruction cache space. By adjusting the confidence threshold, such problems can be avoided or reduced.

[0165] To sum up, the method provided in this embodiment adds a second cache for storing instructions corresponding to the prefetch address of the secondary path. When the instruction fetch request hits the instruction corresponding to the prefetch address of the secondary path, the instruction corresponding to the prefetch address of the secondary path is stored in the first cache, thereby avoiding overwriting of the instructions in the first cache.

[0166] In the above embodiment, steps with the same sequence number can be considered as the same step. Figure 3 The corresponding embodiment, Figure 4 The corresponding embodiments and Figure 5 The corresponding embodiments may be implemented individually or in combination, and this application does not limit this.

[0167] The present application embodiment provides a central processing unit, the structure of which is as follows: Figure 1 As shown, including:

[0168] A branch predictor 110 is used to obtain a main path predicted for each branch instruction, each branch instruction corresponds to two candidate subsequent execution paths, and the main path is a path predicted to be executed in the two subsequent execution paths;

[0169] The branch predictor 110 is used to determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold, and the confidence classification is used to indicate the possibility classification of the prediction accuracy of the main path;

[0170] The branch predictor 110 is used to determine the confidence classification ratio, where the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is the confidence classification with a number of historical mispredictions greater than a confidence threshold;

[0171] The branch predictor 110 is used to adjust the confidence threshold by taking the confidence classification ratio as the expected ratio as a control target.

[0172] In a possible design of this embodiment, the branch predictor 110 is used to increase the confidence threshold when the confidence classification ratio is greater than the expected ratio; and to lower the confidence threshold when the confidence classification ratio is less than the expected ratio.

[0173] In a possible design of this embodiment, the branch predictor 110 is used to increase the confidence threshold based on a predetermined step size when the confidence classification ratio is greater than the expected ratio, or to increase the confidence threshold based on a dynamic step size determined based on a difference between the confidence classification ratio and the expected ratio;

[0174] The branch predictor 110 is configured to reduce the confidence threshold based on a predetermined step size when the confidence classification ratio is less than the expected ratio, or to reduce the confidence threshold based on a dynamic step size determined based on a difference between the confidence classification ratio and the expected ratio.

[0175] In a possible design of this embodiment, the central processing unit includes a first cache 150, and the first cache 150 is used to store the pre-fetch address of the main path and the pre-fetch address of the secondary path, the pre-fetch address of the main path is the address of the main path, and the pre-fetch address of the secondary path is the address of a subsequent execution path different from the main path. The confidence classification includes a first classification and a second classification, and the second classification is a confidence classification in which the number of historical wrong predictions is less than or equal to the confidence threshold;

[0176] The first cache 150 is also used to obtain instruction requests; when the confidence classification is the first classification, the first cache method is adopted; when the confidence classification is the second classification, the second cache method is adopted;

[0177] Among them, the instruction request includes a main path prefetch request or a secondary path prefetch request, and the first caching method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path, and the instruction of the main path is the instruction corresponding to the prefetch address of the main path; or, based on the hit situation of the secondary path prefetch request and the prefetch address of the secondary path, obtaining the instruction of the secondary path, and the instruction of the secondary path is the instruction corresponding to the prefetch address of the secondary path; the second cache 160 method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path.

[0178] In a possible design of this embodiment, the central processor further includes: a second cache 160 and a third cache 170, the third cache 170 being a lower-level cache of the first cache;

[0179] In the case where the secondary path prefetch request hits the prefetch address of the secondary path, the first cache 150 is used to obtain the instruction of the secondary path;

[0180] When the secondary path prefetch request does not hit the prefetch address of the secondary path, the first cache 150 sends the secondary path prefetch request to the third cache 170 , and the third cache 170 stores the instruction of the secondary path into the second cache 160 .

[0181] In a possible design of this embodiment, the instruction request also includes an instruction fetch request, and the second cache 160 is further used for: when the instruction fetch request hits the instruction of the secondary path in the second cache 160, the second cache 160 stores the instruction of the secondary path into the first cache 150.

[0182] In a possible design of this embodiment, the central processing unit further includes a third cache 170, and the third cache 170 is a lower-level cache of the first cache 150;

[0183] When the main path prefetch request hits the prefetch address of the main path, the instruction of the main path is obtained in the first cache 150;

[0184] When the main path prefetch request does not hit the prefetch address of the main path, the first cache sends the main path prefetch request to the third cache 170 , and the third cache 170 stores the instruction of the main path into the first cache 150 .

[0185] For details on the CPU architecture, see Figure 1 The embodiments are not described in detail here.

[0186] An embodiment of the present application also provides a computer device, which includes: a processor and a memory, wherein at least one program is stored in the memory; the processor is used to execute at least one program in the memory to implement the instruction acquisition method provided by the above-mentioned method embodiments.

[0187] In some embodiments, the branch instruction corresponds to two candidate subsequent execution paths, the main path is a path predicted to be executed in the two subsequent execution paths, and the secondary path is a subsequent execution path different from the main path; the processor also includes a second cache, the second cache is used to obtain and store instructions corresponding to the address of the secondary path, and the processor is also used to execute at least one program in the memory to implement the following. Figure 5 The instruction acquisition method of the embodiment, the specific implementation details of the second cache refer to Figure 1 Examples and Figure 5 The embodiments are not described in detail here.

[0188] Figure 6 6 is a block diagram of a computer device 600 provided by an exemplary embodiment of the present application. Generally, the computer device 600 includes: a processor 601 and a memory 602 .

[0189] The processor 601 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 601 may be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 601 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 601 may include a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 601 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0190] The memory 602 may include one or more computer-readable storage media, which may be non-transitory. The memory 602 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 602 is used to store at least one instruction, which is used to be executed by the processor 601 to implement the instruction acquisition method provided in the method embodiment of the present application.

[0191] In some embodiments, the computer device 600 may also optionally include: an input interface 603 and an output interface 604. The processor 601, the memory 602 and the input interface 603, the output interface 604 may be connected via a bus or a signal line. Each peripheral device may be connected to the input interface 603, the output interface 604 via a bus, a signal line or a circuit board. The input interface 603, the output interface 604 may be used to connect at least one peripheral device related to input / output to the processor 601 and the memory 602. In some embodiments, the processor 601, the memory 602 and the input interface 603, the output interface 604 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 601, the memory 602 and the input interface 603, the output interface 604 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0192] Those skilled in the art will appreciate that the structure shown above does not constitute a limitation on the computer device 600 , and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0193] In an exemplary embodiment, a chip is also provided. The chip includes a programmable logic circuit and / or program instructions. When the chip runs on a computer device 600, it is used to implement the instruction acquisition method provided in the method embodiment of the present application.

[0194] In an exemplary embodiment, a computer program product is also provided, which includes computer instructions, which are stored in a computer-readable storage medium. A processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the instruction acquisition method provided in the method embodiment of the present application.

[0195] In an exemplary embodiment, a computer-readable storage medium is also provided, in which at least one program is stored, and the at least one program is loaded and executed by a processor to implement the instruction acquisition method provided in the method embodiment of the present application.

[0196] A person of ordinary skill in the art will appreciate that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned computer-readable storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0197] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable storage medium or transmitted as one or more instructions or codes on a computer-readable storage medium. Computer-readable storage media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0198] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for obtaining an instruction, characterized in that: The method is executed by a central processing unit, and the method includes: Obtaining a main path predicted for each branch instruction, wherein each branch instruction corresponds to two candidate subsequent execution paths, and the main path is a path predicted to be executed in the two subsequent execution paths; Determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold, wherein the confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path; Determining a confidence classification ratio, the confidence classification ratio being a ratio of branch instructions corresponding to a first classification to total instructions, the first classification being a confidence classification in which the number of historical mispredictions is greater than the confidence threshold; The confidence threshold is adjusted by taking the confidence classification ratio as the expected ratio as a control target.

2. The method according to claim 1, characterized in that: The adjusting the confidence threshold by taking the confidence classification ratio as the expected ratio as the control target includes: When the confidence classification ratio is greater than the expected ratio, increasing the confidence threshold; When the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered.

3. The method according to claim 2, characterized in that When the confidence classification ratio is greater than the expected ratio, increasing the confidence threshold includes: In the case where the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased based on a predetermined step size, or the confidence threshold is increased based on a dynamic step size determined based on a difference between the confidence classification ratio and the expected ratio; When the confidence classification ratio is less than the expected ratio, lowering the confidence threshold includes: In the case where the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered based on the predetermined step size, or the confidence threshold is lowered based on the dynamic step size determined based on the difference between the confidence classification ratio and the expected ratio.

4. The method according to any one of claims 1 to 3, characterized in that: The central processing unit includes a first cache, the first cache is used to store a pre-fetch address of a primary path and a pre-fetch address of a secondary path, the pre-fetch address of the primary path is the address of the primary path, the pre-fetch address of the secondary path is the address of a subsequent execution path different from the primary path, the confidence classification includes the first classification and the second classification, the second classification is a confidence classification in which the number of historical mispredictions is less than or equal to the confidence threshold, and the method further includes: Obtaining an instruction request; when the confidence classification is the first classification, adopting a first cache method; when the confidence classification is the second classification, adopting a second cache method; Among them, the instruction request includes a main path prefetch request or a secondary path prefetch request, and the first caching method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path, and the instruction of the main path is the instruction corresponding to the prefetch address of the main path; or, based on the hit situation of the secondary path prefetch request and the prefetch address of the secondary path, obtaining the instruction of the secondary path, and the instruction of the secondary path is the instruction corresponding to the prefetch address of the secondary path; the second caching method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path.

5. The method according to claim 4, characterized in that The central processor further includes: a second cache and a third cache, wherein the third cache is a lower level cache of the first cache; The obtaining of the instruction of the secondary path based on the hit condition of the secondary path prefetch request and the prefetch address of the secondary path comprises: In the case where the secondary path prefetch request hits the prefetch address of the secondary path, the first cache obtains the instruction of the secondary path; In the case that the secondary path prefetch request does not hit the prefetch address of the secondary path, the first cache sends the secondary path prefetch request to the third cache, and the third cache stores the instruction of the secondary path into the second cache.

6. The method according to claim 5, characterized in that The instruction request further includes an instruction fetch request, and the method further includes: When the instruction fetch request hits the instruction of the secondary path in the second cache, the second cache stores the instruction of the secondary path into the first cache.

7. The method according to claim 4, characterized in that The central processing unit further includes a third cache, which is a lower-level cache of the first cache; The obtaining of the main path instruction based on the main path prefetch request and the hit condition of the prefetch address of the main path includes: When the main path prefetch request hits the prefetch address of the main path, acquiring the instruction of the main path in the first cache; In the case that the main path prefetch request does not hit the prefetch address of the main path, the first cache sends the main path prefetch request to the third cache, and the third cache stores the instruction of the main path into the first cache.

8. A central processing unit, characterized in that: The central processing unit comprises: A branch predictor, used to obtain a main path predicted for each branch instruction, each branch instruction corresponding to two candidate subsequent execution paths, the main path being a path predicted to be executed among the two subsequent execution paths; The branch predictor is used to determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold, wherein the confidence classification is used to indicate the possibility classification of the prediction accuracy of the main path; The branch predictor is used to determine a confidence classification ratio, where the confidence classification ratio is a ratio of branch instructions corresponding to a first classification to total instructions, and the first classification is a confidence classification for which the number of historical mispredictions is greater than the confidence threshold; The branch predictor is used to adjust the confidence threshold by taking the confidence classification ratio as an expected ratio as a control target.

9. A computer device, characterized in that: The computer device includes: a processor and a memory, wherein the memory stores at least one program; the processor is used to execute the at least one program in the memory to implement the instruction acquisition method according to any one of claims 1 to 4 or the instruction acquisition method according to claim 7.

10. The computer device according to claim 9, characterized in that The branch instruction corresponds to two candidate subsequent execution paths, the primary path is a path predicted to be executed among the two subsequent execution paths, and the secondary path is a subsequent execution path different from the primary path; The processor also includes a second cache, which is used to obtain and store instructions corresponding to the address of the secondary path. The processor is also used to execute the at least one program in the memory to implement the instruction acquisition method as described in claim 5 or 6.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by a processor to implement the instruction acquisition method according to any one of claims 1 to 7.

12. A computer program product, characterized in that The computer program product includes computer instructions, which are stored in a computer-readable storage medium. A processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the instruction acquisition method according to any one of claims 1 to 7.

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