Method for starting heterogeneous chip, heterogeneous chip, system on chip and computer device

Abstract

The embodiment of the application discloses a heterogeneous chip starting method, a heterogeneous chip, a system on chip and computer equipment, and belongs to the chip field. The heterogeneous chip comprises a first processor core and a second processor core, the first processor core is a RISC-V architecture processor core, and the second processor core is an ARM architecture processor core. The method comprises the following steps: running a first starting firmware stored in a first starting address through the first processor core; and running a second starting firmware stored in a second starting address through the second processor core. The first starting firmware and the second starting firmware are different firmwares obtained by cross-compiling the same starting firmware, the first starting firmware supports the RISC-V architecture, and the second starting firmware supports the ARM architecture. The application saves the workload, effectively reduces the development cost, transplantation difficulty and maintenance cost of the starting firmware, and also reduces the research and development cycle and difficulty of the heterogeneous chip.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip field, and in particular to a heterogeneous chip startup method, a heterogeneous chip, a system on chip and a computer device. BACKGROUND

[0002] With the continuous progress of science and technology, heterogeneous chips have become a new trend in the chip technology field. A heterogeneous chip refers to a chip that integrates processor cores of different architectures. In this way, the most suitable processor core can be selected for processing according to different computing requirements, thereby improving the overall processing efficiency.

[0003] The commonly used heterogeneous chip currently includes a processor core of RISC-V (Reduced Instruction Set Computer-Five, fifth generation reduced instruction set computer) architecture and a processor core of ARM (Advanced Reduced Instruction Set Computer Machine, advanced reduced instruction set computer machine) architecture, which can better exert the advantages of the two architectures. When starting the heterogeneous chip, the processor core of RISC-V architecture uses OpenSBI (a kind of firmware) to boot the Linux (a kind of operating system) kernel, and the processor core of ARM architecture uses ATF (ARM Trusted Firmware, ARM trusted firmware) and U-Boot (Universal Boot Loader, universal boot loader) to boot the Linux kernel.

[0004] However, the processor core of RISC-V architecture and the processor core of ARM architecture use different startup firmwares, and the two startup firmwares need to be developed respectively, resulting in a large amount of work. SUMMARY

[0005] Embodiments of the present application provide a heterogeneous chip startup method, a heterogeneous chip, a system on chip and a computer device, which save the amount of work, effectively reduce the development cost, transplantation difficulty and maintenance cost of the startup firmware, and also reduce the research and development period and difficulty of the heterogeneous chip. The technical solution is as follows:

[0006] On the one hand, a heterogeneous chip startup method is provided, the heterogeneous chip including a first processor core and a second processor core, the first processor core being a processor core of RISC-V architecture, and the second processor core being a processor core of ARM architecture.

[0007] The method includes:

[0008] running, by the first processor core, a first startup firmware stored at a first startup address;

[0009] run, by the second processor core, a second start firmware stored at a second start address;

[0010] The first start firmware and the second start firmware are different firmwares obtained by cross-compiling the same start firmware, and the first start firmware supports the RISC-V architecture, and the second start firmware supports the ARM architecture.

[0011] In another aspect, a heterogeneous chip is provided, which includes a first processor core and a second processor core; the first processor core is a processor core of the RISC-V architecture, and the second processor core is a processor core of the ARM architecture.

[0012] The first processor core is configured to run a first start firmware stored at a first start address;

[0013] The second processor core is configured to run a second start firmware stored at a second start address;

[0014] The first start firmware and the second start firmware are different firmwares obtained by cross-compiling the same start firmware, and the first start firmware supports the RISC-V architecture, and the second start firmware supports the ARM architecture.

[0015] In another aspect, a system on chip is provided, which includes the heterogeneous chip as in the above aspect.

[0016] In another aspect, a computer device is provided, which includes the heterogeneous chip as in the above aspect.

[0017] The embodiments of the present application provide a start mode of a processor core of the RISC-V architecture and a processor core of the ARM architecture, only one set of general start firmware needs to be developed, and then the first start firmware supporting the RISC-V architecture and the second start firmware supporting the ARM architecture are compiled, and the first start firmware and the second start firmware are run by the first processor core and the second processor core respectively, so that the start of the heterogeneous chip is realized. By unifying the first start firmware and the second start firmware into the same code space, the developer does not need to develop two sets of start firmware for the processor core of the RISC-V architecture and the processor core of the ARM architecture, the workload is saved, the development cost, the transplantation difficulty and the maintenance cost of the start firmware are effectively reduced, and the research and development period and the research and development difficulty of the heterogeneous chip are also reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0019] Figure 1 is a schematic diagram of a heterogeneous chip provided by an embodiment of the present application;

[0020] Figure 2 is a flowchart of a starting method of a heterogeneous chip provided by an embodiment of the present application;

[0021] Figure 3 is a flowchart of another starting method of a heterogeneous chip provided by an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of various starting stages in a starting process of a first processor core provided by an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of various starting stages in a starting process of a second processor core provided by an embodiment of the present application;

[0024] Figure 6 is a schematic diagram of SBL0 stage and ATF stage of a second processor core provided by an embodiment of the present application;

[0025] Figure 7 is a flowchart of a method for initializing a peripheral function module provided by an embodiment of the present application;

[0026] Figure 8 is a schematic diagram of a structure of a terminal provided by an embodiment of the present application;

[0027] Figure 9 is a schematic diagram of a structure of a server provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the following will further describe the embodiments of the present application in combination with the drawings.

[0029] It can be understood that the terms "first", "second" and the like used in the present application can be used in the description of various concepts in this document, but unless specifically stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the present application, the first processor core can be referred to as the second processor core, and similarly, the second processor core can be referred to as the first processor core.

[0030] wherein at least two means two or more than two, for example, the at least two processor cores can be two processor cores, three processor cores, or any integer greater than or equal to two processor cores. Each means each of the at least two, for example, each processor core means each of the at least two processor cores, and if the at least two processor cores are three processor cores, each processor core means each of the three processor cores.

[0031] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals (including but not limited to signals transmitted between user terminals and other devices, etc.) involved in the present application are fully authorized by the user or relevant parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0032] Artificial intelligence (AI) is the use of digital computers or digital computer-controlled machines to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology of computer science, which aims to understand the essence of intelligence and produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that machines have the functions of perception, reasoning and decision-making.

[0033] Artificial intelligence technology is a comprehensive discipline, involving a wide range of fields, both hardware and software technologies. Artificial intelligence basic technologies generally include sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-training model technology, operation / interaction system, mechatronics, etc. Among them, the pre-training model is also called large model, basic model, which can be widely applied to downstream tasks in various directions of artificial intelligence after fine-tuning. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning, autonomous driving, intelligent transportation, etc.

[0034] With the research and progress of artificial intelligence technology, artificial intelligence technology has been researched and applied in many fields, such as common smart home, smart wearable devices, virtual assistants, smart speakers, smart marketing, unmanned vehicles, autonomous vehicles, drones, digital twins, virtual humans, robots, artificial intelligence generated content, conversational interaction, intelligent medical care, intelligent customer service, game AI, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more and more fields and play an increasingly important role.

[0035] The scheme provided by the embodiments of the present application relates to artificial intelligence technology, and is specifically explained through the following embodiments:

[0036] First, the concepts involved in the embodiments of the present application are explained as follows:

[0037] 1. Heterogeneous chip: refers to a chip that integrates processor cores of different architectures, so that the most suitable processor core can be selected for processing according to different computing requirements.

[0038] 2. UEFI (Unified Extensible Firmware Interface): a personal computer system specification that defines the software interface between the operating system and the system firmware. UEFI is responsible for power-on self-test, contacting the operating system, and providing an interface connecting the operating system and hardware.

[0039] 3. ASIC (Application Specific Integrated Circuit) chip: an integrated circuit designed for a specific purpose, so the architecture of the ASIC chip is precisely designed based on the specific task that the ASIC chip is facing, and the computing power and efficiency of the ASIC chip strictly match the task algorithm.

[0040] 4. ATF (ARM Trusted Firmware): an open source secure firmware designed to provide a trusted root and secure boot function for systems based on ARM architecture.

[0041] 5. Cross-compilation: refers to generating executable code on one platform on another platform. For example, install a cross-compilation tool chain on a host platform, use the cross-compilation tool chain to compile source code, and generate code that can run on the target platform.

[0042] Figure 1 is a schematic diagram of a heterogeneous chip provided by the embodiments of the present application, referring to Figure 1 The heterogeneous chip includes a first processor core 101 and a second processor core 102. The first processor core 101 is a RISC-V architecture processor core, and the second processor core 102 is an ARM architecture processor core.

[0043] The heterogeneous chip fuses the processor cores of the two architectures together, and can give full play to the advantages of the two architectures to a greater extent. For example, for tasks requiring high-performance computing, the second processor core can be used for processing; and for tasks requiring customized processing, the first processor core can be used for processing. In this way, the computing efficiency of the heterogeneous chip can be improved, and the energy consumption of the heterogeneous chip can be reduced, thereby improving the overall performance.

[0044] Optionally, the heterogeneous chip is an ASIC chip or other type of chip, and embodiments of the present application do not limit this.

[0045] The heterogeneous chip further includes an MCU (Micro Controller Unit) 103, which is configured to be responsible for controlling the start of the heterogeneous chip.

[0046] The heterogeneous chip further includes a bus 104 and a peripheral function module 105, and the MCU 103, the first processor core 101, the second processor core 102 and the peripheral function module 105 are connected with the bus 104.

[0047] Optionally, the bus 104 includes an AXI (Advanced eXtensible Interface) bus, an APB (Advanced Peripheral Bus) and the like.

[0048] Optionally, the peripheral function module 105 refers to a function module located on the heterogeneous chip and independent of the processor cores, which can also be referred to as a peripheral or an IP (Intellectual Property) core. The peripheral function module 105 is shared by the first processor core 101 and the second processor core 102, and the number thereof can be one or more.

[0049] Referring to Figure 1 , the peripheral function module 105 can include a UART (Universal Asynchronous Receiver / Transmitter), an SPI (Service Provider Interface), an I2C (Inter-Integrated Circuit), a Timer, a VDEC (Video Decoder) and the like.

[0050] In the embodiments of the present application, the same starting firmware is cross-compiled to obtain different first starting firmware and second starting firmware, the first starting firmware is stored in the first starting address corresponding to the first processor core, and the second starting firmware is stored in the second starting address corresponding to the second processor core, so that in the starting process of the heterogeneous chip, the first processor core starts from the first starting address and runs the first starting firmware, and the second processor core starts from the second starting address and runs the second starting firmware. The specific process of starting is described in detail in the following embodiments, which will not be described here in detail.

[0051] On the basis of the above-mentioned embodiments, the embodiments of the present application further provide a starting method of a heterogeneous chip. Figure 2 is a flowchart of a starting method of a heterogeneous chip provided by the embodiments of the present application, the method is executed by a heterogeneous chip, the heterogeneous chip includes a first processor core and a second processor core, the first processor core is a processor core of RISC-V architecture, and the second processor core is a processor core of ARM architecture. For example, the heterogeneous chip can be a heterogeneous chip as shown in Figure 1 .

[0052] Referring to Figure 2 , the method includes:

[0053] 201. Running, by the first processor core, the first starting firmware stored in the first starting address.

[0054] 202. Running, by the second processor core, the second starting firmware stored in the second starting address.

[0055] Among them, the first starting firmware and the second starting firmware are different firmware obtained by cross-compiling the same starting firmware, and the first starting firmware supports RISC-V architecture and the second starting firmware supports ARM architecture.

[0056] Among them, the first starting address is the starting address of the first processor core, and the second starting address is the starting address of the second processor core. Inside the heterogeneous chip, the type of the processor core can be automatically detected, and the stored starting firmware is run at different starting addresses, so that the first processor core and the second processor core will run the starting firmware stored in the respective starting addresses.

[0057] Optionally, the heterogeneous chip includes a memory storage, which can be a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory) or other memory storage, etc. The first starting firmware is stored in the first starting address in the memory storage, and the second starting firmware is stored in the second starting address in the memory storage.

[0058] The embodiment of the present application only needs to develop a general-purpose starting firmware, and then compile it into a first starting firmware supporting the RISC-V architecture and a second starting firmware supporting the ARM architecture, so as to realize the starting of the first processor core and the second processor core, without the need for the developer to separately develop two sets of starting firmware for the processor core of the RISC-V architecture and the processor core of the ARM architecture.

[0059] Optionally, the assembly starting code contained in the first starting firmware and the second starting firmware is different, wherein the assembly starting code is a starting code developed based on the architecture of the processor core and is only applicable to the processor core of the target architecture, so the first starting firmware includes the assembly starting code applicable to the first processor core, and the second starting firmware includes the assembly starting code applicable to the second processor core.

[0060] Optionally, except for the assembly starting code, the codes of other parts of the first starting firmware and the second starting firmware contain the same functions, only the supported architectures are different.

[0061] Optionally, since the codes of different functions in the starting firmware can be selected for compilation when cross-compiling, except for the assembly starting code, the codes of other parts of the first starting firmware and the second starting firmware can also contain different functions.

[0062] Therefore, the embodiment of the present application does not limit the difference between the first starting firmware and the second starting firmware.

[0063] The embodiment of the present application Figure 2 For example, in another embodiment, step 201 can also be performed after step 202 or in parallel with step 202, and the embodiment of the present application does not limit this.

[0064] In the related art, the processor core of the RISC-V architecture and the processor core of the ARM architecture adopt independent booting modes. The processor core of the RISC-V architecture uses OpenSBI to boot the Linux kernel, and the processor core of the ARM architecture uses ATF and U-Boot to boot the Linux kernel. The two kinds of starting firmware need to be developed respectively, resulting in a large amount of work. Moreover, the two kinds of starting firmware belong to different software systems, resulting in a large transplantation difficulty and a high maintenance cost.

[0065] The embodiment of the present application provides a starting mode of a processor core of a RISC-V architecture and a processor core of an ARM architecture, only one set of universal starting firmware needs to be developed, and then the first starting firmware supporting the RISC-V architecture and the second starting firmware supporting the ARM architecture are compiled, and the first starting firmware and the second starting firmware are respectively run by the first processor core and the second processor core, so that the starting of the heterogeneous chip can be realized. The first starting firmware and the second starting firmware are unified into the same code space, and the developer does not need to develop two sets of starting firmware for the processor core of the RISC-V architecture and the processor core of the ARM architecture, so that the workload is saved, the development cost, the transplantation difficulty and the maintenance cost of the starting firmware are effectively reduced, and the research and development period and the research and development difficulty of the heterogeneous chip are also reduced.

[0066] On the basis of the above embodiment, referring to Figure 1 The heterogeneous chip can further include an MCU and a memory storage, the MCU is used for being responsible for controlling the starting of the heterogeneous chip, and the memory storage can be a DDR SDRAM or other memory storage.

[0067] The method further includes:

[0068] 203. Resetting the first processor core and the second processor core by the MCU, and initializing the memory storage.

[0069] 204. Loading the first starting firmware into the memory storage by the MCU, and configuring the address of the first starting firmware in the memory storage as a first starting address corresponding to the first processor core.

[0070] The first starting address is the starting address set by the MCU for the first processor core.

[0071] In addition, the MCU can load the first starting firmware into the memory storage from a host, a FLASH (a kind of nonvolatile memory), an EMMC (Embedded MultiMedia Card, embedded multimedia card) or an SD (Secure Digital, secure digital) card controller.

[0072] 205. Loading the second starting firmware into the memory storage by the MCU, and configuring the address of the second starting firmware in the memory storage as a second starting address corresponding to the second processor core.

[0073] The second starting address is the starting address set by the MCU for the second processor core, and the first starting address is different from the second starting address.

[0074] In addition, the MCU can load the second boot firmware into the memory storage from the host, the FLASH, the EMMC or the SD card controller.

[0075] Optionally, the MCU can pre-configure a first address in the memory storage for loading the first boot firmware and a second address in the memory storage for loading the second boot firmware, so as to load the first boot firmware into the first address designated by the memory storage and load the second boot firmware into the second address designated by the memory storage. Then, the first address is configured as the first boot address corresponding to the first processor core, and the second address is configured as the second boot address corresponding to the second processor core.

[0076] For example, Figure 3 is a flowchart of another boot method of a heterogeneous chip provided by an embodiment of the present application, referring to Figure 3 , steps 203-205 are executed before steps 201-202. After the first boot firmware corresponding to the first processor core and the second boot firmware corresponding to the second processor core and the first boot address and the second boot address are configured by the MCU, the first processor core and the second processor core run the respective boot firmware.

[0077] Figure 3 In another embodiment, step 204 can also be executed after step 205 or in parallel with step 205, which is not limited in the embodiments of the present application.

[0078] In a possible implementation manner, the MCU runs in a 32-bit core in the heterogeneous chip, the MCU includes an internal memory, the internal memory stores a MCU firmware, the MCU firmware is the boot firmware required by the MCU to run, and the MCU loads the MCU firmware from an external memory into the internal memory and runs the MCU firmware by the MCU. The internal memory can be an IRAM (Internal Random Access Memory, internal random access memory) or other types of memories, which are not limited in the embodiments of the present application. In the process of running the MCU firmware, the MCU can execute steps 203-205 according to the indication of the MCU firmware, so as to realize the configuration of the first boot address and the second boot address.

[0079] In addition, in addition to the initialization of the memory storage, the loading of the first boot firmware and the second boot firmware, and the configuration of the first boot address and the second boot address, other operations can also be executed by the MCU, for example, the operation of initializing a PCIE (Peripheral Component Interconnect Express, fast peripheral component interconnection standard) interface, and the like, which are not limited in the embodiments of the present application.

[0080] In the related art, for a chip containing only one type of processor core, a ROMCODE is developed for the processor core, the ROMCODE being a piece of code fixed in a ROM (Read-Only Memory) inside the chip by a processor manufacturer, and the chip needs to run the ROMCODE and load a startup firmware according to the instruction of the ROMCODE to implement a startup process. However, for a heterogeneous chip containing two types of processor cores, if a ROMCODE is developed for each type of processor core, a large amount of work is caused and the maintenance cost is high.

[0081] Therefore, in the embodiments of the present application, the ROMCODE can also be fixed in the MCU, the ROMCODE in the MCU is started to load the MCU firmware into the internal memory, and then the MCU firmware is run to load the first startup firmware and the second startup firmware according to the instruction of the MCU firmware, which implements dynamic loading of the startup firmware, and the first startup firmware acts as the ROMCODE of the first processor core, and the second startup firmware acts as the ROMCODE of the second processor core, which can be applied to various business scenarios, is more flexible, avoids the development complexity caused by fixing the first startup firmware and the second startup firmware as the ROMCODE of the processor core, and can effectively shorten the development cycle.

[0082] In the embodiments of the present application, the first startup firmware and the second startup firmware are loaded into the internal memory by the MCU, and the addresses of the first startup firmware and the second startup firmware are configured as the first startup address and the second startup address corresponding to the first processor core, respectively, without the need for the first processor core and the second processor core to load the startup firmware or configure the startup address, and without the need for the first processor core and the second processor core to operate the internal memory, which avoids the conflict caused by the operation of the internal memory by the first processor core and the second processor core, and improves the flexibility.

[0083] On the basis of the above embodiments, the functions of the first startup firmware and the second startup firmware are described as follows in the embodiments of the present application.

[0084] The startup phase of the first processor core includes multiple phases, and the first startup firmware is the firmware of the first startup phase of the first processor core. Similarly, the startup phase of the second processor core includes multiple phases, and the second startup firmware is the firmware of the first startup phase of the second processor core.

[0085] In the embodiments of the present application, the first boot stage is referred to as an SBL0 stage, the firmware of the SBL0 stage is referred to as SBL0 firmware, the first boot firmware is first SBL0 firmware, and the second boot firmware is second SBL0 firmware. The SBL0 firmware includes assembly boot code, code for initializing peripheral function modules, and code for loading firmware of a next boot stage, and functions of the SBL0 firmware include processor core booting, peripheral function module initializing, and firmware loading of a next boot stage.

[0086] Optionally, step 201 includes:

[0087] 2011. Running, by the first processor core, the first boot firmware stored at the first boot address to perform the following operations:

[0088] 1. Initializing peripheral function modules indicated by the first boot firmware.

[0089] The peripheral function modules indicated by the first boot firmware to be initialized can include one or more.

[0090] Optionally, the peripheral function modules indicated by the first boot firmware and the second boot firmware to be initialized are different, so as to avoid conflicts caused by repeated initialization of the same peripheral function modules by the first processor core and the second processor core.

[0091] 2. Loading firmware of a next boot stage.

[0092] For example, the firmware of the next boot stage is loaded from a host or a memory such as a FLASH to a specified location in DDR by the first processor core, so that the firmware of the next boot stage can be run subsequently.

[0093] 3. Verifying the firmware of the next boot stage, and loading the firmware of the next boot stage into a memory after verification.

[0094] Optionally, the verification process includes obtaining version information of the firmware of the next boot stage, and performing integrity verification on the firmware of the next stage based on the version information.

[0095] 4. Setting parameters required by the firmware of the next boot stage, and storing the parameters in a register, so that the required parameters can be read from the register when the firmware of the next boot stage is run subsequently.

[0096] 5. Jumping to run the firmware of the next boot stage, so as to enter the next boot stage.

[0097] Optionally, initializing the peripheral function modules indicated by the first boot firmware includes: initializing cache space and working mode of the cache space, closing the MMU (Memory Management Unit), initializing the PMA (Physical Memory Attributes) and the PMP (Physical Memory Attributes), initializing the GPIO (General-Purpose Input / Output) and the UART, and selecting the initialization of the FLASH, the EMMC or the SD card controller based on the level signal of the GPIO. And loading the firmware of the next boot stage includes: loading the firmware of the next boot stage from the FLASH, the EMMC or the SD card controller based on the level signal of the GPIO. The level signal of the GPIO can be used to determine whether the firmware of the next boot stage is loaded from the FLASH, the EMMC or the SD card controller.

[0098] Optionally, the step 202 includes:

[0099] 2021. Running the second boot firmware stored at the second boot address by the second processor core to perform the following operations:

[0100] 1. Initializing the peripheral function modules indicated by the second boot firmware.

[0101] The peripheral function modules indicated by the second boot firmware to be initialized can include one or more of the following:

[0102] 2. Loading the firmware of the next boot stage.

[0103] For example, the firmware of the next boot stage is loaded from a host or a memory such as a FLASH to a specified location in the DDR by the second processor core, so that the firmware of the next boot stage can be run subsequently.

[0104] 3. Verifying the firmware of the next boot stage, and loading the firmware of the next boot stage into the memory after the verification is passed.

[0105] Optionally, the verification process includes: obtaining version information of the firmware of the next boot stage, and performing integrity verification on the firmware of the next stage based on the version information.

[0106] 4. Setting parameters required by the firmware of the next boot stage, and storing the parameters in a register, so that the required parameters can be read from the register when the firmware of the next boot stage is run subsequently.

[0107] 5. Jump to run the firmware of the next start stage, so as to enter the next start stage.

[0108] The initializing the peripheral function module indicated by the second start firmware includes initializing the cache space and the working mode of the cache space, closing the MMU, initializing the GPIO and the UART, selecting the initialization of the FLASH, the EMMC or the SD card controller based on the level signal of the GPIO. The loading the firmware of the next start stage includes loading the firmware of the next start stage from the FLASH, the EMMC or the SD card controller based on the level signal of the GPIO. The level signal of the GPIO can be used to determine whether the firmware of the next start stage is loaded from the FLASH, the EMMC or the SD card controller.

[0109] In the embodiment of the application, only one set of universal start firmware needs to be developed, and then the first start firmware supporting the RISC-V architecture and the second start firmware supporting the ARM architecture are compiled, and the first start firmware and the second start firmware are respectively run by the first processor core and the second processor core, so that the necessary functions of processor core start, initializing peripheral function module and loading the firmware of the next start stage can be realized, and the developer does not need to develop two sets of start firmware for the processor core of the RISC-V architecture and the processor core of the ARM architecture, thereby saving the workload, effectively reducing the development cost, the transplantation difficulty and the maintenance cost of the start firmware, and also reducing the research and development period and the research and development difficulty of the heterogeneous chip.

[0110] On the basis of the above embodiment, the start process of the first processor core and the second processor core includes multiple start stages, and the start process of the first processor core and the second processor core includes a UEFI stage.

[0111] The first UEFI firmware is the firmware of the UEFI stage of the first processor core;

[0112] The second UEFI firmware is the firmware of the UEFI stage of the second processor core;

[0113] The first UEFI firmware and the second UEFI firmware are different firmware obtained by cross-compiling the same UEFI start firmware, and the first UEFI firmware supports the RISC-V architecture and the second UEFI firmware supports the ARM architecture.

[0114] The embodiments of the present application only need to develop a general UEFI firmware, and then compile the general UEFI firmware into a first UEFI firmware supporting the RISC-V architecture and a second UEFI firmware supporting the ARM architecture, so as to realize the UEFI stage of the first processor core and the second processor core, without the need for the developer to separately develop two sets of UEFI firmware for the processor core of the RISC-V architecture and the processor core of the ARM architecture, thereby saving the workload, effectively reducing the development cost, the porting difficulty and the maintenance cost of the UEFI firmware, and also reducing the research and development period and the research and development difficulty of the heterogeneous chip.

[0115] Optionally, the first UEFI firmware and the second UEFI firmware contain the same functions, and only the supported architectures are different. Alternatively, the first UEFI firmware and the second UEFI firmware contain part of the same functions, and the supported architectures are different. The embodiments of the present application do not limit the difference between the first UEFI firmware and the second UEFI firmware.

[0116] Optionally, Figure 4 is a schematic diagram of each startup stage in a startup process of a first processor core provided by an embodiment of the present application, referring to Figure 4 The startup process of the first processor core of the RISC-V architecture includes an MCU stage, an SBL0 stage, a UEFI stage, a Linux stage and a System stage, and correspondingly, the startup firmware running in the startup process includes an MCU firmware, a first SBL0 firmware, a first UEFI firmware, a Linux firmware and a System firmware.

[0117] Optionally, Figure 5 is a schematic diagram of each startup stage in a startup process of a second processor core provided by an embodiment of the present application, referring to Figure 5 The startup process of the second processor core of the ARM architecture includes an MCU stage, an SBL0 stage, an ATF stage, a UEFI stage, a Linux stage and a System stage, and correspondingly, the startup firmware running in the startup process includes an MCU firmware, a second SBL0 firmware, an ATF firmware, a second UEFI firmware, a Linux firmware and a System firmware.

[0118] The Linux firmware is obtained by adapting the open source Linux kernel, and the System can be various types of systems, which are not limited by the embodiments of the present application.

[0119] Optionally, the first startup firmware is firmware of a first startup stage of the first processor core, and a second startup stage of the first processor core is a UEFI stage. The second startup firmware is firmware of a first startup stage of the second processor core, and a second startup stage of the second processor core is an ATF stage, wherein a BL33 sub-stage in the ATF stage is a UEFI stage.

[0120] After the UEFI stage, the startup process of the first processor core can further include one or more other stages, which are not limited by embodiments of the present application. After the UEFI stage, the startup process of the second processor core can further include one or more other stages, which are not limited by embodiments of the present application.

[0121] For example, Figure 6 is a schematic diagram of a SBL0 stage and an ATF stage of a second processor core provided by an embodiment of the present application, referring to Figure 6 , the first startup stage of the second processor core is a SBL0 stage, and the second startup stage is an ATF stage, the ATF stage includes sub-stages such as BL1, BL2, BL31 and BL33. In embodiments of the present application, the firmware of the BL33 sub-stage is set as the second UEFI firmware, that is, it is ensured that the second UEFI firmware will run in the BL33 sub-stage, thereby achieving the effect of configuring the BL33 sub-stage as a UEFI stage.

[0122] In embodiments of the present application, the BL33 sub-stage in the ATF stage is configured as a UEFI stage, so that UEFI firmware can run in this stage without the need to separately increase the UEFI stage, thereby simplifying the startup process, saving the workload in the startup process, and thus saving the startup time.

[0123] The heterogeneous chip includes various peripheral function modules, and in the startup process of the heterogeneous chip, each processor core initializes the peripheral function modules.

[0124] In the related art, because the processor core of the RISC-V architecture and the processor core of the ARM architecture use different startup firmware and adopt independent startup modes, it is likely that the same peripheral function modules will be initialized in the startup process, resulting in system errors and the need to restart. In addition, the difference between the two startup modes increases, and the startup times of the two processor cores are inconsistent. If a processor core needs to be restarted due to a system error, it will cause the overall startup time to be too long.

[0125] In the embodiment of the present application, the UEFI firmware is compiled based on EDK2 code, EDK2 is a UEFI-based software development kit, which provides a standard framework for UEFI programming and supports the development of UEFI software on different architectures. A driver loading management module is added to the UEFI firmware, which is used to realize the dynamic loading of the driver program of the peripheral function module, thereby avoiding the repeated initialization of the same peripheral function module by different processor cores, avoiding conflicts and system abnormalities, reducing the probability of startup errors, and shortening the startup time. Moreover, the iteration is convenient and the maintenance cost is reduced. The UEFI firmware with the added driver loading management module is suitable for different architecture processor cores and has a wide application range. It is not necessary to repeatedly develop UEFI firmware for each architecture processor core. Compared with U-Boot, the performance of UEFI firmware is better. Using UEFI firmware in the startup process can simplify the operation process and improve stability.

[0126] Optionally, the heterogeneous chip further comprises a plurality of peripheral function modules, Figure 7 is a flowchart of a method for initializing a peripheral function module provided by the embodiment of the present application, referring to Figure 7 The method further comprises:

[0127] 701. By the first processor core, running the first UEFI firmware to load the first driver program, and initializing the first peripheral function module based on the first driver program.

[0128] In the UEFI phase, the first processor core will run the first UEFI firmware. During the running process, the first driver program will be loaded according to the indication of the first UEFI firmware, so as to initialize the first peripheral function module corresponding to the first driver program.

[0129] 702. By the second processor core, running the second UEFI firmware to load the second driver program, and initializing the second peripheral function module based on the second driver program.

[0130] Wherein, the first peripheral function module and the second peripheral function module are different peripheral function modules.

[0131] In the UEFI phase, the second processor core will run the second UEFI firmware. During the running process, the second driver program will be loaded according to the indication of the second UEFI firmware, so as to initialize the second peripheral function module corresponding to the second driver program.

[0132] The driving loading management module is added in the first UEFI firmware and the second UEFI firmware, and is used for realizing dynamic loading of the driving program of the peripheral function module. In the process of running the first UEFI firmware and the second UEFI firmware, the driving program of the peripheral function module can be loaded through the driving loading management module, and then the corresponding peripheral function module is initialized. In addition, the driving loading management module in the first UEFI firmware and the second UEFI firmware can obtain the driving program to be loaded from the specified shared memory according to the configuration, so as to initialize the respective peripheral function modules, thereby ensuring that the first peripheral function module and the second peripheral function module are different peripheral function modules, so as to avoid the case of repeated initialization of the same peripheral function module.

[0133] The embodiment of the present application has the following advantages. Figure 7 In another embodiment, step 701 can also be executed after step 702 or in parallel with step 702, and the present embodiment does not limit this.

[0134] Optionally, the UEFI firmware supports the user to divide the peripheral function modules through the UEFI interface, so as to determine the peripheral function module to be initialized by each processor core. In this case, step 701 includes:

[0135] The first UEFI firmware is run through the first processor core to display the UEFI interface, the first peripheral function module and the second peripheral function module are determined from the plurality of peripheral function modules provided by the UEFI interface, the first driving program corresponding to the first peripheral function module is loaded, the first peripheral function module is initialized based on the first driving program, and the configuration parameter is determined, which is used to indicate the first peripheral function module and the second peripheral function module.

[0136] Step 702 includes: the second UEFI firmware is run through the second processor core to determine the second peripheral function module based on the configuration parameter, load the second driving program corresponding to the second peripheral function module, and initialize the second peripheral function module based on the second driving program.

[0137] Optionally, the plurality of peripheral function modules to be initialized are displayed in the UEFI interface, the user selects the first peripheral function module in the UEFI interface, and then the remaining unselected peripheral function modules are automatically determined as the second peripheral function module.

[0138] After the user divides the first peripheral function module and the second peripheral function module, the configuration parameters can be recorded, so that the first peripheral function module and the second peripheral function module can be determined based on the configuration parameters. Therefore, after the first processor core determines the configuration parameters, the second processor core only needs to read the configuration parameters to determine the second peripheral function module and then initialize the second peripheral function module.

[0139] Optionally, the configuration parameters are created in the FLASH, and the first peripheral function module and the second peripheral function module are recorded in the configuration parameters.

[0140] In this way, the first peripheral function module and the second peripheral function module are divided through the UEFI interface, which can intuitively present multiple peripheral function modules to the user, effectively and accurately determine the peripheral function modules that need to be initialized by different processor cores through human-computer interaction with the user, avoid system errors caused by repeated initialization of the same peripheral function module, save the startup time, and realize dynamic selection of the peripheral function module and improve the flexibility.

[0141] Optionally, the different first peripheral function modules and the second peripheral function modules can also be pre-configured, and the processor core can determine which peripheral function module needs to be initialized by reading the configuration. In this case, step 701 comprises: running the first UEFI firmware by the first processor core to read the configured first peripheral function module, loading the first driver corresponding to the first peripheral function module, and initializing the first peripheral function module based on the first driver.

[0142] For example, the first peripheral function module is configured in the FLASH, and the first processor running the first UEFI firmware reads the configured first peripheral function module from the FLASH, thereby loading the first driver corresponding to the first peripheral function module and initializing the first peripheral function module.

[0143] Step 702 comprises: running the second UEFI firmware by the second processor core to read the configured second peripheral function module, loading the second driver corresponding to the second peripheral function module, and initializing the second peripheral function module based on the second driver.

[0144] For example, the second peripheral function module is configured in the FLASH, and the second processor running the second UEFI firmware reads the configured second peripheral function module from the FLASH, thereby loading the second driver corresponding to the second peripheral function module and initializing the second peripheral function module.

[0145] Optionally, the first peripheral function module and the second peripheral function module can be configured in the FLASH by default by the technician, or a UEFI interface can be displayed, the first peripheral function module and the second peripheral function module are determined from a plurality of peripheral function modules provided by the UEFI interface, and the first peripheral function module and the second peripheral function module are configured in the FLASH, so that the configured first peripheral function module or second peripheral function module can be read from the FLASH at the next start-up.

[0146] The preconfigured first peripheral function module and second peripheral function module can ensure that only reading configuration is needed in the start-up process to effectively and accurately determine the peripheral function modules that need to be initialized by different processor cores, improve the operation efficiency, avoid system errors caused by repeated initialization of the same peripheral function module, save the start-up time, and realize dynamic selection of the peripheral function module and improve the flexibility.

[0147] Optionally, the two ways of configuring the first peripheral function module and the second peripheral function module can be combined. For example, the configuration parameters are pre-stored in the FLASH, the configuration parameters include the preconfigured first peripheral function module and second peripheral function module, and the configuration control is displayed in the process of running the first UEFI firmware by the first processor core. If the user selects the configuration control within a target time, it indicates that the user wants to determine the first peripheral function module and the second peripheral function module by himself / herself, and therefore the UEFI interface is displayed for the user to select from a plurality of peripheral function modules. After the user determines the first peripheral function module and the second peripheral function module, the configuration parameters are updated to match the first peripheral function module and the second peripheral function module determined by the user. Alternatively, if the user does not select the configuration control within the target time, it indicates that the user does not need to determine the first peripheral function module and the second peripheral function module by himself / herself, and therefore the configuration control is cancelled and the first peripheral function module and the second peripheral function module in the configuration parameters are read.

[0148] Optionally, the UEFI phase includes a SEC (Security Phase) phase, a PEI (Pre-EFI Initialization) phase, a DXE (Driver EXecution Environment) phase, a BDS (Boot Device Select) phase, and a RT (Run Time) phase, etc. In the UEFI phase of the first processor core, the SEC phase is run until the RT phase. In the second processor core, since the firmware of the ATF phase has been run in advance, the SEC phase is no longer needed to run repeatedly for security verification in the UEFI phase, and thus the PEI phase is run until the RT phase.

[0149] In the DXE phase of the first processor core and the second processor core, the driver loading management module is added, so that the division of the first peripheral function module and the second peripheral function module can be implemented in the DXE phase.

[0150] On the basis of the above embodiment, an embodiment of the present application further provides a system on chip (SOC), which refers to an integrated circuit with a dedicated target, and contains a complete system and all contents of embedded software.

[0151] The system on chip includes the heterogeneous chip in the above embodiment.

[0152] Optionally, the system on chip can further include other function modules in addition to the above heterogeneous chip, and the embodiment of the present application does not limit this.

[0153] On the basis of the above embodiment, an embodiment of the present application further provides a computer device, which includes the heterogeneous chip in the above embodiment.

[0154] Optionally, the computer device is a terminal or a server, and the type of the computer device is not limited in the embodiment of the present application.

[0155] Figure 8 A structure schematic diagram of a terminal 800 provided by an example embodiment of the present application is shown. The terminal can be the computer device in the above embodiment.

[0156] The terminal 800 includes a processor 801 and a memory 802.

[0157] The processor 801 can include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 801 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field Programmable Gate Array), a PLA (Programmable Logic Array). The processor 801 can also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also known as a CPU (Central Processing Unit), and the coprocessor being a low-power processor for processing data in a standby state. In some embodiments, the processor 801 can be integrated with a GPU (Graphics Processing Unit) for rendering and drawing content required to be displayed by the display screen. In some embodiments, the processor 801 can further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.

[0158] The memory 802 can include one or more computer-readable storage media that can be non-transitory. The memory 802 can also include a high-speed random access memory, and a nonvolatile memory such as one or more disk storage devices, flash storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 802 is used to store at least one computer program for being executed by the processor 801 to implement the determination method of the width combination provided by the method embodiments in the present application.

[0159] In some embodiments, the terminal 800 can also optionally include a peripheral device interface 803 and at least one peripheral device. The processor 801, the memory 802, and the peripheral device interface 803 can be connected through a bus or a signal line. Each peripheral device can be connected to the peripheral device interface 803 through a bus, a signal line, or a circuit board. Optionally, the peripheral device includes at least one of a radio frequency circuit 804, a display screen 805, a camera assembly 806, and a power supply 807.

[0160] The peripheral device interface 803 can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 801 and the memory 802.

[0161] The radio frequency circuit 804 is used for receiving and transmitting RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 804 communicates with communication networks and other communication devices through electromagnetic signals. The radio frequency circuit 804 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals.

[0162] The display screen 805 is used for displaying a UI (User Interface). The UI can include graphics, text, icons, video, and any combination thereof. When the display screen 805 is a touch display screen, the display screen 805 also has the ability to collect touch signals on or above the surface of the display screen 805.

[0163] The camera assembly 806 is used for collecting images or videos. Optionally, the camera assembly 806 includes a front camera and a rear camera. The front camera is arranged on the front panel of the terminal 800, and the rear camera is arranged on the back of the terminal 800.

[0164] The power supply 807 is used for supplying power to various components in the terminal 800. The power supply 807 can be alternating current, direct current, disposable batteries, or rechargeable batteries.

[0165] Those skilled in the art can understand that the structure shown in the above embodiment is not a limitation on the terminal 800, and the terminal 800 can include more or fewer components than those shown in the figure, or combine certain components, or use different component arrangements. Figure 8

[0166] Figure 9 FIG. 9 is a structural schematic diagram of a server provided by an embodiment of the present application. The server 900 can be different in configuration or performance, and can include one or more processors (CPU) 901 and one or more memories 902. The memory 902 stores at least one computer program, which is loaded and executed by the processor 901 to implement the method provided by each method embodiment described above. Of course, the server can also have a wired or wireless network interface, a keyboard, an input and output interface, and other components for realizing the functions of the device, and will not be described here.

[0167] The embodiment of the present application further provides a computer readable storage medium, which stores at least one computer program. The at least one computer program is loaded and executed by a processor to implement the operations performed by the starting method of the heterogeneous chip in the above embodiment. ​

[0168] The embodiment of the present application further provides a computer program product comprising a computer program, which is loaded and executed by a processor to implement the operations performed by the starting method of the heterogeneous chip in the above embodiment.

[0169] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or can be instructed by a program to complete the related hardware, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0170] The above description is only optional embodiments of the present application, and does not limit the embodiments of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the embodiments of the present application shall be included in the protection scope of the present application.

Claims

1. A method of starting a heterogeneous chip, the method comprising: The heterogeneous chip comprises a first processor core and a second processor core, the first processor core is a processor core of RISC-V architecture, and the second processor core is a processor core of ARM architecture. The method comprises: running, by the first processor core, first start firmware stored at a first start address; running, by the second processor core, second start firmware stored at a second start address; The first start firmware and the second start firmware are different firmware obtained by cross-compiling the same start firmware, and the first start firmware supports RISC-V architecture, and the second start firmware supports ARM architecture. The start process of the first processor core and the second processor core comprises a unified extensible firmware interface (UEFI) stage; The first UEFI firmware is the firmware of the UEFI stage of the first processor core; The second UEFI firmware is the firmware of the UEFI stage of the second processor core; The first UEFI firmware and the second UEFI firmware are different firmware obtained by cross-compiling the same UEFI start firmware, and the first UEFI firmware supports RISC-V architecture, and the second UEFI firmware supports ARM architecture; The heterogeneous chip further comprises a micro control unit (MCU) and a memory storage, and the method further comprises: resetting, by the MCU, the first processor core and the second processor core, and initializing the memory storage; loading, by the MCU, the first start firmware into the memory storage, and configuring the address of the first start firmware in the memory storage as the first start address corresponding to the first processor core; loading, by the MCU, the second start firmware into the memory storage, and configuring the address of the second start firmware in the memory storage as the second start address corresponding to the second processor core.

2. The method of claim 1, wherein, The MCU comprises an internal memory, and the method further comprises: loading, by the MCU, MCU firmware from an external memory into the internal memory, and running the MCU firmware.

3. The method of claim 1, wherein, The first start firmware is the firmware of the first start stage of the first processor core, and the running, by the first processor core, of the first start firmware stored at the first start address comprises: running, by the first processor core, the first start firmware stored at the first start address to perform the following operations: initializing a peripheral function module indicated by the first start firmware; loading firmware of a next start stage; verifying the firmware of the next start stage, and after verification, loading the firmware of the next start stage into the memory storage; setting parameters required by the firmware of the next start stage, and storing the parameters in a register; jumping to run the firmware of the next start stage.

4. The method of claim 3, wherein, The initializing the peripheral function module indicated by the first start firmware comprises: initializing cache space and a working mode of the cache space; closing a memory management unit (MMU); initialize physical memory attribute (PMA) and physical memory protection (PMP); initialize general purpose input / output (GPIO) and universal asynchronous receiver / transmitter (UART); select to initialize a FLASH, an embedded multi-media card (EMMC) or an SD card controller based on a level signal of the GPIO; the loading of the firmware of the next boot stage includes: loading the firmware of the next boot stage from the FLASH, the EMMC or the SD card controller based on the level signal of the GPIO.

5. The method of claim 1, wherein, the second boot firmware is a firmware of a first boot stage of the second processor core, and the running of the second boot firmware stored at the second boot address by the second processor core includes: the running of the second boot firmware stored at the second boot address by the second processor core to perform the following operations: initializing a peripheral function module indicated by the second boot firmware; loading a firmware of a next boot stage; verifying the firmware of the next boot stage, and loading the firmware of the next boot stage into the memory storage after the verification is passed; setting a parameter required by the firmware of the next boot stage, and storing the parameter in a register; jumping to run the firmware of the next boot stage.

6. The method of claim 5, wherein, the initializing of the peripheral function module indicated by the second boot firmware includes: initializing a cache space and a working mode of the cache space; turning off a memory management unit (MMU); initializing a general purpose input / output (GPIO) and a universal asynchronous receiver / transmitter (UART); selecting to initialize a FLASH, an embedded multi-media card (EMMC) or an SD card controller based on a level signal of the GPIO; the loading of the firmware of the next boot stage includes: loading the firmware of the next boot stage from the FLASH, the EMMC or the SD card controller based on the level signal of the GPIO.

7. The method of claim 1, wherein: the first boot firmware is a firmware of a first boot stage of the first processor core, and a second boot stage of the first processor core is the UEFI stage; the second boot firmware is a firmware of a first boot stage of the second processor core, and a second boot stage of the second processor core is an ATF stage, wherein a BL33 sub-stage in the ATF stage is the UEFI stage.

8. The method of claim 1, wherein, the heterogeneous chip further includes a plurality of peripheral function modules, and the method further includes: running the first UEFI firmware by the first processor core to load a first driver program and initialize a first peripheral function module based on the first driver program; running the second UEFI firmware by the second processor core to load a second driver program and initialize a second peripheral function module based on the second driver program; wherein the first peripheral function module and the second peripheral function module are different peripheral function modules.

9. The method of claim 8, wherein, The first processor core is configured to run the first UEFI firmware to load a first driver and initialize a first peripheral function module based on the first driver, including: The first processor core is configured to run the first UEFI firmware to display a UEFI interface, determine the first peripheral function module and the second peripheral function module from a plurality of peripheral function modules provided by the UEFI interface, load the first driver corresponding to the first peripheral function module, and initialize the first peripheral function module based on the first driver; configuration parameters are determined, and the configuration parameters are used to indicate the first peripheral function module and the second peripheral function module; The second processor core is configured to run the second UEFI firmware to load a second driver and initialize a second peripheral function module based on the second driver, including: The second processor core is configured to run the second UEFI firmware to determine the second peripheral function module based on the configuration parameters, load the second driver corresponding to the second peripheral function module, and initialize the second peripheral function module based on the second driver.

10. The method of claim 8, wherein, The first processor core is configured to run the first UEFI firmware to load a first driver and initialize a first peripheral function module based on the first driver, including: The first processor core is configured to run the first UEFI firmware to read the first peripheral function module configured, load the first driver corresponding to the first peripheral function module, and initialize the first peripheral function module based on the first driver; The second processor core is configured to run the second UEFI firmware to load a second driver and initialize a second peripheral function module based on the second driver, including: The second processor core is configured to run the second UEFI firmware to read the second peripheral function module configured, load the second driver corresponding to the second peripheral function module, and initialize the second peripheral function module based on the second driver.

11. A heterogeneous chip, comprising: The heterogeneous chip includes a first processor core and a second processor core; the first processor core is a RISC-V architecture processor core, and the second processor core is an ARM architecture processor core; The first processor core is configured to run a first start firmware stored at a first start address; The second processor core is configured to run a second start firmware stored at a second start address; The first start firmware and the second start firmware are different firmwares obtained by cross-compiling the same start firmware, and the first start firmware supports the RISC-V architecture, and the second start firmware supports the ARM architecture; The start process of the first processor core and the second processor core includes a unified extensible firmware interface (UEFI) stage; The first UEFI firmware is a firmware of the UEFI stage of the first processor core; The second UEFI firmware is a firmware of the UEFI stage of the second processor core; The first UEFI firmware and the second UEFI firmware are different firmware cross-compiled from the same UEFI boot firmware, and the first UEFI firmware supports a RISC-V architecture, and the second UEFI firmware supports an ARM architecture; The heterogeneous chip further includes a micro control unit (MCU) and a memory storage, and the MCU is configured to: reset the first processor core and the second processor core, and initialize the memory storage; load the first boot firmware into the memory storage, and configure an address of the first boot firmware in the memory storage as the first boot address corresponding to the first processor core; load the second boot firmware into the memory storage, and configure an address of the second boot firmware in the memory storage as the second boot address corresponding to the second processor core.

12. A system on chip, characterized by The system on chip includes the heterogeneous chip of claim 11.

13. A computer device, comprising: The computer device includes the heterogeneous chip of claim 11.

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