Decision feedback equalizer applied to dual data rate memory

Abstract

The decision feedback equalizer applied to the dual-data-rate memory comprises a sampling circuit for sampling a sampling target in even bits and odd bits, outputting even-bit data on an even-bit path, and outputting odd-bit data on an odd-bit path; and the adder and parallel-serial conversion circuit is coupled with the sampling circuit so as to receive the even-bit data and the odd-bit data and combine the even-bit data and the odd-bit data into full-rate data.

Description

Technical Field

[0001] The present invention relates to an equalizer for chip input and output, and is particularly applicable to double data rate memory (DDR). Background Art

[0002] As the central processing units (CPUs) of servers / personal computers begin to support high-speed double data rate memory (such as the fifth-generation double data rate memory DDR5, or the fifth-generation power-saving double data rate memory LPDDR5, etc., represented by DDR below), DDR has begun to be widely implemented in mobile devices. DDR is not only fast, but also has a large bandwidth, which can significantly improve system performance, but it also brings challenges to the input and output (IO) design of DDR.

[0003] The IO of DDR is usually equipped with an equalizer. Compared with traditional equalization technologies such as Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE) does not amplify signal noise and can effectively solve the signal integrity problem caused by Intersymbol Interference (ISI).

[0004] However, traditional analog DFE includes heavily loaded adders, which limits the maximum transmission rate of DDR receivers. As for traditional digital DFE, the adder circuit timing is tight, and the critical path timing is only 1UI (unit interval), which is difficult to meet with 16nm process.

[0005] Improving DFE speed is an important issue in the DDR field. Summary of the invention

[0006] The digital decision feedback equalizer (DFE) in this case is applied to double data rate memory (DDR) and has a second-order half-rate speculation function. Such a speculation function is also called loop unrolled technology.

[0007] The DFE includes an initialization circuit (including the adjustment of the read to read turn around function), a selection circuit (used for DFE order selection and even DDR mode selection), a sampling circuit, and an adder and parallel-to-serial conversion circuit. In particular, the sampling circuit is placed before the adder, which effectively buys more time for the critical timing path (for example, from 1UI to 2UI). The DDR mode selection enables the system to support multiple DDR modes (such as DDR5 or LPDDR5). In addition, this case also introduces a special control, called read to read turn around control, which can support multiple read to read switching combinations. This case also enables ordinary processes to achieve high transmission rates. For example, a 16nm process can achieve a transmission rate of 6400Mbps.

[0008] In one embodiment, the present invention implements a decision feedback equalizer (DFE) applied to a double data rate memory (DDR), including: a sampling circuit that divides the sampling target into even bits and odd bits for sampling, outputs even bit data on the even bit path, and outputs odd bit data on the odd bit path; and an adder and parallel-to-serial conversion circuit that is coupled to the aforementioned sampling circuit to receive the aforementioned even bit data and the aforementioned odd bit data, and combine them to produce full-rate data.

[0009] The following is a detailed description of the present disclosure with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A decision feedback equalizer (DFE) 100 is implemented according to an embodiment of the present invention;

[0011] Figure 2 is a block diagram illustrating functional blocks in the initialization circuit 102 according to one embodiment of the present invention;

[0012] Figure 3 The implementation details of the initialization circuit 102 are illustrated according to one embodiment of the present invention;

[0013] Figure 4 is a block diagram illustrating functional blocks of the selection circuit 104 according to one embodiment of the present invention;

[0014] Figure 5 The details of the selection circuit 104 are illustrated according to one embodiment of the present invention;

[0015] Figure 6 is a block diagram illustrating functional blocks of the sampling circuit 106 according to one embodiment of the present invention;

[0016] Figure 7 The details of the sampling circuit 106 are illustrated according to one embodiment of the present invention;

[0017] Figure 8 The implementation details of the adder and the parallel-to-serial conversion circuit 108 are illustrated according to one embodiment of the present invention; and

[0018] Fig. 9 FIG. 1 is a block diagram illustrating a double data rate memory (DDR) 900 implemented according to one embodiment of the present invention.

[0019]

Explanation of symbols

[0020] 100: Decision Feedback Equalizer

[0021] 102: Initialize circuit

[0022] 104: Select Circuit

[0023] 106: Sampling Circuit

[0024] 108: Adder and parallel-to-serial conversion circuit

[0025] 202: Enable initialization circuit

[0026] 204: Read and read switching initialization circuit

[0027] 206, 606: logic circuit combination

[0028] 208: Multitasker

[0029] 210, 212: Inverter

[0030] 214, 302, 304: D flip-flop

[0031] 216: AND Gate

[0032] 306: Asynchronous Counter

[0033] 402, 404: first and second selection sub-circuits

[0034] 602: Even-bit path sampling circuit

[0035] 604: Odd-bit path sampling circuit

[0036] 802, 804, 808: Multitasker

[0037] 806: Delay Circuit

[0038] 810, 812, 814: Buffer

[0039] 900: Double Data Rate Memory

[0040] 902: Receiver Circuit

[0041] DDRMODE: Mode selection signal

[0042] DFE0…DFE3: Sampling target

[0043] DFE_EN: DFE enable signal

[0044] CKON, CKOP, DFECLKN, DFECLKP: sampling clock

[0045] DFE_TAP1 / DFE_TAP2, TAP1 / TAP2: first-order / second-order enable signal

[0046] Even0…Even3: Even-numbered bit data

[0047] EVENOUT: Even-numbered bits, half-rate data

[0048] Init0T, InitB, InitNT: Relay signal

[0049] Initevent1, Initevent2, Initoddt2: First digit selection signal

[0050] Muxeven, Muxodd: even-bit, odd-bit multiplexer output

[0051] Muxeven_d, Muxeven_dd, Muxeven_ddN, Muxodd_d, Muxodd_dd, Muxodd_dN, Muxodd_ddN, Sel_dfemux, Sel_eyemux: signals

[0052] Odd0…Odd3: odd bit data

[0053] ODDOUT: odd bit half rate data

[0054] R2RTRUNAROUND: read and read switching signal

[0055] Sel_even1, Sel_even2: Selection signal for even-numbered bit paths

[0056] Sel_odd1, Sel_odd2: Selection signal for odd-numbered bit paths

[0057] ZI: Full rate data DETAILED DESCRIPTION

[0058] The following description lists various embodiments of the present invention to introduce the basic concepts of the present invention, and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the scope of the patent application. The various functional blocks mentioned below can be implemented by a combination of hardware, software, and firmware, and may also include special circuits. The various functional blocks are not limited to being implemented separately, but can also be combined together to share certain functions.

[0059] Figure 1 A decision feedback equalizer (DFE) 100 implemented according to one embodiment of the present invention can be used in a DDR receiver, including an initialization circuit 102, a selection circuit 104 (used for DFE order "TAP" selection, or even DDR mode selection), a sampling circuit 106, and an adder and parallel-to-serial conversion circuit 108. All circuits operate in a digital voltage power domain (DVDD power domain), and the operating voltage is lower than the activation voltage power domain (VPP power domain) of the signal received by the DDR.

[0060] The initialization circuit 102 includes four input signals DFE_EN, DFECLKP, DFECLKN, and R2RTURNAROUND, and three output signals Initevent1, Initevent2, and Initoddt2.

[0061] The signal R2RTURNAROUND is a regulation signal for the read to read turn around function, and comes from a logic circuit (not shown in the figure). When the sampling clock DFECLKP / DFECLKN is a continuous clock, the signal R2RTURNAROUND is set to 1'b0. If the read to read turn around function is enabled, the signal R2RTURNAROUND is set to 1'b1. The signal DFE_EN is a DFE enable signal, which is valid at a high level. The sampling clock DFECLKP is used for rising edge sampling. The sampling clock DFECLKN is used for falling edge sampling. The signals Initevent1, Initevent2, and Initoddt2 generated by the initialization circuit 102 are all fed into the selection circuit 104, and perform logic operations with the signals Muxeven and Muxodd to generate selection signals (Sel_even1, Sel_even2) for the even path and selection signals (Sel_odd1, Sel_odd2) for the odd path, so as to control the adder and the multiplexer in the parallel-to-serial conversion circuit 108.

[0062] As shown in the figure, the selection circuit 104 also receives 6 signals DDRMODE, DFE_EN, DFE_TAP1, DFE_TAP2, DFECLKP, and DFECLKN. The signal DDRMODE is a mode selection signal: when 1'b1, it supports the DDR5 protocol; when 1'b0, it supports the LPDDR5 protocol. The signal DFE_TAP1 is a first-order enable signal, which is valid at a high level and is used to consider the previous bit status when identifying the current bit. When the first-order DFE is not enough to save the eye pattern, the second-order enable signal DFE_TAP2 is turned to a valid high level. When identifying the current bit, the previous two bit statuses are considered, effectively solving the 1 value misjudgment caused by a long 0, or the 0 value misjudgment caused by a long 1. For example, a long 0 needs to correspond to a looser 1 value judgment, and a lower reference value is used to accurately identify the 1 value. For example, a long 1 needs to correspond to a looser 0 value judgment, and a higher reference value is used to accurately identify the 0 value.

[0063] The sampling circuit 106 includes 9 input signals (DFE0, DFE1, DFE2, DFE3, DFE_EN, DFE_TAP1, DFE_TAP2, DFECLKP, DFECLKN), and generates 8 output signals (Even0...Even3, and Odd0...Odd3). The signals DFE0...DFE3 are digital signals received and converted by the DDR, and are contents identified by different reference values ​​Vref, and are sampling targets of the sampling circuit 106. The signals DFE0 and DFE1 are used to implement a first-order DFE, and the signals DFE2 and DFE3 are used to implement a second-order DFE. The signals DFE0 and DFE2 are sampled by the sampling clock DFECLKP, and output even-bit data Even0...Even3 (corresponding to data 0, 2, 4, 6...). The signals DFE1 and DFE3 are sampled by the sampling clock DFECLKN, and output odd-bit data Odd0...Odd3 (corresponding to data 1, 3, 5, 7...).

[0064] First, the first-order DFE is discussed. When the signal DFE_EN = 1'b1, DFE_TAP2 = 1'b0, and DFE_TAP1 = 1'b1, the DFE is only opened in one order, and the sampling circuit 106 samples and obtains the even-bit data Even0 and Even1, and the odd-bit data Odd0 and Odd1. In this way, the odd-bit and even-bit splitting will realize the half-rate serial-to-parallel conversion. The even-bit data Even0 and Even1 and the odd-bit data Odd0 and Odd1 are separated into the even-bit path and the odd-bit path.

[0065] When switching to the second-order DFE, DFE_EN = 1'b1, DFE_TAP2 = 1'b1, and DFE_TAP1 = 1'bx. The sampling circuit 106 samples the even-bit data Even0...Even3 and the odd-bit data Odd0...Odd3. By implementing half-rate serial-to-parallel conversion, the even-bit data Even0...Even3 and the odd-bit data Odd0...Odd3 are separated into the even-bit path and the odd-bit path.

[0066] The even-bit data and the odd-bit data are sent to the adder and parallel-to-serial conversion circuit 108 for further processing.

[0067] In addition to receiving the sampling clocks DFECLKP and DFECLKN, the adder and parallel-to-serial conversion circuit 108 also receives even-bit data Even0...Even3, odd-bit data Odd0...Odd3, even-bit path selection signals Sel_even1 and Sel_even2, and odd-bit path selection signals Sel_odd1 and Sel_odd2. In addition to selecting data, the adder and parallel-to-serial conversion circuit 108 also implements parallel-to-serial conversion (two-to-one) of the output data, and pads the sampling clocks DFECLKP / DFECLKN into a buffer before outputting. The final output signal includes not only even-bit half-rate data EVENOUT and odd-bit half-rate data ODDOUT, but also full-rate data ZI and sampling clocks CKOP / CKON. The sampling clock CKOP corresponds to the even-bit half-rate data EVENOUT. The sampling clock CKON corresponds to the odd-bit half-rate data ODDOUT.

[0068] The initialization circuit 102 generates the first bit selection signals Initevent1, Initevent2, and Initoddt2 for the even bit paths and the odd bit paths in different circuit states (eg, power-on, enable switching, or read-and-read switching) according to its four input signals DFE_EN, DFECLKP, DFECLKN, and R2RTURNAROUND.

[0069] The selection circuit 104 performs a logic operation on each input signal to obtain selection signals (Sel_even1, Sel_even2) for even-numbered bit paths and selection signals (Sel_odd1, Sel_odd2) for odd-numbered bit paths. The selection signals Sel_even1, Sel_odd1 correspond to the first-order DFE. The selection signals Sel_even1, Sel_odd1 cooperate with Sel_even2, Sel_odd2 to select the corresponding second-order DFE.

[0070] The sampling circuit 106 samples the even bit path according to the sampling clock DFECLKP and samples the odd bit path according to the sampling clock DFECLKN. The sampling circuit 106 further determines the output signal of each sampling data channel according to the input signals DFE_TAP1 and DFE_TAP2. The sampling circuit 106 divides the even bit data and the odd bit data into the even bit path and the odd bit path.

[0071] The adder and parallel-to-serial conversion circuit 108 divides the data collected by the sampling circuit 106 into half-rate data (EVENOUT and ODDOUT) and full-rate data ZI according to the output of the selection circuit 104 and the sampling clocks DFECLKP and DFECLKN.

[0072] Since the sampling circuit 106 collects the even-bit data and the odd-bit data separately in the even-bit path and the odd-bit path, and transmits them to the adder and parallel-to-serial conversion circuit 108 for logic operation, half-rate data collection can be achieved, increasing the path timing of the circuit from 1 unit time (1UI) to 2UI.

[0073] In the sampling circuit 106, the sampling clock of the even-numbered bit channel is DFECLKP, and the sampling clock of the odd-numbered bit channel is DFECLKN. The inputs DFE_TAP1 and DFE_TAP2 are the DFE first-order and second-order enable signals, respectively, which will determine which channels the sampled data is output on.

[0074] Figure 2 2 is a block diagram illustrating functional blocks in the initialization circuit 102 according to one embodiment of the present invention, including an enable initialization circuit 202 , a read and read switching initialization circuit 204 , and a logic circuit combination 206 .

[0075] Taking DDR5 as an example, the initialization circuit 102 has two working conditions.

[0076] In the first working state, the circuit is powered on, or the signal DFE_EN switches from 1'b0 to 1'b1. During a read process, the input R2RTRUNAROUND = 1'b0, enabling the initialization circuit 202 to output a pulse signal Init0T with a cycle width (1T) of 0 value, which is inverted by inverters 210 and 212 after being handed over by the multiplexer 208 to become signals Initevent2 and Initevent1, which are used as the selection signal for the first bit data0 of the even-bit path (1st order / 2nd order multiplexing). The D flip-flop 214 further samples the signal Init0T according to the sampling clock DFECLKN, delays 1UI, and inverts it at the output end The signal Initoddt2 is used as a selection signal for the first bit data (data1) of the odd-numbered bit path (applied only to the second order).

[0077] The second working state is that after power-on, the signal DFE_EN = 1'b1. At this time, the enable initialization circuit 202 is enabled to make the signal Inti0T always output 1. If there is a read-to-read transition, the logic controller will make the signal R2RTRUNAROUND generate a pulse with a length of N time periods (NT, 6 < N < 12). Correspondingly, the relay signal InitNT generated by the read-to-read transition initialization circuit 204 outputs a zero-valued pulse with a width of 1 time period in the first cycle according to the sampling clock DFECLKP. The relay signals InitNT and Init0T are subjected to an "AND" operation by the "AND" logic 216 to obtain the relay signal InitB, which is then sent to the inverters 210 and 212 through the multiplexer 208 to be inverted and become Initevent2 and Initevent1, which are used as the selection signals (1st order / 2nd order multiplexing) for the first data bit data0 of the even-bit path. The D flip-flop 214 samples the signal IntiB according to the sampling clock DFECLKN, inverts it after a delay of 1UI, and outputs it at the output end to become the signal Initoddt2, which is used as the selection signal for the first data bit (data1) of the odd-bit path (only applicable to the second order).

[0078] Figure 3 According to an embodiment of the present case, the implementation details of the initialization circuit 102 are illustrated, in which the aforementioned enable switching initialization circuit 202 is composed of two D flip-flops 302 and 304, and the aforementioned read-to-read transition initialization circuit 204 is composed of an asynchronous counter 306. The logic circuit combination 206 then implements the selection function, corresponding to power-on, enable switching, and read-to-read switching, to generate the selection signals Initevent1, Initevent2, and Initoddt2 for the first digits of the even-bit path and the odd-bit path.

[0079] As shown in the figure, the D flip-flop 302 receives the sampling clock DFECLKN in a state where the D input pin receives the signal 1'b0. The D flip-flop 304 receives the sampling clock DFECLKP in a state where the D input pin receives the Q output of the D flip-flop 302, and outputs a relay signal Init0T at a Q inverted output end The asynchronous counter 306 generates a relay signal InitNT according to the read-to-read transition signal R2RTRUNAROUND, the sampling clocks DFECLKP and DFECLKN. The logic circuit combination generates the selection signals (Initevent1, Initevent2, Initoddt2) for the first digits of the digital path and the odd-bit path according to the aforementioned relay signal Init0T, relay signal InitNT, and sampling clock DFECLKN.

[0080] As shown in the figure, the logic circuit combination 206 also includes: an AND logic, receiving the aforementioned relay signal Init0T and InitNT, generating the three relay signals InitB; a multiplexer, and a D flip-flop, wherein the multiplexer receives the aforementioned relay signal Init0T and InitB, and under the control of the inverted signal of the read and read switching signal R2RTRUNAROUND, generates an output to the D input terminal of the D flip-flop, so that the Q inverted output terminal of the D flip-flop output signal Initoddt2; and, two inverters, each inverting the output of the aforementioned multiplexer to generate signals Initevent1 and Initevent2.

[0081] Figure 4 1 is a block diagram illustrating the functional blocks of the selection circuit 104 according to one embodiment of the present invention, including a first selection subcircuit 402 and a second selection subcircuit 404. The first selection subcircuit 402 is used in the first-order DFE and includes a DDR mode (DDRMODE) selection function. The second selection subcircuit 404 is used in the second-order DFE and also includes a DDR mode (DDRMODE) selection function.

[0082] There are two DDR modes (DDRMODE): DDR5 and LPDDR5. The receiving end RX of DDR usually has an on-chip terminal (ODT) design. The on-chip terminal of DDR5 is coupled to the power supply, so the bit before the valid bit is usually high. The on-chip terminal of LPDDR5 is grounded, so the bit before the valid bit is usually low.

[0083] The signal DDRmode shows the DDR mode. DDRMODE=1'b1, indicating that DDR5 is used. DDRMODE=1'b0, indicating that LPDDR5 is used. In DDR5 mode, the signal potential of the on-chip terminal pull-up is defaulted to a high level by the initialization circuit 102, which usually lasts for one cycle. In LPDDR5 mode, the signal potential of the on-chip terminal pull-down is defaulted to a low level by the initialization circuit 102, which usually lasts for one cycle. Different DFE orders are set by signals DFE_TAP1 and DFE_TAP2; the DFE operation order is usually set according to the data rate and the quality of the propagation channel, which includes a calibration procedure. Generally, the first-order DFE operation is used first. After calibration, if the eye diagram meets the requirements, the second-order DFE operation does not need to be turned on to save power consumption. On the contrary, the second-order DFE operation is started, and the selection circuit 102 generates selection signals Sel_even1, Sel_even2, Sel_odd1, Sel_odd2 to control the adder and the parallel-to-serial conversion circuit 108, and selects appropriate signals from the signals Even0...Even3 and Odd0...Odd3, and outputs them to the even bit path and the odd bit path.

[0084] Figure 5 The details of the selection circuit 104 are illustrated according to an embodiment of the present invention. The following takes the second-order DFE of the DDR5 mode as an example to explain how the selection circuit 104 generates the selection signal.

[0085] Referring to the first selection subcircuit 402, the signals Muxeven and Muxodd are outputs of the adder and the parallel-to-serial conversion circuit 108. The signal Muxodd_d is obtained by sampling the signal Muxodd according to the sampling clock DFECLKP. After the signal Muxodd_d is added to the signal initevent1, it is multiplied by the signals DFE_TAP1 and DDRMODE to obtain the selection signal Sel_even1 for the even-numbered bit path. The signal Muxeven_d is obtained by sampling the signal Muxeven according to the sampling clock DFECLKN. After being delayed, the signal Muxeven_d is multiplied by the signals DFE_TAP1 and DDRMODE to obtain the selection signal Sel_odd1 for the odd-numbered bit path.

[0086] Referring to the second selection subcircuit 404, the signals Muxeven_d and Muxodd_d are inputted by the first selection subcircuit 402. After the signal Muxeven_d is sampled by the sampling clock DFECLKP, the signal Muxeven_dd is obtained, which is added to the signal initevent2, and then multiplied by the signal DFE_TAP2 and DDRMODE to obtain the even-bit path selection signal Sel_even2. After the signal Muxodd_d is sampled by the sampling clock DFECLKN, the signal Muxodd_dd is obtained, which is added to the signal initoddt2, and then multiplied by the signal DFE_TAP2 and DDRMODE to obtain the odd-bit path selection signal Sel_odd2.

[0087] In summary, the selection circuit 104 includes generating selection signals Sel_even1 and Sel_even2 (the first-order DFE uses Sel_even1, and the second-order DFE uses [Sel_even2, Sel_even1]) for the even-numbered bit path according to the previous odd-numbered bit data (refer to the signal Muxodd provided by the adder and the parallel-to-serial conversion circuit 108) to control the aforementioned adder and the parallel-to-serial conversion circuit 108; and the selection circuit 104 also generates selection signals Sel_odd1 and Sel_odd2 (the first-order DFE uses Sel_odd1, and the second-order DFE uses [Sel_odd2, Sel_odd1]) for the odd-numbered bit path according to the previous even-numbered bit data (refer to the signal Muxeven provided by the adder and the parallel-to-serial conversion circuit 108) to control the aforementioned adder and the parallel-to-serial conversion circuit 108.

[0088] Regarding the even-numbered bit path selection signal [Sel_even2, Sel_even1] and the odd-numbered bit path selection signal [Sel_odd2, Sel_odd1], different combinations thereof can cause the adder and the parallel-to-serial conversion circuit 108 to perform the following operations:

[0089] When 2'b00 is taken, Muxeven=Even0(Muxodd=Odd0);

[0090] When 2'b01 is taken, Muxeven=Even1(Muxodd=Odd1);

[0091] When 2'b10 is taken, Muxeven=Even2(Muxodd=Odd2);

[0092] When 2'b11 is taken, Muxeven=Even3(Muxodd=Odd3).

[0093] Figure 6 6 is a block diagram illustrating functional blocks of the sampling circuit 106 according to an embodiment of the present invention, including an even-numbered bit path sampling circuit 602, an odd-numbered bit path sampling circuit 604, and a logic circuit assembly 606 to implement serial-to-parallel half-rate conversion of data.

[0094] The even bit path sampling circuit 602 samples the even bit data (i.e., data0, data2, data4, etc.) according to the sampling clock DFECLKP. The odd bit path sampling circuit 604 samples the odd bit data (i.e., data1, data3, data5, etc.) according to the sampling clock DFECLKN. The logic circuit combination 606 is used to control the sampling output. When the signal TAP1 is valid, the sampling circuit 106 only outputs the even bit data Even0 and Even1, and the odd bit data Odd0 and Odd1. When the signal TAP2 is valid, the sampling circuit 106 outputs the even bit data Even0...Even3, and the odd bit data Odd0...Odd3.

[0095] Figure 7 The details of the sampling circuit 106 are illustrated according to an embodiment of the present invention, including eight D flip-flops and a logic circuit combination 606 for generating signals TAP1 and TAP2.

[0096] As shown in the figure, the even-bit path sampling circuit 602 includes four D flip-flops, which receive sampling targets DFE0...DFE3 respectively to generate even-bit data Even0...Even3; wherein the clearing signals of two D flip-flops are connected to the enable signal TAP1 of the first-order decision feedback equalization operation, and the clearing signals of the other two D flip-flops are connected to the enable signal TAP2 of the second-order decision feedback equalization operation. With a similar structure, the odd-bit path sampling circuit 604 includes four D flip-flops, which receive sampling targets DFE0...DFE3 respectively to generate odd-bit data Odd0...Odd3; wherein the clearing signals of two D flip-flops are connected to the enable signal TAP1 of the first-order decision feedback equalization operation, and the clearing signals of the other two D flip-flops are connected to the enable signal TAP2 of the second-order decision feedback equalization operation.

[0097] Figure 8 The implementation details of the adder and the parallel-to-serial conversion circuit 108 are illustrated according to one embodiment of the present invention.

[0098] When the first-order DFE is enabled, the signals Sel_even2 and Sel_odd2 are 0. If the previous bit is 0, the multiplexers 802 and 804 output the signals Even0 and Odd0, respectively. If the previous bit is 1, the multiplexers 802 and 804 output the signals Even1 and Odd1, respectively.

[0099] When the second-order DFE is enabled, the control of multiplexers 802 and 804 is based on the values ​​of the first two bits. The even-numbered bit path is operated according to the selection signal [Sel_even2, Sel_even1]. The odd-numbered bit path is operated according to the selection signal [Sel_odd2, Sel_odd1]. When the value is 2'b00, multiplexers 802 and 804 output signals Even0 and Odd0, respectively. When the value is 2'b01, multiplexers 802 and 804 output signals Even1 and Odd1, respectively. When the value is 2'b10, multiplexers 802 and 804 output signals Even2 and Odd2, respectively. When the value is 2'b11, multiplexers 802 and 804 output signals Even3 and Odd3, respectively.

[0100] The sampling clock DFECLKN is delayed by at least 1UI by the delay circuit 806 to form the signal Sel_dfemux to control the multiplexer 808, and the output signal Muxeven (also known as the even-bit multiplexer output) or Muxodd (also known as the odd-bit multiplexer output) is output to achieve the parallel-to-serial conversion (two-to-one) of the data, and then it is sorted into the full-rate data ZI through the buffer 810. The signal Muxeven can also be sorted into the half-rate output EVENOUT through the buffer 812. The signal Muxodd is sorted into the half-rate output ODDOUT through the buffer 814. In addition, the sampling clock DFECLKP / DFECLKN is further sorted into the sampling clock CKOP / CKON through the buffer.

[0101] Fig. 9 900 is a block diagram illustrating a double data rate memory (DDR) 900 implemented according to one embodiment of the present invention, wherein a receiver circuit 902 receives a signal and generates signals DFE0-DFE3 to be processed by the aforementioned decision feedback equalizer 100. Any electronic device in which the DDR includes a decision feedback equalizer 100 with a second-order half-rate function falls within the scope of the present invention.

[0102] Although the present invention has been disclosed as above in terms of preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this technology may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A decision feedback equalizer, applied to a dual data rate memory, comprising: a sampling circuit that samples the sampling target into even bits and odd bits, outputs even bit data on the even bit path, and outputs odd bit data on the odd bit path; and An adder and parallel-to-serial conversion circuit are coupled to the sampling circuit to receive the even-bit data and the odd-bit data and combine them to generate full-rate data.

2. The decision feedback equalizer of claim 1, wherein: The sampling circuit performs rising edge sampling according to a first sampling clock and performs falling edge sampling according to a second sampling clock to obtain the even-numbered bit data and the odd-numbered bit data.

3. The decision feedback equalizer of claim 2, wherein: The adder and the parallel-to-serial conversion circuit further convert the even-bit data into even-bit half-rate data; and The adder and the parallel-to-serial conversion circuit further organize the odd-bit data into odd-bit half-rate data.

4. The decision feedback equalizer of claim 3, wherein: The adder and the parallel-to-serial conversion circuit further convert the first sampling clock into a third sampling clock corresponding to the even-bit half-rate data; and The adder and the parallel-to-serial conversion circuit further adjust the second sampling clock to a fourth sampling clock corresponding to the odd-bit half-rate data.

5. The decision feedback equalizer of claim 3, wherein: The sampling targets received by the sampling circuit are multiple, which are received by the double data rate memory and identified corresponding to different reference values; and Corresponding to the plurality of sampling targets, the sampling circuit samples a plurality of even-numbered bit data and a plurality of odd-numbered bit data.

6. The decision feedback equalizer of claim 5, further comprising: A selection circuit generates a selection signal to control the adder and the multiplexer in the parallel-to-serial conversion circuit to sort out the even-bit half-rate data and the odd-bit half-rate data from the multiple even-bit data and the multiple odd-bit data, and combine them into the full-rate data.

7. The decision feedback equalizer of claim 6, wherein: The selection circuit includes generating a selection signal for an even-numbered bit path according to previous odd-numbered bit data to control the adder and the parallel-to-serial conversion circuit; and The selection circuit includes generating a selection signal for an odd bit path according to previous even bit data to control the adder and the parallel-to-serial conversion circuit.

8. The decision feedback equalizer of claim 7, wherein: According to the selection signal of the even-numbered bit path, the adder and the parallel-to-serial conversion circuit obtain an even-numbered bit multiplexer output of the even-numbered bit path from the plurality of even-numbered bit data (Even#); According to the selection signal of the odd-numbered bit path, the adder and the parallel-to-serial conversion circuit obtain an odd-numbered bit multiplexer output of the odd-numbered bit path from the plurality of odd-numbered bit data; The adder and the parallel-to-serial conversion circuit output the even-bit multiplexer output and the odd-bit multiplexer output to generate the even-bit half-rate data (EVENOUT) and the odd-bit half-rate data, and combine them to generate the full-rate data.

9. The decision feedback equalizer of claim 8, wherein: The adder and the parallel-to-serial conversion circuit further supplies the output of the odd-bit multiplexer to the selection circuit as the previous odd-bit data; and The adder and the parallel-to-serial conversion circuit further output the even-bit multiplexer to the selection circuit as the previous even-bit data.

10. The decision feedback equalizer as described in claim 9, wherein the default operation of the decision feedback equalizer is to perform a first-order decision feedback equalization operation, and when identifying the current bit, the status of the previous bit is considered, and when the first-order decision feedback equalization operation cannot meet the eye diagram requirements, the decision feedback equalizer is switched to perform a second-order decision feedback equalization operation, and when identifying the current bit, the status of the previous two bits is considered.

11. The decision feedback equalizer of claim 10, wherein: The sampling circuit receives four sampling targets and samples four even-bit data and four odd-bit data.

12. The decision feedback equalizer of claim 11, wherein: The aforementioned sampling circuit comprises: The four D flip-flops of the even path receive the four sampling targets respectively to generate the four even-bit data, wherein the clearing signals of two D flip-flops are connected to the enable signals of the first-order decision feedback equalization operation, and the clearing signals of the other two D flip-flops are connected to the enable signals of the second-order decision feedback equalization operation; and The four D flip-flops of the odd channel receive the aforementioned four sampling targets respectively to generate the aforementioned four odd-bit data, wherein the clearing signals of two D flip-flops are connected to the enable signals of the first-order decision feedback equalization operation, and the clearing signals of the other two D flip-flops are connected to the enable signals of the second-order decision feedback equalization operation.

13. The decision feedback equalizer of claim 11, wherein: In response to the first-order decision feedback equalization operation, the selection circuit provides a first even-bit path selection signal for the adder and the parallel-to-serial conversion circuit to select the output of the even-bit multiplexer from the zeroth even-bit data and the first even-bit data; Corresponding to the first-order decision feedback equalization operation, the selection circuit further provides a first odd-bit path selection signal for the adder and the parallel-to-serial conversion circuit to select the odd-bit multiplexer output from a zeroth odd-bit data and a first odd-bit data; In response to the second-order decision feedback equalization operation, the selection circuit provides the first even-bit path selection signal and the second even-bit path selection signal for the adder and the parallel-to-serial conversion circuit to select the even-bit multiplexer output from the zeroth even-bit data, the first even-bit data, the second even-bit data, and the third even-bit data; and Corresponding to the second-order decision feedback equalization operation, the aforementioned selection circuit provides the aforementioned first odd-bit path selection signal and a second odd-bit path selection signal for the aforementioned adder and parallel-to-serial conversion circuit to select the aforementioned odd-bit multiplexer output from the aforementioned zeroth odd-bit data, the aforementioned first odd-bit data, a second odd-bit data, and a third odd-bit data.

14. The decision feedback equalizer of claim 13, wherein: The aforementioned adder and parallel-to-serial conversion circuit comprises: a first multiplexer, under the control of the first even-bit path selection signal and the second even-bit path selection signal, outputting the zeroth even-bit data, the first even-bit data, the second even-bit data, or the third even-bit data (Even3) to form the even-bit multiplexer output; a second multiplexer, under the control of the first odd bit path selection signal and the second odd bit path selection signal, outputting the zeroth odd bit data, the first odd bit data, the second odd bit data, or the third odd bit data to form the odd bit multiplexer output; A third multiplexer receives the even-bit multiplexer output and the odd-bit multiplexer output to combine the full-rate data (ZI).

15. The decision feedback equalizer of claim 9 wherein: The aforementioned selection circuit further operates according to a mode selection signal; When the mode selection signal is a first value, the selection circuit corresponds to an on-chip terminal of a first type double data rate memory coupled to a power supply, and generates a selection signal for an even bit path and a selection signal for an odd bit path; and When the mode selection signal is at a second value, the selection circuit corresponds to an on-chip terminal of a second type double data rate memory connected to ground, and generates a selection signal for an even bit path and a selection signal for an odd bit path.

16. The decision feedback equalizer of claim 13, wherein: The aforementioned selection circuit also includes: A first selection subcircuit generates a first even-bit path selection signal and a first odd-bit path selection signal according to the output of the odd-bit multiplexer, the output of the even-bit multiplexer, an enable signal of the first-order decision feedback equalization operation, and a mode selection signal, for the operation of the adder and the parallel-to-serial conversion circuit.

17. The decision feedback equalizer of claim 16, wherein: The aforementioned selection circuit also includes: A second selection subcircuit generates a second even-bit path selection signal and a second odd-bit path selection signal according to the output of the odd-bit multiplexer, the output of the even-bit multiplexer, the enable signal of the second-order decision feedback equalization operation, and the mode selection signal, for the operation of the adder and the parallel-to-serial conversion circuit.

18. The decision feedback equalizer of claim 9, further comprising: An initialization circuit responds to power-on, enable switching, and read-and-read switching to provide a first bit selection signal for the even bit path and the odd bit path, and is delivered to the aforementioned selection circuit to generate a selection signal for the even bit path and a selection signal for the odd bit path.

19. The decision feedback equalizer of claim 18, further comprising: a first D flip-flop, receiving the second sampling clock (DFECLKN) when the D input pin receives the signal 1'b0; a second D flip-flop, receiving the first sampling clock and outputting a first relay signal at a Q inverting output terminal when the D input pin receives the Q output of the first D flip-flop; an asynchronous counter, generating a second relay signal according to a read-and-read switching signal, the first sampling clock, and the second sampling clock; as well as A logic circuit combination generates a first bit selection signal for a digital bit path and an odd bit path according to the first relay signal, the second relay signal, and the second sampling clock, and delivers the first bit selection signal to the selection circuit to generate a selection signal for the even bit path and a selection signal for the odd bit path.

20. The decision feedback equalizer of claim 19, wherein: The aforementioned logic circuit combination further includes: An AND logic receives the first relay signal and the second relay signal to generate a third relay signal; a multiplexer and a third D flip-flop, wherein the multiplexer receives the first relay signal and the third relay signal and generates an output to the D input terminal of the third D flip-flop under the control of the inverted signal of the read and read switching signal, so that the Q inverted output terminal of the third D flip-flop outputs the first digit selection signal; and The two inverters each invert the output of the multiplexer to form the first digit selection signal.

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