Hash table operation method and device, electronic equipment and storage medium

Abstract

The invention provides a hash table operation method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving a hash table operation instruction sent by a control plane, wherein the hash table operation instruction comprises an operation type and an index value of a next conflict chain to be operated; determining a to-be-operated conflict chain according to the index value of the next to-be-operated conflict chain, and performing processing operation of the operation type on table items in the to-be-operated conflict chain by utilizing the acceleration instruction; and writing the operation result into the PCIE buffer area to enable the control plane to read the operation result. According to the method, the acceleration operation of batch table items is realized through the acceleration instruction of the network processor, and the method has the advantages of high operation speed, controllable operation speed, reliable operation result and extensible service.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a hash table operation method, device, electronic device and storage medium. Background Art

[0002] As the demand for network intelligence and visual operation and maintenance grows, data forwarding equipment often needs to classify, count and process messages. A common practice is for the network processor (NP) to copy a message and send it to the control plane (CP), which then parses and counts the message. This approach is often limited by the link bandwidth between the control plane and the network processor and the processing power of the central processing unit (CPU) of the control plane, making it difficult to achieve high performance. To improve performance, the industry often uses the network processor to learn the hardware flow table to classify and process messages for acceleration, and the control plane operates the existing hardware flow table to provide external functions.

[0003] However, the current way of operating the hardware hash flow table on the control plane in data forwarding equipment has the disadvantages of low operation rate, unreliable operation results, uncontrollable operation rate, and inconvenient business expansion. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the present application provides a hash table operation method, device, electronic device and storage medium.

[0005] According to a first aspect of an embodiment of the present application, a hash table operation method is provided, the method being applied to a network processor, the network processor being connected to a control plane through a PCIE channel, the method comprising:

[0006] Receive a hash table operation instruction issued by the control plane, wherein the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0007] Determine the conflict chain to be operated according to the index value of the next conflict chain to be operated, and perform the processing operation of the operation type on the entries in the conflict chain to be operated using the acceleration instruction;

[0008] The operation result is written into the PCIE buffer so that the control plane reads the operation result.

[0009] According to a second aspect of an embodiment of the present application, a hash table operation method is provided, the method being applied to a control plane, the control plane being connected to a network processor through a PCIE channel, the method comprising:

[0010] Generate a hash table operation instruction, wherein the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0011] Sending the hash table operation instruction to the network processor, so that the network processor determines the conflict chain to be operated according to the index value of the next conflict chain to be operated, performs the operation type processing operation on the table items in the conflict chain to be operated by using the acceleration instruction and writes the operation result into the PCIE buffer;

[0012] The operation result is read from the PCIE buffer.

[0013] According to a third aspect of an embodiment of the present application, a hash table operation device is provided, the device is applied to a network processor, the network processor is connected to a control plane through a PCIE channel, and the device includes:

[0014] A receiving module, configured to receive a hash table operation instruction issued by a control plane, wherein the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0015] A processing operation module, used for determining the conflict chain to be operated according to the index value of the next conflict chain to be operated, and performing the processing operation of the operation type on the entries in the conflict chain to be operated by using an acceleration instruction;

[0016] The writing module is used to write the operation result into the PCIE buffer so that the control plane can read the operation result.

[0017] According to a fourth aspect of an embodiment of the present application, a hash table operation device is provided, the device is applied to a control plane, the control plane is connected to a network processor through a PCIE channel, and the device includes:

[0018] A traversal module, used to generate a hash table operation instruction, wherein the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0019] A sending module, configured to send the hash table operation instruction to a network processor, so that the network processor determines the conflict chain to be operated according to the index value of the next conflict chain to be operated, performs the operation type processing operation on the table items in the conflict chain to be operated by using the acceleration instruction, and writes the operation result into the PCIE buffer;

[0020] The reading module is used to read the operation result from the PCIE buffer.

[0021] According to a fifth aspect of an embodiment of the present application, there is provided an electronic device, comprising a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor is prompted by the machine-executable instructions to implement the method steps described above.

[0022] According to a sixth aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method steps described above are implemented.

[0023] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0024] In the embodiment of the present application, the network processor receives the hash table operation instruction issued by the control plane through the PCIE channel, and batch-operates all the table items in the conflict chain according to the operation type and conflict chain index value contained in the hash table operation instruction, and finally returns the operation result through the PCIE channel for the control plane to use. In other words, the embodiment of the present application separates the two layers of traversal required for traversing the hash table structure, the control plane is responsible for traversing the conflict chain in the main table, and the network processor is responsible for traversing the table items in the conflict chain. The batch table item operation is accelerated through the acceleration instruction of the network processor, which has the advantages of fast operation rate, controllable operation rate, reliable operation result, and scalable business.

[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in the specification and constitute a part of this application, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

[0027] Figure 1 A schematic diagram of a control plane operation hardware hash flow table solution provided in an embodiment of the present application;

[0028] Figure 2 A first flow chart of a hash table operation method provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the basic structure of a hash table provided in an embodiment of the present application;

[0030] Figure 4 A process diagram of a hash table operation method provided in an embodiment of the present application;

[0031] Figure 5 A second flow chart of a hash table operation method provided in an embodiment of the present application;

[0032] Figure 6 A third flow chart of a hash table operation method provided in an embodiment of the present application;

[0033] Figure 7 A fourth flow chart of a hash table operation method provided in an embodiment of the present application;

[0034] Figure 8 An interactive schematic diagram of a hash table operation method provided in an embodiment of the present application;

[0035] Fig. 9 A fifth flow chart of a hash table operation method provided in an embodiment of the present application;

[0036] Fig.10 A first structural diagram of a hash table operation device provided in an embodiment of the present application;

[0037] Fig.11 A second structural diagram of a hash table operation device provided in an embodiment of the present application;

[0038] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0040] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0041] It should be understood that, although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" or "if" as used herein may be interpreted as "at the time of" or "when...".

[0042] In the data forwarding device, the control plane is connected to the network processor. Most of the hardware flow tables in the network processor exist in the form of hash tables. Therefore, the operation of the control plane on the hardware flow table of the network processor can be further defined as the operation on the hash table, such as Figure 1 As shown, the network processor stores a hardware hash table (HARDWARE_HASH_TABLE), and the control plane stores a software hash table (SOFTWARE_HASH_TABLE). The control plane has the following requirements for the hash table operation of the network processor:

[0043] Speed ​​of operation: Data forwarding devices must operate large-scale hardware flow tables quickly. Taking NetStream as an example, data forwarding devices need to periodically send flow log information to the log server. If the control plane accesses the hardware flow table too slowly, it may affect the log server's statistical results. At the same time, devices generally support local printing of flow information through the command line. If the access speed is too slow, the command line experience will be reduced or even unavailable.

[0044] Reliability of operation results: In the traditional scheme of message classification and statistics of the control plane, if the message sent by the network processor is lost, it only affects the statistical results of a certain flow. This type of monitoring function is generally used in combination with sampling, and the loss of a single message has little effect on the statistical results. Different from this, when the network processor performs message classification and statistics, the flow table and flow-related statistical information are stored in the network processor. Once the control plane loses the access to the network processor resource information, the monitoring information of an entire data flow will be lost, which has a great impact. Therefore, the control plane must operate the network processor resources in a reliable way.

[0045] To meet the above requirements, the present application provides a hash table operation method, device, electronic device and storage medium. Next, the embodiments of the present application are described in detail.

[0046] The embodiment of the present application provides a hash table operation method, which is applied to a network processor, wherein the network processor is connected to a control plane through a PCIE channel, such as Figure 2 As shown, the method may include the following steps:

[0047] Step 210: Receive a hash table operation instruction issued by the control plane, where the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0048] Step 220: determine the conflict chain to be operated according to the index value of the next conflict chain to be operated, and use the acceleration instruction to perform the processing operation of the operation type on the table items in the conflict chain to be operated;

[0049] Step 230: Write the operation result into the PCIE buffer so that the control plane can read the operation result.

[0050] In the embodiment of the present application, the control plane is connected to the network processor through a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) channel, and the PCIE channel provides basic memory read and write functions. The network processor receives the hash table operation instruction issued by the control plane through the PCIE channel, and batch operates all the table items in the conflict chain to be operated according to the operation type contained in the hash table operation instruction and the index value of the next conflict chain to be operated, and finally returns the operation results to the control plane through the PCIE channel.

[0051] The basic structure of a hash table is as follows Figure 3 As shown in FIG. 1 , the hash table consists of a main table (MAIN TABLE) and a conflict chain. All entries (ENTRY) with the same hash value (HASH) of the key (KEY) are stored in a conflict chain in the form of a linked list. In the current implementation scheme, when the control plane needs to operate the hash table of the network processor, it first calculates the memory address where the hash table to be operated is located, and then reads the content of the specified location of the network processor memory through the PCIE channel and parses to determine whether there is an entry and whether there is a next entry. If there is associated information, it is necessary to initiate the read again through the PCIE channel. This method requires the control plane to initiate multiple PCIE read requests. Taking 1M entries and 512K main table as an example, the control plane needs to initiate at least 1.5M PCIE requests. If there is associated information in the hash table, it is also necessary to further read the associated information according to the read entry, which will result in more PCIE requests. PCIE is essentially a memory sharing based on direct memory access (DMA). The control plane is only responsible for initiating read requests. The DMA process does not require control plane processing. For the same volume of data operations, the more PCIE access times, the longer the time required, and the worse the performance. In addition, the hash table structure design in the network processor chip will be optimized to a certain extent for hardware table lookup efficiency and table entry space, thereby changing the hash table structure, which will further lead to an increase in the number of PCIE requests when the control plane operates the hardware hash table entries.

[0052] In response to the above problems, the embodiment of the present application disassembles the task of the control plane traversing the entire hash table, and unloads some of the tasks to the network processor. Specifically, in the embodiment of the present application, the control plane is responsible for traversing the conflict chain in the main table of the hash table, determining the next conflict chain to be operated and issuing a hash operation instruction to the network processor. The network processor is responsible for traversing the table items in the conflict chain according to the hash operation instruction and returning the operation result to the control plane. Based on this method, on the one hand, using the acceleration instruction of the network processor to process the table items can increase the table item operation rate. On the other hand, the network processor performs a batch of table item processing operations each time and returns the operation results to the control plane, which can reduce the number of PCIE channel requests of the control plane. On the third hand, the logical operations such as determining whether the conflict chain is empty and determining whether the conflict chain has traversed to the last table item are transferred from the control plane to the network processor for execution, which can reduce the impact of the CPU performance of the control plane on the efficiency of hash table operations.

[0053] The embodiment of the present application can be implemented based on the hardware resources in the network processor. Specifically, some hardware resources are pre-divided in the network processor, such as reserving some thread resources or adding coprocessors, and the above-mentioned hash table operation method is implemented using these hardware resources. Taking the use of coprocessors to implement the above-mentioned hash table operation method as an example, the overall process is as follows: Figure 4 As shown, the network processor receives the data stream (DATAFRAME), the data plane (DATA PLANE) organizes the data stream into a hash table structure, the control plane (CONTROL PLANE) actively sends hash table operation instructions to the coprocessor (COPROCESSER) of the network processor, the coprocessor operates the hash table according to the hash table operation instructions, and sends the operation results to the control plane through the PCIE channel.

[0054] In the embodiment of the present application, the control plane refers to the device in the data forwarding device that is responsible for formulating network policies and routing planning, which can specifically be the main control board of a traditional device, a software-defined network (SDN) controller, etc.; the network processor refers to the device in the data forwarding device that is responsible for actual data transmission.

[0055] It is worth mentioning that in the embodiment of the present application, the network processor can operate all the entries of one conflict chain at a time, or can operate all the entries of multiple conflict chains at a time. When the network processor operates one conflict chain at a time, the hash table operation method flow is as follows: Figure 5 As shown, the following steps are included:

[0056] Step 510: Receive a hash table operation instruction issued by the control plane, where the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0057] Step 520: determine the conflict chain whose index value is equal to the index value of the next conflict chain to be operated as the conflict chain to be operated, and use the acceleration instruction to perform the processing operation of the operation type on the table items in the conflict chain to be operated;

[0058] Step 530: Write the operation result into the PCIE buffer so that the control plane can read the operation result.

[0059] When the network processor operates multiple conflict chains each time, it is necessary to set the termination condition of the network processor operation table item. Since the network processor needs to write the operation result into the PCIE buffer, it is possible to consider setting the termination condition to fill the PCIE buffer, or to consider limiting the number of table items or conflict chains operated by the network processor each time. Therefore, when the network processor operates multiple conflict chains each time, the hash table operation method flow is as follows: Figure 6 As shown, the following steps are included:

[0060] Step 610: Receive a hash table operation instruction issued by the control plane, where the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0061] Step 620: Starting from the target conflict chain whose index value is equal to the index value of the next conflict chain to be operated, use the acceleration instruction to perform the processing operation of the operation type on the table entries in the target conflict chain and each conflict chain after the target conflict chain until any termination condition is met;

[0062] Step 630: Write the operation result into the PCIE buffer so that the control plane can read the operation result.

[0063] The above termination conditions include: the number of entries that have completed processing operations reaches the maximum number of operation entries, the number of conflict chains that have completed processing operations reaches the maximum number of operation conflict chains, and the operation results fill the PCIE buffer.

[0064] Specifically, when the network processor processes multiple conflict chains, the operation result returned by the network processor to the control plane may further include the index value of the last conflict chain that has completed the processing operation, so that the control plane can determine the next conflict chain to be operated accordingly.

[0065] It is understandable that, since each operation request is initiated by the control plane, when the termination condition is set to the number of table entries that have completed the processing operation reaches the maximum number of operation table entries or the number of conflict chains that have completed the processing operation reaches the maximum number of operation conflict chains, the effect of limiting the table entry operation rate can be achieved. In practical applications, the CPU processing performance of the control plane of the data forwarding device is generally limited. When the network processor performs flow table learning and statistics, the performance bottleneck of the data forwarding device providing functions to the outside generally exists on the control plane. Therefore, the control plane cannot obtain the network processor flow table rate too fast, otherwise it may cause information loss due to the CPU performance bottleneck. The embodiment of the present application can limit the table entry operation rate based on the above method, thereby avoiding the problem of information loss caused by the excessively fast table entry operation rate.

[0066] In addition, in actual applications, the CPU selection of the control plane is relatively flexible, and the processing performance of different CPU models varies greatly. In response to this situation, the embodiment of the present application flexibly adjusts the above-mentioned maximum number of operation table items or the maximum number of operation conflict chains, and correspondingly adjusts the table item operation rate to adapt to different CPU performance.

[0067] It is worth mentioning that even if the termination condition is set to that the number of table entries that have completed processing operations reaches the maximum number of operation table entries or the number of conflict chains that have completed processing operations reaches the maximum number of operation conflict chains, the situation where the PCIE buffer is full should be avoided. Therefore, in actual applications, after the network processor processes the table entries of a conflict chain, it needs to complete two layers of judgment. One layer of judgment is to judge whether the PCIE buffer is full, and the other layer of judgment is to judge whether the number of table entries that have completed processing operations reaches the maximum number of operation table entries or the number of conflict chains that have completed processing operations reaches the maximum number of operation conflict chains. If and only if both judgment results are no, the network processor will continue to process the table entries of the next conflict chain.

[0068] In actual applications, the information required for statistics in different monitoring service flow tables may be different. At the same time, the associated information and operation logic of different monitoring service flow tables may be different. In view of the above situation, the embodiment of the present application provides a universal hash table operation method as described above, and sets a callback function on this basis to meet the flow table operation requirements of different service types through different callback functions. Therefore, as a preferred implementation, the above hash table operation instruction also includes the service type of the target hash table. The overall hash table operation method flow is shown in Figure 7, including the following steps:

[0069] Step 710: Receive a hash table operation instruction issued by the control plane, where the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0070] Step 720: determine the conflict chain to be operated according to the index value of the next conflict chain to be operated, and use the acceleration instruction to perform the processing operation of the operation type on the table items in the conflict chain to be operated;

[0071] Step 730: Call the callback function of the above service type to process the table item in the conflict chain to be operated and / or the associated information of the table item;

[0072] Step 740: Write the operation result into the PCIE buffer so that the control plane can read the operation result.

[0073] According to different business requirements, the above callback function may be used to operate the associated information corresponding to the table item in the conflict chain to be operated, may be used to operate the table item in the conflict chain to be operated, or may be used to operate the table item in the conflict chain to be operated and the associated information corresponding to the table item at the same time. The specific definition can be made in the callback function, and the embodiment of the present application does not limit this. When adding a new business, it is only necessary to add a new callback function. It can be seen that the embodiment of the present application effectively guarantees the good business scalability of the hash table operation method.

[0074] In summary, the embodiment of the present application provides a scheme for a control plane to operate a network processor hardware hash flow table with a fast operation rate, controllable operation rate, reliable operation results, and scalable business. Specifically, first, the embodiment of the present application uses the PCIE channel to realize the underlying data transmission. Whether it is the transmission of the hash table operation instruction initiated by the control plane or the operation result returned by the coprocessor, it is guaranteed by PCIE, and no data loss will occur. Furthermore, in the embodiment of the present application, the hash table operation is actively initiated by the control plane, the number of table entries returned by a single operation request can be controlled, and if there is an overload task between two operations of the control plane, the hash table traversal can be suspended, and the conflict chain from the last breakpoint can be continued when the CPU is idle, without affecting the operation result. Finally, the hash table operation method of the embodiment of the present application is universal, and can be used for hash flow tables of different services. The difference in the processing of hash flow tables of different service types is only reflected in the coprocessor table entry processing callback function. When adding new services, only a new callback function needs to be added, which has good scalability.

[0075] In combination with the above embodiments, the overall solution implementation is introduced by taking a specific application as an example. This embodiment implements the above hash table operation method based on the coprocessor in the network processor, limiting the maximum number of table entries per operation of the coprocessor. First, define the hash table operation instruction sent by the control plane to the coprocessor and the operation result sent by the coprocessor to the control plane:

[0076] The hash table operation instructions sent to the coprocessor may include the following fields:

[0077] Hash table descriptor: used to identify the target hash table being operated, which may include the hash table storage base address, single table item size, key length, result area length, etc.

[0078] Business type: used to identify the service / function provided by the target hash table. The coprocessor can determine whether there is associated information and the type of associated information in the hash table based on this field, and can also perform action extensions for table entry operations based on this field.

[0079] Conflict chain index value: used to indicate which conflict chain of the target hash table the coprocessor should start operating from;

[0080] Operation type: including but not limited to read (READ), aging (AGE), and forced deletion (RESET);

[0081] Maximum number of entries: used to control the number of entries requested by the coprocessor for a single operation;

[0082] The starting address of the PCIE buffer: used to indicate the location where the coprocessor returns the operation result;

[0083] The size of the PCIE buffer.

[0084] The result of the coprocessor writing to the PCIE buffer may include the following:

[0085] Return the number of entries: used to indicate the number of entries contained in the PCIE buffer;

[0086] Table entry size: used to indicate the size of a single hash table entry;

[0087] Associated data size: used to indicate the associated data size;

[0088] Operation completed conflict chain index value: used to indicate the index value of the last conflict chain whose operation has been completed, and is used by the control plane to initiate the next hash table operation request.

[0089] In this embodiment, the interaction process between the control plane and the coprocessor is as follows: Figure 8 As shown:

[0090] When the control plane needs to traverse the hardware hash flow table, the control plane first obtains the number of hash table conflict chains, traverses on the main table, and sets the conflict chain index value in the hash table operation instruction to 0 (i.e., PROCESS REQUEST SLOT = 0) when issuing the hash table operation instruction for the first time. After issuing the hash table operation instruction, the control plane waits for the coprocessor (COPROCERRER) to notify the completion of the operation. After the coprocessor receives the instruction, taking the operation type of read as an example, the coprocessor accesses the table item from the conflict chain No. 0 according to the instruction content. The table item access uses the table item access command ACC_READ optimized by the network processor, and the access speed is very fast. After the coprocessor reads a table item, in the table item processing callback function, it parses the flow table item according to the service type, reads the possible flow table association information, and writes it completely into the PCIE buffer. After that, the coprocessor repeats the above process until the maximum number of table item operations is reached or the PCIE buffer is full, and informs the control plane of the completion of this operation by interrupting or writing the status register. Figure 8 In the example, SLOT M represents the last conflict chain that completes the processing operation, where M is the index value of the conflict chain.

[0091] The coprocessor writes all operation results (PROCESS RESULT SLOT M) into the PCIE buffer. After the control plane waits for the coprocessor to notify that the operation is completed, it obtains all operation results from the PCIE buffer, divides the PCIE buffer according to the number of table entries, the size of a single table entry and the size of associated data, and processes each table entry.

[0092] After the control plane processes all the operation results returned by the coprocessor at one time, if it has not reached the last conflict chain, it will initiate a hash table operation instruction again, and the conflict chain index value in the instruction is the index value returned by the coprocessor last time plus 1 (ie, PROCESS RESULT SLOT M+1). The control plane repeats the above process until all conflict chains of the hash table are finally processed (ie, SLOT N), where N is the total number of conflict chains in the hash table.

[0093] It can be seen from the above technical solutions that the embodiment of the present application splits the two layers of traversal required for traversing the hash table structure (traversal of the conflict chain in the main table and traversal of the table items in the conflict chain), the control plane is responsible for traversing the conflict chain in the main table, and the coprocessor is responsible for traversing the table items in the conflict chain, thereby realizing batch return of table item operation results. Taking 1M table items, 512K conflict chains, and 4 counters as the flow table associated data as an example, if the number of conflict chains for a single operation is set to 1, then the control plane initiates only 512K PCIE requests. In addition, the number of interactions can be further reduced by increasing the number of conflict chains for a single operation to achieve higher operating performance.

[0094] Based on the same inventive concept, the present application also provides a hash table operation method, which is applied to a control plane, where the control plane is connected to a network processor via a PCIE channel, such as Fig. 9 As shown, the method comprises the following steps:

[0095] Step 910: Generate a hash table operation instruction, where the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0096] Step 920: Send the hash table operation instruction to the network processor, so that the network processor determines the conflict chain to be operated according to the index value of the next conflict chain to be operated, performs the above operation type processing operation on the table items in the conflict chain to be operated by using the acceleration instruction, and writes the operation result into the PCIE buffer;

[0097] Step 930: Read the operation result from the PCIE buffer.

[0098] Optionally, before generating the hash table operation instruction, the method further includes: traversing the main table of the target hash table to determine the next conflict chain to be operated.

[0099] Based on the same inventive concept, the present application also provides a hash table operation device, which is applied to a network processor, and the network processor is connected to the control plane through a PCIE channel. The schematic diagram of the device structure is shown in FIG. Fig.10 As shown, specifically including:

[0100] The receiving module 1010 is used to receive a hash table operation instruction issued by the control plane, where the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0101] The processing operation module 1020 is used to determine the conflict chain to be operated according to the index value of the next conflict chain to be operated, and perform the above-mentioned operation type of processing operation on the table items in the conflict chain to be operated by using the acceleration instruction;

[0102] The writing module 1030 is used to write the operation result into the PCIE buffer so that the control plane can read the operation result.

[0103] It is understandable that when the above hash operation process is implemented using a coprocessor in a network processor, the above receiving module 1010, processing operation module 1020, and writing module 1030 can be regarded as modules divided according to functions within the coprocessor.

[0104] Based on the same inventive concept, the present application also provides a hash table operation device, which is applied to a control plane, and the control plane is connected to a network processor through a PCIE channel, such as Fig.11 As shown, the device comprises:

[0105] A traversal module 1110 is used to generate a hash table operation instruction, where the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated;

[0106] The sending module 1120 is used to send the hash table operation instruction to the network processor, so that the network processor determines the conflict chain to be operated according to the index value of the next conflict chain to be operated, performs the above-mentioned operation type processing operation on the table items in the conflict chain to be operated by using the acceleration instruction and writes the operation result into the PCIE buffer;

[0107] The reading module 1130 is used to read the operation result from the PCIE buffer.

[0108] The present application also provides an electronic device, such as Fig.12 As shown, it includes a processor 1210 and a machine-readable storage medium 1220, wherein the machine-readable storage medium 1220 stores machine-executable instructions that can be executed by the processor 1210, and the processor 1210 is prompted by the machine-executable instructions to implement the steps of any of the above-mentioned hash table operation methods.

[0109] The machine-readable storage medium may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk storage. Optionally, the machine-readable storage medium may also be at least one storage device located away from the processor.

[0110] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0111] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned hash table operation methods are implemented.

[0112] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A hash table operation method, It is characterized in that The method is applied to a network processor, the network processor is connected to a control plane via a PCIE channel, and the method comprises: Receive a hash table operation instruction issued by the control plane, wherein the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated; Determine the conflict chain to be operated according to the index value of the next conflict chain to be operated, and perform the processing operation of the operation type on the entries in the conflict chain to be operated using the acceleration instruction; The operation result is written into the PCIE buffer so that the control plane reads the operation result.

2. The method according to claim 1, It is characterized in that The hash table operation instruction also includes a maximum number of operation table entries or a maximum number of operation conflict chains; Determining the conflict chain to be operated according to the index value of the next conflict chain to be operated, and performing the operation type processing operation on the entries in the conflict chain to be operated by using the acceleration instruction, including: Starting from the target conflict chain whose index value is equal to the index value of the next conflict chain to be operated, the target conflict chain and the table items in each conflict chain after the target conflict chain are subjected to the processing operation of the operation type using acceleration instructions until the number of table items that have completed the processing operation reaches the maximum number of operation table items or the number of conflict chains that have completed the processing operation reaches the maximum number of operation conflict chains, and an operation result is obtained, wherein the operation result includes the index value of the last conflict chain that has completed the processing operation.

3. The method according to claim 1, It is characterized in that Determining the conflict chain to be operated according to the index value of the next conflict chain to be operated, and performing the operation type processing operation on the entries in the conflict chain to be operated by using the acceleration instruction, including: Starting from the target conflict chain whose index value is equal to the index value of the next conflict chain to be operated, the acceleration instruction is used to perform the processing operation of the operation type on the table items in the target conflict chain and each conflict chain located after the target conflict chain until the operation result fills the PCIE buffer, and the operation result includes the index value of the last conflict chain that completes the processing operation.

4. The method according to claim 1, It is characterized in that The hash table operation instruction also includes the service type of the target hash table; After performing the operation type processing operation on the table items in the conflict chain to be operated by using the acceleration instruction, the method further includes: The callback function of the service type is called to process the table item in the conflict chain to be operated and / or the associated information of the table item.

5. A hash table operation method, It is characterized in that The method is applied to a control plane, the control plane is connected to a network processor via a PCIE channel, and the method includes: Generate a hash table operation instruction, wherein the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated; Sending the hash table operation instruction to a network processor, so that the network processor determines the conflict chain to be operated according to the index value of the next conflict chain to be operated, performs the operation type processing operation on the table items in the conflict chain to be operated by using the acceleration instruction and writes the operation result into the PCIE buffer; The operation result is read from the PCIE buffer.

6. The method according to claim 5, It is characterized in that Before generating hash table operation instructions, it also includes: Traverse the main table of the target hash table to determine the next conflict chain to be operated.

7. A hash table operation device, It is characterized in that The device is applied to a network processor, the network processor is connected to a control plane via a PCIE channel, and the device includes: A receiving module, configured to receive a hash table operation instruction issued by a control plane, wherein the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated; A processing operation module, used for determining the conflict chain to be operated according to the index value of the next conflict chain to be operated, and performing the processing operation of the operation type on the entries in the conflict chain to be operated by using the acceleration instruction; The writing module is used to write the operation result into the PCIE buffer so that the control plane can read the operation result.

8. A hash table operation device, It is characterized in that The device is applied to a control plane, the control plane is connected to a network processor via a PCIE channel, and the device includes: A traversal module, used to generate a hash table operation instruction, wherein the hash table operation instruction includes an operation type and an index value of a next conflict chain to be operated; A sending module, configured to send the hash table operation instruction to a network processor, so that the network processor determines the conflict chain to be operated according to the index value of the next conflict chain to be operated, performs the operation type processing operation on the table items in the conflict chain to be operated by using the acceleration instruction, and writes the operation result into the PCIE buffer; The reading module is used to read the operation result from the PCIE buffer.

9. An electronic device, It is characterized in that The method comprises a processor and a machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor, and the processor is prompted by the machine-executable instructions to implement the method steps described in any one of claims 1 to 6.

10. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps of any one of claims 1 to 6 are implemented.

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