Data processing system, method and device for database, storage medium and computer program product

Abstract

The invention relates to a data processing system, method and device for a database, a storage medium and a computer program product. The system comprises a first FPGA, a first GPU, a CPU and a memory, the first FPGA is used for obtaining a target operation instruction for a database, sending the target operation instruction to the first GPU, and reading first data required for executing the target operation instruction from the memory and / or the database; the first GPU is used for predicting demand data of the first FPGA according to the target operation instruction and a preorder operation instruction of the target operation instruction, and feeding back the demand data to the CPU; and the CPU is used for determining target data according to the demand data, acquiring the target data from the database and writing the target data into the memory. By adopting the system provided by the invention, the operation efficiency for the database can be improved.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a data processing system, method, device, storage medium and computer program product for a database. Background Art

[0002] Database performance becomes particularly important in scenarios where the database needs to handle a large number of highly concurrent requests. If the database's data processing method is not optimized, it may lead to a series of situations such as slow storage, response delays, and even database crashes, which seriously affect the security and stability of the database and cause problems in the business system. Therefore, there is a need to provide a solution that can improve the efficiency of database operations. Summary of the invention

[0003] Based on this, it is necessary to provide a data processing system, method, device, storage medium and computer program product for a database in order to address the above technical issues.

[0004] In a first aspect, the present application provides a data processing system for a database, the system comprising a first FPGA, a first GPU, a CPU and a memory, wherein:

[0005] The first FPGA is used to obtain a target operation instruction for a database, send the target operation instruction to the first GPU, and read first data required to execute the target operation instruction from the memory and / or the database;

[0006] The first GPU is used to predict the required data of the first FPGA according to the target operation instruction and the preceding operation instruction of the target operation instruction, and feed the required data back to the CPU;

[0007] The CPU is used to determine target data according to the demand data, obtain the target data from the database, and write the target data into the memory.

[0008] In one embodiment, the step of reading the first data required to execute the target operation instruction from the memory and / or the database includes:

[0009] The first data required for executing the target operation instruction is read from the memory, and when the first data does not exist in the memory, the first data is read from the database.

[0010] In one of the embodiments, the first FPGA is also used to, when obtaining multiple operation instructions for the database, determine a first target operation instruction from the multiple operation instructions, merge each of the first target operation instructions to obtain a merged instruction, and use the merged instruction and the instructions in the multiple operation instructions except the first target operation instruction as the target operation instruction.

[0011] In one embodiment, the demand data is multiple, and the demand data has a corresponding prediction call order; determining the target data according to the demand data includes:

[0012] Determine the historical prediction accuracy of the first GPU for each of the prediction call sequences, and determine a target prediction call sequence from each of the prediction call sequences according to the historical prediction accuracy;

[0013] The demand data corresponding to the target prediction calling sequence is used as the target data.

[0014] In one of the embodiments, the demand data is predicted by a data prediction model;

[0015] The CPU is further configured to determine, within an accuracy evaluation cycle, for any of the predicted call sequences, a historical prediction accuracy corresponding to the predicted call sequence according to each target demand data corresponding to the predicted call sequence and actual demand data of the first FPGA corresponding to each target demand data;

[0016] The CPU is further configured to feed back each of the actual demand data to the first GPU when the historical prediction accuracy corresponding to each of the prediction call sequences does not meet a preset accuracy requirement;

[0017] The first GPU is further configured to adjust the data prediction model according to each of the actual demand data.

[0018] In one of the embodiments, the first FPGA is further used to generate a data table for the data to be stored when the target operation instruction is a storage instruction, and determine the time characteristics and data characteristics of the data to be stored, generate a two-dimensional hash index value of the data table according to the time characteristics and the data characteristics, and store the two-dimensional hash index value in the two-dimensional hash index table for the database.

[0019] In one of the embodiments, the system further comprises a second FPGA;

[0020] The first FPGA is further used to determine first data required to execute the target operation instruction according to the target operation instruction, and send a first data retrieval request to the second FPGA based on the first data;

[0021] The second FPGA is used to retrieve the original data corresponding to the first data from the memory and / or the database according to the first data retrieval request, decompress and / or decrypt the original data to obtain the first data, and send the first data to the first FPGA.

[0022] In one of the embodiments, the system further includes a second GPU;

[0023] The first FPGA is further used to determine the complexity of the target operation instruction, and send the target operation instruction to the second GPU if the complexity is greater than a complexity threshold;

[0024] The second GPU is used to execute the target operation instruction sent by the first FPGA.

[0025] In a second aspect, the present application further provides a data processing method for a database. The data processing system for the database includes a first FPGA, a first GPU, a CPU, and a memory. The first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database. The method is applied to the first GPU and includes:

[0026] Receiving the target operation instruction sent by the first FPGA;

[0027] Predicting required data of the first FPGA according to the target operation instruction and a preceding operation instruction of the target operation instruction;

[0028] The demand data is fed back to the CPU, so that the CPU determines the target data according to the demand data, obtains the target data from a database, and writes the target data into a memory.

[0029] In a third aspect, the present application further provides a data processing device for a database. The data processing system for a database includes a first FPGA, a first GPU, a CPU, and a memory. The first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database. The device is applied to the first GPU and includes:

[0030] A receiving module, used for receiving the target operation instruction sent by the first FPGA;

[0031] A prediction module, configured to predict the required data of the first FPGA according to the target operation instruction and a preceding operation instruction of the target operation instruction;

[0032] The feedback module is used to feed back the demand data to the CPU, so that the CPU determines the target data according to the demand data, obtains the target data from the database, and writes the target data into the memory.

[0033] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, any of the above methods is implemented.

[0034] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0035] The above-mentioned data processing system, method, device, storage medium and computer program product for the database predicts the data that needs to be retrieved from the database in the future according to the currently executed operation instruction and the previous operation instruction that has been executed, and determines the target data that needs to be written into the memory with a higher read-write rate from the predicted demand data, so that the required target data can be read from the memory when the operation instruction is subsequently executed, thereby improving the efficiency of operating the database. At the same time, the embodiment of the present application adopts a heterogeneous computing mode, using a GPU with stronger processing capabilities for large amounts of data to predict demand data, using an FPGA with better performance for specific tasks to execute operation instructions, and using a CPU with stronger performance for complex control and task scheduling to execute the step of writing the target data into the memory, which can further improve the execution efficiency of the above steps, and thus can further improve the efficiency of operating the database. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a data processing system for a database in one embodiment;

[0037] Figure 2 A schematic diagram of a flow chart of a CPU evaluating whether a data prediction model needs to be adjusted in one embodiment;

[0038] Figure 3 A schematic diagram of a database storage structure in one embodiment;

[0039] Figure 4 is a schematic diagram of a data processing system for a database in one embodiment;

[0040] Figure 5 is a schematic diagram of a data processing system for a database in one embodiment;

[0041] Figure 6 is a schematic diagram of a data processing system for a database in one embodiment;

[0042] Figure 7 is a flow chart of a method for processing data in a database according to an embodiment;

[0043] Figure 8 It is a flowchart of a data processing device for a database in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] In one embodiment, Figure 1 As shown, a data processing system for a database is provided, characterized in that the system includes a first FPGA, a first GPU, a CPU and a memory, wherein the first FPGA is used to obtain a target operation instruction for the database, send the target operation instruction to the first GPU, and read the first data required for executing the target operation instruction from the memory and / or the database; the first GPU is used to predict the required data of the first FPGA according to the target operation instruction and the preceding operation instruction of the target operation instruction, and feed the required data back to the CPU; the CPU is used to determine the target data according to the required data, obtain the target data from the database, and write the target data to the memory; wherein the read and write rate of the memory is greater than the read and write rate of the database.

[0046] In the embodiment of the present application, the target operation instruction is an instruction for operating a database. The device that needs to operate the database can send the target operation instruction to the data processing system for the database. After the system processes the target operation instruction, the operation specified by the target operation instruction is performed on the database. The data processing system for the database is composed of a first FPGA (Field Programmable Gate Array), a first GPU (Graphics Processing Unit), a CPU (Central Processing Unit), and a memory (which can be any memory with a read and write speed greater than that of the database, such as DDR memory (Double Data Rate Synchronous Dynamic Random Access Memory), DRAM (Dynamic Random Access Memory), etc., which can be specifically determined by the storage medium used by the database that needs to be operated). The first FPGA is mainly used to execute the target operation instruction, the first GPU is mainly used to run the model for predicting demand data, and the CPU is mainly used to control the first FPGA and the first GPU, and to perform other functions required in the operation of the database. The first FPGA, the first GPU and the CPU can communicate with each other. Both the first FPGA and the CPU can be connected to the memory via a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus and share the same memory space.

[0047] After receiving the target operation instruction, the first FPGA reads the first data required to execute the target operation instruction, and sends the target operation instruction to the first GPU. For example, when the target operation instruction is to read data in a data table, the first data required to execute the target operation instruction is the data table to be read, and when the target operation instruction is to merge two tables, the first data required to execute the target operation instruction is the two tables to be merged. In one embodiment, the first FPGA can receive multiple operation instructions at one time. When multiple operation instructions for the database are obtained, the first FPGA determines the first target operation instruction (that is, each operation instruction that can be merged) from the multiple operation instructions, merges each first target operation instruction to obtain a merge instruction, and uses the merge instruction and the instructions other than the first target operation instruction in the multiple operation instructions as the target operation instruction. For example, when the operation instruction is an SQL instruction, the read operations for different tables can be merged into one SQL statement, and the insert operations for different tables can also be merged into one SQL statement. After merging all the operation instructions that can be merged into the merge instruction, the first FPGA uses the merge instruction and other operation instructions that have not been merged as target operation instructions.

[0048] The first FPGA can retrieve the first data from the database and the memory at the same time. Since the first GPU has previously predicted the required data that the first FPGA may need when executing the operation instruction, and the CPU will read the data predicted by the first GPU from the database and write it to the memory, there is a high probability that the first data will exist in the memory. In the case where the first GPU makes an error in prediction, the first data may not exist in the memory, or only a part of the first data may exist. In one embodiment, the first FPGA can read the first data required to execute the target operation instruction from the memory, and read the first data from the database if the first data does not exist in the memory. In another embodiment, if the first FPGA reads the second data from the memory (the second data is part of the first data), the third data that needs to be read from the memory is determined based on the first data and the second data, and the third data is read from the database, so as to obtain all the first data required for the first FPGA to execute the target operation instruction.

[0049] After the first FPGA reads the first data, it executes the target operation instruction. The first FPGA also sends the target operation instruction to the first GPU, so that the first GPU predicts the required data needed for the first FPGA to execute the next operation instruction based on the preceding operation instruction and the target operation instruction. The preceding operation instruction refers to each operation instruction executed by the first FPGA before executing the target operation instruction. The specific number of previously executed operation instructions as preceding operation instructions can be determined based on the input required by the prediction model used by the first GPU. The required data can be the data required for the first FPGA to execute 1 or N subsequent operation instructions.

[0050] Since the types of services that the external device that operates the database needs to perform are usually fixed, there is a regularity in the order in which the external device calls the data, and the first GPU can predict the demand data based on this regularity. For example, the service currently performed by the external device that needs to operate the database is to calculate the average call duration of users in a certain area last year, and then write the average call duration into another table. The order in which the device issues the operation instructions is generally to first read the users in a certain area and the IDs corresponding to these users from the data table storing the user information, and then read the call duration corresponding to these user IDs from the call duration data table corresponding to each month of last year according to the user ID, calculate the average call duration, and finally call the data table storing the average call duration, and write the calculated average call duration into the table. Therefore, after the first GPU sequentially receives the operation instructions to read the user ID, the operation instructions to read the call duration from the call duration data table in January last year, and the operation instructions to read the call duration from the call duration data table in February last year, it can predict that the next operation instruction is likely to require the call duration data table from March to December last year. The first GPU can use the trained data prediction model to predict the demand data required by the system in the future. Each preceding operation instruction can be formed into an instruction sequence in the order received by the first GPU, and the instruction sequence can be input into the data prediction model to obtain the demand data. If the demand data is the data required for the first FPGA to execute N operation instructions, the demand data output by the model can be a data sequence, in which each demand data is arranged in the order in which it is predicted to be called (predicted call order). If the predicted call order of the demand data is 1, it means that the model predicts that the first operation instruction executed by the first FPGA will call the demand data, and so on. Since the first GPU predicts the demand data once every time it obtains the target operation instruction, when predicting N demand data at a time, the demand data with the predicted call order of n in the last prediction and the predicted call order of n-1 in this prediction are the demand data predicted by the model for the same operation instruction. The embodiment of the present application does not specifically limit the structure of the data prediction model, and any model that can predict subsequent data in the sequence based on the data sequence is applicable to the embodiment of the present application. For example: bidirectional recurrent network, recurrent neural network, etc.

[0051] After the first GPU predicts the demand data, it sends the demand data to the CPU. The CPU can determine the target data that actually needs to be loaded into the memory from the demand data. For example, when some demand data already exists in the memory, the CPU can use the data in the demand data except the data already existing in the memory as the target data. In one embodiment, the CPU determines the remaining storage space of the memory, and when the total data size of the demand data is less than or equal to the size of the remaining storage space, all the demand data is used as the target data, or when the total data size of the demand data is greater than the size of the remaining storage space, the demand data is used as the target data in the predicted call order from near to far until the total data size of the target data reaches the size of the remaining storage space. In the process of using the demand data as the target data, the CPU can calculate whether the data size of the target data will exceed the size of the remaining storage space after using the demand data as the target data before using each demand data as the target data. If not, the demand data can be used as the target data. If so, the CPU does not use the demand data as the target data, and terminates the process of using the demand data as the target data in sequence.

[0052] In another embodiment, the CPU determines the historical prediction accuracy of the first GPU based on the actual call data and the demand data corresponding to the actual call data each time the first FPGA executes an operation instruction, and determines the number of target data based on the historical prediction accuracy, so that the number of target data is proportional to the historical prediction accuracy, and the number of target data closest to the predicted call order in the demand data is used as the target data. In this way, when the historical prediction accuracy is low, only a small amount of data in the database is written into the memory, avoiding the situation where a large amount of data that is actually not needed by the first FPGA occupies the memory space. In the case where the historical prediction accuracy is lower than the threshold, the CPU can also retrain and adjust the data prediction model used by the first GPU based on the data actually called by the first FPGA each time and the data predicted by the first GPU to be called by the first FPGA.

[0053] In another embodiment, the CPU is also used to determine the historical prediction accuracy of the first GPU for each prediction call sequence, and determine the target prediction call sequence from each prediction call sequence based on the historical prediction accuracy; and use the demand data corresponding to the target prediction call sequence as the target data. In the embodiment of the present application, the CPU can determine the historical prediction accuracy for each prediction call sequence respectively. Generally speaking, the data prediction model has a higher prediction accuracy for more recent prediction call sequences and a lower prediction accuracy for more distant prediction call sequences. A historical prediction accuracy threshold can be preset, and a prediction call sequence with a historical prediction accuracy greater than the historical prediction accuracy threshold can be used as the target prediction call sequence, and the demand data corresponding to the target prediction call sequence in the demand data can be used as the target data, so as to also achieve the effect of avoiding a large amount of data that the first FPGA does not actually need to use occupying memory space.

[0054] In one embodiment, Figure 2 As shown, the CPU is also used to determine the historical prediction accuracy corresponding to the prediction call sequence within an accuracy evaluation cycle for any prediction call sequence, according to the target demand data corresponding to the prediction call sequence, and the actual demand data corresponding to each target demand data of the first FPGA; the CPU is also used to feed back each actual demand data to the first GPU when the historical prediction accuracy corresponding to each prediction call sequence does not meet the preset accuracy requirement; the first GPU is also used to adjust the data prediction model according to each actual demand data. In an embodiment of the present application, the CPU collects the actual demand data actually called when the first FPGA executes each target operation instruction within an accuracy evaluation cycle. The above data can be fed back to the CPU by the first FPGA. After an accuracy evaluation cycle ends, the CPU determines the target demand data corresponding to the prediction call sequence among all the demand data predicted by the first GPU within the cycle for each prediction call sequence, and determines the actual demand data corresponding to the target demand data. According to whether the target demand data matches the actual demand data, the historical prediction accuracy of the prediction call sequence is determined. If the historical accuracy of the data prediction model within an accuracy evaluation cycle does not meet the preset accuracy requirements (the specific requirements can be set by technical personnel according to actual needs, for example, an accuracy threshold can be set for each prediction call sequence, and the preset accuracy requirement can be set to at least a preset proportion of prediction call sequences with a historical prediction accuracy greater than the corresponding threshold, or set to a historical prediction accuracy of the m most recent prediction call sequences greater than the corresponding threshold, etc.), the CPU can send the actual demand data to the first GPU, so that the first GPU re-trains the data prediction model according to the actual demand data corresponding to each target demand data to improve the prediction accuracy of the first GPU.

[0055] In one embodiment, the CPU determines the frequency at which each target data in the memory is called, and for any target data, when the frequency at which the target data is called is less than a frequency threshold, the CPU deletes the target data from the memory. That is, the CPU can determine which target data should be deleted based on the frequency at which the first FPGA uses each target data in the memory, thereby freeing up memory space.

[0056] In one embodiment, the first FPGA is also used to generate a data table for the data to be stored when the target operation instruction is a storage instruction, and determine the time characteristics and data characteristics of the data to be stored, generate a two-dimensional hash index value of the data table according to the time characteristics and the data characteristics, and store the two-dimensional hash index value in the two-dimensional hash index table for the database.

[0057] In an embodiment of the present application, each data table in the database can be managed through a two-dimensional hash index table. When data needs to be stored in the database, the first FPGA can extract the time characteristics of the data to be stored (such as the date, month or year when the data to be stored is generated, etc.) and data characteristics (such as the type of data to be stored, the source region, etc.), and generate a two-dimensional hash index value of the data table where the data to be stored is located based on the time characteristics and data characteristics, and store the index value in the two-dimensional hash index table. Later, when the user inputs the time characteristics and data characteristics of the data to be stored, the system can calculate the two-dimensional hash index value of the data table that the user needs to find based on these two characteristics, and find the storage location of the data table corresponding to the two-dimensional hash index value from the two-dimensional hash index table, so as to quickly find the data table where the data to be stored is located from the database. Figure 3 The figure shows the storage structure of the database when the data feature is the source region of the data to be stored.

[0058] In one embodiment, after the data to be stored is written into the newly generated data table for the data to be stored, the first FPGA writes the data table into the memory. The CPU can monitor whether the data table in the memory meets the preset conditions. When the data table meets the preset conditions, the CPU writes the data table into the database. This is because the external device usually needs to write to a certain data table multiple times in succession when storing, so the data table can be temporarily stored in the memory as a memory table, which is convenient for the first FPGA to call the data table when storing data. The preset conditions can be set by the external device and transmitted to the CPU. For example, when the external device requires that the data of each month is written into the same table, if the data to be stored transmitted by the external device to the system is changed from the data of a certain month to the data of the next month, the CPU can consider that the data of a certain month has been transmitted, and convert the data table corresponding to the data of a certain month into a pre-stored table, and then write the pre-stored table into the storage device where the database is located when the conditions for the pre-stored table to be stored in the database are also met.

[0059] In one embodiment, the CPU determines the business type corresponding to the data to be stored, and determines the number of database connections and the database storage engine according to the business type. The external device can transmit the business type to the CPU, and the CPU can pre-store the maximum number of database connections corresponding to the business type and the database storage engine corresponding to the business type, and according to the above-mentioned pre-stored data, the number of connections to the database is set according to the maximum number of database connections, and the storage engine used when performing storage operations on the database is set according to the database storage engine corresponding to the business type. For example, in the case where the database is a MySQL database, the storage engines supported by the MySQL database may include InnoDB or MyISAM. The InnoDB storage engine is suitable for the resource configuration library, supports transactions, row-level locks, and foreign keys, and the MyISAM storage engine is suitable for the historical query library, which has a higher insertion and query speed, but does not support transactions and foreign keys. The technician can determine the storage engine corresponding to the business type in advance according to the characteristics of the business, and the CPU then selects InnoDB or MyISAM as the storage engine used when writing data to the database.

[0060] In one embodiment, Figure 4 As shown, the system also includes a second FPGA. The first FPGA is also used to determine the first data required to execute the target operation instruction according to the target operation instruction, and send a first data retrieval request to the second FPGA based on the first data; the second FPGA is used to retrieve the original data corresponding to the first data from the memory and / or database according to the first data retrieval request, decompress and / or decrypt the original data to obtain the first data, and send the first data to the first FPGA.

[0061] In an embodiment of the present application, since the data in the database may be compressed or encrypted, a second FPGA may be set to specifically decompress or decrypt the first data. In this case, the first FPGA can be programmed as an FPGA dedicated to executing operation instructions, and the second FPGA can be programmed as an FPGA dedicated to decompressing or decrypting data, thereby utilizing the FPGA's strong ability to perform a single task to further improve the efficiency of operating the database. After determining the first data, the first FPGA sends the first data to be retrieved to the second FPGA. The second FPGA is responsible for reading the compressed or encrypted original data corresponding to the first data from the memory or database, decompressing or decrypting the original data to obtain the first data, and returning the first data to the first FPGA, so that the first FPGA can execute the target operation instruction according to the first data.

[0062] In one embodiment, Figure 5As shown, the system also includes a second GPU; the first FPGA is also used to determine the complexity of the target operation instruction, and when the complexity is greater than the complexity threshold, the target operation instruction is sent to the second GPU; the second GPU is used to execute the target operation instruction sent by the first FPGA. In the embodiment of the present application, a second GPU can be set in the system to accelerate the processing of complex operation instructions. The complexity can be determined according to the number of first data required for the target operation instruction or the length of the target operation instruction. The more the number of first data required for the target operation instruction and the longer the length of the target operation instruction, the higher the complexity of the operation instruction. When the complexity of the target operation instruction is greater than the threshold, the first FPGA forwards the target operation instruction to the second GPU, and the second GPU executes the target operation instruction. The second GPU can also send the target operation instruction to the first GPU so that the first GPU predicts the required data according to the target operation instruction, and can also send a first data retrieval request to the second FPGA so that the second FPGA sends the decompressed or decrypted first data to the second GPU.

[0063] In one embodiment, Figure 6 As shown, the memory is DDR memory, and the system also includes a DMA (Direct Memory Access) controller and a Nand-flash memory. The CPU is also used to obtain target operation instructions and write the target operation instructions to the DDR memory through the DMA controller and the Nand-flash memory. The first FPGA and the CPU can both read and write data from the DDR memory.

[0064] In one embodiment, Figure 7 As shown, a data processing method for a database is provided. In the embodiment of the present application, the method is applied to Figure 1 The first GPU in the data processing system for the database is described, including:

[0065] Step 702, receiving a target operation instruction sent by the first FPGA;

[0066] Step 704, predicting the required data of the first FPGA according to the target operation instruction and the preceding operation instruction of the target operation instruction;

[0067] Step 706 , feeding back the demand data to the CPU, so that the CPU determines the target data according to the demand data, obtains the target data from the database, and writes the target data into the memory.

[0068] In the embodiment of the present application, after receiving the target operation instruction for the database sent by the first FPGA, the first GPU can predict the required data required for the subsequent execution of the instruction by the system according to the target operation instruction and the preceding operation instruction of the target operation instruction, and send the required data to the CPU, so that the CPU determines the target data actually required to be written into the memory according to the required data, obtains the target data from the database, and writes the target data into the memory, so that when the operation instruction is subsequently executed, the first FPGA can obtain the first data required for the operation instruction from the memory instead of the database, thereby speeding up the operation speed for the database. The specific execution method of each step can refer to the relevant description of the aforementioned embodiment, and the embodiment of the present application will not be repeated.

[0069] In the data processing method for a database provided in an embodiment of the present application, the GPU predicts the data that needs to be retrieved from the database in the future based on the currently executed operation instruction and the previous operation instruction executed previously, so that the CPU can determine the target data that needs to be written to the memory with a higher read / write rate from the predicted demand data, so that the FPGA can read the required target data from the memory when the operation instruction is executed subsequently, thereby improving the efficiency of operations on the database.

[0070] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0071] Based on the same inventive concept, the embodiment of the present application also provides a data processing device for a database for implementing the data processing method for a database involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the one or more data processing device embodiments for a database provided below can refer to the limitations of the data processing method for a database above, and will not be repeated here.

[0072] In one embodiment, Figure 8As shown, a data processing device 800 for a database is provided. The data processing system for a database includes a first FPGA, a first GPU, a CPU and a memory. The first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database. The device is applied to the first GPU and includes: a receiving module 802, a prediction module 804 and a feedback module 806, wherein:

[0073] A receiving module 802 is used to receive the target operation instruction sent by the first FPGA;

[0074] A prediction module 804, configured to predict the required data of the first FPGA according to the target operation instruction and a preceding operation instruction of the target operation instruction;

[0075] The feedback module 806 is used to feed back the demand data to the CPU, so that the CPU determines the target data according to the demand data, obtains the target data from the database, and writes the target data into the memory.

[0076] In the data processing device for a database provided in an embodiment of the present application, the GPU predicts the data that needs to be retrieved from the database in the future based on the currently executed operation instruction and the previous operation instruction executed previously, so that the CPU can determine the target data that needs to be written to the memory with a higher read-write rate from the predicted demand data, so that the FPGA can read the required target data from the memory when the operation instruction is executed subsequently, thereby improving the efficiency of operations on the database.

[0077] Each module in the above device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module above.

[0078] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0079] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0080] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0081] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0082] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data processing system for a database, characterized in that: The system includes a first FPGA, a first GPU, a CPU and a memory, wherein: The first FPGA is used to obtain a target operation instruction for a database, send the target operation instruction to the first GPU, and read first data required to execute the target operation instruction from the memory and / or the database; The first GPU is used to predict the required data of the first FPGA according to the target operation instruction and the preceding operation instruction of the target operation instruction, and feed the required data back to the CPU; The CPU is used to determine target data according to the demand data, obtain the target data from the database, and write the target data into the memory.

2. The system according to claim 1, characterized in that The step of reading the first data required for executing the target operation instruction from the memory and / or the database includes: The first data required for executing the target operation instruction is read from the memory, and when the first data does not exist in the memory, the first data is read from the database.

3. The system according to claim 1, characterized in that The first FPGA is also used to determine a first target operation instruction from the multiple operation instructions when multiple operation instructions for the database are obtained, merge the first target operation instructions to obtain a merged instruction, and use the merged instruction and the instructions in the multiple operation instructions except the first target operation instruction as the target operation instruction.

4. The system according to claim 1, characterized in that There are multiple demand data, and the demand data have a corresponding prediction call order; and determining the target data according to the demand data includes: Determine the historical prediction accuracy of the first GPU for each of the prediction call sequences, and determine a target prediction call sequence from each of the prediction call sequences according to the historical prediction accuracy; The demand data corresponding to the target prediction calling sequence is used as the target data.

5. The system according to claim 4, characterized in that The demand data is obtained by prediction through a data prediction model; The CPU is further configured to determine, within an accuracy evaluation cycle, for any of the predicted call sequences, a historical prediction accuracy corresponding to the predicted call sequence according to each target demand data corresponding to the predicted call sequence and actual demand data of the first FPGA corresponding to each target demand data; The CPU is further configured to feed back each of the actual demand data to the first GPU when the historical prediction accuracy corresponding to each of the prediction call sequences does not meet a preset accuracy requirement; The first GPU is further configured to adjust the data prediction model according to each of the actual demand data.

6. The system according to claim 1, characterized in that The first FPGA is also used to generate a data table for the data to be stored when the target operation instruction is a storage instruction, and determine the time characteristics and data characteristics of the data to be stored, generate a two-dimensional hash index value of the data table according to the time characteristics and the data characteristics, and store the two-dimensional hash index value in the two-dimensional hash index table for the database.

7. The system according to claim 1, characterized in that The system also includes a second FPGA; The first FPGA is further used to determine first data required to execute the target operation instruction according to the target operation instruction, and send a first data retrieval request to the second FPGA based on the first data; The second FPGA is used to retrieve the original data corresponding to the first data from the memory and / or the database according to the first data retrieval request, decompress and / or decrypt the original data to obtain the first data, and send the first data to the first FPGA.

8. The system according to claim 1, characterized in that The system also includes a second GPU; The first FPGA is further used to determine the complexity of the target operation instruction, and send the target operation instruction to the second GPU if the complexity is greater than a complexity threshold; The second GPU is used to execute the target operation instruction sent by the first FPGA.

9. A data processing method for a database, characterized in that: The data processing system for a database includes a first FPGA, a first GPU, a CPU, and a memory. The first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database. The method is applied to the first GPU and includes: Receiving the target operation instruction sent by the first FPGA; Predicting required data of the first FPGA according to the target operation instruction and a preceding operation instruction of the target operation instruction; The demand data is fed back to the CPU, so that the CPU determines the target data according to the demand data, obtains the target data from a database, and writes the target data into a memory.

10. A data processing device for a database, characterized in that: The data processing system for a database includes a first FPGA, a first GPU, a CPU and a memory, wherein the first FPGA reads first data required to execute a target operation instruction for the database from the memory and / or the database, and the device is applied to the first GPU, including: A receiving module, used for receiving the target operation instruction sent by the first FPGA; A prediction module, configured to predict the required data of the first FPGA according to the target operation instruction and a preceding operation instruction of the target operation instruction; The feedback module is used to feed back the demand data to the CPU, so that the CPU determines the target data according to the demand data, obtains the target data from the database, and writes the target data into the memory.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 9 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to claim 9 are implemented.

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