A method and device for synchronous simulation of small-step simulation machine of distribution network

Abstract

The present invention belongs to the technical field of distribution network operation, and specifically relates to a method and device for synchronous simulation of a distribution network small-step simulator, including: based on a distributed capacitance equivalent calculation method, the distribution network is divided into multiple line sub-partitions, each line sub-partition has at least one simulation machine, and the simulation step size of each simulation machine is not uniform; each line sub-partition is simulated in parallel according to a preset simulation time period and simulation step size based on its own simulation machine; in the process of collaborative parallel simulation: interpolation processing is performed on the data that needs to be interacted between simulation machines with different simulation rates; and / or, partition delay compensation is realized for line sub-partitions with partition delays in the form of compensation voltage signals; after the simulation is completed, the simulation results of each line sub-partition are merged. The technical solution provided by the present application realizes accurate simulation of the operating status of the distribution network, improves the simulation speed, and improves the accuracy and reliability of the simulation results.

Description

Technical Field

[0001] The invention belongs to the technical field of distribution network operation, and in particular relates to a distribution network small-step simulation machine synchronous simulation method and device. Background Art

[0002] At present, the distribution network has gradually developed into a hub platform that supports the large-scale access and coordinated operation of power electronic power sources / loads / equipment such as distributed new energy and electric vehicle charging and swapping stations. This means that the coupling interaction between power electronic equipment in the distribution network is stronger, the flexible resources are more dispersed and random, and the system stability control and power balance regulation are more difficult, which brings huge challenges to the distribution network model accuracy, simulation speed, algorithm effectiveness and other aspects. As a cutting-edge core technology and testing method in the research of new power systems, the real-time simulation technology of distribution networks can ensure that the physical / digital models of primary and secondary equipment such as lines, switches, fans, photovoltaics, and smart terminals are connected to the distribution network simulation system in a state that is highly consistent with the actual state, and accurately simulate the operating state of the distribution network. It has become an important platform for research related to new power systems.

[0003] The small-step real-time simulation of the distribution network can simulate dynamic processes such as distribution network faults and distributed power supply on / off-grid through accurate models and smaller simulation steps. It has the advantages of high simulation accuracy and good real-time performance. It is an important means to realize distribution network planning verification, operation analysis, intelligent decision-making and equipment detection.

[0004] At present, one development direction of small-step real-time simulation is to consider that the scale of simulation is affected by simulation step and computing resources, and to simplify the model, reduce the dimension and order, and use the method of increasing step to simulate by averaging or equivalence of the detailed model of complex distribution network, ignoring the high-frequency content in the model, so as to achieve the scale of real-time simulation under certain computing resources. However, the essence of this method is to improve the scale of real-time simulation of complex active distribution network by reducing the amount of calculation and the complexity of calculation, and its disadvantage is that the simulation accuracy will be reduced accordingly.

[0005] The improvement of distribution network simulation accuracy depends on the accuracy of the simulation model on the one hand, and on the choice of simulation step size on the other hand. The more accurate the simulation model is, the smaller the corresponding simulation calculation step size is, and the more accurate the simulation results are. In small-step real-time simulation, the amount of calculation is huge due to the small simulation step size. In order to maintain the real-time performance of the simulation, the scale of the simulation is drastically reduced, which is also a pain point that has not been solved in real-time simulation.

[0006] Another development direction of small-step real-time simulation is to partition and decouple complex distribution networks. By placing distribution networks in different partitions on different CPUs or FPGA cores of the same simulation machine board for calculation, the scale of small-step real-time simulation of complex distribution networks can be expanded through parallel computing. However, the resources of a single small-step simulation machine are limited and cannot meet the ever-expanding demand for distribution network simulation scale.

[0007] Huang Wei, Pang Lin, Cao Bin and Hua Liangliang published the distributed parallel computing of distribution network state estimation based on partition decoupling, which belongs to the long transmission line partition decoupling technology. However, the disadvantage of long transmission partition decoupling technology is that it requires relatively long branchless and segmented power supply lines in the power grid. For medium and low voltage distribution networks, the power supply lines are relatively short and have multiple segments and multiple connections. Especially for low voltage distribution networks, the power supply lines are often only a few hundred meters long, which is not suitable for long transmission partition decoupling and easily causes large errors.

[0008] The fully digital real-time simulation device for power systems published by Tian Fang, Li Yalou, Zhou Xiaoxin, Wu Zhongxi and Zhang Xing belongs to a single-rate simulation technology with a fixed step size. The fixed-step simulation strategy, such as setting the simulation step size to 50 microseconds, means that a numerical calculation is performed on the simulated power grid every 50 microseconds to obtain the simulation results of the entire network. During the entire simulation process, the simulation step size no longer changes. The traditional fixed-step simulation method is a simulation mode with a single simulation rate. The same simulation step size is used for different distribution networks. The differentiated requirements for simulation step sizes of distribution networks in different regions are not taken into account. As a result, a small step size is used in areas that can be simulated with a large step size, and a larger step size is used in areas that need a small step size. On the one hand, this causes a decrease in simulation speed, and on the other hand, it is easy to cause a decrease in simulation accuracy due to unreasonable step size selection.

[0009] The small-step real-time simulation method considering the loss characteristics of the converter published by Su Hang, Xu Jin, Wang Keyou, Xu Peng and Wu Pan belongs to the real-time simulation technology of a single simulator. The real-time simulation technology of a single simulator uses a single simulator to implement simulation calculations, optimization algorithms, real-time scheduling strategies and data exchange, and utilizes the performance computing resources, computing algorithms, real-time task scheduling and data transmission of a single simulator to respond to real-time simulation needs. However, the real-time simulation technology of a single simulator has the following disadvantages: (1) Computing resource limitations: The computing power and storage capacity of a single simulator are limited, and may not meet the requirements of complex simulation models and large-scale simulation tasks, resulting in slow simulation speed or inability to process in real time; (2) Data transmission delay: In real-time simulation, the network bandwidth and transmission speed of a single simulator may not meet the requirements of real-time simulation, resulting in increased data transmission delay and affecting real-time response capabilities; (3) Hardware equipment cost: To implement real-time simulation technology, it may be necessary to use high-performance computing resources and high-speed network equipment, which will increase the cost of hardware equipment. Summary of the invention

[0010] In order to overcome the problems existing in the above-mentioned related technologies, the present application provides a distribution network small-step simulation machine synchronous simulation method and device.

[0011] According to a first aspect of an embodiment of the present application, a distribution network small-step simulation machine synchronization simulation method is provided, comprising:

[0012] Based on the distributed capacitance equivalent calculation method, the distribution network is divided into multiple line sub-divisions, each line sub-division has at least one simulation machine, and the simulation step size of each simulation machine is not uniform;

[0013] Each of the line sub-divisions performs collaborative parallel simulation based on its own simulation machine according to a preset simulation time period and simulation step size;

[0014] During the collaborative parallel simulation: interpolation processing is performed on the data that needs to be interacted between simulation machines with different simulation rates; and / or, partition delay compensation is implemented for line sub-partitions with partition delays by means of compensating voltage signals;

[0015] After the simulation is completed, the simulation results of each line sub-partition are merged.

[0016] Preferably, the method for calculating the equivalent value of distributed capacitance divides the distribution network into a plurality of line sub-divisions, including:

[0017] Performing a network topology analysis on the distribution network to obtain the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure;

[0018] Dividing the distribution network into a plurality of initial partitions according to the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure;

[0019] Adding a short line equivalent model considering distributed capacitance between two adjacent initial partitions, and adjusting parameters of the short line equivalent model considering distributed capacitance;

[0020] The real-time simulation technology is used to simulate and verify the distribution network after being divided into multiple initial partitions. If the operating effect of the distribution network after being divided into multiple initial partitions is consistent with that of the distribution network before being divided into multiple initial partitions, the multiple initial partitions are the multiple line sub-partitions; otherwise, the distribution network is re-divided.

[0021] Preferably, the topological structure of the short line equivalent model considering distributed capacitance includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a first inductor, a second inductor and a third inductor;

[0022] The first resistor, the first inductor, the second resistor, the second inductor, the third resistor and the third inductor are sequentially connected in series on a transmission line connected between two adjacent line sub-divisions;

[0023] One end of the first capacitor is connected to a connection point between the first inductor and the second resistor, and the other end is grounded;

[0024] One end of the second capacitor is connected to a connection point between the second inductor and the third resistor, and the other end is grounded.

[0025] Preferably, the process of obtaining the preset simulation step length of each simulation machine includes:

[0026] The simulation step size of the simulator in the line sub-division without fast-changing power electronic equipment is set to the first simulation step size, and the simulation step size of the simulator in the line sub-division with a preset number of photovoltaic grid-connected inverters is set to the second simulation step size;

[0027] The first simulation step size is smaller than the second simulation step size.

[0028] Preferably, each of the line sub-divisions performs collaborative parallel simulation based on its own simulation machine according to a preset simulation time period and simulation step size, including:

[0029] Determine the number of simulation machines for each line sub-partition and the preset simulation rate of each simulation machine according to the simulation requirements;

[0030] Allocate the preset simulation models of each line sub-division to the corresponding simulation machines;

[0031] The respective simulation machines in each line sub-division perform collaborative parallel simulation according to a preset simulation time period, a preset simulation step size and a preset simulation rate.

[0032] Preferably, the interpolation processing of the data to be interacted between the simulation machines with different simulation rates includes:

[0033] When at t n At the moment [t n-2 , t n-1 ]Simulation results within the time step x n-1 and in [t n-1 , t n ]Simulation results within the time step x n The second simulation machine transmits its own [t n-1 , t n ]Simulation results within the time step yn , where n is a positive integer;

[0034] In [t n , t n+1 ] time step, the first simulation machine uses the simulation result y of the second simulation machine n Perform a simulation calculation;

[0035] In [t n , t n+1 ] time step, the second simulator uses the external system state quantity x n-1 and x n Performing interpolation to obtain a plurality of external system state quantities, and performing multiple iterative calculations using the plurality of external system state quantities;

[0036] Among them, t n For the tth n Time, t n-2 For the tth n-2 Time, t n-1 For the tth n-1 Time, t n+1 For the tth n+1 time.

[0037] Preferably, the method of implementing partition delay compensation for line sub-partitions with partition delay by means of compensating voltage signals includes:

[0038] An orthogonal signal generator based on second-order orthogonal integration is used to process the voltage sampling signal of the physical side of the digital-analog hybrid simulation system in the simulation model of each preset short-circuit partition to obtain a pair of orthogonal voltage signals of equal amplitude;

[0039] Performing compensation calculation on the orthogonal voltage signal to obtain a compensated voltage signal;

[0040] The compensation voltage signal is input into the simulator in each short line partition to obtain a signal without phase delay.

[0041] Preferably, before each of the line sub-partitions performs collaborative parallel simulation based on their respective simulation machines according to a preset simulation time period and simulation step, the method further comprises:

[0042] Each line sub-division adopts an array interconnection simulation method based on an optical fiber network card to connect between simulation machines.

[0043] Preferably, each line sub-division adopts an array interconnection simulation method based on a fiber optic network card to connect the simulation machines, including:

[0044] Use optical fiber network cards to interconnect the simulation machines and set the communication protocols between the simulation machines;

[0045] The data of each simulation machine is transmitted to the preset FIFO queue through the optical fiber network card in a stream manner;

[0046] During the simulation process, each simulation machine exchanges data between simulation machines by reading and writing FIFO queues.

[0047] Preferably, the collaborative parallel simulation is performed using a real-time simulation method based on a CPU-FPGA hybrid step size and a hardware-in-the-loop simulation technology.

[0048] Preferably, the simulation requirements include at least the following two: time resolution and simulation time span.

[0049] Preferably, the calculation formulas for the multiple external system state quantities include:

[0050] x n,k =x n-1 +[(k-1) / m]( x n -x n-1 )

[0051] In the above formula, k∈[1,m], m is the total number of interpolation iterations; x n,k is the external system state quantity obtained by the kth interpolation, x n-1 For the first simulation machine in [t n-2 , t n-1 ]Simulation results within the time step, x n For the first simulation machine in [t n-1 , t n ]Simulation results within the time step.

[0052] According to a second aspect of an embodiment of the present application, there is provided a distribution network small-step simulation machine synchronization simulation device, comprising:

[0053] A partition unit is used to divide the distribution network into a plurality of line sub-partitions based on a distributed capacitance equivalent calculation method, each line sub-partition has at least one simulation machine, and the simulation step lengths of the simulation machines are not uniform;

[0054] A simulation unit, used for performing collaborative parallel simulation on each of the line sub-partitions based on respective simulation machines according to a preset simulation time period and simulation step size;

[0055] The processing unit is used for: performing interpolation processing on data that need to be interacted between simulation machines with different simulation rates during the collaborative parallel simulation; and / or realizing partition delay compensation for line sub-partitions with partition delay by means of compensating voltage signals;

[0056] The merging unit is used to merge the simulation results of each line sub-partition after the simulation is completed.

[0057] Preferably, the partition unit is specifically used for:

[0058] Performing a network topology analysis on the distribution network to obtain the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure;

[0059] Dividing the distribution network into a plurality of initial partitions according to the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure;

[0060] Adding a short line equivalent model considering distributed capacitance between two adjacent initial partitions, and adjusting parameters of the short line equivalent model considering distributed capacitance;

[0061] The real-time simulation technology is used to simulate and verify the distribution network after being divided into multiple initial partitions. If the operating effect of the distribution network after being divided into multiple initial partitions is consistent with that of the distribution network before being divided into multiple initial partitions, the multiple initial partitions are the multiple line sub-partitions; otherwise, the distribution network is re-divided.

[0062] Preferably, the topological structure of the short line equivalent model considering distributed capacitance includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a first inductor, a second inductor and a third inductor;

[0063] The first resistor, the first inductor, the second resistor, the second inductor, the third resistor and the third inductor are sequentially connected in series on a transmission line connected between two adjacent line sub-divisions;

[0064] One end of the first capacitor is connected to a connection point between the first inductor and the second resistor, and the other end is grounded;

[0065] One end of the second capacitor is connected to a connection point between the second inductor and the third resistor, and the other end is grounded.

[0066] Preferably, the device further comprises: a determination unit, configured to obtain a preset simulation step length of each simulation machine;

[0067] The determining unit is specifically configured to:

[0068] The simulation step size of the simulator in the line sub-division without fast-changing power electronic equipment is set to the first simulation step size, and the simulation step size of the simulator in the line sub-division with a preset number of photovoltaic grid-connected inverters is set to the second simulation step size;

[0069] The first simulation step size is smaller than the second simulation step size.

[0070] Preferably, the simulation unit comprises:

[0071] A determination module, used to determine the number of simulation machines in each line sub-partition and the preset simulation rate of each simulation machine according to the simulation requirements;

[0072] An allocation module, used for allocating the preset simulation models of each line sub-division to the corresponding simulation machines;

[0073] The simulation module is used for the respective simulation machines in each line sub-division to perform collaborative parallel simulation according to a preset simulation time period, a preset simulation step size and a preset simulation rate.

[0074] Preferably, the processing unit comprises:

[0075] Interpolation module, used when t n At the moment [t n-2 , t n-1 ]Simulation results within the time step x n-1 and in [t n-1 , t n ]Simulation results within the time step x n The second simulation machine transmits its own [t n-1 , t n ]Simulation results within the time step y n , where n is a positive integer;

[0076] In [t n , t n+1 ] time step, the first simulation machine uses the simulation result y of the second simulation machine n Perform a simulation calculation;

[0077] In [t n , t n+1 ] time step, the second simulator uses the external system state quantity x n-1 and x n Performing interpolation to obtain a plurality of external system state quantities, and performing multiple iterative calculations using the plurality of external system state quantities;

[0078] Among them, t n For the tth n Time, t n-2 For the tth n-2 Time, t n-1 For the tth n-1 Time, t n+1 For the tth n+1 time.

[0079] Preferably, the processing unit comprises:

[0080] The compensation module is used to process the voltage sampling signal of the physical side of the digital-analog hybrid simulation system in the simulation model of each preset short line partition by using an orthogonal signal generator based on second-order orthogonal integration to obtain a pair of orthogonal voltage signals of equal amplitude;

[0081] Performing compensation calculation on the orthogonal voltage signal to obtain a compensated voltage signal;

[0082] The compensation voltage signal is input into the simulator in each short line partition to obtain a signal without phase delay.

[0083] Preferably, the device further comprises:

[0084] The connection unit is used to connect the simulation machines by using an array interconnection simulation method based on an optical fiber network card to divide the line sub-partitions.

[0085] Preferably, the connecting unit is specifically used for:

[0086] Use optical fiber network cards to interconnect the simulation machines and set the communication protocols between the simulation machines;

[0087] The data of each simulation machine is transmitted to the preset FIFO queue through the optical fiber network card in a stream manner;

[0088] During the simulation process, each simulation machine exchanges data between simulation machines by reading and writing FIFO queues.

[0089] Preferably, the collaborative parallel simulation is performed using a real-time simulation method based on a CPU-FPGA hybrid step size and a hardware-in-the-loop simulation technology.

[0090] Preferably, the simulation requirements include at least the following two: time resolution and simulation time span.

[0091] Preferably, the calculation formulas for the multiple external system state quantities include:

[0092] x n,k =x n-1 +[(k-1) / m]( x n -x n-1 )

[0093] In the above formula, k∈[1,m], m is the total number of interpolation iterations; x n,k is the external system state quantity obtained by the kth interpolation, x n-1 For the first simulation machine in [t n-2 , t n-1 ]Simulation results within the time step, x n For the first simulation machine in [tn-1 , t n ]Simulation results within the time step.

[0094] According to a third aspect of an embodiment of the present application, there is provided an electronic device, comprising: at least one processor and a memory; the memory and the processor are connected via a bus;

[0095] The memory is used to store one or more programs;

[0096] When the one or more programs are executed by the at least one processor, the distribution network small-step simulator synchronous simulation method is implemented.

[0097] According to a fourth aspect of an embodiment of the present application, a readable storage medium is provided, on which an execution program is stored. When the execution program is executed, the distribution network small-step simulation machine synchronous simulation method is implemented.

[0098] The technical solution provided by the present invention has the following beneficial effects:

[0099] The present invention provides a method and device for synchronous simulation of a distribution network with a small-step simulator. The method divides the distribution network into a plurality of line sub-partitions based on a distributed capacitance equivalent calculation method. Each line sub-partition has at least one simulation machine. The simulation step of each simulation machine is not uniform. Each line sub-partition performs collaborative parallel simulation based on its own simulation machine according to a preset simulation time period and simulation step. In the process of collaborative parallel simulation: interpolation processing is performed on data that needs to be interacted between simulation machines with different simulation rates; and / or, partition delay compensation is realized for line sub-partitions with partition delays in the form of a compensation voltage signal. After the simulation is completed, the simulation results of each line sub-partition are merged, thereby realizing accurate simulation of the operating state of the distribution network, improving the simulation speed, and improving the accuracy and reliability of the simulation results. BRIEF DESCRIPTION OF THE DRAWINGS

[0100] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0101] Figure 1 It is a flow chart of a method for synchronous simulation of a distribution network small-step simulation machine provided by an embodiment of the present invention;

[0102] Figure 2 is a schematic diagram of a short line equivalent calculation model considering distributed capacitance provided by an embodiment of the present invention;

[0103] Figure 3 is a schematic diagram of an equivalent model of two ends of a short line of a distribution network considering distributed capacitance provided by an embodiment of the present invention;

[0104] Figure 4 It is a schematic diagram of the partition decoupling result of the power distribution short line provided by an embodiment of the present invention;

[0105] Figure 5 It is a schematic diagram of multi-simulation machine collaborative multi-rate parallel simulation provided by an embodiment of the present invention;

[0106] Figure 6 is a schematic diagram of multi-simulation machine collaborative simulation based on multiple interpolation method provided by an embodiment of the present invention;

[0107] Figure 7 is a schematic diagram of partition interface delay provided by an embodiment of the present invention;

[0108] Figure 8 is a schematic diagram of the second-order orthogonal integration principle provided by an embodiment of the present invention;

[0109] Fig. 9 is a schematic diagram of an orthogonal signal generator based on second-order orthogonal integration provided by an embodiment of the present invention;

[0110] Fig.10 is a schematic diagram of a CPU-FPGA mixed step size simulation provided by an embodiment of the present invention;

[0111] Fig.11 It is a schematic diagram of a CPU-FPGA hybrid step-size simulation system based on optical fiber network card array interconnection provided by an embodiment of the present invention;

[0112] Fig.12 It is a schematic diagram of hardware-in-the-loop simulation of a distribution network intelligent terminal provided by an embodiment of the present invention;

[0113] Fig.13 It is a flow chart of a method for synchronous simulation of a distribution network small-step simulation machine provided by an embodiment of the present invention;

[0114] Fig.14 It is a structural block diagram of a synchronous simulation device for a small-step simulation machine of a distribution network provided by an embodiment of the present invention;

[0115] Fig.15 Is a block diagram of an electronic device provided by an embodiment of the present invention;

[0116] In the figure, C1 is the first capacitor, C2 is the second capacitor, R1 is the first resistor, R2 is the second resistor, R3 is the third resistor, L1 is the first inductor, L2 is the second inductor, and L3 is the third inductor. DETAILED DESCRIPTION

[0117] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the following embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0118] Embodiment 1

[0119] The present invention provides a distribution network small step size simulation machine synchronization simulation method, such as Figure 1 As shown, the following steps are included:

[0120] Step 101: Based on a distributed capacitance equivalent calculation method, the distribution network is divided into a plurality of line sub-divisions, each line sub-division has at least one simulation machine, and the simulation step lengths of the simulation machines are not uniform;

[0121] Step 102: each line sub-division performs collaborative parallel simulation based on its own simulation machine according to a preset simulation time period and simulation step size;

[0122] Step 103: during the collaborative parallel simulation: interpolation processing is performed on the data that needs to be interacted between the simulation machines with different simulation rates; and / or, partition delay compensation is implemented for the line sub-partitions with partition delay in the form of compensation voltage signals;

[0123] Step 104: After the simulation is completed, the simulation results of each line sub-partition are merged.

[0124] It can be understood that real-time simulation: refers to executing simulation tasks in real time, simulating the dynamic behavior of the system in a real-time environment, and reflecting the real-time response and evolution of the system under specific conditions;

[0125] In some embodiments, after each simulation machine completes the simulation task, all simulation results are merged and an overall performance analysis is performed to optimize and improve the system; based on the simulation results and analysis, the system model or simulation parameters are adjusted and optimized.

[0126] Small-step real-time simulation: A real-time simulation technique used to simulate system dynamics with precise small simulation steps.

[0127] The present invention divides the system into different sub-areas through partition decoupling, thereby decoupling the system, simplifying the system model and improving the simulation efficiency.

[0128] The basis for realizing parallel simulation of distribution network through multiple simulation machines is how to partition and decouple the distribution network. In the transmission network, the long transmission line partition decoupling method is generally adopted, which uses the time delay of electromagnetic waves on long transmission lines to be greater than the simulation step size, thereby realizing decoupling between different partitions. Since there are no long transmission lines in the distribution network, the long transmission line step delay decoupling method commonly used in the transmission network cannot be adopted. The present invention proposes a distribution network short line partition decoupling method based on distributed capacitance equivalent calculation for the distribution network. Further, step 101 includes:

[0129] Step 1011: performing a network topology analysis on the distribution network to obtain the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure;

[0130] Step 1012: dividing the distribution network into a plurality of initial partitions according to the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure;

[0131] Step 1013: adding a short line equivalent model considering distributed capacitance between two adjacent initial partitions, and adjusting parameters of the short line equivalent model considering distributed capacitance;

[0132] Step 1014: Use real-time simulation technology to simulate and verify the distribution network after being divided into multiple initial partitions. If the operating effect of the distribution network after being divided into multiple initial partitions is consistent with that of the distribution network before being divided into multiple initial partitions, the multiple initial partitions are divided into multiple line sub-partitions; otherwise, the distribution network is re-divided.

[0133] In some embodiments, the overall network structure of the distribution network may include but is not limited to: the location of equipment such as lines, transformers and switches, and the connection relationship between each distribution network equipment in the overall network structure may include but is not limited to: the connection method of equipment such as lines, transformers, switches, etc.

[0134] In some embodiments, the distribution network can be divided into multiple short-line partitions based on, but not limited to, network topology, load distribution, and line analysis results. The principle of division can be considered based on factors such as load density, network topology, and equipment capacity. Generally, the areas are divided on an equal basis, aiming to make the system in each partition relatively independent and able to achieve parallel segmentation.

[0135] It should be noted that the method of "adjusting the parameters of the short line equivalent model taking into account the distributed capacitance" involved in the embodiments of the present invention is well known to those skilled in the art. Therefore, its specific implementation method will not be described in detail. In some embodiments, the parameters of the short line equivalent model taking into account the distributed capacitance are adjusted based on the principle that the model can operate stably.

[0136] It can be understood that the real-time simulation technology is used to simulate and verify the divided distribution network and evaluate the effect of partition decoupling. The model can operate stably to ensure that the safety and reliability of the system are improved.

[0137] Further, such as Figure 2 As shown, the topological structure of the short line equivalent model considering distributed capacitance includes: a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a first inductor L1, a second inductor L2 and a third inductor L3;

[0138] A first resistor R1, a first inductor L1, a second resistor R2, a second inductor L2, a third resistor R3 and a third inductor L3 are sequentially connected in series on a transmission line connected between two adjacent short line partitions;

[0139] One end of the first capacitor C1 is connected to the connection point between the first inductor L1 and the second resistor R2, and the other end is grounded;

[0140] One end of the second capacitor C2 is connected to a connection point between the second inductor L2 and the third resistor R3 , and the other end is grounded.

[0141] The present invention proposes a distribution network short-line partition decoupling technology, which realizes network segmentation and decoupling between different partitions under a short power supply radius of a medium and low voltage distribution network.

[0142] In the distribution network, due to the low voltage level, the resistance and inductance are on the same order of magnitude, and the existence of resistance cannot be ignored. In addition, since the lines in the distribution network are not as long as the main grid transmission lines, the parallel simulation method using the main grid distributed parameter line decoupling may not converge in the distribution network simulation. Assuming that the length of the transmission line is x, the principle of distributed parameter line decoupling is simplified as follows: Figure 2 As shown, Figure 2 The wave equation for includes:

[0143] (1)

[0144] In the above formula, u is the line voltage, i is the line current, L0 is the line reactance, t is the time, R0 is the line resistance, C0 is the line capacitance, and G0 is the line conductance;

[0145] Assume that the propagation speed of the traveling wave is v and the characteristic impedance during the traveling wave transmission is Z c According to the principle of traveling wave propagation:

[0146] (2)

[0147] In the above formula, L is the line reactance and C is the line capacitance;

[0148] According to the fixed-step parallel simulation principle, in multi-core parallelism, there will be a step delay of Δt between cores. The following is an analysis of the wave equation with two cores as the object. Assuming that the traveling wave propagates forward at a speed of v, f1(x-vΔt) is the minimum time for the traveling wave to propagate forward, that is, the solution of one step propagation time, and f2(x+vΔt) is the minimum time for the traveling wave to propagate backward, that is, the solution of one step propagation time. The solution is described by the voltage and current equation as follows:

[0149] (3)

[0150] In the above formula, i(x,t) is the line current at time t, and u(x,t) is the line voltage at time t;

[0151] From the perspective of the backward propagation of the traveling wave, multiply both sides of the current equation by Zc and subtract them from the voltage equation to obtain equation (4):

[0152] (4)

[0153] From the perspective of the forward propagation of the traveling wave, multiply both sides of the current equation by Zc and add them to the voltage equation to obtain equation (5):

[0154] (5)

[0155] If the distance of the distributed parameter line is set to l, whether it is propagating forward or backward, the propagation time can be considered constant, that is, x+vΔt and x-vΔt are constants, then the transmission time from the beginning to the end is:

[0156] (6)

[0157] In multi-core parallel simulation, there is a step delay Δt between multi-core CPUs. Assuming that the transmission time in the distributed parameter line is Δt, the voltage at both ends of the distributed parameter line can be obtained:

[0158] (7)

[0159] In the above formula, u i (t-Δt) is the voltage signal at the partition after delay, i i (t-Δt) is the current signal at the partition after delay, u j (t) is the voltage signal at the partition at time t, i j (t) is the current signal at the partition at time t.

[0160] The negative sign on the right side of the equation indicates that the traveling wave propagates forward, and t-Δt indicates that the CPU operation time lags behind by one step, that is, within the operation time of this step, the data of the cutting point is the data of the previous step of the core connected to it.

[0161] like Figure 3 As shown in the figure, the equivalent model of the two ends of the distributed parameter line has no direct connection between the two ends. The electrical quantities at the two ends are exchanged through current data sharing. According to formula (7), the decoupling method of short-line partition of distribution network based on distributed capacitance equivalent calculation can achieve decoupling in simulation calculation.

[0162] For example, Figure 4 As shown, by utilizing the short-circuit partition decoupling method proposed in the present invention, the target distribution network can be divided into two different areas, thereby laying a foundation for parallel calculation of different partitions on different simulation machines. In the figure, numbers 0-32 represent the node numbers of the loads.

[0163] Furthermore, the process of obtaining the preset simulation step length of each simulation machine includes:

[0164] The simulation step size of the simulator in the line sub-division without fast-changing power electronic equipment is set to the first simulation step size, and the simulation step size of the simulator in the line sub-division with a preset number of photovoltaic grid-connected inverters is set to the second simulation step size;

[0165] The first simulation step size is smaller than the second simulation step size.

[0166] The present invention proposes a multi-rate parallel simulation technology with coordinated large and small step sizes, which achieves a significant improvement in the parallel acceleration ratio through the selection and adaptation of large and small step sizes between multiple simulation machines and parallel computing between different simulation machines.

[0167] After completing the decoupling of distribution network partitions, the second problem is how to implement simulation calculations between different partitions. Usually, power system simulation uses a unified fixed step size for simulation calculations between two partitions. Since different partitions are simulated in parallel, the speed of simulation can be improved. However, for real-time simulation calculations of large-scale distribution networks, there is still room for further improving simulation efficiency. The present invention proposes to use different step sizes for simulation calculations between different types of partitions. On the basis of parallel simulation calculations, the size of the simulation step size between different partitions is further coordinated. Compared with traditional parallel simulation methods, the advantages of multi-rate parallel simulation calculations are obtained, the simulation speed is greatly improved, and larger-scale distribution network simulation can be performed while meeting real-time requirements. Furthermore, step 102 includes:

[0168] Step 1021: Determine the number of simulation machines for each line sub-partition and the preset simulation rate of each simulation machine according to the simulation requirements;

[0169] Step 1022: assigning the preset simulation model of each line sub-division to its corresponding simulation machine;

[0170] Step 1023: The respective simulation machines in each line sub-division perform collaborative parallel simulation according to a preset simulation time period, a preset simulation step size and a preset simulation rate.

[0171] Furthermore, simulation requirements include at least the following two: time resolution and simulation time span.

[0172] In some other optional embodiments, the number of simulation machines is determined according to the simulation scale, and the simulation rate is determined according to the step size required for each part of the simulation.

[0173] Furthermore, in step 103, interpolation processing is performed on data that needs to be interacted between simulation machines with different simulation rates, including:

[0174] Step 1031: When t n At the moment, the simulation rate of the second simulation machine is different from the simulation rate of the first simulation machine, then the first simulation machine transmits its own [ t n-2 , t n-1 ]Simulation results within the time step x n-1 and in [ t n-1 , t n ]Simulation results within the time step x n , the second simulation machine transmits its own [ t n-1 , t n ]Simulation results within the time step y n , where n is a positive integer;

[0175] Step 1032: In [t n , t n+1 ] time step, the first simulation machine uses the simulation result y of the second simulation machine n Perform a simulation calculation;

[0176] Step 1033: In [t n , t n+1 ] time step, the second simulation machine uses the external system state x n-1 and x n Perform interpolation to obtain multiple external system state quantities, and perform multiple iterative calculations using the multiple external system state quantities;

[0177] Specifically, the calculation formulas for multiple external system state quantities include:

[0178] xn,k =x n-1 +[(k-1) / m]( x n -x n-1 )

[0179] In the above formula, k∈[1,m], m is the total number of interpolation iterations; x n,k is the external system state quantity obtained by the kth interpolation, x n-1 For the first simulation machine in [t n-2 , t n-1 ]Simulation results within the time step, x n For the first simulation machine in [t n-1 , t n ]Simulation results within the time step.

[0180] It is understandable that when the simulation rate of some simulators is different from that of other simulators, data exchange and synchronization are required, which can be achieved through interpolation technology, that is, interpolating data between different rates to ensure the consistency and continuity of simulation data.

[0181] For example, Figure 5 As shown, Figure 4 The simulation models of different partitions are loaded into different simulation machines. Partition 1 is a passive distribution network without fast-changing power electronic equipment, so the simulation step size T1 is used; Partition 2 is a distribution network with a large number of photovoltaic grid-connected inverters, which requires a smaller simulation step size for accurate simulation, and a small simulation step size T2 is used.

[0182] During the simulation, Figure 6 As shown, set T1=mT2, m is a positive integer, and [t n-1 ,t n ] The time step is divided into m equal parts to obtain { t n-1,1 , t n-1,2 , t n-1,3 ,…, t n-1,m ,}, t n-1,1 For the first copy, t n-1,2 For the second part, t n-1,3 For the third part, t n-1,m For the mth partition, partition 1 is in [t n ,t n+1 ]The simulation result within the time step is x n+1 , partition 2 in [t n-2 ,t n-1 ]The simulation result within the time step is y n-1 , partition 2 in [t n ,t n+1 ]The simulation result within the time step is y n+1 .

[0183] In tn At time [t n-2 ,t n-1 ]Simulation results within the time step x n-1 and in [t n-1 ,t n ]Simulation results within the time step x n ; Partition 2 passes itself to partition 1 in [t n-1 ,t n ]Simulation results within the time step y n . In [t n ,t n+1 ] time step, partition 1 uses the external system state y n Perform an iterative calculation; Partition 2 uses the external system state x n-1 and x n Interpolation is performed, and m external system state quantities {x n,1 ,x n,2 ,x n,3 ,……x n,m}, perform m iterations, where x n,1 is the external system state quantity obtained by the first interpolation, x n,2 is the external system state quantity obtained by the second interpolation, x n,3 is the external system state quantity obtained by the third interpolation, x n,m is the external system state quantity obtained by the mth interpolation.

[0184] x n,k =x n-1 +[(k-1) / m]( x n -x n-1 ) (8)

[0185] The external system data used by partition 2 in the simulation process lags behind partition 1 by one simulation step T1, but its data interaction process is still real-time. The interpolation method is used to update the external system state at the beginning of each short-step simulation time step, which can effectively eliminate the peaks of the voltage and current simulation waveforms, reduce non-characteristic harmonics, and play a role in smoothing the waveforms.

[0186] After completing the decoupling and partition calculation of the distribution network, the third problem is how to solve the asynchrony problem of different partitions caused by delays. The present invention mainly adopts distributed simulation synchronization technology, mainly by introducing a partition delay compensation mechanism in the system, dynamically adjusting the event execution delay of each partition according to the communication delay to ensure synchronization, and can adjust the event execution time according to the network delay, thereby avoiding the asynchrony problem. Based on the physical characteristics of the distribution network partitions, the second-order orthogonal integration method is used to perform partition delay compensation. Furthermore, in step 103, the partition delay compensation is realized for the line sub-partition with partition delay in the form of a compensation voltage signal, including:

[0187] Step 1034: adopt the second-order orthogonal integration method to realize partition delay compensation for the line sub-partitions with partition delay in the form of compensating voltage signals.

[0188] Further, step 1034 includes:

[0189] Step 10341: using an orthogonal signal generator based on second-order orthogonal integration to process the voltage sampling signals of the physical side of the digital-analog hybrid simulation system in the simulation models of each preset short line partition, to obtain a pair of orthogonal voltage signals of equal amplitude;

[0190] Specifically, the calculation formula of the orthogonal voltage signal includes:

[0191]

[0192] In the above formula, U' a is the voltage sampling signal on the physical side of the digital-analog hybrid simulation system, q is orthogonal, qU' a For U' a The orthogonal voltage signal, ω is the angular frequency of the digital-analog hybrid simulation system, U is the voltage amplitude on the digital side, t is the time, δ is the delay compensation angle, qU' a and cosδ are the pair of orthogonal voltage signals of equal amplitude;

[0193] Step 10342: performing compensation calculation on the orthogonal voltage signal to obtain a compensated voltage signal;

[0194] Specifically, the calculation formula of the compensation voltage signal includes:

[0195]

[0196] In the above formula, U'' a is the compensation voltage signal, δ is the delay compensation angle, U' a is the voltage sampling signal on the physical side of the digital-analog hybrid simulation system, q is orthogonal, qU' a For U' a The voltage signal after orthogonality.

[0197] Step 10343: Input the compensation voltage signal into the simulator in each short line partition to obtain a signal without phase delay.

[0198] For example, Figure 7~Figure 9 As shown, s is the s domain, T is the time, U1(s) is the original signal voltage (i.e. the signal voltage before delay), Us(s) is the power supply voltage of partition 1, Zs(s) is the impedance of partition 1, I1(s) is the current of partition 1, I2(s) is the current of partition 2, U2(s) is the signal voltage after delay, U H (s) is the power supply voltage of zone 2, Z H (s) is the impedance of partition 2, 1 / S is the integral link, u is the input voltage, v′ is the output voltage, qv′ is the output voltage orthogonal to v′, ε v is the difference between the input voltage and the output voltage. The second-order orthogonal integration method is used to compensate for the partition delay of the line sub-partition with partition delay by means of compensating voltage signals, including:

[0199] (1) An orthogonal signal generator based on second-order orthogonal integration is used to process the voltage sampling signals of the physical side (generally referring to the actual equipment) in the digital-analog hybrid simulation system in the simulation model of each preset short-circuit partition to obtain a pair of orthogonal voltage signals with equal amplitudes;

[0200] Since the delay compensation angle δ can be calculated based on the waveform pre-measured interface delay or calculated based on the preset interface delay, that is, sinδ and cosδ are known quantities, the key issue of voltage sampling delay compensation is that it does not rely on the grid voltage symmetry and obtains the voltage sampling U a1 The orthogonal vector qU' a , then:

[0201] U a1 =U' a =Ucos(ωt)(9)

[0202] (10)

[0203] Specifically, the calculation formula of the orthogonal voltage signal includes:

[0204] (11)

[0205] In the above formula, U' a is the voltage sampling signal on the physical side of the digital-analog hybrid simulation system, q is orthogonal, qU' a For U' a The orthogonal voltage signal, ω is the angular frequency of the digital-analog hybrid simulation system, U is the voltage amplitude on the digital side, t is the time, δ is the delay compensation angle, qU'a and cosδ are a pair of orthogonal voltage signals of equal amplitude;

[0206] (2) Based on the partition calculation delay, the orthogonal voltage signal is compensated to obtain a compensated voltage signal;

[0207] like Fig. 9 As shown in the figure, ε is the voltage difference, S is the integral, and specifically, the calculation formula for the compensation voltage signal includes:

[0208] (12)

[0209] In the above formula, U'' a is the compensation voltage signal, δ is the delay compensation angle, U' a is the voltage sampling signal on the physical side of the digital-analog hybrid simulation system, q is orthogonal, qU' a For U' a Voltage signal after orthogonality;

[0210] (3) The compensation voltage signal is input into each simulation machine after the simulation step size is determined to obtain a signal without phase delay to complete the partition delay compensation.

[0211] The present invention adopts distributed simulation synchronization technology and introduces a delay compensation mechanism into the system, thereby avoiding the delay and asynchrony problems among multiple simulation machines.

[0212] After completing the distributed simulation synchronization, the problem that needs to be solved is the simulation scale. Real-time simulation of power systems usually uses real-time simulation technology of a single simulation machine, but it is limited by the computing power and storage capacity of a single simulation machine and may not be able to meet the needs of complex simulation models and large-scale simulation tasks, nor can it meet the computing speed requirements. The present invention adopts an array interconnection simulation method based on a fiber optic network card to expand the simulation scale, that is, a method of using a fiber optic network card for interconnection and simulation in an array system. This method uses a fiber optic network card as an interconnection device in the array system, and realizes data transmission and exchange between modules in the array in a FIFO queue-based manner, thereby realizing the simulation of the array system. Furthermore, before step 102, it also includes:

[0213] Each line sub-partition adopts an array interconnection simulation method based on a fiber optic network card to connect between simulation machines.

[0214] Furthermore, each line sub-division adopts an array interconnection simulation method based on a fiber optic network card to connect between simulation machines, including:

[0215] Use optical fiber network cards to interconnect the simulation machines and set the communication protocols between the simulation machines;

[0216] The data of each simulation machine is transmitted to the preset FIFO queue through the optical fiber network card in a stream manner;

[0217] During the simulation process, each simulation machine exchanges data between simulation machines by reading and writing FIFO queues.

[0218] It should be noted that FIFO: First In First Out is a common storage management method, similar to the queuing system, first come first served. It is also the working principle of the queue data structure, that is, the element that enters the queue first will be processed or removed first.

[0219] For example, in some embodiments, the array interconnection simulation method based on the optical fiber network card includes the following steps:

[0220] Step 1: Use the fiber optic network card as the interconnection device in the array system, and interconnect each simulation machine through optical fiber;

[0221] Step 2: Set up the communication protocol between the simulation machines, and transfer the data to the FIFO queue through the fiber optic network card in a stream manner;

[0222] Step 3: During the simulation process, each simulation machine exchanges data by reading and writing FIFO queues;

[0223] Step 4: Transmit the data in the FIFO queue to the next simulation machine through the optical fiber network card, thereby realizing operations such as dequeueing, enqueuing and delaying.

[0224] The advantage of this method is that it uses optical fiber interconnection, which has the characteristics of high-speed data transmission, high reliability, and small transmission delay. At the same time, by using optical fiber network cards, it can reduce the electromagnetic interference and errors generated during the simulation process and ensure the simulation accuracy.

[0225] Furthermore, the collaborative parallel simulation is performed using a real-time simulation method based on a CPU-FPGA hybrid step size and hardware-in-the-loop simulation technology.

[0226] The present invention uses a real-time simulation method based on a CPU-FPGA hybrid step size to improve the simulation speed, that is, to use the parallelism and low latency characteristics of FPGA hardware to achieve high-performance, low-latency, and high-accuracy simulation effects. The basic idea is to use the CPU to execute the main loop of the simulation algorithm, and use FPGA hardware to execute the circuit model calculation of the critical path, thereby realizing real-time simulation of the circuit system. In some embodiments, such as Fig.10 As shown, t is the starting time, Δt is the stage time difference, w is the number of stage time differences, and ΔT is the total time difference. The specific steps include:

[0227] Step 1: Split the circuit model (i.e., the entire simulation model for parallel simulation) into computationally intensive critical paths and other simpler paths;

[0228] It should be noted that the method of "splitting the entire simulation model for parallel simulation into computationally intensive critical paths and other relatively simple paths" involved in the embodiments of the present invention is well known to those skilled in the art, and therefore, its specific implementation method is not described in detail. In some embodiments, the splitting can be performed based on, but not limited to, experimental data or expert experience;

[0229] Step 2: Use the CPU to execute the main loop of the simulation algorithm, which includes steps such as clock and state update;

[0230] It can be understood that simulation algorithms usually refer to the algorithms used in simulation models to calculate state updates and refer to data updates, etc.;

[0231] Step 3: Use FPGA hardware to accelerate the calculation of the circuit model of the critical path, and use the hybrid step method to control the step size of the FPGA accelerated circuit model calculation to ensure the accuracy and timeliness of the simulation. That is, the CPU performs low-frequency and large-step network simulation, and the FPGA performs high-frequency and small-step calculation and delay compensation. The two perform asynchronous communication to form a CPU-FPGA joint simulation.

[0232] Step 4: The result calculated by the FPGA hardware is transmitted back to the CPU for updating the state of the circuit system, that is, the result calculated by the FPGA is given to the circuit system for assignment; wherein the circuit system refers to the circuit in the simulation system;

[0233] Step 5: Repeat the above steps until the simulation ends.

[0234] The advantage of this method is that it can greatly shorten the simulation time and improve the simulation efficiency without losing the simulation accuracy. At the same time, the hardware acceleration based on FPGA-CPU also greatly reduces the system delay. Fig.11 As shown, the array interconnection simulation method based on fiber optic network cards and the real-time simulation method of CPU-FPGA mixed step size can realize collaborative real-time simulation of multiple simulation machines, among which the heterogeneous simulation resource management and control system in the figure is a host computer software system.

[0235] The present invention adopts an array interconnection simulation method based on optical fiber network cards, uses optical fiber network cards for interconnection and simulation in a small-step simulation machine array system, thereby expanding the simulation scale, and adopts a real-time simulation method based on CPU-FPGA mixed step size to reduce delay and improve simulation speed.

[0236] Based on the above technology, real-time, fast and accurate simulation of large-scale distribution networks has been achieved. On this basis, the present invention has also made a breakthrough in application scenarios, namely, the use of distribution network intelligent terminal hardware-in-the-loop simulation technology based on online adaptive trigger synchronization to realize the distribution network small-step simulation machine interconnection method and the hardware-in-the-loop simulation application of the array system.

[0237] FTU (Fault Test Unit, which can be used to collect electrical parameters and perform fault diagnosis and processing) and line selection device hardware are key equipment in the power system, used for fault detection, isolation and protection functions. In the power system, in order to ensure the reliability and safety of the equipment, it needs to be simulated and tested.

[0238] like Fig.12 As shown, in this process, in-loop simulation technology can be used. The basic idea is to generate fault signals through the interconnected array system of the distribution network small-step simulator. The real-time signal is amplified by the power amplifier and used as the real-time signal input of the device. The device takes action and feeds the action signal back to the control system in the host computer. During the simulation process, the synchronization and consistency of the simulation time and the real-time time must be ensured. The specific steps are as follows:

[0239] Step 1: In the host computer, build an application example simulation model and set up faults (that is, add a fault module in the simulation model) to generate fault signals;

[0240] Step 2: The simulation model performs partition decoupling, parallel computing, delay compensation, and array interconnection in a large-scale active distribution network small-step simulator interconnected array system to generate real-time signals (i.e., real-time signals of the simulator, including parameters and data);

[0241] Step 3: The real-time signal is transformed based on the online adaptive trigger synchronization method, and is linearly amplified by the power amplifier to obtain a real-time signal that meets the input conditions of the line selection device / FTU and other distribution network intelligent terminals (for example, the input signal conditions of the line selection device action);

[0242] Step 4: Collect real-time signals through intelligent terminal hardware of the distribution network such as FTU or line selection device, perform FTU action / line selection and other operations, and return the action signal to the host computer for judgment and decision-making (for example, if the input signal from the simulator meets the action standard, it will act, such as the current value exceeds a certain value, exceeds a certain time, etc.).

[0243] The advantage of this hardware-in-the-loop simulation technology is that it can perform simulation tests in the actual system without affecting the system operation. Because only the simulation signal needs to be obtained as the device input, it can meet the device testing under different working conditions. At the same time, during the simulation process, the response and performance of the system in different scenarios can be tested and verified, thereby helping to optimize the protection strategy and control algorithm.

[0244] like Fig.13 As shown, the invention provides a method for synchronous simulation of a small-step simulator of a distribution network, which is a decoupling method for short-line partitions of a distribution network based on distributed capacitance equivalent calculation. Through multi-rate parallel calculation with large and small step coordination, dynamic simulation of different scales is realized, and distributed simulation synchronization technology and an array interconnection method based on optical fiber network cards are designed, so that the simulation system can adapt to the simulation calculation scale and speed requirements of large-scale distribution networks. In simulation applications, a hardware-in-the-loop simulation technology for intelligent terminals of distribution networks based on online adaptive trigger synchronization is invented, which achieves a breakthrough in the application of hardware-in-the-loop simulation of distribution networks, and can complete basic calculations, operation control and advanced analysis simulations in various scenarios.

[0245] The invention provides a method for synchronous simulation of distribution network with small step length simulators, which solves the problem of parallel calculation of partitions in the case of short lines in the distribution network, breaks through the error caused by the decoupling of traditional partitions of long transmission lines, improves the accuracy of partitions, and provides a model basis for parallel simulation calculation of different partitions under multiple simulators.

[0246] Solve the problem of difficulty in coordinating the accuracy and efficiency of multiple simulation machines, break through the limitation of fixed-step simulation in different partitions of traditional power grid simulation, and use multi-rate parallel simulation technology based on large and small step coordination and distributed simulation synchronization technology to greatly improve the efficiency of real-time simulation;

[0247] Solve the problem of limited computing performance and computing scale of distribution network real-time simulation, break through the limitations of real-time simulation technology of traditional single simulation machine, and use array interconnection simulation method based on fiber optic network card and hardware-in-the-loop simulation technology of distribution network intelligent terminal based on online adaptive trigger synchronization to effectively improve the computing capacity of distribution network real-time simulation cluster and expand the scale of hardware-in-the-loop real-time simulation.

[0248] The invention provides a method for synchronous simulation of a distribution network with a small step size simulator, which has the following advantages: (1) the invention can effectively improve the scale and efficiency of real-time simulation of the distribution network, and can ensure that the physical / digital models of primary and secondary equipment such as lines, switches, fans, photovoltaics, and smart terminals are connected to the distribution network simulation system in a state that is highly consistent with the actual situation, thereby constructing distribution networks with different structural forms, equipment forms, and control forms, accurately simulating the operating state of the distribution network, and realizing simulation of multiple scenarios of the distribution network;

[0249] (2) The present invention has broken through the technical bottlenecks of distribution network real-time simulation model decomposition, parallel computing, digital-physical interface, etc., and has focused on the implementation of equipment and technology research and development. Through the interconnection of optical fiber network cards, a large-scale distribution network real-time simulation array has been constructed. It has obvious advantages such as fast simulation speed and high accuracy. It can effectively implement the action plan of building a "digitalized" new power system, and can realize panoramic simulation deduction such as dynamic evaluation of distributed energy carrying capacity, flexible grid connection strategy analysis, and distribution and micro-cooperative operation optimization and control, effectively improving the distributed energy grid connection and absorption capacity, and supporting the construction of a new power system;

[0250] (3) The present invention breaks through bottleneck technologies such as decoupling of short-line partitions in distribution networks, large-scale cluster collaboration, multi-core parallel simulation of heterogeneous resources, and hardware power-in-the-loop, and can achieve advanced functions such as unified management and control of heterogeneous simulation resources, large-scale digital simulation parallel simulation, and multi-time scale-multi-spatial resolution simulation;

[0251] (4) The present invention can overcome the technical difficulties of real-time simulation of new distribution systems with large line scales, numerous equipment types, high proportion of renewable energy and high proportion of power electronic equipment, and help realize the basic calculation, operation control, simulation analysis and other requirements of large-scale distributed power sources connected to the distribution network;

[0252] (5) The present invention can achieve a minimum simulation step of 200 nanoseconds, and proposes a short-line partition decoupling method suitable for distribution networks, realizing multi-rate parallel simulation with coordinated large and small steps, and can achieve a maximum cascade simulation array of 20 units;

[0253] (6) The present invention supports ultra-large-scale network fast computing and ultra-high precision real-time simulation with adaptive variable step length at the level of 100 nanoseconds, and can realize the autonomous control of the core equipment of the distribution network simulation and the localization substitution of the simulation array. The distribution network small step simulation interconnected array is an upgraded version of the distribution network small step real-time simulation machine, which can be promoted and applied in the future, and can comprehensively improve the work efficiency of the user unit, which will definitely improve the return on investment, promote the maximization of profits, and increase the net asset return rate of the user unit. The direct and indirect economic benefits are expected to be very optimistic. Therefore, the market capacity of the distribution network small step simulation interconnected array system of the present invention is huge and has broad market application prospects.

[0254] Embodiment 2

[0255] The present invention also provides a small-step-length simulation machine synchronous simulation device for a distribution network, such as Fig.14 As shown, including:

[0256] A partition unit is used to divide the distribution network into a plurality of line sub-partitions based on a distributed capacitance equivalent calculation method, each line sub-partition has at least one simulation machine, and the simulation step lengths of the simulation machines are not uniform;

[0257] A simulation unit, used for each line sub-division to perform collaborative parallel simulation based on its own simulation machine according to a preset simulation time period and simulation step size;

[0258] The processing unit is used for: performing interpolation processing on data that need to be interacted between simulation machines with different simulation rates during the collaborative parallel simulation; and / or realizing partition delay compensation for line sub-partitions with partition delay by means of compensating voltage signals;

[0259] The merging unit is used to merge the simulation results of each line sub-partition after the simulation is completed.

[0260] Furthermore, the partition unit is specifically used for:

[0261] Conduct network topology analysis on the distribution network to obtain the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure;

[0262] According to the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure, the distribution network is divided into a plurality of initial partitions;

[0263] A short line equivalent model considering distributed capacitance is added between two adjacent initial partitions, and parameters of the short line equivalent model considering distributed capacitance are adjusted;

[0264] The real-time simulation technology is used to simulate and verify the distribution network after being divided into multiple initial partitions. If the operating effect of the distribution network after being divided into multiple initial partitions is consistent with that before being divided into multiple initial partitions, the multiple initial partitions are divided into multiple line sub-partitions; otherwise, the distribution network is re-divided.

[0265] Further, a topological structure of a short line equivalent model considering distributed capacitance includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a first inductor, a second inductor and a third inductor;

[0266] A first resistor, a first inductor, a second resistor, a second inductor, a third resistor and a third inductor are sequentially connected in series on a transmission line connected between two adjacent line sub-divisions;

[0267] One end of the first capacitor is connected to the connection point between the first inductor and the second resistor, and the other end is grounded;

[0268] One end of the second capacitor is connected to a connection point between the second inductor and the third resistor, and the other end is grounded.

[0269] Furthermore, the device also includes: a determination unit, used to obtain a preset simulation step size of each simulation machine;

[0270] Determine the unit, specifically for:

[0271] The simulation step size of the simulator in the line sub-division without fast-changing power electronic equipment is set to the first simulation step size, and the simulation step size of the simulator in the line sub-division with a preset number of photovoltaic grid-connected inverters is set to the second simulation step size;

[0272] The first simulation step size is smaller than the second simulation step size.

[0273] Furthermore, the simulation unit comprises:

[0274] A determination module, used to determine the number of simulation machines in each line sub-partition and the preset simulation rate of each simulation machine according to the simulation requirements;

[0275] An allocation module, used for allocating the preset simulation models of each line sub-division to the corresponding simulation machines;

[0276] The simulation module is used for the respective simulation machines in each line sub-division to perform collaborative parallel simulation according to a preset simulation time period, a preset simulation step size and a preset simulation rate.

[0277] Furthermore, the processing unit comprises:

[0278] Interpolation module, used when t n At the moment, the simulation rate of the second simulation machine is different from the simulation rate of the first simulation machine, then the first simulation machine transmits its own simulation rate at [t n-2 , t n-1 ]Simulation results within the time step x n-1 and in [t n-1 ,t n ]Simulation results within the time step x n The second simulation machine transmits its own [t n-1 , t n ]Simulation results within the time step y n , where n is a positive integer;

[0279] In [t n , t n+1 ] time step, the first simulation machine uses the simulation result y of the second simulation machine n Perform a simulation calculation;

[0280] In [t n , t n+1 ] time step, the second simulation machine uses the external system state x n-1 and x n Interpolation is performed to obtain multiple external system state quantities, and multiple iterative calculations are performed using the multiple external system state quantities.

[0281] Furthermore, the processing unit comprises:

[0282] The compensation module is used to use the second-order orthogonal integration method to achieve partition delay compensation for the line sub-partitions with partition delay in the form of compensation voltage signals.

[0283] Furthermore, the compensation module is specifically used for:

[0284] An orthogonal signal generator based on second-order orthogonal integration is used to process the voltage sampling signal of the physical side of the digital-analog hybrid simulation system in the simulation model of each preset short-circuit partition to obtain a pair of orthogonal voltage signals with equal amplitudes;

[0285] Performing compensation calculation on the orthogonal voltage signal to obtain a compensated voltage signal;

[0286] The compensation voltage signal is input into the simulator in each short line section to obtain a signal without phase delay.

[0287] Furthermore, the device further comprises:

[0288] The connection unit is used to connect the simulation machines by using the array interconnection simulation method based on the optical fiber network card to divide each line sub-partition.

[0289] Furthermore, the connection unit is specifically used for:

[0290] Use optical fiber network cards to interconnect the simulation machines and set the communication protocols between the simulation machines;

[0291] The data of each simulation machine is transmitted to the preset FIFO queue through the optical fiber network card in a stream manner;

[0292] During the simulation process, each simulation machine exchanges data between simulation machines by reading and writing FIFO queues.

[0293] Furthermore, the collaborative parallel simulation is performed using a real-time simulation method based on a CPU-FPGA hybrid step size and hardware-in-the-loop simulation technology.

[0294] Furthermore, simulation requirements include at least the following two: time resolution and simulation time span.

[0295] Furthermore, the calculation formulas of multiple external system state quantities include:

[0296] x n,k =x n-1 +[(k-1) / m]( x n -x n-1 )

[0297] In the above formula, k∈[1,m], m is the total number of interpolation iterations; x n,k is the external system state quantity obtained by the kth interpolation, xn-1 For the first simulation machine in [t n-2 , t n-1 ]Simulation results within the time step, x n For the first simulation machine in [t n-1 , t n ]Simulation results within the time step.

[0298] Furthermore, the calculation formula of the orthogonal voltage signal includes:

[0299]

[0300] In the above formula, U' a is the voltage sampling signal on the physical side of the digital-analog hybrid simulation system, q is orthogonal, qU' a For U' a The orthogonal voltage signal, ω is the angular frequency of the digital-analog hybrid simulation system, U is the voltage amplitude on the digital side, t is the time, δ is the delay compensation angle, qU' a and cosδ are a pair of orthogonal voltage signals of equal amplitude.

[0301] Furthermore, the calculation formula of the compensation voltage signal includes:

[0302]

[0303] In the above formula, U'' a is the compensation voltage signal, δ is the delay compensation angle, U' a is the voltage sampling signal on the physical side of the digital-analog hybrid simulation system, q is orthogonal, qU' a For U' a The voltage signal after orthogonality.

[0304] It can be understood that the device embodiment provided above corresponds to the method embodiment described above, and the corresponding specific contents can be referenced to each other and will not be repeated here.

[0305] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0306] Embodiment 3

[0307] like Fig.15As shown, the present invention also provides an electronic device, which may be a computer device, a single-chip device, an intelligent mobile device, etc. The electronic device in this embodiment may include a processor, a memory, a transceiver component, etc. The memory, the processor, and the transceiver component are connected via a bus; the memory may be used to store an execution program, and an exemplary execution program may include instructions; the processor is used to execute the instructions stored in the memory. The memory may also be used to store data, which may be called and / or modified when the instructions are executed.

[0308] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions in a storage medium to implement the corresponding method flow or corresponding functions, so as to realize the steps of a synchronous simulation method of a distribution network small-step simulation machine in the above embodiment.

[0309] Embodiment 4

[0310] Based on the same inventive concept, the present invention also provides a readable storage medium, specifically an electronic device readable storage medium (Memory), which is a memory device in an electronic device for storing programs and data. It can be understood that the storage medium here can include both built-in storage media in electronic devices and extended storage media supported by electronic devices. The storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by a processor are also stored in the storage space, and these instructions can be one or more execution programs (including program codes). It should be noted that the storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. The processor loads and executes one or more instructions stored in the storage medium, which can implement the steps of a synchronous simulation method of a small-step simulator for a distribution network in the above embodiment.

[0311] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0312] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0313] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0314] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0315] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A distribution network small step size simulator synchronous simulation method, characterized in that: include: Based on the distributed capacitance equivalent calculation method, the distribution network is divided into multiple line sub-divisions, each line sub-division has at least one simulation machine, and the simulation step size of each simulation machine is not uniform; Each of the line sub-divisions performs collaborative parallel simulation based on its own simulation machine according to a preset simulation time period and simulation step size; During the collaborative parallel simulation: interpolation processing is performed on the data that needs to be interacted between simulation machines with different simulation rates; and partition delay compensation is achieved by compensating voltage signals for line sub-partitions with partition delays; After the simulation is completed, the simulation results of each line sub-partition are merged; The distributed capacitance equivalent calculation method is used to divide the distribution network into multiple line sub-divisions, including: Performing a network topology analysis on the distribution network to obtain the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure; Dividing the distribution network into a plurality of initial partitions according to the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure; Adding a short line equivalent model considering distributed capacitance between two adjacent initial partitions, and adjusting parameters of the short line equivalent model considering distributed capacitance; The distribution network after being divided into a plurality of initial partitions is simulated and verified by using real-time simulation technology. If the operation effect of the distribution network after being divided into a plurality of initial partitions is consistent with that of the distribution network before being divided into a plurality of initial partitions, the plurality of initial partitions are the plurality of line sub-partitions; otherwise, the distribution network is re-divided; The topological structure of the short line equivalent model considering distributed capacitance includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a first inductor, a second inductor and a third inductor; The first resistor, the first inductor, the second resistor, the second inductor, the third resistor and the third inductor are sequentially connected in series on a transmission line connected between two adjacent line sub-divisions; One end of the first capacitor is connected to a connection point between the first inductor and the second resistor, and the other end is grounded; One end of the second capacitor is connected to a connection point between the second inductor and the third resistor, and the other end is grounded; The method of implementing partition delay compensation for the line sub-partition with partition delay by means of compensating voltage signals includes: An orthogonal signal generator based on second-order orthogonal integration is used to process the voltage sampling signal of the physical side of the digital-analog hybrid simulation system in the simulation model of each preset short-circuit partition to obtain a pair of orthogonal voltage signals with equal amplitudes; Performing compensation calculation on the orthogonal voltage signal to obtain a compensated voltage signal; The compensation voltage signal is input into the simulator in each short line partition to obtain a signal without phase delay.

2. The method according to claim 1, characterized in that The process of obtaining the preset simulation step length of each simulation machine includes: The simulation step size of the simulator in the line sub-division without fast-changing power electronic equipment is set to the first simulation step size, and the simulation step size of the simulator in the line sub-division with a preset number of photovoltaic grid-connected inverters is set to the second simulation step size; The first simulation step size is smaller than the second simulation step size.

3. The method according to claim 1, characterized in that The line sub-divisions are respectively based on their own simulation machines and perform collaborative parallel simulation according to a preset simulation time period and simulation step size, including: Determine the number of simulation machines for each line sub-partition and the preset simulation rate of each simulation machine according to the simulation requirements; Allocate the preset simulation models of each line sub-division to the corresponding simulation machines; The respective simulation machines in each line sub-division perform collaborative parallel simulation according to a preset simulation time period, a preset simulation step size and a preset simulation rate.

4. The method according to claim 1, characterized in that The interpolation processing is performed on the data that needs to be interacted between the simulation machines with different simulation rates, including: When t n At the moment, the simulation rate of the second simulation machine is different from the simulation rate of the first simulation machine, then the first simulation machine transmits its own [ t n-2 , t n-1 ]Simulation results within the time step x n-1 and in [ t n-1 , t n ]Simulation results within the time step x n The second simulation machine transmits its own [ t n-1 , t n ]Simulation results within the time step y n , where n is a positive integer; exist[ t n , t n+1 ] time step, the first simulation machine uses the simulation results of the second simulation machine y n Perform a simulation calculation; exist[ t n , t n+1 ] time step, the second simulator uses the external system state quantity x n-1 and x n Performing interpolation to obtain a plurality of external system state quantities, and performing multiple iterative calculations using the plurality of external system state quantities; in, t n For the t n time, t n-2 For the t n-2 time, t n-1 For the t n-1 time, t n+1 For the t n+1 time.

5. The method according to claim 1, characterized in that Before each line sub-division performs collaborative parallel simulation based on its own simulation machine according to a preset simulation time period and simulation step, the method further includes: Each line sub-division adopts an array interconnection simulation method based on an optical fiber network card to connect between simulation machines.

6. The method according to claim 5, characterized in that Each line sub-division adopts an array interconnection simulation method based on a fiber optic network card to connect the simulation machines, including: Use optical fiber network cards to interconnect the simulation machines and set the communication protocols between the simulation machines; The data of each simulation machine is transmitted to the preset FIFO queue through the optical fiber network card in a stream manner; During the simulation process, each simulation machine exchanges data between simulation machines by reading and writing FIFO queues.

7. The method according to claim 1, characterized in that The collaborative parallel simulation is performed using a real-time simulation method based on a CPU-FPGA hybrid step size and a hardware-in-the-loop simulation technology.

8. The method according to claim 3, characterized in that The simulation requirements include at least the following two: time resolution and simulation time span.

9. The method according to claim 4, characterized in that The calculation formulas of the multiple external system state quantities include: x n,k =x n-1 +[(k-1) / m]( x n -x n-1 ) In the above formula, k ∈[ 1,m ], m is the total number of interpolation iterations; x n,k is the external system state quantity obtained by the k-th interpolation, x n-1 For the first simulation machine in [ t n-2 , t n-1 ] simulation results within the time step, x n For the first simulation machine in [ t n-1 , t n ]Simulation results within the time step.

10. A small-step-length simulator synchronous simulation device for a distribution network, characterized in that: include: A partition unit is used to divide the distribution network into a plurality of line sub-partitions based on a distributed capacitance equivalent calculation method, each line sub-partition has at least one simulation machine, and the simulation step lengths of the simulation machines are not uniform; A simulation unit, used for performing collaborative parallel simulation on each of the line sub-partitions based on respective simulation machines according to a preset simulation time period and simulation step size; The processing unit is used for: performing interpolation processing on data that need to be interacted between simulation machines with different simulation rates during the collaborative parallel simulation; and realizing partition delay compensation for line sub-partitions with partition delays by means of compensating voltage signals; A merging unit, used to merge the simulation results of each line sub-partition after the simulation is completed; The partition unit is specifically used for: Performing a network topology analysis on the distribution network to obtain the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure; Dividing the distribution network into a plurality of initial partitions according to the overall network structure of the distribution network and the connection relationship between the distribution network devices in the overall network structure; Adding a short line equivalent model considering distributed capacitance between two adjacent initial partitions, and adjusting parameters of the short line equivalent model considering distributed capacitance; The distribution network after being divided into a plurality of initial partitions is simulated and verified by using real-time simulation technology. If the operation effect of the distribution network after being divided into a plurality of initial partitions is consistent with that of the distribution network before being divided into a plurality of initial partitions, the plurality of initial partitions are the plurality of line sub-partitions. Otherwise, the distribution network is re-divided; The topological structure of the short line equivalent model considering distributed capacitance includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a first inductor, a second inductor and a third inductor; The first resistor, the first inductor, the second resistor, the second inductor, the third resistor and the third inductor are sequentially connected in series on a transmission line connected between two adjacent line sub-divisions; One end of the first capacitor is connected to a connection point between the first inductor and the second resistor, and the other end is grounded; One end of the second capacitor is connected to a connection point between the second inductor and the third resistor, and the other end is grounded; The processing unit comprises: The compensation module is used to process the voltage sampling signal of the physical side of the digital-analog hybrid simulation system in the simulation model of each preset short line partition by using an orthogonal signal generator based on second-order orthogonal integration to obtain a pair of orthogonal voltage signals of equal amplitude; Performing compensation calculation on the orthogonal voltage signal to obtain a compensated voltage signal; The compensation voltage signal is input into the simulator in each short line partition to obtain a signal without phase delay.

11. The device according to claim 10, characterized in that The device further comprises: a determination unit, configured to obtain a preset simulation step length of each simulation machine; The determining unit is specifically configured to: The simulation step size of the simulator in the line sub-division without fast-changing power electronic equipment is set to the first simulation step size, and the simulation step size of the simulator in the line sub-division with a preset number of photovoltaic grid-connected inverters is set to the second simulation step size; The first simulation step size is smaller than the second simulation step size.

12. The device according to claim 10, characterized in that The simulation unit comprises: A determination module, used to determine the number of simulation machines in each line sub-partition and the preset simulation rate of each simulation machine according to the simulation requirements; An allocation module, used for allocating the preset simulation models of each line sub-division to the corresponding simulation machines; The simulation module is used for the respective simulation machines in each line sub-division to perform collaborative parallel simulation according to a preset simulation time period, a preset simulation step size and a preset simulation rate.

13. The device according to claim 10, characterized in that The processing unit comprises: Interpolation module, used when t n At the moment, the simulation rate of the second simulation machine is different from the simulation rate of the first simulation machine, then the first simulation machine transmits its own [ t n-2 , t n-1 ]Simulation results within the time step x n-1 and in [ t n-1 , t n ]Simulation results within the time step x n The second simulation machine transmits its own [ t n-1 , t n ]Simulation results within the time step y n , where n is a positive integer; exist[ t n , t n+1 ] time step, the first simulation machine uses the simulation results of the second simulation machine y n Perform a simulation calculation; exist[ t n , t n+1 ] time step, the second simulator uses the external system state quantity x n-1 and x n Performing interpolation to obtain a plurality of external system state quantities, and performing multiple iterative calculations using the plurality of external system state quantities; in, t n For the t n time, t n-2 For the t n-2 time, t n-1 For the t n-1 time, t n+1 For the t n+1 time.

14. The device according to claim 10, characterized in that The device further comprises: The connection unit is used to connect the simulation machines by using an array interconnection simulation method based on an optical fiber network card to divide the line sub-partitions.

15. The device according to claim 14, characterized in that The connecting unit is specifically used for: Use optical fiber network cards to interconnect the simulation machines and set the communication protocols between the simulation machines; The data of each simulation machine is transmitted to the preset FIFO queue through the optical fiber network card in a stream manner; During the simulation process, each simulation machine exchanges data between simulation machines by reading and writing FIFO queues.

16. The device according to claim 10, characterized in that The collaborative parallel simulation is performed using a real-time simulation method based on a CPU-FPGA hybrid step size and a hardware-in-the-loop simulation technology.

17. The device according to claim 12, characterized in that The simulation requirements include at least the following two: time resolution and simulation time span.

18. The device according to claim 13, characterized in that The calculation formulas of the multiple external system state quantities include: x n,k =x n-1 +[(k-1) / m]( x n -x n-1 ) In the above formula, k ∈[ 1,m ], m is the total number of interpolation iterations; x n,k is the external system state quantity obtained by the k-th interpolation, x n-1 For the first simulation machine in [ t n-2 , t n-1 ] simulation results within the time step, x n For the first simulation machine in [ t n-1 , t n ]Simulation results within the time step.

19. An electronic device, characterized in that: include: at least one processor and memory; The memory and the processor are connected via a bus; The memory is used to store one or more programs; When the one or more programs are executed by the at least one processor, the distribution network small-step simulation machine synchronous simulation method according to any one of claims 1 to 9 is implemented.

20. A readable storage medium, characterized in that: An execution program is stored thereon, and when the execution program is executed, the distribution network small-step simulation machine synchronous simulation method as described in any one of claims 1 to 9 is implemented.

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