Method and device for converting natural language into netlist of combinational logic circuit
By decomposing combinational logic circuits into basic functional modules and training the large language model with corresponding netlists, the method addresses the vocabulary mismatch, achieving efficient and precise conversion of natural language into netlists.
Patent Information
- Application Number
- CN202411171240.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2024-12-13
AI Technical Summary
Large language models struggle to directly convert natural language descriptions of combinational logic circuits into netlists due to the complexity and mismatch between the rich vocabulary of natural language and the limited vocabulary of netlists, which primarily uses logical operators like AND, OR, NOR, NAND, NOT, XOR, and registers.
The method involves decomposing the combinational logic circuit into basic functional modules, generating a netlist for each module, and combining them, using a large language model trained with descriptions and netlists of these modules, and incorporating reasoning processes to handle complex circuits.
This approach enables faster and more accurate conversion of natural language into netlists by breaking down complex circuits into simpler modules, allowing the large language model to generate netlists efficiently and accurately.
Smart Images
Figure CN119129490A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of artificial intelligence technology, and in particular to a method and device for converting natural language into a netlist of a combinational logic circuit. Background Art
[0002] The large language model (LLM) is good at understanding and processing various languages and characters. It can handle complex language structures and contextual relationships and generate accurate and coherent texts. It can be applied to many fields such as translation, article generation, and article summarization.
[0003] At present, the large language model has the function of converting natural language into machine language. Therefore, designers also hope to use the large language model to convert the natural language of the combinational logic circuit into the netlist of the combinational logic circuit. The netlist of the combinational logic circuit is used to describe the connection relationship between circuit components. Since the vocabulary of natural language description is very rich, but the vocabulary used in the netlist is relatively small, only AND, OR, NOR, NAND, NOT, XOR and register (flip flop, register) are used, and the logical relationship between the two is very complex, so the large language model cannot directly convert the natural language description of the combinational logic circuit into the corresponding netlist of the combinational logic circuit.
[0004] Therefore, there is an urgent need for a solution to convert the natural language of a combinational logic circuit into a netlist of the combinational logic circuit through a large language model. Summary of the invention
[0005] The present application provides a method and device for converting natural language into a netlist of a combinational logic circuit, which is used to convert the natural language of a combinational logic circuit into a netlist of a combinational logic circuit through a large language model.
[0006] In a first aspect, the present application provides a method for converting natural language into a netlist of a combinational logic circuit, which is applied to a large language model, and the method comprises: receiving a natural language description of a target combinational logic circuit from a user; the natural language description of the target combinational logic circuit comprises a description of an input, an output and a function of the combinational logic circuit; according to the natural language description of the target combinational logic circuit, decomposing the target combinational logic circuit into at least one basic functional module, and generating a description of each basic functional module; based on the description of each basic functional module, generating a netlist corresponding to each basic functional module; and combining the netlist corresponding to the at least one basic functional module to obtain a netlist of the target combinational logic circuit.
[0007] In the above technical solution, compared with directly generating a netlist corresponding to a combinational logic circuit, generating a netlist corresponding to a basic function module is faster and more accurate. When the large language model of the embodiment of the present application generates a corresponding netlist from the natural language description of the target combinational logic circuit, it first splits the complex combinational logic circuit into relatively simple intermediate-level basic function modules, then generates a netlist corresponding to each basic function module, and then combines the netlist corresponding to at least one basic function module to obtain the netlist of the target logic circuit. This enables the large language model to generate a netlist of a combinational logic circuit more accurately and quickly.
[0008] In one possible design, based on the natural language description of the target combinational logic circuit, the target combinational logic circuit is decomposed into at least one basic functional module, and a description of each basic functional module is generated, including: based on the reasoning process of decomposing the combinational logic circuit into basic functional modules in the training sample, the target combinational logic circuit is decomposed into at least one basic functional module, and a description of each basic functional module is generated.
[0009] In the above technical solution, the training samples include the reasoning process of decomposing the combinational logic circuit into basic functional modules. The reasoning process includes multiple intermediate steps, which can enable the large language model to learn the thinking mode of decomposing complex combinational logic circuits into relatively simple basic functional modules, so that the large language model has better logical reasoning ability.
[0010] In a possible design, a netlist corresponding to each basic function module is generated according to the description of each basic function module, including: if the number of bits of a first basic function module is less than or equal to a set threshold, directly calling a preset netlist corresponding to the first basic function module as the netlist corresponding to the first basic function module; if the number of bits of the first basic function module is greater than the set threshold, decomposing the second basic function module into multiple first basic function modules according to the generation principle of the second basic function module, and generating a netlist corresponding to the second basic function module according to the preset netlist corresponding to each first basic function module.
[0011] In the above technical solution, the large language model cannot learn the netlists corresponding to the basic function modules of all digits. Therefore, for the basic function modules with smaller digits, the corresponding netlists are simpler, so that the large language model can directly learn the corresponding netlists. Then, the corresponding netlists can be directly called when actually used. For the basic function modules with larger digits, the large language model is made to learn the splitting principle of the basic function modules, that is, how to split the basic function modules with larger digits into the basic function modules with smaller digits. Then, when actually used, the basic function modules are first split into the basic function modules with smaller digits according to the splitting principle, and then the corresponding netlists are called.
[0012] In a possible design, according to the generation principle of the second basic function module, the second basic function module is decomposed into multiple first basic function modules, including: determining the type of the second basic function module; deriving the second basic function module according to the generation principle of the basic function module of the type in the training sample, and decomposing the second basic function module into multiple first basic function modules.
[0013] In the above technical solution, different types of basic function modules have different generation principles, so the basic function modules need to be split according to the generation principles of the basic function modules of the corresponding types.
[0014] In a second aspect, an embodiment of the present application provides a method for training a large language model, the method comprising: using the description of each basic functional module in the combinational logic circuit and the corresponding netlist as prompt words of the large language model, training the large language model so that the large language model has the function of generating a netlist corresponding to the basic functional module according to the description of the basic functional module; using the natural language description of each target combinational logic circuit and the reasoning process of decomposing each combinational logic circuit into basic functional modules as prompt words of the large language model, training the large language model so that the large language model has the function of decomposing the target combinational logic circuit into at least one basic functional module.
[0015] In the above technical solution, in the process of training the large language model, the training samples include two parts, one part is used to train the large language model so that the large language model has the function of generating the netlist corresponding to the basic function module according to the description of the basic function module; the other part is used to train the large language model so that the large language model has the function of decomposing the target combinational logic circuit into at least one basic function module. When the large language model generates the corresponding netlist from the natural language description of the target combinational logic circuit, it can first split the complex combinational logic circuit into relatively simple intermediate-level basic function modules, and then generate the netlist corresponding to each basic function module, so that the large language model can generate the netlist of the combinational logic circuit more accurately and quickly.
[0016] In a possible design, the description of each basic function module in the combinational logic circuit and the corresponding netlist are used as prompt words of the large language model to train the large language model, including: for each first basic function module whose number of bits is less than or equal to a set threshold, the description of the first basic function module and the corresponding netlist are used as prompt words of the large language model to train the large language model; for each second basic function module whose number of bits is greater than the set threshold, the description of each second basic function module, the reasoning process of decomposing each second basic function module into multiple first basic function modules, and the netlist corresponding to each first basic function module are used as prompt words of the large language model to train the large language model.
[0017] In a possible design, the method further includes: if the output result of the large language model is incorrect, adding details of the prompt word according to the output result of the large language model.
[0018] In a third aspect, an embodiment of the present application provides a device for converting a natural language into a netlist of a combinational logic circuit, the device comprising:
[0019] A receiving module, configured to receive a natural language description of a target combinational logic circuit from a user; the natural language description of the target combinational logic circuit includes a description of the input, output and function of the combinational logic circuit;
[0020] A processing module, configured to decompose the target combinatorial logic circuit into at least one basic functional module according to the natural language description of the target combinatorial logic circuit, and generate a description of each basic functional module;
[0021] The processing module is further used to generate a netlist corresponding to each basic function module based on the description of each basic function module;
[0022] The processing module is further used to combine the netlist corresponding to the at least one basic function module to obtain the netlist of the target combinational logic circuit.
[0023] In one possible design, the processing module, when decomposing the target combinatorial logic circuit into at least one basic functional module according to the natural language description of the target combinatorial logic circuit and generating a description of each basic functional module, is specifically used to decompose the target combinatorial logic circuit into at least one basic functional module according to the reasoning process of decomposing the combinatorial logic circuit into basic functional modules in the training samples, and generate a description of each basic functional module.
[0024] In a possible design, when the processing module generates a netlist corresponding to each basic function module according to the description of each basic function module, it is specifically used to directly call the preset netlist corresponding to the first basic function module as the netlist corresponding to the first basic function module if the number of bits of the first basic function module is less than or equal to the set threshold; if the number of bits of the first basic function module is greater than the set threshold, the second basic function module is decomposed into multiple first basic function modules according to the generation principle of the second basic function module, and the netlist corresponding to the second basic function module is generated according to the preset netlist corresponding to each first basic function module.
[0025] In one possible design, the processing module is specifically used to determine the type of the second basic function module when decomposing the second basic function module into multiple first basic function modules according to the generation principle of the second basic function module; derive the second basic function module according to the generation principle of the basic function module of the type in the training sample, and decompose the second basic function module into multiple first basic function modules.
[0026] In a fourth aspect, an embodiment of the present application provides a large language model training device, the device comprising:
[0027] A first training module is used to use the description of each basic function module in the combinational logic circuit and the corresponding netlist as prompt words of the large language model, and train the large language model so that the large language model has the function of generating the netlist corresponding to the basic function module according to the description of the basic function module;
[0028] The second training module is used to use the natural language description of each target combinational logic circuit and the reasoning process of decomposing each combinational logic circuit into basic functional modules as prompt words of the large language model, and train the large language model so that the large language model has the function of decomposing the target combinational logic circuit into at least one basic functional module.
[0029] In a possible design, the first training module, when using the description of each basic function module in the combinational logic circuit and the corresponding netlist as prompt words of the large language model to train the large language model, is specifically used for each first basic function module whose number of bits is less than or equal to a set threshold, using the description of the first basic function module and the corresponding netlist as the prompt words of the large language model to train the large language model; for each second basic function module whose number of bits is greater than the set threshold, using the description of each second basic function module, the reasoning process of decomposing each second basic function module into multiple first basic function modules, and the netlist corresponding to each first basic function module as the prompt words of the large language model to train the large language model.
[0030] In a possible design, the first training module and the second training module are further used to increase the details of the prompt word according to the output result of the large language model if the output result of the large language model is incorrect.
[0031] In a fifth aspect, an embodiment of the present application further provides a computing device, including:
[0032] A memory for storing program instructions;
[0033] A processor is used to call the program instructions stored in the memory, and execute the method described in any possible design of the first aspect or the second aspect according to the obtained program instructions.
[0034] In a sixth aspect, an embodiment of the present application further provides a computer-readable storage medium, in which computer-readable instructions are stored. When a computer reads and executes the computer-readable instructions, the method described in any possible design of the first aspect or the second aspect mentioned above is implemented. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0036] Figure 1 A flowchart of a method for converting a natural language into a netlist of a combinational logic circuit applicable to an embodiment of the present application;
[0037] Figure 2 A flowchart of a method for training a large language model provided in an embodiment of the present application;
[0038] Figure 3 A schematic diagram of training a large language model provided in an embodiment of the present application;
[0039] Figure 4 A schematic diagram of the structure of a device for converting natural language into a netlist of a combinational logic circuit provided in an embodiment of the present application;
[0040] Figure 5 A schematic diagram of the structure of a large language model training device provided in an embodiment of the present application;
[0041] Figure 6 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.
[0043] In the embodiments of the present application, a plurality refers to two or more than two. The words "first", "second" and the like are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance or order.
[0044] Figure 1 A flow chart of a method for converting natural language into a netlist of a combinational logic circuit provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method includes:
[0045] Step 101: Receive a natural language description of a target combinational logic circuit from a user.
[0046] In the embodiment of the present application, the target combinational logic circuit is a combinational logic circuit for which the user wants to generate a netlist. The user inputs a natural language description of the target combinational logic circuit into the large language model as a prompt of the large language model. The natural language description of the target combinational logic circuit includes a description of the input, output, and function of the combinational logic circuit.
[0047] For example, the natural language description of the target combinational logic circuit by the user is: We have the following basic functional modules: adder, substractor, multiplier, multiplexer, shift register, comparator. There are 5 inputs and one output for an arithmetic unit. The 5 inputs are AA, BB, CC, DD, ZZ. The output is EE. In the input, AA and BB are data input with M bits, DD is the selection signal with 2 bits. CC is the condition signal with 1 bit. ZZ is a number with 2 bits. If DD = 0, we need to check CC at first: if CC = 0, then EE = AA + BB, if CC = 1, then EE = AA - BB. If DD = 1, then EE = 0 if AA > BB. If DD = 1, then EE = 1 if AA <= BB. If DD = 2 and ZZ = N, then we circular shift AA to the left by N bit at first, then EE = shifted AA + BB. If DD = 3, then EE = AA * BB. Please divide this arithmetic unit into the basic functional modules by their functions, and connect these functional modules by the signal wires in the netlist style。
[0048] The corresponding translation of the above natural language description of the target combinational logic circuit is: We have the following basic functional modules: adder, subtractor, multiplier, multiplexer, shift register, comparator. The arithmetic unit has 5 inputs and 1 output. The 5 inputs are AA, BB, CC, DD and ZZ. The output is EE. In the input, AA and BB are M-bit data inputs, and DD is a 2-bit selection signal. CC is a 1-bit conditional signal. ZZ is a two-digit number. If DD=0, we first need to check CC: if CC=0, then EE=AA+BB, if CC=1, then EE=AA-BB. If DD=1, then if AA>BB, EE=0. If DD=1, then if AA<=BB, then EE=1. If DD=2, ZZ=N, then we first cyclically shift AA to the left by N bits, and then EE=shift AA+BB. If DD=3, then EE=AA*BB. Please divide the operation unit into basic functional modules according to their functions, and connect these functional modules in the form of a netlist through signal lines.
[0049] It can be seen that in the natural language description of the target combinational logic circuit, “There are 5 inputs and one output for an arithmetic unit. The 5 inputs are AA, BB, CC, DD, ZZ. The output is EE. In the input, AA and BB are data input with M bits, DD is the selection signal with 2 bits. CC is the condition signal with 1 bit. ZZ is a number with 2 bits.” is a description of the input and output of the combinational logic circuit; “If DD=0, we need to check CC at first: if CC=0, then EE=AA+BB, if CC=1, then EE=AA-BB. If DD=1, then EE=0ifAA>BB. If DD=1, then EE=1if AA<=BB. If DD=2and ZZ=N, then we circular shift AA to the left by N bit at first, then EE=shifted AA+BB. If DD=3, then EE=AA*BB." is a description of the function of the combinational logic circuit. In addition, the natural language description of the target combinational logic circuit can also include the limitation of the basic functional module categories "We have the following basic functional modules: adder, substractor, multiplier, multiplexer, shift register, comparator." and the purpose of using the large language model this time "Please divide this arithmetic unit into the basic functional modules by their functions, and connect these functional modules by the signals wires in the netlist style".
[0050] It should be noted that during use, the natural language description of the target combinational logic circuit input by the user into the large language model needs to be consistent with the language habits of the training data during the training process to improve the accuracy of the large language model in generating the netlist. Among them, the consistency of language habits includes consistent word descriptions and consistent structures. For example, consistent word descriptions mean that for conditionals, the format of "if..., then..., else..." ("if..., then..., otherwise...") is used for description. Structural consistency means that the natural language description of the target combinational logic circuit in the training data first describes the input, then the output, and then the function. Then, when the large language model is actually used to generate the netlist, the order of the natural language description of the target combinational logic circuit input by the user into the large language model is also to describe the input first, then the output, and then the function.
[0051] Step 102: Decompose the target combinational logic circuit into at least one basic functional module according to the natural language description of the target combinational logic circuit, and generate a description of each basic functional module.
[0052] Among them, the basic functional modules are components that can realize some basic functions, including adder, complement generator, multiplier, multiplexer, comparator, shift register, encoder and decoder, etc.
[0053] Specifically, according to the natural language description of the target combinational logic circuit, the target combinational logic circuit is decomposed into at least one basic functional module, and a description of each basic functional module is generated, including: according to the reasoning process of decomposing the combinational logic circuit into basic functional modules in the training sample, the target combinational logic circuit is decomposed into at least one basic functional module, and a description of each basic functional module is generated.
[0054] The reasoning process of decomposing the combinational logic circuit into basic functional modules is learned by the large language model during the training process. The trained large language model can decompose the target combinational logic circuit into at least one basic functional module according to the natural language description of the target combinational logic circuit.
[0055] Continuing with the natural language description of the target combinational logic circuit by the user in step 101 as an example, it is decomposed into at least one basic functional module, and the description of each basic functional module is obtained as follows:
[0056]
[0057]
[0058] In order to better understand the above content, the corresponding translation is as follows:
[0059]
[0060]
[0061]
[0062] It can be seen that based on the user's natural language description of the target combinational logic circuit, the large language model decomposes it into an adder, a subtractor, a multiplier, a shift register, a comparator, a 2-to-1 multiplexer, and a 4-to-1 multiplexer. In addition, the input signals and output signals of each basic functional module are clearly described. Specifically, the output of the target combinational logic circuit is the output of the 4-to-1 multiplexer, and the inputs of the 4-to-1 multiplexer are the output of the 2-to-1 multiplexer, the comparison result of the comparator, the output of the shifter, and the output of the multiplier, respectively. Among them, the inputs of the 2-to-1 multiplexer are the outputs of the adder and the subtractor, respectively.
[0063] Step 103: Based on the description of each basic function module, generate a netlist corresponding to each basic function module.
[0064] The netlist of a combinational logic circuit is used to describe the connection relationship between circuit elements, usually represented by words such as AND, OR, NOR, NAND, NOT, XOR, and register (flip flop, register). After splitting the combinational logic circuit into at least one basic functional module, a netlist corresponding to each basic functional module is generated based on the description of each basic functional module. The netlist corresponding to the basic functional module is learned by the large language model during the training process.
[0065] By way of example, the following is a netlist for a 4-to-1 multiplexer:
[0066]
[0067]
[0068] Specifically, according to the description of each basic functional module, a netlist corresponding to each basic functional module is generated, including the following two cases:
[0069] The first one is that if the number of bits of the first basic function module is less than or equal to a set threshold, the preset netlist corresponding to the first basic function module is directly called as the netlist corresponding to the first basic function module.
[0070] This situation refers to the situation that during the training process of the large language model, the training data includes the descriptions of each basic functional module with a number of bits less than or equal to the set threshold and the corresponding netlist, so that the large language model learns what the corresponding netlist looks like for the descriptions of each basic functional module with a number of bits less than or equal to the set threshold. Then, in the actual use of the large language model, for the basic functional modules with a number of bits less than the set threshold that have been learned, their corresponding netlists can be directly called. For example, the number of bits of combinational logic circuits is usually greater than 16 bits at present, so the netlists corresponding to each basic functional module with a number of bits less than or equal to 16 bits can be learned during the training process of the large language model so that the large language model can be directly called during use.
[0071] The second type is that if the number of bits of the first basic function module is greater than a set threshold, the second basic function module is decomposed into multiple first basic function modules according to the generation principle of the second basic function module, and a netlist corresponding to the second basic function module is generated according to the preset netlist corresponding to each first basic function module.
[0072] Specifically, when decomposing the second basic function module into multiple first basic function modules according to the generation principle of the second basic function module, the type of the second basic function module can be determined first, and then the second function module can be derived according to the generation principle of the basic function module of this type in the training sample, and the second basic function module can be decomposed into multiple first basic function modules.
[0073] During the training process of the large language model, it is impossible to learn the netlists corresponding to the basic function modules of all bit numbers. Therefore, during the training process of the large language model, for various types of basic function modules, the training data also includes the reasoning process of decomposing the high-order basic function modules into multiple low-order basic function modules, so that the large language model can learn how to split the basic function modules with a number of bits greater than the set threshold into basic function modules with a number of bits less than or equal to the set threshold, or the large language model also learns how to split the basic function modules that have not been learned into the basic function modules that have been learned.
[0074] For example, when training a large language model, based on the training data, the netlist corresponding to the adder of less than or equal to 16 bits and the reasoning process of splitting a 32-bit adder into two 16-bit adders can be learned. Then, in actual use, for a 64-bit adder, the large language model can split it into two 32-bit adders, and then split each 32-bit adder into two 16-bit adders. Alternatively, when training a large language model, based on the training data, the netlist corresponding to the adder of less than or equal to 16 bits and the complement generator of less than or equal to 16 bits can be learned, and for the subtractor, the subtractor can be split into an adder and a complement generator. Then, in actual use, for a 32-bit subtractor, the large language model can first split it into a 32-bit adder and a 32-bit complement generator, and then split the 32-bit adder into two 16-bit adders, and split the 32-bit complement generator into two 16-bit complement generators.
[0075] Step 104: Combine the netlist corresponding to at least one basic functional module to obtain a netlist of a target combinational logic circuit.
[0076] The netlist of the target combinational logic circuit can be obtained by combining the netlists corresponding to all the functional modules after decomposition of the target combinational logic circuit.
[0077] Compared with directly generating a netlist corresponding to a combinational logic circuit, generating a netlist corresponding to a basic function module is faster and more accurate. When the large language model of the embodiment of the present application generates a corresponding netlist from the natural language description of the target combinational logic circuit, it first splits the complex combinational logic circuit into relatively simple intermediate-level basic function modules, then generates a netlist corresponding to each basic function module, and then combines the netlist corresponding to at least one basic function module to obtain the netlist of the target logic circuit. This enables the large language model to generate a netlist of a combinational logic circuit more accurately and quickly.
[0078] Figure 2 A flow chart of a method for training a large language model provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the method includes:
[0079] Step 201: Use the description of each basic functional module in the combinational logic circuit and the corresponding netlist as prompt words for the large language model, and train the large language model so that the large language model has the function of generating the netlist corresponding to the basic functional module according to the description of the basic functional module.
[0080] refer to Figure 3A schematic diagram of training a large language model, wherein the description of each basic functional module in the combinational logic circuit of training data 1 and the corresponding netlist are used as prompt words for the large language model, and the large language model is trained so that the large language model has the function of generating the netlist corresponding to the basic functional module according to the description of the basic functional module.
[0081] Among them, the basic functional modules are components that can realize some basic functions, including adder, complement generator, multiplier, multiplexer, comparator, shift register, encoder and decoder, etc.
[0082] Specifically, the description of each basic functional module in the combinational logic circuit and the corresponding netlist are used as prompt words of the large language model to train the large language model, including the following two cases:
[0083] The first method is to train the large language model by using the description of the first basic function module and the corresponding netlist as prompt words of the large language model for each first basic function module whose bit number is less than or equal to a set threshold.
[0084] This situation refers to the situation that during the training process of the large language model, the training data includes the descriptions of each basic functional module whose number of bits is less than or equal to the set threshold and the corresponding netlist, so that the large language model learns what the corresponding netlist looks like when the descriptions of each basic functional module whose number of bits is less than or equal to the set threshold are. Then, in the actual use of the large language model, for the basic functional modules whose number of bits has been learned is less than the set threshold, their corresponding netlists can be directly called. For example, the number of bits of combinational logic circuits is usually greater than 16 bits at present, so the netlists corresponding to each basic functional module whose number of bits is less than or equal to 16 bits can be learned during the training process of the large language model so that the large language model can be directly called during use. For different large language models, the set threshold can be adaptively adjusted according to factors such as their parameter size and learning ability.
[0085] The second method is to use the description of each second basic function module, the reasoning process of decomposing each second basic function module into multiple first basic function modules, and the netlist corresponding to each first basic function module as prompt words of the large language model to train the large language model.
[0086] During the training process of the large language model, it is impossible to learn the netlists corresponding to the basic function modules of all bit numbers. Therefore, during the training process of the large language model, for various types of basic function modules, the training data also includes the reasoning process of decomposing the high-order basic function modules into multiple low-order basic function modules, so that the large language model can learn how to split the basic function modules with a number of bits greater than the set threshold into basic function modules with a number of bits less than or equal to the set threshold, or the large language model also learns how to split the basic function modules that have not been learned into the basic function modules that have been learned.
[0087] For example, when training a large language model, in addition to allowing the large language model to learn the netlists corresponding to each basic functional module less than or equal to 16 bits, the training data may also include the reasoning process of splitting a 32-bit adder into two 16-bit adders. Then, in actual use, for a 64-bit adder, the large language model can split the 64-bit adder into two 32-bit adders based on the reasoning process of splitting the 32-bit adder, and then split each 32-bit adder into two 16-bit adders. Alternatively, when training a large language model, in addition to allowing the large language model to learn the netlists corresponding to adders less than or equal to 16 bits and complement generators less than or equal to 16 bits, the training data may also include the reasoning process of splitting a subtractor into an adder and a complement generator. Then, in actual use, for a 32-bit subtractor, the large language model can split the 32-bit subtractor into a 32-bit adder and a 32-bit complement generator according to the reasoning process of the subtractor splitting, and then split the 32-bit adder into two 16-bit adders, and split the 32-bit complement generator into two 16-bit complement generators.
[0088] The following is an example to illustrate this. The training data provides a generation principle of a 3-bit*3-bit multiplier. After the large language model learns the generation principle of the 3-bit*3-bit multiplier, it can generate a 4-bit*4-bit multiplier according to the generation principle of the 3-bit*3-bit multiplier.
[0089] The generation principle of 3-bit*3-bit multiplier is as follows:
[0090]
[0091]
[0092] In order to better understand the above content, the corresponding translation is as follows:
[0093] For a 3*3 digital multiplier, the product output is 6 bits because 3+3=6. If the input is AA[2:0] and BB[2:0], we can derive the output PP[5:0] as follows:
[0094] We deduce that PP[0] = AA[0] & BB[0], where & represents the function of an AND gate in digital logic. For PP[1], it comes from an adder with output C1.
[0095] For this adder, its first input is AA[0]&BB[1], the second input is AA[1]&BB[0], and its output C1 is 2 bits. Since the maximum output can be 1+1=2, C1[1:0]=(AA[0]&BB[1])+(AA[1]&BB[0]).
[0096] We deduce that PP[1] = C1[0], and
[0097] C1[1] is used to derive the carry from PP[2].
[0098] For PP[2], it comes from an adder with output C2.
[0099] For this adder, the first input is AA[0]&BB[2], the second input is AA[1]&BB[1], the third input is AA[2]&BB[0], the fourth input is C1[1], and the output C2 is 3 bits. Since the maximum output can be 1+1+1+1=4,
[0100] C2[2:0]=(AA[0]&BB[2])+(AA[1]&BB[1])+(AA[2]&BB[0]+C1[1].
[0101] We deduce that PP[2] = C2[0], and
[0102] C2[1] is used to derive the carry of PP[3],
[0103] C2[2] is used to derive the carry from PP[4].
[0104] For PP[3], it comes from an adder with output C3.
[0105] For this adder, the first input is AA[1]&BB[2], the second input is AA[2]&BB[1], the third input is C2[1], and the output C3 is 2 bits because the maximum output can be 1+1+1=3, so C3[1:0]=(AA[1]&BB[2])+(AA[2]&BB[1])+C2[1].
[0106] We deduce that PP[3]=C3[0],
[0107] And C3[1] is used as the carry to derive PP[4].
[0108] For PP[4], it comes from an adder with output C4.
[0109] For this adder, the first input is AA[2]&BB[2], the second input is C2[2], the third input is [3[1], and the output C4 is 2 bits because the maximum output can be 1+1+1=3, so C4[1:0]=(AA[2]&BB[2])+C2[2]+C3[1].
[0110] We deduce that PP[4]=C4[0].
[0111] Finally, we deduce that PP[5]=C4[1].
[0112] Please follow the example above and use the 4-bit input AA[3:0]*4-bit input BB[3:0] to derive the output PP[7:0] of this digital multiplier.
[0113] Based on the above 3-bit*3-bit multiplier generation process, the 4-bit*4-bit multiplier generated by the large language model is as follows:
[0114]
[0115]
[0116] In order to better understand the above content, the corresponding translation is as follows:
[0117] PP[0] is the AND of the least significant bits of AA and BB:
[0118] PP[0]=AA[0]&BB[0]
[0119] PP[1] involves the sum of two partial products:
[0120] PP[1]=(AA[0]&BB[1])+(AA[1]&BB[0])
[0121] If we use a full adder on this sum, the full adder will give us two outputs: a sum and a carry in. We'll record the carry in from this addition as C1[1] and the sum as PP[1]. The full adder will take into account any carries from previous less significant bits, but since PP[1] is the first addition after PP[0], there is no previous carry in.
[0122] PP[2] involves the sum of three partial products and the carry from the previous addition:
[0123] PP[2]=(AA[0]&BB[2])+(AA[1]&BB[1])+(AA[2]&BB[0])+C1[1]
[0124] We will use a 3-bit adder (or multiple full adders) to do the summing. The sum is PP[2] and the carry is C2[1:0], where C2[0] is the carry into the next less significant bit and C2[1] is the carry into the next more significant bit.
[0125] PP[3] involves the sum of four partial products and the carry from the previous addition:
[0126] PP[3]=(AA[0]&BB[3])+(AA[1]&BB[2])+(AA[2]&BB[1])+(AA[3]&BB[0])+
[0127] The sum of C2[0] is PP[3], and the carry is C3[1:0], the logic is the same as before.
[0128] PP[4] involves the sum of four partial products and two carries from previous additions: PP[4] = (AA[1] &
[0129] BB[3])+(AA[2]&BB[2])+(AA[3]&BB[1])+C2[1]+C3[0]
[0130] The sum is PP[4] and the carry is C4[1:0].
[0131] PP[5] involves the sum of three partial products and two carries:
[0132] PP[5]=(AA[2]&BB[3])+(AA[3]&BB[2])+C3[1]+C4[0]
[0133] The sum is PP[5] and the carry is C5[1:0].
[0134] PP[6] involves the sum of two partial products and two carries:
[0135] PP[6]=(AA[3]&BB[3])+C4[1]+C5[0]
[0136] The sum is PP[6] and the carry is C6[0].
[0137] PP[7] is the carry from the previous addition:
[0138] PP[7]=C5[1]+C6[0]
[0139] Since this is the most significant bit, no other carries need to be considered.
[0140] It can be seen that the large language model can accurately generate a 4-bit*4-bit multiplier based on the above 3-bit*3-bit multiplier generation process. If the output result of the large language model is incorrect, the details of the prompt word are added according to the output result of the large language model to make the output result of the large language model more accurate.
[0141] Step 202: Use the natural language description of each target combinational logic circuit and the reasoning process of decomposing each combinational logic circuit into basic functional modules as prompt words of the large language model, and train the large language model so that the large language model has the function of decomposing the target combinational logic circuit into at least one basic functional module.
[0142] refer to Figure 3 Schematic diagram of training a large language model. During the training process of the large language model, training data 2 includes an inference process of decomposing a combinational logic circuit into basic functional modules, so that the large language model can learn how to decompose a target combinational logic circuit into at least one basic functional module based on a natural language description of the target combinational logic circuit.
[0143] Specifically, training data 2 needs to meet the following points:
[0144] 1. It has a reasoning process that decomposes combinational logic circuits into basic functional modules, and this reasoning process can be understood by a large language model.
[0145] 2. The input interface of each basic functional module is consistent with the output interface of the previous basic functional module. For example, the two 16-bit adders and two 16-bit complement generators in the above example should be connected to the correct input and output ports.
[0146] 3. The language habits of the training data are consistent. The language habits are consistent, including consistent word descriptions and consistent structures. For example, consistent word descriptions mean that for conditional expressions, "if..., then..., else..." ("if..., then..., otherwise...") are used. In order to produce reliable results, the descriptions of such conditional expressions are split in a unified way. For example: if (A = 0, then B = W), else (if A = 1, then B = X), else (if A = 2, then B = Y), else (B = Z), then the various conditions of A are implemented by the multiplexer method. Structural consistency means that the structure of the natural language description of the target combinational logic circuit in the training data is to describe the input first, then the output, and then the function.
[0147] It should be noted that the above training method of the embodiment of the present application is performed under the premise that the large language model has mastered the basic knowledge of combinational logic circuits (including various logic gates, netlists, truth tables, Boolean definitions and functions, etc.). If the large language model has not mastered the basic knowledge of combinational logic circuits, it is necessary to first train the large language model to master the basic knowledge of combinational logic circuits.
[0148] In the process of training the large language model, if the output result of the large language model is incorrect, the details of the prompt words are added according to the output result of the large language model to make the output result of the large language model more accurate.
[0149] Based on the same technical concept, Figure 4 A schematic diagram of a device for converting natural language into a netlist of a combinational logic circuit provided in an embodiment of the present application, such as Figure 4 As shown, the device comprises:
[0150] The receiving module 401 is used to receive a natural language description of a target combinational logic circuit from a user; the natural language description of the target combinational logic circuit includes a description of the input, output and function of the combinational logic circuit;
[0151] A processing module 402 is used to decompose the target combinational logic circuit into at least one basic functional module according to the natural language description of the target combinational logic circuit, and generate a description of each basic functional module;
[0152] The processing module 402 is further used to generate a netlist corresponding to each basic function module based on the description of each basic function module;
[0153] The processing module 402 is further configured to combine the netlist corresponding to the at least one basic functional module to obtain the netlist of the target combinational logic circuit.
[0154] In one possible design, the processing module 402, when decomposing the target combinatorial logic circuit into at least one basic functional module according to the natural language description of the target combinatorial logic circuit and generating a description of each basic functional module, is specifically used to decompose the target combinatorial logic circuit into at least one basic functional module according to the reasoning process of decomposing the combinatorial logic circuit into basic functional modules in the training samples, and generate a description of each basic functional module.
[0155] In a possible design, the processing module 402, when generating a netlist corresponding to each basic function module according to the description of each basic function module, is specifically used to directly call a preset netlist corresponding to a first basic function module as the netlist corresponding to the first basic function module if the number of bits of the first basic function module is less than or equal to a set threshold; if the number of bits of the first basic function module is greater than the set threshold, the second basic function module is decomposed into multiple first basic function modules according to the generation principle of the second basic function module, and a netlist corresponding to the second basic function module is generated according to the preset netlists corresponding to the first basic function modules.
[0156] In one possible design, the processing module 402 is specifically used to determine the type of the second basic function module when decomposing the second basic function module into multiple first basic function modules according to the generation principle of the second basic function module; derive the second basic function module according to the generation principle of the basic function module of the type in the training sample, and decompose the second basic function module into multiple first basic function modules.
[0157] Based on the same technical concept, Figure 5 A schematic diagram of a large language model training device provided in an embodiment of the present application, such as Figure 5 As shown, the device comprises:
[0158] The first training module 501 is used to use the description of each basic functional module in the combinational logic circuit and the corresponding netlist as prompt words of the large language model, and train the large language model so that the large language model has the function of generating the netlist corresponding to the basic functional module according to the description of the basic functional module;
[0159] The second training module 502 is used to use the natural language description of each target combinational logic circuit and the reasoning process of decomposing each combinational logic circuit into basic functional modules as prompt words of the large language model, and train the large language model so that the large language model has the function of decomposing the target combinational logic circuit into at least one basic functional module.
[0160] In a possible design, the first training module 501, when using the description of each basic function module in the combinational logic circuit and the corresponding netlist as prompt words of the large language model to train the large language model, is specifically used for, for each first basic function module whose number of bits is less than or equal to a set threshold, using the description of the first basic function module and the corresponding netlist as the prompt words of the large language model to train the large language model; for each second basic function module whose number of bits is greater than the set threshold, using the description of the second basic function module, the reasoning process of decomposing the second basic function module into multiple first basic function modules, and the netlist corresponding to the first basic function module as the prompt words of the large language model to train the large language model.
[0161] In a possible design, the first training module 501 and the second training module 502 are further used to increase the details of the prompt word according to the output result of the large language model if the output result of the large language model is incorrect.
[0162] Based on the same technical concept, the present application embodiment provides a computing device, such as Figure 6 As shown, it includes at least one processor 601 and a memory 602 connected to the at least one processor. The specific connection medium between the processor 601 and the memory 602 is not limited in the embodiment of the present application. Figure 6 For example, the processor 601 and the memory 602 are connected via a bus. The bus can be divided into an address bus, a data bus, a control bus, etc.
[0163] In an embodiment of the present application, the memory 602 stores instructions that can be executed by at least one processor 601. By executing the instructions stored in the memory 602, at least one processor 601 can execute the above-mentioned method of converting natural language into a netlist of a combinational logic circuit and the training method of a large language model.
[0164] The processor 601 is the control center of the computing device, and can use various interfaces and lines to connect various parts of the computer device, and perform resource settings by running or executing instructions stored in the memory 602 and calling data stored in the memory 602.
[0165] Optionally, the processor 601 may include one or more processing units, and the processor 601 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the modem processor may not be integrated into the processor 601. In some embodiments, the processor 601 and the memory 602 may be implemented on the same chip, and in some embodiments, they may also be implemented separately on separate chips.
[0166] Processor 601 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware processor for execution, or can be executed by a combination of hardware and software modules in the processor.
[0167] The memory 602 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 602 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, etc. The memory 602 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 602 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.
[0168] Based on the same technical concept, an embodiment of the present application also provides a computer-readable storage medium, which stores a computer executable program. The computer executable program is used to enable a computer to execute any of the above-mentioned methods for converting natural language into a netlist of a combinational logic circuit and a training method for a large language model.
[0169] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0170] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0171] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0172] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0173] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0174] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A method for converting natural language into a netlist of a combinational logic circuit, applied to a large language model, characterized in that: The method comprises: Receiving a natural language description of a target combinational logic circuit from a user; the natural language description of the target combinational logic circuit includes a description of an input, an output, and a function of the combinational logic circuit; According to the natural language description of the target combinational logic circuit, decompose the target combinational logic circuit into at least one basic functional module, and generate a description of each basic functional module; Based on the description of each basic functional module, generate a netlist corresponding to each basic functional module; The netlist corresponding to the at least one basic function module is combined to obtain the netlist of the target combinational logic circuit.
2. The method according to claim 1, characterized in that According to the natural language description of the target combinational logic circuit, the target combinational logic circuit is decomposed into at least one basic functional module, and a description of each basic functional module is generated, including: According to the reasoning process of decomposing the combinational logic circuit into basic functional modules in the training sample, the target combinational logic circuit is decomposed into at least one basic functional module, and a description of each basic functional module is generated.
3. The method according to claim 1, characterized in that: According to the description of each basic functional module, a netlist corresponding to each basic functional module is generated, including: If the number of bits of the first basic function module is less than or equal to the set threshold, directly calling the preset netlist corresponding to the first basic function module as the netlist corresponding to the first basic function module; If the number of bits of the first basic function module is greater than a set threshold, the second basic function module is decomposed into multiple first basic function modules according to the generation principle of the second basic function module, and a netlist corresponding to the second basic function module is generated according to the preset netlist corresponding to each first basic function module.
4. The method according to claim 1, characterized in that: According to the generation principle of the second basic function module, the second basic function module is decomposed into a plurality of first basic function modules, including: Determining the type of the second basic functional module; According to the generation principle of the basic function module of the type in the training sample, the second function module is derived and decomposed into a plurality of first basic function modules.
5. A method for training a large language model, characterized in that: The method comprises: The description of each basic function module in the combinational logic circuit and the corresponding netlist are used as prompt words of the large language model, and the large language model is trained so that the large language model has the function of generating the netlist corresponding to the basic function module according to the description of the basic function module; The natural language description of each target combinational logic circuit and the reasoning process of decomposing each combinational logic circuit into basic functional modules are used as prompt words of the large language model, and the large language model is trained so that the large language model has the function of decomposing the target combinational logic circuit into at least one basic functional module.
6. The method according to claim 5, characterized in that The method uses the description of each basic functional module in the combinational logic circuit and the corresponding netlist as prompt words of the large language model, and trains the large language model, including: For each first basic function module whose bit number is less than or equal to a set threshold, the description of the first basic function module and the corresponding netlist are used as prompt words of the large language model to train the large language model; For each second basic function module whose bit number is greater than a set threshold, the description of each second basic function module, the reasoning process of decomposing each second basic function module into multiple first basic function modules, and the netlist corresponding to each first basic function module are used as prompt words of the large language model to train the large language model.
7. The method according to claim 5, characterized in that The method further comprises: If the output result of the large language model is incorrect, the details of the prompt word are added according to the output result of the large language model.
8. A device for converting natural language into a netlist of a combinational logic circuit, characterized in that: The device comprises: A receiving module, configured to receive a natural language description of a target combinational logic circuit from a user; the natural language description of the target combinational logic circuit includes a description of the input, output and function of the combinational logic circuit; A processing module, configured to decompose the target combinatorial logic circuit into at least one basic functional module according to the natural language description of the target combinatorial logic circuit, and generate a description of each basic functional module; The processing module is further used to generate a netlist corresponding to each basic function module based on the description of each basic function module; The processing module is further used to combine the netlist corresponding to the at least one basic function module to obtain the netlist of the target combinational logic circuit.
9. A computing device, characterized in that include: A memory for storing program instructions; A processor is used to call the program instructions stored in the memory, and execute the method according to any one of claims 1 to 6 according to the obtained program instructions.
10. A computer-readable storage medium, characterized in that: The method comprises computer-readable instructions, and when a computer reads and executes the computer-readable instructions, the method according to any one of claims 1 to 6 is implemented.