Integrated circuit with complementary non-volatile resistive memory elements

Abstract

An integrated circuit having a memory element is provided. The memory elements may include non-volatile resistive elements coupled together in a back-to-back configuration or a queued configuration. Erasing, programming, and margining operations may be performed on the resistive element. Each resistive memory element may receive a positive voltage, a ground voltage, or a negative voltage on the anode terminal or the cathode terminal.

Description

[0001] This application is a divisional application of an application filed on May 15, 2018, with application number 201810461700.9 and invention name “Integrated circuit with complementary non-volatile resistance memory elements”. Background Art

[0002] Integrated circuits such as programmable integrated circuits often contain volatile memory elements in the form of static random access memory (SRAM) cells. In a programmable integrated circuit, an SRAM cell can be used as a configuration random access memory (CRAM) cell. A programmable integrated circuit is a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. A CRAM cell is used to store configuration data supplied by a user. Once loaded, the CRAM cell supplies control signals to the transistor to configure the transistor to implement the desired logic function.

[0003] A pair of cross-coupled inverters are generally used to form volatile memory elements, such as SRAM and CRAM cells. In each memory cell, the pair of cross-coupled inverters may be connected to an address transistor, which is turned on when data is read from or written to the memory cell. When no data is read from or written to the memory cell, the address transistor is turned off to isolate the memory cell.

[0004] There is a trend to scale transistors toward smaller sizes, lower threshold voltages, and lower supply voltages with each successive generation of integrated circuit technology. Lower supply voltages and smaller devices may result in reduced read / write margins for volatile memory elements. This may present challenges for reliable device operation.

[0005] However, smaller devices tend to be more subject to process, voltage, and temperature variations (PVT variations).Operating memory elements at lower supply voltages can further exacerbate the amount of variation experienced by the memory elements, resulting in reduced memory yields.

[0006] The embodiments described herein arise within this context. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram of an illustrative programmable integrated circuit in accordance with an embodiment.

[0008] Figure 2 is a diagram of an illustrative memory array in accordance with an embodiment.

[0009] Figure 3A and 3B is a diagram of an illustrative back-to-back nonvolatile resistive memory element according to an embodiment.

[0010] Figure 4 is a circuit diagram illustrating a single-bit erase operation on a resistance memory array according to an embodiment.

[0011] Figure 5 is a circuit diagram illustrating a single-bit program operation on a resistance memory array according to an embodiment.

[0012] Figure 6 is a circuit diagram illustrating a global erase operation on a resistive memory array according to an embodiment.

[0013] Figure 7 is a circuit diagram illustrating a normal retention operation for a resistance memory array according to an embodiment.

[0014] Figure 8 is a circuit diagram illustrating a read operation on a resistive memory array according to an embodiment.

[0015] Fig.9A is a circuit diagram illustrating a top-bit margin test operation on a resistive memory array according to an embodiment.

[0016] Fig. 9B is a circuit diagram illustrating a bottom-bit margin test operation on a resistive memory array according to an embodiment.

[0017] Fig. 9C is a circuit diagram illustrating a set bit margin test operation on a resistive memory array according to an embodiment.

[0018] Fig.10 is a diagram of an illustrative inline nonvolatile resistive memory element according to an embodiment.

[0019] Fig.11 is a circuit diagram illustrating a combined program-erase operation on a resistive memory array according to an embodiment. DETAILED DESCRIPTION

[0020] The present embodiment relates to an integrated circuit including an array of memory elements. The array of memory elements can be used to store data during data processing operations. In a programmable integrated circuit such as a programmable logic device, the array of memory elements can be loaded with configuration data used when configuring the programmable logic circuit. The memory elements used when storing configuration data for a programmable integrated circuit are sometimes referred to as configuration random access memory (CRAM) cells. Memory cells used in other types of random access memory (RAM) arrays are sometimes referred to as RAM cells.

[0021] The memory cells may be used in any suitable integrated circuit that uses memory. Such types of integrated circuits may include memory chips, digital signal processing circuits with memory arrays, microprocessors, application specific integrated circuits with memory arrays, programmable integrated circuits (e.g., programmable logic device integrated circuits in which memory cells are used for configuration memory), or any other suitable integrated circuit.

[0022] exist Figure 1 1 and 2. An illustrative integrated circuit 10 including a memory is shown in FIG. Device 10 may have input-output (I / O) circuits 12 for driving signals away from device 10 and for receiving signals from other devices via input-output pins 14. Interconnect resources 16 (e.g., global and local vertical and horizontal conductive lines and buses) may be used to route signals on device 10. Interconnect resources 16 include fixed interconnects (conductive lines) and programmable interconnects (i.e., programmable connections between corresponding fixed interconnects). Programmable logic 18 may include combinational and sequential logic circuits. Programmable logic 18 may be configured to perform custom logic functions. Programmable interconnects associated with interconnect resources may be considered part of programmable logic 18.

[0023] Device 10 includes volatile memory cells 20 that can be loaded with configuration data (also referred to as programming data) using pins 14 and input-output circuits 12. Once loaded, the memory cells can provide corresponding static control output signals that control the state of associated logic components in programmable logic 18. Memory cells 20 can be used in an SRAM-type memory array if desired (e.g., to store data for processing circuits during operation of device 10).

[0024] The memory cell 20 may be formed of a plurality of transistors configured to form a bi-stable circuit. The memory cell may be loaded from an external erasable programmable read-only memory and control chip or other suitable data source via the pins 14 and the input-output circuit 12. The loaded CRAM memory cell 20 may provide a static control signal that is applied to the terminals (e.g., gates) of circuit elements (e.g., metal oxide semiconductor transistors) in the programmable logic 18 to control those elements (e.g., to turn certain transistors on or off) and thereby configure the logic in the programmable logic 18. The circuit elements may be transistors, such as pass transistors, portions of multiplexers, lookup tables, logic arrays, AND, OR, NAND, and NOR logic gates, etc.

[0025] The memory cells 20 may be arranged in an array pattern. In a typical modern programmable logic device, there may be millions of memory cells 20 on the chip 10. During a programming operation, the array of memory cells is provided with configuration data by a user (e.g., a logic designer). Once loaded with the configuration data, the memory cells 20 selectively control portions of the circuitry in the programmable logic 18 and thereby customize its functionality so that it will operate as desired.

[0026] Any suitable architecture may be used to organize the circuits of device 10. As an example, the logic of device 10 may be organized in a series of rows and columns of larger programmable logic regions, each of which contains multiple smaller logic regions. The logic resources of device 10 may be interconnected by interconnection resources 16 (e.g., associated vertical and horizontal conductors). These conductors may include global conductive lines that span substantially all of device 10, fractional lines (e.g., half lines or quarter lines) that span a portion of device 10, staggered lines of a specific length (e.g., sufficient to interconnect several logic regions), smaller local lines, or any other suitable interconnection resource arrangement. If desired, the logic of device 10 may be arranged in more hierarchies or layers, with multiple large regions interconnected to form even larger portions of logic. Other device arrangements may still use logic that is not arranged in rows and columns.

[0027] When the memory cells 20 are arranged in an array, the horizontal and vertical conductors and associated control circuitry can be used to access the memory cells. The control circuitry can, for example, be used to clear all or some of the memory cells. The control circuitry can also write data to the memory cells and can read data from the memory cells. For example, in a CRAM array, the memory cells can be loaded with configuration data. Before the device 10 is used during normal operation in a system, the loaded configuration data can then be read out from the array to confirm the correct data loading operation.

[0028] As described above, any suitable memory array architecture may be used to arrange the memory cells 20. Figure 2 A suitable arrangement is shown in FIG. Figure 2 There are only three rows and columns of memory cells 20 in the illustrative array of , but there may typically be hundreds or thousands of rows and columns in memory array 28. Array 20 may be one of multiple arrays on device 10, may be a sub-array that is part of a larger array, or may be any other suitable grouping of memory cells 20.

[0029] Each memory cell 20 may provide a respective output signal OUT at a respective output path 38. In a CRAM array, each signal OUT is a static output control signal that may be transmitted on a respective path 40 and may be used in configuring an associated transistor, such as transistor 36 (e.g., a pass transistor), or other appropriate circuit element in an associated programmable logic circuit.

[0030] Integrated circuit 10 may have control circuitry 24 for supplying signals to memory array 28. Control circuitry 24 may receive supply voltage, data, and other signals from an external source using pins 14 and from an internal source using paths such as path 30. Control circuitry 24 may include circuitry such as addressing circuitry, data register circuitry, read / write circuitry, etc. Control circuitry 24 may use the supply voltage supplied through pins 14 to generate desired time-varying and fixed signals on paths 32 and 34.

[0031] In general, there may be any suitable number of conductive lines associated with paths 32 and 34. For example, each row of array 28 may have a corresponding path 32 including an associated address line (e.g., a word line) and / or an associated read / write enable line (as examples). Each column of array 28 may have a corresponding path 34 including one or more data lines.

[0032] In general, power can be distributed in a global manner. For example, a positive power supply voltage Vcc can be supplied in parallel to each cell 20 using a pattern of shared horizontal or vertical conductors. A ground voltage Vss can also be supplied in parallel to the cells 20 using a pattern of shared horizontal or vertical lines. Control lines (e.g., address lines) and data lines are generally orthogonal to each other (e.g., address lines are horizontal, while data lines are vertical, or vice versa).

[0033] Positive power supply voltage Vcc can be provided on the positive power line, and ground voltage Vss can be provided on the ground power line.Any appropriate value can be used for positive power supply voltage Vcc and ground voltage Vss.For example, positive power supply voltage Vcc can be 2V, 1.2V, 1.1V, 1.0V, 0.9V, less than 0.9V or any other appropriate voltage.Ground voltage Vss can be zero volt or 0.1V (as an example).In general arrangement, power supply voltage Vcc can be 0.85V, Vss can be zero volt, and the signal level of address, data and clear signal can range from zero volt or -2V (when low) to +2V (when high).If necessary, also can use wherein Vcc changes according to time, Vss is less than zero volt and control signal is overdriven (that is, wherein control signal has signal strength greater than Vcc-Vss).

[0034] The terms "row" and "column" represent merely a way of referring to a particular group of cells 20 in memory array 28, and are sometimes used interchangeably. Other patterns of lines may be used in paths 32 and 34 if desired. For example, different numbers of power signals, data signals, and address signals may be used.

[0035] Conventionally, configuration memory elements are implemented using volatile memory elements (e.g., SRAM memory cells). Volatile memory elements only retain data as long as the integrated circuit is powered. In the event of a power loss, the data in the volatile memory element is lost. Volatile memory elements are subject to a phenomenon known as a single event upset. Single event upset events are caused by cosmic rays and radioactive impurities embedded in integrated circuits and their packaging. Cosmic rays and radioactive impurities produce high-energy atomic particles, such as neutrons and alpha particles. Memory elements contain transistors and other components formed from a patterned silicon substrate. When atomic particles strike the silicon in the memory element, electron-hole pairs are generated. Electron-hole pairs create a conductive path that can discharge a charged node in the memory element and flip the state of the memory element. If, for example, "1" is stored in a memory element, a single event upset (SEU) can change "1" to "0."

[0036] Upset events in integrated circuits destroy data stored in memory elements and can have severe effects on system performance. In certain system applications such as remote installations of telecommunication equipment, repairing faulty equipment is extremely burdensome. Unless integrated circuits exhibit good immunity to single event upsets, they will not be suitable for these types of applications.

[0037] According to an embodiment, integrated circuit 10 may include memory circuits implemented using non-volatile memory elements (eg, memory cells that retain their state regardless of whether device 10 is supplied with power). Figure 3A and 3B is a diagram of an illustrative back-to-back nonvolatile resistive memory element 20 according to an embodiment.

[0038] like Figure 3A As shown, the memory element 20 (sometimes referred to as a memory cell) may include a first non-volatile resistance element 300-1 and a second non-volatile resistance element 300-2 coupled in series between a positive power supply line 302 (e.g., a first power supply line, on which a positive power supply voltage Vcc is provided) and a ground power supply line 304 (e.g., a second power supply line, on which a ground power supply voltage Vss is provided). The power supply voltage Vcc may have a positive voltage level +V (e.g., 1V, 1.2V, 1.8V, 2V, etc.). The power supply voltage Vss may have a ground voltage level (e.g., 0V).

[0039] In particular, resistor element 300-1 may have a first (anode) terminal connected to line 302 and a second (cathode) terminal connected to output node Out. Resistor element 300-2 may have a first (anode) terminal connected to line 304 and a second (cathode) terminal connected to node Out. Typically, lines 302 and 304 may be provided with adjustable supply voltages or may be in a high impedance mode. This arrangement in which the cathode of resistor element 300-1 is connected to and facing the cathode of resistor element 300-2 is sometimes referred to as a "back-to-back" configuration.

[0040] An address transistor such as transistor 306 may be coupled between data line DL and node Out. Transistor 306 may be activated using word line signal WL to load a desired data value into memory cell 20. Transistor 306 is therefore sometimes referred to as a programming transistor or an access transistor.

[0041] The output node Out of the memory cell 20 can be connected to the output node via the output path 38 (see also Figure 2 ) are coupled to corresponding pass transistors 36. Pass transistors 36 (sometimes referred to as pass gates) may be, as examples, part of a routing multiplexer for routing active user signals from a first logic region to a second logic region on an integrated circuit, part of a programmable switch in a lookup table, or part of other configurable logic circuits 18 on an integrated circuit.

[0042] Each resistor element 300 (e.g., resistor elements 300-1 and 300-2) can be a two-terminal electrochemical metallization memory device that relies on a redox reaction to form (i.e., "program") or decompose (i.e., "erase") a conductive filament between the two terminals. The presence of the conductive filament between the two terminals produces a low resistance state (LRS), while the absence of the conductive filament between the two terminals produces a high resistance state (HRS). In LRS, the resistor element is sometimes referred to as being short-circuited or closed (i.e., activated, set, or programmed). In HRS, the resistor element is sometimes referred to as being disconnected or deactivated (i.e., out of use). The resistor element 300 configured in this manner is sometimes referred to as a programmable metallization cell (PMC) or a conductive bridge RAM (CBRAM). If desired, a magnetic RAM cell may also be used. Complementary memory cells configured in this manner can exhibit non-volatile behavior, single-particle upset immunity, and very low standby current.

[0043] exist Figure 3AIn the example of , memory cell 20 can be set to a high state (e.g., resistor element 300-1 can be programmed in a low resistance state, as indicated by the bold internal connection, while resistor element 300-2 is erased to a high resistance state, as indicated by the absence of the internal connection). Configured in this manner, node Out will be pulled up by positive supply voltage Vcc through resistor element 300-1, thereby passing voltage level V+ to turn on corresponding pass transistor 36.

[0044] exist Figure 3B In the example of , memory cell 20 can be set to a low state (e.g., resistor element 300-2 can be programmed in a low resistance state, as indicated by the bold internal connection, while resistor element 300-1 is erased to a high resistance state, as indicated by the absence of the internal connection). Configured in this manner, node Out will be pulled down by ground supply voltage Vss through resistor element 300-2, thereby passing zero volts to turn off the corresponding pass transistor 36.

[0045] Figure 4 4 is a circuit diagram showing a single-bit erase operation on a memory array 400 including memory cells 20 formed using complementary back-to-back resistance memory elements. Figure 4 As shown, the memory array 400 can be controlled by a column addressing circuit 402 and a row driver circuit 404. The addressing circuit 402 (e.g., a shift register circuit or a decoder circuit) can output address signals to corresponding address transistors in each column of memory cells 20. Figure 4 In the example of FIG. 4 , the address circuit 402 may output address signal AL0 to the corresponding address transistors 306-00, 306-10 and other transistors in the first column, and may also output address signal AL1 to the corresponding address transistors 306-01, 306-11 and other transistors in the second column, and so on. The address circuit 402 may activate only one column at a time (e.g., may have at most one address signal asserted at any given time). The addressing circuit enables logic "1" and disables logic "0" equivalent to the address circuit in FIG. Figure 4 and Figure 5 The +V or -V voltage defined in the bias.

[0046] The row driver circuit 404 may be coupled to associated data register circuits, power driver circuits, and read-write circuits. For example, the row driver circuit 404-0 in the first row may receive a data signal from the first data register DR0 and may drive the received data signal onto the first data line DL0 using the data line driver 408-0. During a read operation, the data line driver 408-0 may be deactivated, and the read driver 410-0 may be turned on to sense a read voltage on the data line DL0. Transistors 420 and 422 (e.g., n-channel transistors) may be coupled in series between the power line 424 and the data line DL0 to help read and / or monitor the performance of each memory cell 20. Transistor 420 may receive a bias control signal Vbias, and transistor 422 may receive a verification control signal Verify. The control signals Vbias and Verify may be global signals applied to each row (as an example) in the array 400.

[0047] Row driver circuit 404-0 may also selectively provide power signals to the power terminals of each memory cell 20 in the first row via power drivers 406T0 and 406B0. In particular, power driver 406T0 may provide an adjustable power signal T0 to the "top" power terminal of each memory cell 20 in the first row, while power driver 406B0 may provide an adjustable power signal B0 to the "bottom" power terminal of each memory cell in the first row. Power driver 406 may be, for example, a tri-state buffer. In an active mode, power driver 406 may output signals T0 and B0 equal to a positive voltage level +V or a negative voltage level -V. In a tri-state mode, the output of driver 406 may be in a high impedance state (e.g., the output node cannot be actively driven to any voltage level).

[0048] Similarly, the row driver circuit 404-1 in the second row can receive the data signal from the second data register DR1 and can drive the received data signal onto the second data line DL1 using the data line driver 408-1. During a read operation, the data line driver 408-1 can be deactivated and the read driver 410-1 can be turned on to sense the read voltage on the data line DL1. The data line DL1 can also be coupled to its own set of transistors 420 and 422 for reading and / or monitoring the performance of each memory cell 20 in the second row.

[0049] Row driver circuit 404-1 may also selectively provide power signals to power terminals of each memory cell 20 in the second row via power drivers 406T1 and 406B1 (e.g., tri-state buffer 406). In particular, power driver 406T1 may provide an adjustable power signal T1 to a top power terminal of each memory cell 20 in the second row, and power driver 406B1 may provide an adjustable power signal B1 to a bottom power terminal of each memory cell in the second row.

[0050] exist Figure 4 There are only two rows and two columns of memory cells 20 in the illustrative array of , but there may typically be hundreds or thousands of rows and columns in the memory array 400. The resistive memory element array 400 may be one of multiple arrays on a given device 10, may be a sub-array that is part of a larger array, or may be any other suitable grouping of memory cells 20.

[0051] Still reference Figure 4 , consider examples in which the memory element 20 in the upper left corner is initially configured in a high state (i.e., resistance element RT00 is in LRS and resistance element RB00 is in HRS) and in which the memory element 20 in the lower left corner is initially configured in a low state (i.e., resistance element RB10 is in LRS and resistance element RT10 is in HRS).

[0052] In order to perform a single-bit erase in the first row, driver 406T0 can drive signal T0 to a negative voltage level -V, while driver 406B0 is placed in a tri-state mode so that signal B0 is electrically floating (as indicated by the high impedance symbol "Z"). During this time, driver 408-0 can be activated to provide a voltage level +V to data line DL0. Address signal AL0 can be overdriven to a voltage level (+V+Vt), where Vt represents the threshold voltage level of transistor 306-00. Overdriving address transistor 306-00 can help pull the corresponding output node Out00 up to a voltage level +V. By driving the cathode of resistor element RT00 to +V and the anode of resistor element RT00 to -V in this way, resistor element RT00 can be erased to HRS. As long as signal B0 is in a high impedance state, resistor element RB00 can remain unchanged.

[0053] In order to perform a single-bit erase in the second row, driver 406T1 can drive signal T1 to a tri-state mode so that signal T1 is electrically floating (as indicated by the high impedance symbol Z), while driving signal B1 to a negative voltage level -V. During this time, driver 408-1 can be activated to provide a voltage level +V to data line DL1. Address signal AL0 can be overdriven to a voltage level (+V+Vt), where Vt represents the threshold voltage level of transistor 306-10. Overdriving address transistor 306-10 can help pull the corresponding output node Out10 up to a voltage level +V. By driving the cathode of resistor element RB10 to +V and the anode of resistor element RB10 to -V in this way, resistor element RB10 can be erased to HRS. As long as signal T1 is in a high impedance state, resistor element RT10 can remain unchanged.

[0054] This single bit erase operation may be performed in parallel for each memory cell 20 in a column, followed by erasing on a column-by-column basis (e.g., by sequentially asserting address signals AL0, AL1, etc.). Selectively tri-stating buffer 406 in Z-mode may also help provide zero voltage stress across all unselected resistor elements (see, e.g., Figure 4 There is no voltage stress across the resistor elements RB01 and RB11 in the circuit, so the unselected cells will not be disturbed).

[0055] Figure 5 4 is a circuit diagram illustrating a single-bit programming operation on a previously erased bit that may be performed on the resistor memory array 400. To program the upper left memory cell in the first row to store a logic "0" (as indicated by the data signal "0" in the data register DR0), the driver 406T0 may be placed in a tri-state mode such that the signal T0 is in a high impedance state Z, and the driver 406B0 may drive the signal B0 to a positive voltage level +V. During this time, the driver 408-0 may be activated to provide a negative voltage level -V to the data line DL0. The address signal AL0 may be enabled to a voltage level +V. The address signal AL0 does not need to be overdriven in this case because the transistor 306-00 passes a low voltage. By driving the cathode of the resistor element RB00 to -V and the anode of the resistor element RB00 to +V in this manner, the resistor element RB00 may be programmed to LRS. As long as the signal T0 is in a high impedance state, the resistor element RT00 may remain unchanged.

[0056] To program the lower left memory cell in the first row to store a logic "1" (as indicated by data signal "1" in data register DR1), driver 406B1 can be placed in a tri-state mode such that signal B1 is in a high impedance state Z, while driver 406T1 can drive signal T1 to a positive voltage level +V. During this time, driver 408-1 can be activated to provide a negative voltage level -V onto data line DL1 while address signal AL0 can be asserted to a voltage level +V. By driving the cathode of resistor element RT10 to -V and the anode of resistor element RT10 to +V in this manner, resistor element RT10 can be programmed to LRS. As long as signal B1 is in a high impedance state, resistor element RB10 can remain unchanged.

[0057] A single-bit programming operation may be performed in parallel for each memory cell 20 in a column, followed by programming on a column-by-column basis (e.g., by successively asserting address signals AL0, AL1, etc.). Configured in this manner, most of the associated memory circuitry (e.g., address transistor 306, addressing circuit 402, row driver circuit 404, data register, power driver 406, read / write circuits 408 and 410, transistors 420 and 422, etc.) is subjected to a voltage stress of at most +V. The voltage level +V may be equal to the positive power supply voltage Vcc. For example, the positive power supply voltage Vcc may have a voltage level +V equal to 1V.

[0058] As in Figure 5 As shown in the example of , a programming operation may require a total voltage of 2*(+V) across the resistor element 300. For example, an erase operation may require at least 2*(-V) across the anode and cathode terminals. On the other hand, a programming operation may require at least 2*(+V) across the anode and cathode terminals. Only the address transistor 306 may be exposed to a total voltage stress of 2*(+V) because during programming, it receives +V (e.g., 1V) at its gate and -V (e.g., -1V) from the data line (see Figure 5 ). In other words, the magnitude of the negative voltage level -V and the magnitude of the positive voltage level +V may be equal. This can be tolerable for up to a predetermined number of program cycles (e.g., at least 3000 configuration cycles) for reliability considerations. In yet other suitable embodiments, the programming voltage may be at least 1.5*Vcc, at least 1.8*Vcc, or greater than 2*Vcc.

[0059] By splitting the programming voltage between the positive rail (+V) and the negative rail (-V) on either side of the resistive memory element, all associated memory circuits can be implemented using core transistor devices (e.g., transistors having the thinnest gate oxide thickness allowed by current manufacturing design rules). Typically, input-output circuits (e.g., transistors having relatively thicker gate oxides than core transistor devices) are formed using input-output transistor devices. Figure 1 The I / O circuits 12) are made thicker so that the I / O transistors can withstand higher voltage stresses (i.e., thicker gate oxides exhibit greater junction breakdown voltage levels). Using primarily core transistors within the memory array 400 can help reduce the memory die area while improving or at least maintaining reliability.

[0060] Figure 6 4 is a circuit diagram showing a global erase operation that can be performed on the resistive memory array 400. Figure 6 As shown, all power drivers 406 may output a negative voltage level -V to the anode terminal of each resistor element. At the same time, the driver 408 in each row may drive all data lines to a positive voltage level +V by overdriving the address transistors 306 (e.g., all address transistors may be activated simultaneously) so that the cathode terminal of each resistor element receives +V. Operating in this manner, each individual resistor element in the memory array 400 may be erased to HRS in parallel (e.g., the entire resistor memory array may be reset simultaneously in a single write cycle). The address transistors 306 may have to be doubled in width to allow for simultaneous top and bottom resistor element resets.

[0061] Figure 7 4 is a circuit diagram showing a normal retention operation of the resistance memory array 400. Figure 7 As shown, the top power driver (e.g., driver 406T0, 406T1, etc.) can drive the top power voltage signal to a logic "1" (e.g., to Vcc or +V). At the same time, the bottom power driver (e.g., driver 406B0, 406B1, etc.) can drive the bottom power voltage signal to a logic "0" (e.g., to Vss or 0V). All address signals can be invalidated, so the state of the data line will not affect the output node of each memory cell 20.

[0062] exist Figure 7In the example of , the upper left memory cell 20 can be programmed in a high state (e.g., node Out00 can output a logic "1" to a first corresponding transmission gate - not shown). The upper right memory cell 20 can be programmed in a low state (e.g., node Out01 can output a logic "0" to a second corresponding transmission gate - not shown). The lower left memory cell 20 can be programmed in a high state (e.g., node Out10 can output a logic "1" to a third corresponding transmission gate - not shown). The lower right memory cell 20 can be programmed in a low state (e.g., node Out11 can output a logic "0" to a fourth corresponding transmission gate - not shown). The memory array 400 configured in this manner can exhibit non-volatile behavior, soft error upset immunity, and very low standby current.

[0063] Figure 8 4 is a circuit diagram showing a read operation on the resistive memory array 400. Figure 7 In a normal mode, the top power driver (e.g., driver 406T0, 406T1, etc.) can drive the top power voltage signal to a logic "1" (e.g., to Vcc or +V). At the same time, the bottom power driver (e.g., driver 406B0, 406B1, etc.) can drive the bottom power voltage signal to a logic "0" (e.g., to Vss or 0V).

[0064] exist Figure 8 In the example of , addressing circuit 402 may overdrive signal AL0 to turn on the address transistors in the first column. The upper left memory cell 200 currently stores a logic zero, while the lower left memory cell 200 currently stores a logic one. As a result, data line DL0 may be pulled low by node Out00, while data line DL1 may be pulled high by node Out10. Driver 410-0 may be activated to sense a low voltage on data line DL0, while driver 410-1 may be activated to sense a high voltage on data line DL1-1, and drivers 408-0 and 408-1 need to be tri-stated. During this time, signals Vbias and Verify may also be enabled (e.g., driven high) to act as weak keeper circuits for the data lines. Operating in this manner, resistor elements RB00 and RB10 are read out from the first and second rows, respectively, to determine whether the correct set and reset resistances have been achieved for the two memory cells 20.

[0065] Furthermore, this verify operation can be performed with or without a precharge operation. The precharge operation precharges the data lines before validating the address signals, which can help increase read speed and consistency.

[0066] Figures 9A-9C Shows how individual resistor elements can be margin tested to determine if the correct set resistance has been achieved. Fig.9A900 and 902. To perform top bit margining, the top power supply driver (e.g., driver 406T0, 406T1, etc.) may output 0V, while the bottom power supply driver (e.g., driver 406B0, 406B1, etc.) may be placed in a tri-state mode. Signals Vbias and Verify may be asserted during the margining operation. Signal AL0 may be asserted to access the first column.

[0067] Because the top bit RT00 in the first row is in HRS and because the signal B0 is in high impedance mode, transistors 420 and 422 can pull the data line DL0 and node Out00 up to 1V. However, the top bit RT10 in the second row is in LRS, which pulls the node Out10 and thus the data line DL1 down to 0V. The data line DL1 will be pulled down to logic "0" to resist the pull-up strength of transistors 420 and 422, as long as the set resistance of element RT10 is low enough. If the set resistance of element RT10 is low enough, the read circuit 410-1 will sense the low voltage at the data line DL1. Successive columns of memory cells 20 will be tested in this way.

[0068] Fig. 9B 1 and 2. It is shown how the bottom resistance element of each memory cell 20 is margined, as indicated by regions of interest 910 and 912. To perform bottom bit margining, the top power supply driver (e.g., driver 406T0, 406T1, etc.) can be placed in a tri-state mode, while the bottom power supply driver (e.g., driver 406B0, 406B1, etc.) can output 0 V. Signals Vbias and Verify can be asserted during the margining operation. Signal AL0 can be asserted to access the first column.

[0069] Because the bottom bit RB10 in the second row is in HRS and because the signal T1 is in high impedance mode, transistors 420 and 422 can pull the data line DL1 and node Out10 up to 1V. However, the bottom bit RB00 in the first row is in LRS, which pulls the node Out00 and thus the data line DL0 down to 0V. The data line DL0 will be pulled down to a logic "0" to resist the pull-up strength of transistors 420 and 422, as long as the set resistance of element RB00 is low enough. If the set resistance of element RB00 is low enough, the read circuit 410-0 will sense a low voltage at the data line DL0. Successive columns of memory cells 20 can be tested in this way.

[0070] Fig. 9C920 and 922. Because only the bottom bit RB00 is programmed in the upper left memory cell 20, the bottom bit margining configuration will be applied to the cell (e.g., by driving signal B0 to 0V and signal T0 to high impedance Z). If the set resistance of element RB00 is low enough, read circuit 410-0 will sense a low voltage at data line DL0. On the other hand, because only the top bit RT10 is programmed in the lower left memory cell 20, the top bit margining configuration will be applied to the cell (e.g., by driving signal T1 to 0V and signal B1 to high impedance Z). If the set resistance of element RT10 is low enough, read circuit 410-1 will sense a low voltage at data line DL1. In this way, consecutive columns of memory cells 20 can be tested.

[0071] The step of margining the resistance of the nonvolatile resistive element relative to the quantized level of current flowing through transistors 420 and 422 may help further increase reliability.

[0072] The embodiment of FIGS. 3-9 using complementary back-to-back resistor elements to implement the memory cell is merely illustrative. In another suitable arrangement, the memory cell 20 may be implemented using resistor elements connected in a "line-up" configuration (see, for example, FIG. Fig.10 ).like Fig.10 As shown, the memory cell 20 may include a first nonvolatile resistance element 1000-1 and a second nonvolatile resistance element 1000-2 coupled in series between power supply lines 302 and 304. The power supply voltage Vcc on line 302 may have a positive voltage level +V (e.g., 1V, 1.2V, 1.8V, 2V, etc.). The power supply voltage Vss on line 304 may have a ground voltage level (e.g., 0V).

[0073] In particular, resistor element 1000-1 may have a first (anode) terminal connected to line 302 and a second (cathode) terminal connected to output node Out. Resistor element 1000-2 may have a first (anode) terminal connected to node Out and a second (cathode) terminal connected to line 304. This arrangement in which the cathode of resistor element 1000-1 is connected to and faces the anode of resistor element 1000-2 is sometimes referred to as a "line-up" configuration. Compared to the line-up configuration, the back-to-back configuration can provide a smaller unit layout because the cathode terminal is shared between the top and bottom resistor elements. Typically, lines 302 and 304 may be provided with an adjustable power supply voltage or may be in a high impedance mode.

[0074] An address transistor such as transistor 306 may be coupled between data line DL and node Out. Transistor 306 may be activated using word line signal WL to load a desired data value into memory cell 20. Transistor 306 is therefore sometimes referred to as a programming transistor or an access transistor.

[0075] The output node Out of the memory cell 20 can be connected to the output node via the output path 38 (see also Figure 2 ) are coupled to corresponding pass transistors 36. Pass transistors 36 (sometimes referred to as pass gates) may be, as examples, part of a routing multiplexer for routing active user signals from a first logic region to a second logic region on an integrated circuit, part of a programmable switch in a lookup table, or part of other configurable logic circuits 18 on an integrated circuit.

[0076] Each resistor element 1000 (e.g., resistor elements 1000-1 and 1000-2) can be a programmable metallization cell (PMC) or a conductive bridge RAM (CBRAM) that can be configured in a low resistance state (LRS) or a high resistance state (HRS). Complementary memory cells configured in this manner can exhibit non-volatile behavior, soft error upset immunity, and zero standby current.

[0077] exist Fig.10 In the example, either resistance element 1000-1 can be set in LRS while element 1000-2 is in HRS, so that cell 20 is configured to store logic "1", or resistance element 1000-2 can be set in LRS while element 1000-1 is in HRS, so that cell 20 is configured to store logic "0".

[0078] generally, Fig.10 The type of in-line nonvolatile memory cells 20 shown may be arranged in an array, and each memory cell 20 may be configured using the above combination of Figure 4 -9 are programmed, erased and tested using similar principles and techniques as described above.

[0079] One advantage of an in-line memory array is that all cells 20 along a column can be set (programmed) and reset (erased) simultaneously. Fig.11 is a circuit diagram illustrating a combined program-erase operation on a resistive memory array 400. To configure the memory cell 20 to store a logic "0" (as shown in the upper left memory cell in the first row), the top and bottom tri-state power buffers 406T0 and 406B0 may output a negative voltage level -V, while the write driver 408-0 outputs a positive voltage level +V. At the same time, the addressing circuit 402 may overdrive the transistor 306-00, thereby driving the node Out00 to a positive voltage level +V. Operating in this manner, the resistive element RT00 will be erased, while the resistive element RB00 will be programmed in parallel.

[0080] To configure the memory cell 20 to store a logic "1" (as shown in the lower left memory cell in the second row), the top and bottom tri-state power buffers 406T1 and 406B1 may output a positive voltage level +V, while the write driver 408-1 outputs a negative voltage level -V. At the same time, the addressing circuit 402 may overdrive the transistor 306-10, thereby driving the node Out10 to a negative voltage level -V. Operating in this manner, the resistor element RT10 will be programmed, while the resistor element RT10 will be erased at the same time. Successive columns of memory cells 20 may be programmed and erased simultaneously in this manner. Thus, a two-step process involving a global reset followed by a separate programming operation may be simplified to a single operation.

[0081] Embodiments have been described so far with respect to integrated circuits. The methods and apparatus described herein may be incorporated into any suitable circuit. For example, they may be incorporated into various types of devices, such as programmable logic devices, application specific standard products (ASSPs), and application specific integrated circuits (ASICs). Examples of programmable logic devices include programmable array logic (PAL), programmable logic arrays (PLA), field programmable logic arrays (FPLA), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), to name just a few examples.

[0082] The programmable logic device described in one or more embodiments of the present invention can be part of a data processing system including one or more of the following components: a processor; a memory; an IO circuit; and a peripheral device. Data processing can be used in a variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other suitable application (where the advantages of using programmable or reprogrammable logic are desirable). Programmable logic devices can be used to perform a variety of different logic functions. For example, a programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. A programmable logic device can also be used as an arbitrator for arbitrating access to shared resources in a data processing system. In another example, a programmable logic device can be configured as an interface between a processor and one of the other components in the system.

[0083] Although the method of operations is described in a particular order, it should be understood that other operations may be performed between the operations described, the operations described may be adjusted so that they occur at slightly different times, or the operations described may be distributed in a system that allows the processing operations to occur at various intervals associated with the processing, as long as the processing of the overlapping operations is performed in the desired manner.

[0084] The foregoing merely illustrates the principles of the present invention, and various modifications may be made by those skilled in the art.The foregoing embodiments may be implemented individually or in any combination.

Claims

1. An integrated circuit, comprising: a first power supply terminal receiving a first adjustable power supply voltage; a second power supply terminal receiving a second adjustable power supply voltage; A first nonvolatile resistance element comprising: a first anode terminal coupled to the first power supply terminal; and a first cathode terminal; and A second nonvolatile resistance element comprising: a second anode terminal coupled to the second power supply terminal; and A second cathode terminal is coupled to the first cathode terminal of the first nonvolatile resistive element.

2. The integrated circuit of claim 1, wherein the first nonvolatile resistive element and the second nonvolatile resistive element form a conductive bridge random access memory cell.

3. The integrated circuit of claim 1 , further comprising: a first tri-state buffer driving the first power supply terminal; as well as A second tri-state buffer drives the second power supply terminal.

4. An integrated circuit as claimed in any one of claims 1 to 3, wherein the first adjustable supply voltage is negative.

5. An integrated circuit as claimed in any one of claims 1 to 3, wherein the second adjustable supply voltage is negative.

6. The integrated circuit of claim 1, further comprising: Data cable; an address transistor coupled between the data line and the first cathode terminal; Additional power cord; a first transistor coupled between the additional power line and the data line, the first transistor receiving a bias control voltage; as well as A second transistor is coupled in series with the first transistor between the additional power line and the data line, the second transistor receiving a verification control voltage.

7. The integrated circuit of claim 1, further comprising: A pass transistor has a gate terminal receiving a static control signal from the first cathode terminal.

8. The integrated circuit of any one of claims 1 to 3 or 6 to 7, further comprising: an input-output circuit having a first gate oxide thickness; as well as An address transistor is coupled to the first cathode terminal, the address transistor having a second gate oxide thickness less than the first gate oxide thickness.

9. A method of operating an integrated circuit, the method comprising: driving a data line to a negative voltage level, wherein the integrated circuit includes a first nonvolatile resistive element and a second nonvolatile resistive element coupled in series between a first power line and a second power line, and wherein the first nonvolatile resistive element and the second nonvolatile resistive element are coupled to the data line; and The first nonvolatile resistive element is programmed by driving the first power supply line to a positive voltage level while the first nonvolatile resistive element receives the negative voltage level.

10. The method of claim 9, wherein the magnitude of the negative voltage level and the magnitude of the positive voltage level are equal.

11. The method of claim 9, further comprising: The second nonvolatile resistance element is erased by driving the data line to the positive voltage level while driving the second power line to the negative voltage level.

12. The method of claim 9, wherein the first nonvolatile resistance element has a first cathode terminal, and wherein the second nonvolatile resistance element has a second cathode terminal facing the first cathode terminal.

13. The method of any of claims 9-12, further comprising configuring the second power line in a high impedance state.

14. The method according to any one of claims 9 to 12, further comprising: During a global erase operation, the first and second power lines are driven to the negative voltage level while the data line is driven to the positive voltage level.

15. The method of any one of claims 9 to 13, further comprising: It is determined whether the resistance of the second nonvolatile resistance element is sufficiently low.

16. An integrated circuit comprising: a first nonvolatile resistive element having a first anode terminal and a first cathode terminal; a second nonvolatile resistive element having a second anode terminal and a second cathode terminal, the second anode terminal coupled to the first cathode terminal; as well as A pass transistor has a gate terminal that receives a static control signal from the first cathode terminal.

17. The integrated circuit of claim 16, further comprising: a first power line coupled to the first anode terminal, the first power line receiving a first adjustable power supply voltage; as well as A second power line is coupled to the second cathode terminal, the second power line receiving a second adjustable power supply voltage.

18. The integrated circuit of claim 17, wherein the first adjustable supply voltage is negative.

19. The integrated circuit of claim 18, wherein the second adjustable supply voltage is also negative.

20. The integrated circuit of claim 19, further comprising: A data line is coupled to the first cathode terminal, the data line receiving a positive voltage level while the first adjustable power supply voltage and the second adjustable power supply voltage are simultaneously negative.

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