Non-volatile memory

Abstract

A non-volatile memory device includes: a memory cell array including a plurality of memory cell blocks; and an address decoder connected to the memory cell array through a plurality of word lines and configured to apply a read pass voltage to unselected word lines of a selected memory cell block among the plurality of memory cell blocks, and apply read pass voltages of different levels to different memory cell blocks among the plurality of memory cell blocks.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0075710 filed in the Korean Intellectual Property Office on June 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field The present application relates to memory, and in particular, to non-volatile memory. Background Art Memory devices can be used to store data and can be classified into volatile memory devices and nonvolatile memory devices. Nonvolatile memory devices can store data even when the power is off. Nonvolatile memory devices are mainly used as large-capacity storage for storing programs and data in various application devices such as computers and portable communication devices. With the recent increases in density and capacity of non-volatile memory devices, various problems have arisen. Summary of the invention In general, in some aspects, the disclosed subject matter encompasses nonvolatile memory devices, storage devices, and methods of operating storage devices for preventing read disturb degradation. In general, in some aspects, the disclosed subject matter encompasses nonvolatile memory devices, storage devices, and methods of operating storage devices for preventing uncorrectable error correction code (UECC) from occurring. According to some aspects of the present disclosure, a nonvolatile memory device includes: a memory cell array, which includes multiple memory cell blocks; and an address decoder, which is connected to the memory cell array through multiple word lines and is configured to apply a read pass voltage to unselected word lines of a selected memory cell block among the multiple memory cell blocks, and apply read pass voltages of different levels to different memory cell blocks among the multiple memory cell blocks. According to some aspects of the present disclosure, a storage device includes: a nonvolatile memory device including a memory cell block; and a storage controller configured to check a retention level of the memory cell block and control the nonvolatile memory device to apply a read pass voltage determined based on the retention level to the memory cell block. According to some aspects of the present disclosure, a method for operating a storage device includes: checking a retention level of a memory cell block included in a nonvolatile memory device; determining a level of a read pass voltage applied to the memory cell block based on the retention level; and sending a command for controlling the level of the read pass voltage to the determined level to the nonvolatile memory device. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects and features will become more apparent from the following description of embodiments with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a storage device and a memory system including the storage device according to some embodiments. Figure 2 is a flow chart of a method of operating a storage device according to some embodiments. Figure 3 is a block diagram of a non-volatile memory device according to some embodiments. Figure 4 is included in Figure 3 A perspective view of a memory cell block in a memory cell array of a non-volatile memory device. Figure 5 Cell strings included in a memory cell block and voltages applied to the cell strings according to some embodiments are illustrated. Figure 6 is a block diagram of a storage controller according to some embodiments. Figure 7 is a block diagram of a control circuit of a nonvolatile memory device according to some embodiments. Figure 8 is a block diagram of a voltage generator of a nonvolatile memory device according to some embodiments. Fig. 9 is a block diagram of a voltage generator, an address decoder, and a memory cell block of a nonvolatile memory device according to some embodiments. Fig.10 is a flowchart of a method of operating a storage device according to some embodiments. Fig.11 is a distribution diagram illustrating an off-cell count operation of a nonvolatile memory device according to some embodiments. Fig.12 is a table of offset values ​​of read pass voltages corresponding to turn-off cell count values ​​according to some embodiments. Fig.13 According to some embodiments, a method of operating a storage device is applied to Figure 5 Timing diagram of the voltage of the cell string. Fig.14 is a flow chart illustrating a method of operating a storage device according to some embodiments. Fig.15 is a flow chart illustrating a method of operating a storage device according to some embodiments. Fig.16is a flow chart illustrating a method of operating a storage device according to some embodiments. Fig.17 is a flow chart illustrating a method of operating a storage device according to some embodiments. Fig.18 is a perspective view showing a semiconductor device according to some embodiments. Fig.19 is a cross-sectional view illustrating an example of a semiconductor device according to some embodiments. Fig. 20 Cell strings included in a memory cell block and voltages applied to the cell strings according to some embodiments are illustrated. Fig.21 is a flow chart illustrating a method of operating a storage device according to some embodiments. Fig. 22 is a flow chart illustrating a method of operating a storage device according to some embodiments. Fig.23 is a flow chart illustrating a method of operating a storage device according to some embodiments. Fig.24 is a graph showing the number of error bits per 4 KB as a function of the number of page reads for each read pass voltage, according to some embodiments. Fig.25 is a graph showing threshold voltage distributions for each read pass voltage according to some embodiments. Fig.26 is a graph showing the number of executions of defense code for each read pass voltage according to some embodiments. Fig. 27 is a block diagram illustrating an example of a solid state drive (SSD) system applied to a nonvolatile memory device according to some embodiments. DETAILED DESCRIPTION Example embodiments will be described more fully below with reference to the accompanying drawings. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. In the following detailed description, only certain embodiments of the present invention are shown and described by way of illustration only. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Figure 1 is a block diagram of a storage device and a memory system including the storage device according to some embodiments. refer to Figure 1, the storage system 100 may include a host device 110 and a storage device 120. In some embodiments, the storage system 100 is a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, and a mobile system such as a healthcare device or an Internet of Things (IOT) device. In some embodiments, the storage system 100 is a computing device such as a personal computer, a laptop computer, a server, or a media player, or a system such as an automotive device (e.g., a navigation device). The host device 110 may store data in the storage device 120 or read data stored in the storage device 120. The host device 110 includes a host controller 111 and a host memory 112. The host controller 111 may be configured to control the storage device 120. The host controller 110 may have an operating system (OS) installed therein, and the overall internal operation of the host device 110 may be controlled by the operating system (OS). The operating system (OS) may be, for example, any one of the Windows series, the Unix series, and the Linux series. In some embodiments, the host controller 111 may communicate with the storage device 120 based on a predetermined interface. For example, these interfaces may be implemented with various interfaces, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Minicomputer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), various interfaces such as PCI express (PCI-E), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) Card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Compact Flash (CF) Card, etc. The host memory 112 may be a buffer memory, a working memory, or a system memory of the host device 110. For example, the host memory 112 may be configured to store various information required for the operation of the host device 110. The host memory 112 may be used as a buffer memory or a working memory for temporarily storing data to be sent to the storage device 120 or data received from the storage device 120. For example, the host memory 112 may be implemented with a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) or a non-volatile memory such as a phase change random access memory (PRAM) or a flash memory. The host memory 112 may support access to the storage device 120. According to some embodiments, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 120 may be integrated on the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded processor included in the application memory, or may be a non-volatile memory or a memory module provided outside the application memory. The storage device 120 may be a storage medium configured to store data or output stored data according to a request from the host device 110. As an example, the storage device 120 may include at least one of a solid-state drive (SSD), an embedded memory, and a removable external memory. When the storage device 120 is an SSD, the storage device 120 may be a device that complies with standards such as non-volatile memory express (NVMe), SATA, and SAS. When the storage device 120 is an embedded memory or an external memory, the storage device 120 may be a device that complies with standards such as universal flash storage (UFS), embedded multimedia card (eMMC), or secure digital (SD), and the standard is not limited thereto. The host device 110 and the storage device 120 may generate and send packets, respectively, according to the adopted standard protocol. The storage device 120 may include a storage controller 121 and a nonvolatile memory device 124. In addition, the storage device 120 may further include a temperature sensor 123. The memory controller 121 may store the data DATA in the nonvolatile memory device 124 or read the data DATA stored in the nonvolatile memory device 124. For example, the memory controller 121 may store the data DATA in the nonvolatile memory device 124 or read the data DATA stored in the nonvolatile memory device 124 by sending a control signal CTRL, a command CMD, and an address ADDR to the nonvolatile memory device 124. In some embodiments, the storage controller 121 may check the retention level of the non-volatile memory device 124. For example, the storage controller 121 may perform a shutdown cell count operation on the non-volatile memory device 124 and check the retention level based on the shutdown cell count value. The storage controller 121 may check the retention level based on the time elapsed since the programming operation was performed. The storage controller 121 may check the retention level based on the number of errors generated in the non-volatile memory device 124. When the storage device 120 is in an idle state, the shutdown cell count operation may be performed so as not to affect the performance of the host device 110. In some embodiments, the storage controller 121 may control the nonvolatile memory device 124 to change the level of the read pass voltage VREAD based on the retention level. When the retention level is high (i.e., when the retention degradation occurs relatively small), the storage controller 121 may control the nonvolatile memory device 124 to change the level of the read pass voltage VREAD to a relatively small level. When the retention level is low (i.e., when the retention degradation occurs relatively high), the storage controller 121 may control the nonvolatile memory device 124 to change the level of the read pass voltage VREAD. In some embodiments, the storage controller 121 includes a health monitor 122 that checks the retention level of the nonvolatile memory device 124. The storage controller 121 may generate a command CMD for controlling the level of the read pass voltage VREAD based on the checked retention level. In some embodiments, the storage controller 121 may check the retention level of the nonvolatile memory device 124 by referring to the temperature information TD provided from the temperature sensor 123. For example, when a time period determined based on the temperature information TD has passed, the storage controller 121 may check the retention level of the nonvolatile memory device 124. The temperature sensor 123 may measure the internal temperature of the nonvolatile memory device 124 and generate a driving temperature TD converted into numerical information. For example, the temperature sensor 123 may be a thermoelectromotive force (or thermocouple) sensor using an electromotive force that varies with temperature, a thermal conductivity sensor that detects a resistance magnitude that varies with temperature, and the like. However, it will be well understood that the temperature measurement method of the temperature sensor 123 is not limited thereto and may be applied in various ways. The nonvolatile memory device 124 may perform an erase, write, or read operation under the control of the memory controller 121. To this end, the nonvolatile memory device 124 receives a command CMD and an address ADDR from the memory controller 121 through an input line and an output line, and transmits and receives data DATA for a program operation or a read operation with the memory controller 121. In addition, the nonvolatile memory device 124 may receive a control signal CTRL through a control line, and the nonvolatile memory device 124 may receive power PWR from the memory controller 121. The non-volatile memory device 124 includes a memory cell array 125 and a voltage generator 126. The memory cell array 125 may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. The flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. Hereinafter, some embodiments of the present disclosure will be described by taking the case where the plurality of memory cells are NAND flash memory cells as an example. However, the technical concept of the present disclosure is not limited thereto, and the plurality of memory cells may be various types of non-volatile memory cells. In some embodiments, the plurality of memory cells may be resistive memory cells, such as resistive RAM (RRAM), PRAM, or magnetic RAM (MRAM). The memory cell array 125 may include a plurality of memory cell blocks. Each of the memory cell blocks may include a plurality of cell strings sharing a bit line. Each of the plurality of cell strings may include a ground selection transistor, a plurality of memory cells connected to a plurality of word lines, and a string selection transistor. The memory cell array 125 may be a two-dimensional (2D) memory array. Alternatively, the memory cell array 125 may be a three-dimensional (3D) memory array. The voltage generator 126 may generate a voltage applied to the memory cell array 125. For example, the voltage generator 126 may generate a read voltage VRD supplied to a selected word line and a read pass voltage VREAD supplied to unselected word lines in a read operation. In some embodiments, the voltage generator 126 may change the magnitude of the read pass voltage VREAD based on the retention level of the memory cell array 125. For example, the voltage generator 126 may receive a command CMD from the memory controller 121 to change the voltage level of the read pass voltage VREAD to a voltage level determined based on the retention level, and may change the voltage level of the read pass voltage VREAD. In some embodiments, the voltage generator 126 may generate a read pass voltage VREAD of a different level for each memory cell block. The voltage generator 126 may generate a read pass voltage VREAD of a different level for each word line. According to some embodiments, since a read pass voltage (VREAD) supplied to a memory cell block or word line having a relatively low retention level is greater than a read pass voltage (VREAD) supplied to a memory cell block or word line having a relatively high retention level, read disturbance degradation due to a read pass voltage (VREAD) of a memory cell block or memory cell connected to a word line having a relatively high retention level is prevented, and a read error of a memory cell block or memory cell connected to a word line having a relatively low retention level can be prevented. Figure 2is a flow chart of a method of operating a storage device according to some embodiments.

[0057] Reference together Figure 1 and Figure 2 , the storage controller 121 checks the retention level of the nonvolatile memory device 124 (S210). For example, the storage controller 121 may perform a shutoff unit count operation on the nonvolatile memory device 124, and check the retention level based on the shutoff unit count value. The storage controller 121 may check the retention level based on the time elapsed since the programming operation was performed. For example, the storage controller 121 may check the retention level in response to the time elapsed after the programming operation was performed. The storage controller 121 may check the retention level based on the number of read errors generated in the nonvolatile memory device 124. For example, the storage controller 121 may check the retention level corresponding to the range of the number of read errors generated in the nonvolatile memory device 124. The storage controller 121 may determine that the nonvolatile memory device 124 with a relatively large number of read errors has a relatively low retention level. The storage controller 121 may determine that the nonvolatile memory device 124 in which UECC has occurred has a relatively low retention level. The memory controller 121 may check the retention level based on the number of UECCs generated in the nonvolatile memory device 124. For example, the memory controller 121 may check the retention level corresponding to a range including the number of UECCs generated in the nonvolatile memory device 124. The memory controller 121 may check a retention level of each of a plurality of memory cell blocks included in the nonvolatile memory device 124. The memory controller 121 may check a retention level of memory cells of each word line included in each of the plurality of memory cell blocks. In some embodiments, the memory controller 121 may check the retention level of the nonvolatile memory device 124 by referring to the temperature information TD provided from the temperature sensor 123. For example, the memory controller 121 may check the retention level of the nonvolatile memory device 124 when a period determined based on the temperature information TD elapses. The memory controller 121 determines the read pass voltage VREAD based on the retention level (S220). When the retention level of the nonvolatile memory device 124 is low, the memory controller 121 may determine that the read pass voltage VREAD has a higher voltage level. For example, the memory controller 121 may determine that the level of the read pass voltage VREAD applied to the unselected word lines during the read operation of the first memory cell block is higher than the level of the read pass voltage VREAD applied to the unselected word lines during the read operation of the first memory cell block when the retention level of the first memory cell block included in the nonvolatile memory device 124 is the first level when the retention level of the first memory cell block is the second level. When the retention level of the first memory cell block included in the nonvolatile memory device 124 is the first level and the retention level of the second memory cell block is the second level, the memory controller 121 may determine that the level of the read pass voltage VREAD applied to the unselected word lines during the read operation of the first memory cell block is higher than the level of the second read pass voltage VREAD applied to the unselected word lines during the read operation of the second memory cell block. In some embodiments, the memory controller 121 may generate a command CMD that controls the voltage generator 126 to generate the read pass voltage VREAD at the determined level of the read pass voltage VREAD. Figure 3 is a block diagram of a non-volatile memory device according to some embodiments. refer to Figure 3 , the nonvolatile memory device 300 may include a memory cell array 310 , an address decoder 320 , a page buffer circuit 330 , a data input / output circuit 340 , a control circuit 350 , and a voltage generator 360 . The memory cell array 310 may include a plurality of memory cell blocks 311a, 311b, ..., 311h. Each of the memory cell blocks 311a, 311b, ..., 311h may include a plurality of nonvolatile memory cells. Each of the memory cell blocks 311a, 311b, ..., 311h may be connected to the address decoder 320 through a plurality of string selection lines (SSL), a plurality of word lines (WL), and a plurality of ground selection lines (GSL). In addition, the memory cell array 310 may be connected to the page buffer circuit 330 through a plurality of bit lines BL. The memory cell blocks 311a, 311b, ..., 311h may be connected to a plurality of bit lines BL in common. The plurality of nonvolatile memory cells included in the memory cell blocks 311a, 311b, ..., 311h may have the same structure. In some embodiments, the memory cell array 310 may be a 3D memory cell array formed in a three-dimensional structure (or a vertical structure) on a substrate. In this case, the memory cell array 310 may include a vertical cell string including a plurality of memory cells stacked on each other. The address decoder 320 may be connected to the memory cell array 310 through a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. During a program operation or a read operation, the address decoder 320 may determine one of the plurality of word lines WL as a selected word line and the other word lines as unselected word lines based on a row address R_ADDR provided from the control circuit 350. The address decoder 320 determines one of the plurality of string selection lines SSL as a selected string selection line and the remaining string selection lines as non-selected strings based on a switching control signal SCS provided from the control circuit 350. The address decoder 320 may adjust the floating timing of the ground selection line GSL according to the switching control signal SCS during an erase operation. For example, during programming, the address decoder 320 may apply a program voltage to a selected word line of a selected memory cell block based on the row address R_ADDR, and apply a pass voltage to unselected word lines of the selected memory cell block. During reading, the address decoder 320 may apply a read voltage to a selected word line of a selected memory cell block, and may apply a read pass voltage to unselected word lines of the selected memory cell block based on the row address R_ADDR. During erasing, the address decoder 320 may apply an erase voltage (e.g., a ground voltage or a low voltage having a level similar to the ground voltage) to the word line of the selected memory cell block. In some embodiments, the address decoder 320 may apply different levels of read pass voltages transmitted from the voltage generator 360 to different memory cell blocks. The address decoder 320 may apply a read pass voltage of a first level to an unselected word line in one memory cell block at a first time point, and apply a read pass voltage different from the first level to an unselected word line in the memory cell block at a second time point. In this case, the second time point is a time point after the first time point, and the second level may be greater than the first level. The address decoder 320 may apply read pass voltages of different levels transmitted from the voltage generator 360 to different unselected word lines in the same memory cell block, respectively. The page buffer circuit 330 may be connected to the memory cell array 310 through a plurality of bit lines BL. The page buffer circuit 330 may include a plurality of page buffers. The page buffer circuit 330 may temporarily store data to be programmed in a selected page during a program operation, and may temporarily store data read from a selected page during a read operation. The data input / output circuit 340 may be connected to the page buffer circuit 330 through a plurality of data lines DL. During a programming operation, the data input / output circuit 340 may receive data from the memory controller ( Figure 1The data input / output circuit 340 receives the program data DATA and provides the program data DATA to the page buffer circuit 330 based on the column address C_ADDR provided from the control circuit 350. During a read operation, the data input / output circuit 340 may provide the read data DATA stored in the page buffer circuit 330 to the memory controller 121 based on the column address C_ADDR provided from the control circuit 350. The control circuit 350 may receive a command signal CMD and an address signal ADDR from the memory controller 121, and control an erase cycle, a program cycle, and a read operation of the nonvolatile memory device 300 based on the command signal CMD and the address signal ADDR. Here, the program cycle may include a program operation and a program verification operation, and the erase cycle may include an erase operation and an erase verification operation. Here, the read operation may include a normal read operation and a data recovery read operation. For example, the control circuit 350 may generate a control signal for controlling the voltage generator 360, a page buffer control signal (PCTL) for controlling the page buffer circuit 330, and a control signal (VCS) for controlling the voltage detector 370, and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 350 may provide the row address R_ADDR to the address decoder 320 and the column address C_ADDR to the data input / output circuit 340. In addition, the control circuit 350 may provide a switching control signal SCS to the address decoder 320 based on the command signal CMD. The control circuit 350 may generate a control signal CTL and / or a switching control signal SCS based on the command signal CMD. In some embodiments, the control circuit 350 may generate a control signal CTL that changes the level of the read pass voltage generated by the voltage generator 360 based on the command signal CMD. The control circuit 350 may generate a switching control signal (SCS) so that the read pass voltage with a changed level is applied to a corresponding memory cell block among the memory cell blocks 311a, 311b, ..., 311h through the address decoder 320. For example, in order to apply a read pass voltage of a first level to a first memory cell block among the memory cell blocks 311a, 311b, ..., 311h, and apply a read pass voltage of a second level different from the first level to a second memory cell block among the memory cell blocks 311a, 311b, ..., 311h, the control circuit 350 may generate a control signal CTL and / or a switching control signal SCS based on the command signal CMD so that the voltage generator 360 generates read pass voltages of the first level and the second level. And the address decoder 320 applies the read pass voltage of the first level to the first memory cell block, and applies the read pass voltage of the second level to the second memory cell block. The voltage generator 360 may generate a word line voltage VWL, a string selection line voltage, and a ground selection line voltage required for the operation of the nonvolatile memory device 300 using a power source PWR based on a control signal CTL provided from the control circuit 350 . The word line voltage VWL generated by the voltage generator 360 may be applied to a plurality of word lines WL through the address decoder 320. The string selection line voltage generated by the voltage generator 360 may be applied to a plurality of string selection lines SSL through the address decoder 320. The ground selection line voltage generated by the voltage generator 360 may be applied to a plurality of ground selection lines GSL through the address decoder 320. Figure 4 is included in Figure 3 A perspective view of a memory cell block in a memory cell array of a nonvolatile memory device. refer to Figure 4 , the cell array of the nonvolatile memory device may include a plurality of memory cell blocks. The memory cell block BLKi may include cell strings CS1, CS2, and CS3 arranged two-dimensionally along a second direction D2 and a third direction D3 that intersect each other and extend along a first direction D1. The cell strings CS1, CS2, and CS3 may be connected to bit lines BL1, BL2, and BL3. The two-dimensionally arranged cell strings CS1, CS2, and CS3 may be commonly connected to a common source line CSL. Each of the cell strings CS1, CS2, and CS3 may include a plurality of memory cells MC1, ..., MC8 connected in series with each other in a first direction D1, a ground selection transistor GST connected in series between a common source line CSL and the plurality of memory cells MC1, ..., MC8, and a string selection transistor SST connected between the plurality of memory cells MC1, ..., MC8 and corresponding bit lines among the bit lines BL1, BL2, and BL3. Figure 3 , each of the cell strings CS1, CS2, and CS3 is illustrated as including eight memory cells MC1, . . . , MC8, but is not limited thereto. Memory cells MC1, ..., and MC8 may be controlled by a plurality of word lines WL1, ..., and WL8, respectively. Gate electrodes of memory cells MC1, ..., and MC8 located at the same level as a common source line CSL may be commonly connected to one of the word lines WL1, ..., and WL8. In addition, each of memory cells MC1, ..., MC8 includes a data storage element. Ground selection lines GSL1, GSL2, and GSL3 and string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Figure 5Cell strings included in a memory cell block and voltages applied to the cell strings according to some embodiments are illustrated. refer to Figure 5 , during a read operation and / or a program verification operation, the nonvolatile memory device may read data stored in memory cells connected to a selected word line WL5 by applying a read voltage VRD to a selected word line WL5 connected to selected cell strings CS1, CS2, and CS3. Predetermined turn-on voltages VSON and VGON may be applied to the first string selection line SSL1 as a selection string selection line and the first ground selection line GSL1 as a selection ground selection line, respectively. A read voltage VRD may be applied to a selected word line, namely, the fifth word line WL5. A read pass voltage VREAD may be applied to the first word line WL1 to the fourth word line WL4 and the sixth word line WL6 to the eighth word line WL8, which are unselected word lines. Figure 6 is a block diagram of a storage controller according to some embodiments. refer to Figure 6 The storage controller 600 may include a central processing unit (CPU) 610 , a working memory 620 , an error correction code (ECC) engine 630 , a host interface circuit, a buffer memory 650 , and a flash memory interface circuit 660 . The CPU 610 may control the overall operation of the storage controller 600. The CPU 610 may respond to a request from a host device ( Figure 1 The processor 610 may control the operation of the storage controller 600 by using commands received from the processor 610 (110). For example, the processor 610 may control each component by utilizing firmware for driving a storage device. The working memory 620 may operate under the control of the CPU 610 and may be used as a working memory, a buffer memory, a cache memory, etc. For example, the working memory 620 may be implemented with a volatile memory such as a DRAM or an SRAM or a nonvolatile memory such as a PRAM or a flash memory. A flash translation layer (FTL) 622 may be loaded into the working memory 620. When the CPU 610 executes the FTL 622, the nonvolatile memory device ( Figure 1124). FTL 622 may perform various functions, such as address mapping, wear leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from a host into a physical address for actually storing data in the nonvolatile memory device 124. Wear leveling is a technique for preventing excessive degradation of a specific block by uniformly using blocks in the nonvolatile memory device 124, for example, which may be implemented by a firmware technique that balances the erase counts of physical blocks. Garbage collection is a technique for ensuring available capacity in the nonvolatile memory device 124 by copying valid data of a block to a new block and then erasing the old block. In some embodiments, FTL 622 may be implemented in software or hardware. When FTL 622 is implemented in software, program code or information related to FTL 622 may be stored in buffer memory 650 and executed by CPU 610. When FTL 622 is implemented in hardware, a hardware accelerator configured to perform operations of FTL 622 may be provided separately from CPU 610. The health monitor 624 may be implemented in firmware or software and may be loaded into the working memory 620. Alternatively, the health monitor 624 may be implemented in hardware. The health monitor 624 may check the retention level of the non-volatile memory device 124. In some embodiments, the health monitor 624 may initiate an operation to check the retention level of the non-volatile memory device 124 under the control of the host device 110. The health monitor 624 may monitor the retention level of the non-volatile memory device 124 by referring to the temperature sensor ( Figure 1 123) to start checking the retention level of the non-volatile memory device 124. In some embodiments, the health monitor 624 may generate a command CMD to cause the nonvolatile memory device 124 to perform a shutdown cell count operation, and may check a retention level based on a cell count value output from the nonvolatile memory device 124. The health monitor 624 may check a retention level based on a time elapsed after a program command is sent to the nonvolatile memory device 124. The health monitor 624 may check a retention level based on the number of errors detected by the ECC engine 630, whether a UECC has occurred, and the number of UECCs. The CPU 610 may generate a command for controlling a level of a read pass voltage of the nonvolatile memory device 124 based on the retention level of the nonvolatile memory device 124 checked by the health monitor 624. The ECC engine 630 may perform error detection and correction functions on data read from the nonvolatile memory device 124. The ECC engine 630 may generate an error correction code for correcting a fail bit or an error bit of data sent to / received from the nonvolatile memory device 124. More specifically, the ECC engine 630 may generate parity bits (or error correction codes) for write data to be written in the nonvolatile memory device 124, and the parity bits generated by the ECC engine 630 may be stored in the nonvolatile memory device 124 together with the write data. When reading data from the nonvolatile memory device 124, the ECC engine 630 may correct errors in the read data using the read data and the parity bits read from the nonvolatile memory device 124, and output the read data in which the errors have been corrected. The ECC engine 630 may detect and correct errors in the data to determine whether a UECC has occurred. The UECC may indicate a state including errors that were not corrected by the ECC engine 630. The ECC engine 630 may detect the UECC during error correction decoding of data received from the nonvolatile memory device 124. The host interface circuit 640 may send and receive packets to and from the host device 110 . Packets sent from host device 110 to host interface circuit 640 may include commands or data to be written to non-volatile memory device 124, and packets sent from host interface circuit 640 to host device 110 may include responses to commands or data read from non-volatile memory device 124. In some embodiments, host interface circuit 640 may be configured to communicate with host device 110 according to a predetermined interface protocol. The predetermined interface protocol may include at least one of various interface protocols, such as an Advanced Technology Attachment (ATA) interface, a Serial ATA (SATA) interface, an e-SATA (external SATA) interface, a SCSI (Small Computer Small Interface) interface, a Serial Attached SCSI (SAS) interface, a Peripheral Component Interconnect (PCI) interface, a PCI Express (PCIe) interface, an NVM Express (NVMe) interface, IEEE 1394, a Universal Serial Bus (USB) interface, a Secure Digital (SD) card, a Multimedia Card (MMC) interface, an Embedded Multimedia Card (eMMC) interface, a Universal Flash Storage (UFS) interface, an Embedded Universal Flash Storage (eUFS) interface, a Compact Flash (CF) card interface, or a network interface. The host interface circuit 640 may receive a signal from the host device 110 based on the predetermined interface protocol and operate based on the received signal. Alternatively, the host interface circuit 640 may send a signal to the host device 110 based on the predetermined interface protocol. The buffer memory 650 may be a write buffer or a read buffer configured to temporarily store data input to the storage controller 600. Alternatively, the buffer memory 650 may be configured to store various information required for the operation of the storage controller 600. For example, the buffer memory 650 may store a mapping table managed by the FTL 622. The buffer memory 650 may store software, firmware, or information related to the FTL 622. In some embodiments, the buffer memory 650 may be an SRAM, but the scope of the present disclosure is not limited thereto, and the buffer memory 650 may be implemented with various types of memory devices such as DRAM, MRAM, and PRAM. For the sake of simplicity of drawing and convenience of description, the buffer memory 650 is shown in FIG. Figure 6 Buffer memory 650 is illustrated as being included in memory controller 600, but the scope of the present disclosure is not limited thereto. Buffer memory 650 may be located outside memory controller 600, and memory controller 600 may communicate with the buffer memory through a separate communication channel or interface. The flash interface circuit 660 may send data to be written into the nonvolatile memory device 124 to the nonvolatile memory device 124, or may receive data read from the nonvolatile memory device 124. The flash interface circuit 660 may be configured to communicate with the nonvolatile memory device 124 according to a predetermined interface protocol. In some embodiments, the predetermined interface protocol may include at least one of various interface rules, such as a toggle interface and an ONFI interface. In some embodiments, the flash interface circuit 660 may communicate with the nonvolatile memory device 124 based on a toggle interface. In this case, the flash interface circuit 660 may communicate with the nonvolatile memory device 124 through a plurality of channels. In some embodiments, each of the plurality of channels may include a plurality of signal lines configured to send various control signals (e.g., / CE, CLE, ALE, / WE, / RE, R / B, etc.), a data signal (DQ), and a data strobe signal (DQS). Figure 7 is a block diagram of a control circuit of a nonvolatile memory device according to some embodiments. refer to Figure 7 , the control circuit 700 may include a command decoder 710 , an address buffer 720 , and a control signal generator 730 . The command decoder 710 may decode the command signal CMD and provide the decoded command D_CMD to the control signal generator 730 . The address buffer 720 can receive the address signal ADDR and provide the row address R_ADDR in the address signal ADDR to the address decoder ( Figure 3320 in the data input / output circuit ( Figure 3 340 in ). The control signal generator 730 may receive the decoded command D_CMD, generate a control signal CTL based on the operation indicated by the decoded command D_CMD, and provide the control signal CTL to the voltage generator ( Figure 3 360), generating a page buffer control signal PCTL, and providing the page buffer control signal PCTL to the page buffer circuit ( Figure 3 The control signal generator 730 may generate a switching control signal SCS based on the decoded command D_CMD and provide the switching control signal SCS to the address decoder 320. Figure 8 is a block diagram of a voltage generator of a nonvolatile memory device according to some embodiments. refer to Figure 8 , the voltage generator 800 includes a high voltage generator 810 and a low voltage generator 820 . The high voltage generator 810 may generate a high voltage VPP, a program voltage VPGM, a program pass voltage VPPASS, a verification pass voltage VVPASS, a read pass voltage VREAD, and an erase voltage VRES according to an operation indicated by a command CMD in response to a first control signal CTL1 . A high voltage VPP can be applied to the address decoder ( Figure 3 320 in). A program voltage VPGM may be applied to a selected word line, a program pass voltage VPPASS, a program verification pass voltage VVPASS, and a read pass voltage VRPASS may be applied to unselected word lines, and an erase voltage VRES may be applied to a well of a memory cell block. The first control signal CTL1 may include a plurality of bits and indicate an operation indicated by a decoded command D_CMD. The low voltage generator 820 generates a program verification voltage VPV, a read voltage VRD, an erase verification voltage VEV, a string selection voltage Va, a ground selection voltage Vb, and a reference voltage VREF according to an operation indicated by a command CMD in response to a second control signal CTL2 . The program verification voltage VPV, the read voltage VRD, and the erase verification voltage VEV may be applied to the selected word line according to the operation. The string selection on voltage VSON and the string selection off voltage VSOFF may be applied to the string selection transistors of the selected cell string and the unselected cell string, respectively. The ground selection on voltage VGON and the ground selection off voltage VGOFF may be applied to the ground selection transistors of the cell string. The second control signal CTL2 may include a plurality of bits and indicate the operation indicated by the decoded command D_CMD. In the above description and the following description, "on" voltage and "off" voltage are used to distinguish voltage levels. Despite their names, these terms do not necessarily refer to the voltage levels that actually turn on or off a transistor. Fig. 9 is a block diagram of a voltage generator, an address decoder, and a memory cell block of a nonvolatile memory device according to some embodiments. refer to Fig. 9 , the voltage generator 900 may generate a voltage provided to the address decoder 910 and the memory cell array 912 in response to the control signal CTL. The voltage generator 900 may provide the generated voltage to the connection line CL. In some embodiments, the voltage generator 900 may apply different levels of read pass voltages to a connection line over time. For example, if the retention level of the memory cell block at a first time point is higher than the retention level of the memory cell block at a second time point after the first time point, the voltage generator 900 may apply a first level of read pass voltage to the connection line at the first time point, and apply a second level of read pass voltage higher than the first level to the connection line at the second time point. In some embodiments, the voltage generator 900 may apply different levels of read pass voltages to a plurality of connection lines at the same time. In this case, the driver circuits 920, ..., 922 may receive different levels of read pass voltages and provide different levels of pass voltages to the corresponding memory cell blocks 940, ..., 942. The address decoder 910 may include a plurality of driver circuits 920, ..., 922 and a plurality of pass switch circuits 930, ..., 932. The plurality of driver circuits 920, ..., 922 and the plurality of pass switch circuits 930, ..., 932 may be connected to corresponding memory cell blocks among a plurality of memory cell blocks 940, ..., 942. Hereinafter, the driver circuit 920 and the pass switch circuit 930 connected to the memory cell block 940 will be described as an example. The driver circuit 920 may be connected to a connection line CL to which a voltage generated by the voltage generator 900 is provided. The driver circuit 920 provides the voltage provided from the voltage generator 900 to the memory cell block 940 in response to a switch control signal SCS. The driver circuit 920 may provide a high voltage VPP provided from the voltage generator 900 to the transmission switch circuit 930. The driver circuit 920 may provide a high voltage to a block word line BLKWL connected to gates of a plurality of transmission transistors GPT, PT1, . . . , PTn, and SSPT included in the transmission switch circuit 930. The driver circuit 920 may control the timing of applying the word line voltage VWL, the string selection line voltage Va, and the ground selection line voltage Vb. The driver circuit 920 may provide the word line voltage VWL provided from the voltage generator 900 to the word lines WL1, ..., WLn through the driving lines S1, ..., Sn and the pass transistors PT1, ..., PTn. The driver circuit 920 may provide the string selection line voltage Va to the string selection line SSL through the pass transistor SSPT. The driver circuit 920 may provide the ground selection line voltage Vb to the ground selection line GSL through the pass transistor GPT. In some embodiments, the driver circuit 920 may apply read pass voltages of different levels to a plurality of word lines of the same memory cell block 930 based on the switching control signal SCS. For example, during an operation of reading one page of the memory cell block 930, the driver circuit 920 may apply a first-level read pass voltage to a first word line WL1 of the memory cell block 930, and apply a second-level read pass voltage different from the first level to an n-th word line WLn of the memory cell block 930. The pass transistors GPT, PT1, ..., PTn and SSPT are configured to electrically connect the ground selection line GPT, the word line WL1, ..., WL8 and the string selection line SSL to the corresponding driving line in response to the high voltage signal VPP applied through the block word line BLKWL. The pass transistors GPT, PT1, ..., PTn and SSPT may include high voltage transistors capable of withstanding high voltage. Fig.10 is a flow chart of a method of operating a storage device according to some embodiments. refer to Fig.10 , Storage Controller ( Figure 1 121) to the non-volatile memory device ( Figure 1 124) applies power PWR (S1000). The nonvolatile memory device 124 performs a cell counting operation on a memory cell block (S1010). Specifically, the storage controller 121 may provide a command CMD indicating a cell counting operation to the nonvolatile memory device 124. In some embodiments, the nonvolatile memory device 124 may count memory cells (turn-off cells) that block a current path to a channel in response to a read voltage (or a verification voltage) at a specific point in time in response to the provided command CMD. In some embodiments, when the memory device 120 is in an idle state, the nonvolatile memory device 124 may perform a cell counting operation. In the following, the turn-off cell counting operation will be described assuming that the turn-off cell counting operation means the turn-off cell counting operation. Reference will be made together to Fig.11 Describe the unit counting operation. Fig.11is a distribution diagram illustrating a turn-off cell count operation of a nonvolatile memory device according to some embodiments. exist Fig.11 In the distribution diagram of FIG. 1 , the horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of the memory cells. Fig.11 2 shows the change in threshold voltage when 3 bits are added to each memory cell. Figure 1 Each of the memory cells 124) in the memory cell array is a triple level cell (TLC) configured to store 3 bits. However, the scope of the present invention is not limited thereto, and each of the memory cells may be implemented in various forms, such as an SLC (single-level cell) storing 1 bit per cell or an MLC (multi-level cell) storing n bits (n is a natural number greater than 1) per cell (e.g., TLC (triple-level cell), QLC (quadruple-level cell), PLC (quintuple-level cell)). The first graph S0 represents an initial programming threshold voltage distribution (eg, initial threshold voltage distribution) of memory cells of the memory cell block at a first point in time, and the second graph S1 shows a threshold voltage distribution of memory cells of the memory cell block at a second point in time. The width between the threshold voltage distributions at the first time point may decrease over time, similar to the threshold voltage distribution at the second time point. As time passes after the memory cell is programmed, the threshold voltage distribution of the memory cell may change due to the physical properties of the memory cell or external factors. In particular, as time passes after the memory cell is programmed, charge loss may occur, wherein electrons captured in the floating gate or tunnel oxide are released, and thus the threshold voltage distribution may change. In addition, although operations such as programming and erasing are repeated on the memory cell, the tunnel oxide degrades and the charge loss may further increase. Charge loss may reduce the threshold voltage. Therefore, compared with the initial programming threshold voltage distribution S0, the threshold voltage distribution S1 may be shifted to the left. That is, as time passes, the captured charge may leak, and the threshold voltage of the memory cell may change. Therefore, even if the cell count operation is performed with the same voltage, the cell count may be different. The nonvolatile memory device 124 may perform a cell count operation on the first memory cell block at a first point in time. For example, the nonvolatile memory device 124 may perform a turn-off cell count operation with respect to the seventh read voltage VRD7. The turn-off cell count (i.e., the first cell count CC1) of the first memory cell block at the seventh read voltage RD7 at the first point in time may be a first value. The nonvolatile memory device 124 may transmit the first cell count CC1 having the first value to the memory controller 121. The memory controller 121 may store the received first cell count CC1 in association with the first memory block. The nonvolatile memory device 124 may perform a cell count operation on the first memory cell block at the second time point. For example, the nonvolatile memory device 124 may perform a turn-off cell count operation with respect to the seventh read voltage VRD7. The turn-off cell count (i.e., the second cell count CC2) of the seventh read voltage RD7 of the first memory cell block at the second time point may be a second value. The nonvolatile memory device 124 may send the second cell count CC2 having the second value to the memory controller 121. The memory controller 121 may store the received second cell count CC2 in association with the first memory block. In the above, it has been described that the nonvolatile memory device 124 performs an off-cell counting operation, but the nonvolatile memory device 124 can count the memory cells (on-cells) that form a current path in the channel in response to a read voltage (or a verification voltage) at a specific time point in response to the provided command CMD. Back to Fig.10 , the memory controller 121 determines a read pass voltage of the memory cell block based on the cell count value (S1020). When the cell count value is large, the memory controller 121 may determine that the read pass voltage is at a lower level. For example, the memory controller 121 may determine the read pass voltage based on the cell count value so that the read pass voltage when the cell count value is a first value is less than the read pass voltage when the cell count value is a second value less than the first value. In some embodiments, the memory controller 121 may determine a read pass voltage of a memory cell block, receive a read request for the memory cell block whose read pass voltage is determined in step S1060 , and perform a read operation according to step S1070 . Fig.12 is a table of offset values ​​of read pass voltages corresponding to turn-off cell count values. refer to Fig.12, when the off-cell count value is 0, the read pass voltage VREAD may have a preset voltage level. When the off-cell count value is 6000 or more, the memory controller 121 may determine the read pass voltage VREAD as a voltage 600 mV lower than the preset voltage level. When the off-cell count value is greater, the memory controller 121 may determine the read pass voltage VREAD so that the read pass voltage has a low voltage level. Back to Fig.10 , the memory controller 121 checks the temperature information TD provided from the temperature sensor 123 (S1030). The storage controller 121 sets a set time period according to the temperature information (S1040). For example, the storage controller 121 can set a time period as shown in Table 1 below according to the temperature value according to the temperature information TD. (Table 1) Temperature value Duration T≤0 7 days 0<T≤20 3 days 20<T≤40 1 day 40<T≤60 12 hours 60<T≤80 4 hours 80<T 1 hour The storage controller 121 determines whether the time elapsed from the set time period or the time elapsed from checking the temperature information exceeds the set time period (S1050). For example, the storage controller 121 may determine whether the time elapsed from checking the temperature information TD having a temperature value of 30 exceeds 12 hours. If the time elapsed from the set time period or the time elapsed from checking the temperature information exceeds the set time period, the storage controller 121 performs step S1010 . If the time elapsed from the set time period or the time elapsed from checking the temperature information is less than or equal to the set time period, the memory controller 121 determines whether a read request is received from the host device 110 (S1060). When receiving the read request, the memory controller 121 controls the nonvolatile memory device 124 to perform a read operation (S1070). If there is no read request, the memory controller 121 may check the time elapsed from the set time period or the time elapsed from checking the temperature information. Although steps S1010, ..., and S1050 have been described above as being performed by the storage controller 121, steps S1010, ..., and S1050 may be performed by a control circuit ( Figure 3 350) in the execution. Fig.13 According to some embodiments, a method of operating a storage device is applied to Figure 5 Timing diagram of the voltage of the cell string. exist Fig.13 , the horizontal axis indicates time, and the vertical axis shows voltages of the string selection line SSL, the selected word line SEL_WL, the unselected word line UNSEL_WL, and the ground selection line GSL. Between the first time point t1 and the second time point t2, a development operation for a read operation may be performed, and a latch operation may be performed after the second time point t2. Figure 3 320 in the figure) can apply a string selection on voltage VSON to the selected string selection line. The string selection on voltage VSON can be used to turn on the string selection transistor ( Figure 5 The string selection on voltage VSON may be a power supply voltage or a high voltage having a higher level than the power supply voltage. The address decoder 320 may maintain the voltage of the unselected string selection line as the string selection off voltage VSOFF. The address decoder 320 may apply a first read pass voltage VREAD1 to an unselected word line UNSEL_WL. The first read pass voltage VREAD1 may be a voltage for turning on a memory cell. The first read pass voltage VREAD1 may have a first voltage level. The address decoder 320 may apply read voltages VRD1 to VRD7 to a selected word line SEL_WL. The address decoder 320 may apply a ground selection on voltage VGON to a selected ground selection line. The ground selection on voltage VGON may be a voltage for turning on a ground selection transistor GST. The ground selection on voltage VGON may be a power supply voltage or a high voltage higher than the power supply voltage. The address decoder 320 may maintain the voltage of an unselected ground selection line as a ground selection off voltage VGOFF. During the development operation, the string selection transistors SST1, SST2, and SST3 of the selected plane of the selected memory cell block may be turned on by the string selection turn-on voltage VSON. The ground selection transistors GST of the selected plane may be turned on by the ground selection turn-on voltage VGON. The memory cells connected to the unselected word lines in the selected plane may be turned on by the first read pass voltage VREAD1. The memory cells connected to the selected word lines in the selected plane may be turned on or off by the read voltages VRD1, ..., VRD7. For example, a memory cell in which '1' is written as the least significant bit (LSB) may be turned on by a read voltage VRD1. The voltage of the bit line corresponding to the turned-on cell is discharged to the common source line CSL. Therefore, the voltage of the bit line corresponding to the turned-on cell is reduced during the development operation. A memory cell in which '0' is written as the least significant bit (LSB) may be turned off by a read voltage VRD1. The voltage of the bit line corresponding to the turned-off cell is not discharged to the common source line CSL. Therefore, the voltage of the bit line corresponding to the turned-off cell is maintained without being reduced during the development operation. After the second time point t2, the address decoder 320 may apply the string selection off voltage VSOFF to the string selection line. The address decoder 320 may apply the word line voltage V0 to the unselected word line UNSEL_WL and the selected word line SEL_WL. The word line voltage V0 may be a ground voltage or a voltage having a level similar to the ground voltage. The address decoder 320 may apply the ground selection off voltage VGOFF to the ground selection line. Assume that steps S1010 and S1020 are performed between the second time point t2 and the third time point t3. As time passes from the second time point t2, the charge trapped in the memory cell may flow out, and thus the threshold voltage of the memory cell may change. Therefore, the turn-off cell count values ​​at the first time point t1 and the third time point t3 may be different, and the read pass voltages VREAD1 and VREAD2 may also be determined to have different voltage levels. Between the third time point t3 and the fourth time point t4, a developing operation for a read operation may be performed, and a latching operation may be performed after the fourth time point t4. The address decoder 320 may apply a string selection on voltage VSON to a selected string selection line. The address decoder 320 may maintain a voltage of an unselected string selection line as a string selection off voltage VSOFF. The address decoder 320 may apply a second read pass voltage VREAD2 to an unselected word line UNSEL_WL. The second read pass voltage VREAD2 may be a voltage for turning on a memory cell. The second read pass voltage VREAD1 may have a second voltage level higher than that of the first read pass voltage VREAD2. The address decoder 320 may apply read voltages VRD1 to VRD7 to a selected word line SEL_WL. The address decoder 320 may apply the ground selection on voltage VGON to the selected ground selection line. The address decoder 320 may maintain the voltage of the unselected ground selection line as the ground selection off voltage VGOFF. although Fig.13 Although not shown in FIG. 1 , a ground voltage or a low voltage having a level similar to the ground voltage may be applied to the common source line CSL. The method of operating a memory device according to some embodiments can prevent read disturbance degradation by applying a low read pass voltage VREAD1 when the memory cells are initially narrowly distributed, and improve the read characteristics of the nonvolatile memory device 124 by applying a read pass voltage VREAD2 higher than the read pass voltage VREAD1 after the retention degradation progresses. That is, since the higher the off-cell count value, the less the retention degradation progresses, the memory device performs a read operation with the low read pass voltage VREAD1, and as the off-cell count value decreases, the retention degradation further progresses, and the memory device can perform a read operation with the high read pass voltage VREAD2 to prevent the execution of a defensive code or UECC. Fig.14 is a flow chart illustrating a method of operating a storage device according to some embodiments. exist Fig.14 In the steps of the method for operating a storage device, Fig.10 The steps of the method for operating a storage device described in the description are the same as or similar to the steps described in the description. refer to Fig.14 , non-volatile memory devices ( Figure 1 124) for the memory cell array ( Figure 1 A program operation (S1400) is performed on the memory cell block included in 125). The nonvolatile memory device 124 performs a cell counting operation on the memory cell block (S1410). In some embodiments, when the memory device ( Figure 1 When the non-volatile memory device 121 is in an idle state, the non-volatile memory device 124 can perform a cell counting operation. The memory controller 121 determines the read pass voltage of the memory cell block based on the cell count value (S1420). In some embodiments, the memory controller 121 may determine the read pass voltage of the memory cell block, receive a read request for the memory cell block whose read pass voltage is determined in step S1460, and perform a read operation according to step S1470. The memory controller 121 checks the temperature information TD provided from the temperature sensor 123 (S1430). The memory controller 121 sets a set time period according to the temperature information (S1440). The storage controller 121 determines whether the time elapsed from the set time period or the time elapsed from checking the temperature information exceeds the set time period (S1450). If the time elapsed from the set time period or the time elapsed from checking the temperature information exceeds the set time period, the storage controller 121 performs step S1410. If the time elapsed from the set time period or the time elapsed from checking the temperature information is less than or equal to the set time period, the storage controller 121 determines whether a read request is received from the host device 110 (S1460). When the read request is received, the storage controller 121 controls the nonvolatile memory device 124 to perform a read operation (S1470). Fig.15 is a flow chart illustrating a method of operating a storage device according to some embodiments. exist Fig.15 In the steps of the method for operating a storage device, Fig.10 The steps of the method for operating a storage device described in the description are the same as or similar to the steps described in the description. refer to Fig.15 , non-volatile memory devices ( Figure 1 124) for the memory cell array ( Figure 1 A program operation (S1500) is performed on the memory cell block included in 125). The storage device 120 counts a time period after performing a program operation on a memory cell block (S1510). The storage device 120 may store a time when a program operation is performed on each of the memory cell blocks and count a time elapsed from the stored time. The memory controller 121 determines a read pass voltage of the memory cell block based on the time period (S1520). In detail, the memory controller 121 may check the retention level based on the time period, and determine the read pass voltage based on the retention level. For example, the memory controller 121 may determine that the retention level is lower as the length of the time period is longer, and determine a read pass voltage with a higher level. The memory controller 121 may determine the read pass voltage based on the length of the time period, so that the read pass voltage when the length of the time period is a first value is greater than the read pass voltage when the length of the time period is a second value less than the first value. The memory controller 121 determines whether a read request is received from the host device 110 (S1530). When the read request is received, the memory controller 121 controls the nonvolatile memory device 124 to perform a read operation (S1540). Fig.16 is a flow chart illustrating a method of operating a storage device according to some embodiments. exist Fig.16 In the steps of the method for operating a storage device, Fig.10 The steps of the method for operating a storage device described in the description are the same as or similar to the steps described in the description. refer to Fig.16 , storage devices ( Figure 1 121) for non-volatile memory devices ( Figure 1 124) performs a read operation (S1600). The storage device 120 detects and corrects errors in the data read from the nonvolatile memory device 124 to determine whether a UECC has occurred (S1610). The storage device 120 may perform an error detection and correction function on the read data read from the nonvolatile memory device 124. The storage device 120 may detect the UECC during error correction decoding of the data received from the nonvolatile memory device 124. If it is determined that UECC has occurred, the memory controller 121 changes the read pass voltage of the memory cell block (S1620). The memory controller 121 may determine the read pass voltage based on the number and frequency of UECC occurrences for each memory cell block. In some embodiments, when the number of occurrences of UECC is large, the memory controller 121 may determine that the read pass voltage has a higher level. For example, the memory controller 121 may determine the read pass voltage based on the number of occurrences of UECC, so that the read pass voltage when the number of occurrences of UECC is a first value is greater than the read pass voltage when the number of occurrences of UECC is a second value less than the first value. In some embodiments, the memory controller 121 may increase the read pass voltage of the memory cell block in which the UECC has occurred. Whenever the UECC occurs, the memory controller 121 may increase the read pass voltage. If it is determined that UECC has not occurred, the memory controller 121 maintains the read pass voltage of the memory cell block ( S1622 ). Fig.17 is a flow chart illustrating a method of operating a storage device according to some embodiments. exist Fig.17 In the steps of the method for operating a storage device, Fig.10 The steps of the method for operating a storage device described in the description are the same as or similar to the steps described in the description. refer to Fig.17 , Storage Controller ( Figure 1 121) to the non-volatile memory device ( Figure 1 124) applies power PWR (S1700). The nonvolatile memory device 124 performs a cell counting operation on a word line group within a memory cell block (S1710). Specifically, the storage controller 121 may provide a command CMD indicating a cell counting operation to the nonvolatile memory device 124. In some embodiments, in response to the provided command CMD, the nonvolatile memory device 124 may count memory cells (turn-off cells) that block a current path to a channel in response to a read voltage (or a verification voltage) at a specific time point. In some embodiments, the nonvolatile memory device 124 may perform a cell counting operation on each word line group in response to the provided command CMD. For example, a memory cell block of the nonvolatile memory device 124 may include a plurality of word line groups, and each word line group may include a plurality of word lines. These word line groups may correspond to a plurality of gate electrodes disposed in a physically identifiable channel structure. This will refer to Fig.18 and Fig.19 Give a description. Fig.18 is a perspective view showing a semiconductor device according to some embodiments, and Fig.19 is a cross-sectional view illustrating an example of a semiconductor device according to some embodiments. refer to Fig.18 and Fig.19 , the semiconductor device 1800 may include a cell array structure CS and a peripheral circuit structure PS overlapping each other in a vertical direction Z. The cell array structure CS may include a reference Figure 3 The memory cell array 310 described above and the peripheral circuit structure PS may include reference Figure 3 The peripheral circuits 320, . . . , 360 are described. The cell array structure CS includes a plurality of memory cell blocks BLK1, BLK2, ..., BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn may include a memory cell arranged in three dimensions. The cell array structure CS may include a cell region CELL, and the peripheral circuit structure PS may include a peripheral circuit transistor 60TR and a peripheral circuit wiring structure 70 disposed on a substrate 50. The active region AC may be located on the substrate 50 through a device isolation layer 52, and the plurality of peripheral circuit transistors 60TR may be located on the active region AC. The plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and a source / drain region 62 disposed on a portion of the substrate 50 on both sides of the peripheral circuit gate 60G. The substrate 50 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium. The substrate 50 may be provided as a bulk wafer or an epitaxial layer. In other embodiments, the substrate 50 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI, GeOI) substrate. The peripheral circuit wiring structure 70 may include a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit wiring layers 74. An interlayer insulating layer 80 covering the peripheral circuit transistor 60TR and the peripheral circuit wiring structure 70 may be disposed on the substrate 50. The plurality of peripheral circuit wiring layers 74 may have a multilayer structure including a plurality of metal layers disposed at different vertical levels. Fig.19 It is shown that multiple peripheral circuit wiring layers 74 are all formed at the same height, but alternatively, peripheral circuit wiring layers 74 arranged on some levels (for example, arranged on the top layer) can be formed to a higher height than peripheral circuit wiring layers 74 arranged on other levels. The base structure 210B may be disposed on the peripheral circuit structure PS, and the base structure 210B may include a base substrate 210S, a lower base layer 210L, and an upper base layer 210U sequentially disposed on the interlayer insulating layer 80 . The base substrate 210S may include a semiconductor material such as silicon. The lower base layer 210L may include impurity-doped polysilicon or undoped polysilicon, and the upper base layer 210U may include impurity-doped polysilicon or undoped polysilicon. The lower base layer 210L may correspond to the reference Figure 5 The upper base layer 210U may be used as a support layer to prevent a mold stack from collapsing or collapsing during the process of removing a sacrificial material layer to form the lower base layer 210L. The first gate stack GS1 may be disposed on the base structure 210B, and the second gate stack GS2 may be disposed on the first gate stack GS1. The first gate stack GS1 includes a plurality of first gate electrodes 230 and a plurality of first insulating layers 240 disposed alternately, and the second gate stack GS2 may include a plurality of second gate electrodes 230A and a plurality of second insulating layers 240A disposed alternately. The plurality of channel structures 260A may be located inside the first channel hole 260H1 penetrating the first gate stack GS1 and the second channel hole 260H2 penetrating the second gate stack GS2. The plurality of channel structures 260A may have a shape protruding outward from a boundary between the first channel hole 260H1 and the second channel hole 260H2. A plurality of channel structures 260A may pass through the upper base layer 210U and the lower base layer 210L and contact the base substrate 210S. A portion of the gate insulating layer 262 may be removed at the same level as the lower base layer 210L, and the channel layer 264 may contact the extension portion 210LE of the lower base layer 210L. The sidewall portion 262S and the bottom portion 262L of the gate insulating layer 262 are spaced apart from each other, wherein the extension portion 210LE of the lower base layer 210L is interposed between the sidewall portion 262S and the bottom portion 262L, the bottom portion 262L of the gate insulating layer 262 surrounds the bottom surface of the channel layer 264, and the channel layer 264 may be electrically connected to the lower base layer 210L instead of directly contacting the base substrate 210S. The plurality of first gate electrodes 230 included in the first gate stack GS1 and the plurality of second gate electrodes 230A included in the second gate stack GS2 may correspond to different word line groups, respectively. For example, the first word line group may include the plurality of first gate electrodes 230 included in the first gate stack GS1, and the second word line group may include the plurality of second gate electrodes 230A included in the second gate stack GS2. Although it has been described above that a plurality of word line groups correspond to gate electrodes included in physically separated gate stacks, the embodiment is not limited thereto. For example, a plurality of word line groups may be classified according to a distance from a ground selection line GSL, a distance from a string selection line SSL, or a distance from a base structure 210B. In addition, the number of word lines included in each of the plurality of word line groups may be the same or different. Fig. 20 Cell strings included in a memory cell block and voltages applied to the cell strings according to some embodiments are illustrated. refer to Fig. 20 , during a read operation and / or a program verification operation, the nonvolatile memory device may read data stored in memory cells connected to a selected word line WL5 by applying a read voltage VRD to a selected word line WL5 connected to selected cell strings CS1, CS2, and CS3. The predetermined turn-on voltages VSON and VGON may be applied to the first string selection line SSL1 as a selected string selection line and the ground selection line GSL as a selected ground selection line. The read voltage VRD may be applied to the selected word line, i.e., the fifth word line WL5. The second read pass voltage VREAD2 may be applied to the unselected word lines WL1, ..., WL4, WL6 ..., and WL32 included in the first word line group GWL1. The first read pass voltage VREAD1 different from the second read pass voltage VREAD2 may be applied to the unselected word lines WL33, ..., and WL64 included in the second word line group GWL2. In some embodiments, the second read pass voltage VREAD2 applied to the upper second word line group GWL2 (or a word line group adjacent to the string selection line (SSL1)) may be set to be higher than the second read pass voltage VREAD2 applied to the lower first word line group GWL1 (or a word line group adjacent to the ground selection line (GSL)). Fig.21 is a flow chart illustrating a method of operating a storage device according to some embodiments. exist Fig.21 In the steps of the method for operating a storage device, Fig.17 The steps of the method for operating a storage device described in the description are the same as or similar to the steps described in the description. refer to Fig.21 , non-volatile memory devices ( Figure 1 124) for the memory cell array ( Figure 1 A program operation (S2100) is performed on the memory cell block included in 125). The nonvolatile memory device 124 performs a cell counting operation on a word line group within a memory cell block (S2110). In some embodiments, when the memory device ( Figure 1 When the non-volatile memory device 121 is in an idle state, the non-volatile memory device 124 can perform a cell counting operation. The memory controller 121 determines a read pass voltage for each of the word line groups based on the cell count value (S2120). In some embodiments, the memory controller 121 may determine a read pass voltage for each of the word line groups, receive a read request for a memory cell block including the word line group whose read pass voltage is determined in operation S2160, and perform a read operation according to step S2170. The memory controller 121 checks the temperature information TD provided from the temperature sensor 123 (S2130). The memory controller 121 sets a set time period according to the temperature information (S2140). The storage controller 121 determines whether the time elapsed from the set time period or the time elapsed from checking the temperature information exceeds the set time period (S2150). If the time elapsed from the set time period or the time elapsed from checking the temperature information exceeds the set time period, the storage controller 121 performs step S2110. If the time elapsed from the set time period or the time elapsed from checking the temperature information is less than or equal to the set time period, the storage controller 121 determines whether a read request is received from the host device 110 (S2160). When a read request is received, the storage controller 121 controls the nonvolatile memory device 124 to perform a read operation (S2170). Fig. 22 is a flow chart illustrating a method of operating a storage device according to some embodiments. exist Fig. 22 In the steps of the method for operating a storage device, Fig.17 The steps of the method for operating a storage device described in the description are the same as or similar to the steps described in the description. refer to Fig. 22 , non-volatile memory devices ( Figure 1 124) pairs connected to the memory cell array ( Figure 1 A programming operation is performed on memory cells of a word line group (125) of FIG. 125 (S2200). The storage device 120 counts a time period after performing a program operation on memory cells connected to the word line group (S2210). The storage device 120 may store a time when the program operation is performed on each of the word line groups, and may count a time elapsed from the stored time. The memory controller 121 determines a read pass voltage of the word line group based on the time period (S2220). As the length of the time period is longer, the memory controller 121 may determine that the read pass voltage is at a higher level. For example, the memory controller 121 may determine the read pass voltage based on the length of the time period so that the read pass voltage when the length of the time period is a first value is greater than the read pass voltage when the length of the time period is a second value less than the first value. The memory controller 121 determines whether a read request is received from the host device 110 (S2230). When the read request is received, the memory controller 121 controls the nonvolatile memory device 124 to perform a read operation (S2240). Fig.23 is a flow chart illustrating a method of operating a storage device according to some embodiments. exist Fig.23 In the steps of the method for operating a storage device, Fig.17The steps of the method for operating a storage device described in the description are the same as or similar to the steps described in the description. refer to Fig.23 , storage devices ( Figure 1 121) for non-volatile memory devices ( Figure 1 124) performs a read operation (S2300). The storage device 120 determines whether a UECC has occurred by detecting and correcting errors in the data read from the nonvolatile memory device 124 (S2310). The storage device 120 may perform an error detection and correction function on the read data read from the nonvolatile memory device 124. The storage device 120 may detect the UECC during error correction decoding of the data received from the nonvolatile memory device 124. If it is determined that UECC has occurred, the memory controller 121 changes the read pass voltage of the word line group (S2320). The memory controller 121 may determine the read pass voltage based on the number and frequency of occurrences of UECC for each word line group. In some embodiments, when the number of occurrences of UECC is large, the memory controller 121 may determine that the read pass voltage has a higher level. For example, the memory controller 121 may determine the read pass voltage based on the number of occurrences of UECC, so that the read pass voltage when the number of occurrences of UECC is a first value is greater than the read pass voltage when the number of occurrences of UECC is a second value less than the first value. In some embodiments, the memory controller 121 may increase the read pass voltage of the word line group in which the UECC has occurred. Whenever the UECC occurs, the memory controller 121 may increase the read pass voltage. If it is determined that UECC has not occurred, the memory controller 121 maintains the read pass voltage of the memory cell block ( S2322 ). Fig.24 is a graph showing the number of error bits per 4 KB as a function of the number of page reads for each read pass voltage, according to some embodiments. refer to Fig.24 , the read pass voltage VREAD2 is higher than the read pass voltage VREAD1. When the number of page reads is 0, the difference in the number of error bits according to the read pass voltages VREAD1 and VREAD2 is small. When the number of page reads increases, the number of error bits according to the read pass voltage VREAD2 is greater than the number of error bits according to the read pass voltage VREAD1. That is, when the low read pass voltage VREAD1 is used, the generation of error bits can be prevented. Fig.25 is a graph showing threshold voltage distributions for each read pass voltage according to some embodiments. exist Fig.25In the graph of , the horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of memory cells. refer to Fig.25 , the read pass voltage VREAD2 is higher than the read pass voltage VREAD1. Compared with the threshold voltage distribution when the page read operation is performed using the read pass voltage (VREAD2), the threshold voltage distribution when the page read operation is performed using the read pass voltage (VREAD1) is uneven. Specifically, the threshold voltage distribution of the memory cell having the first state E when the page read operation is performed using the read pass voltage (VREAD2) is shifted closer to the threshold voltage distribution of the memory cell having the second state P1. That is, when the low read pass voltage VREAD1 is used, the threshold voltage distribution can be prevented from shifting. Therefore, in the case of using the low read pass voltage VREAD1 , read disturbance degradation can be prevented. Fig.26 is a graph showing the number of executions of defense code for each read pass voltage according to some embodiments. exist Fig.26 In the graph of FIG. 1 , the horizontal axis indicates the magnitude of the read pass voltage, and the vertical axis indicates the number of executions of the defense code. refer to Fig.26 , the read pass voltage VREAD3 is higher than the read pass voltage VREAD2, and the read pass voltage VREAD2 is higher than the read pass voltage VREAD1. The number of executions of the defense code when the page read operation is performed using the read pass voltage VREAD2 is less than the number of executions of the defense code when the page read operation is performed using the read pass voltage VREAD1. The number of executions of the defense code when the page read operation is performed using the read pass voltage VREAD3 is less than the number of executions of the defense code when the page read operation is performed using the read pass voltage VREAD2. That is, in order to reduce the number of executions of the defense code, a higher read pass voltage VREAD needs to be applied. According to some embodiments, since the voltage level of the read pass voltage VREAD provided to the memory cell block or word line having a relatively low retention level is greater than the voltage level of the read pass voltage VREAD provided to the memory cell block or word line having a relatively high retention level, read disturbance degradation caused by the read pass voltage VREAD of the memory cell block having a relatively high retention level or the memory cells connected to the word line is prevented, and read errors (e.g., execution of defense code, generation of UECC, etc.) of the memory cell block having a relatively low retention level or the memory cells connected to the word line can be prevented. Fig. 27is a block diagram illustrating an example of a solid state drive (SSD) system applied to a nonvolatile memory device according to some embodiments. refer to Fig. 27 , the SSD system 2700 may include a host 2710 and an SSD 2720 . SSD 2720 can use reference Figures 1 to 26 The SSD 2720 may exchange signals with the host 2710 through the signal connector (SGL) and receive power (PWR) through the power connector. The SSD 2720 may receive a firmware image download command and a firmware image to be downloaded through the signal connector SGL. The SSD 2720 may include a controller 2721, an auxiliary power supply 2722, and a plurality of memory systems 2723, 2324, and 2325. Each of the plurality of memory systems 2723, 2324, and 2325 may include one or more flash memory devices as storage devices. In addition, each flash memory device may include one or more dies (DIEs), and one or more blocks may be provided in each die (DIE). The controller 2721 may communicate with the plurality of memory systems 2723, 2324, and 2325 through the plurality of channels Ch1, . . . , Chn. The controller 2721 may change the level of a read pass voltage applied to a memory cell block or a word line group based on a retention level of the memory cell block or the word line group included in the plurality of memory systems 2723, 2324, and 2325. Therefore, read disturbance degradation caused by read pass voltage of a memory cell block having a relatively high retention level or memory cells connected to a word line is prevented, and read errors of a memory cell block having a relatively low retention level or memory cells connected to a word line can be prevented. Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the protection claimed. Certain features described in the context of separate implementations in the present disclosure may also be implemented in combination in a single implementation. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiples individually or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, one or more features from the combination may be removed from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination. While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A non-volatile memory device, include: a memory cell array comprising a plurality of memory cell blocks; as well as An address decoder is connected to the memory cell array through a plurality of word lines, wherein the address decoder is configured to: applying a plurality of read pass voltages of different levels to a plurality of memory cell blocks among the plurality of memory cell blocks, respectively, and For a selected memory cell block among the plurality of memory cell blocks, a corresponding read pass voltage is applied to a plurality of unselected word lines of the selected memory cell block.

2. The non-volatile memory device according to claim 1, wherein The address decoder is configured to apply a read pass voltage, which is higher than a read pass voltage corresponding to the selected memory cell block, to a memory cell block in which retention degradation is more advanced than in a selected memory cell block.

3. The non-volatile memory device according to claim 1, wherein The address decoder is configured to apply a read pass voltage, which is higher than a read pass voltage corresponding to the selected memory cell block, to a memory cell block having a lower off cell count value than the selected memory cell block.

4. The nonvolatile memory device according to claim 1, wherein The address decoder is configured to apply a read pass voltage, which is higher than a read pass voltage corresponding to the selected memory cell block, to a memory cell block in which a greater number of read errors have occurred than in a selected memory cell block.

5. The nonvolatile memory device according to claim 1, wherein The address decoder is configured to change a read pass voltage level of a memory cell block in which an uncorrectable error correction code UECC is generated, and apply the changed read pass voltage to the memory cell block in which the UECC is generated.

6. The nonvolatile memory device according to claim 1, wherein The address decoder is configured to apply a read pass voltage having a first level to a first memory cell block among the plurality of memory cell blocks at a first time point, and to apply a read pass voltage having a second level different from the first level to the first memory cell block at a second time point different from the first time point.

7. The non-volatile memory device according to claim 6, wherein The second time point is after the first time point, and the second level is greater than the first level.

8. The nonvolatile memory device according to claim 1, wherein The address decoder is configured to apply a read pass voltage having a first level to a plurality of unselected word lines among a plurality of word lines connected to a memory cell block among the plurality of memory cell blocks, and to apply a read pass voltage having a second level different from the first level to another one or more unselected word lines.

9. The nonvolatile memory device according to claim 8, wherein the memory cell array include: Infrastructure; A first gate stack, which is disposed on the base structure and includes a plurality of first gate electrodes, a plurality of first insulating layers and a first channel hole, wherein the plurality of first gate electrodes and the plurality of first insulating layers are alternately disposed; A second gate stack is disposed on the first gate stack and includes a plurality of second gate electrodes, a plurality of second insulating layers, and a second channel hole, wherein the plurality of second gate electrodes and the plurality of second insulating layers are alternately disposed; as well as a plurality of channel structures located inside the first channel hole and the second channel hole and having a shape protruding outward from a boundary between the first channel hole and the second channel hole, The plurality of unselected word lines correspond to the plurality of first gate electrodes, and the one or more other unselected word lines correspond to the plurality of second gate electrodes.

10. A storage device, include: A non-volatile memory device comprising a block of memory cells; as well as A storage controller configured to: checking the retention level of the memory cell block, determining a read pass voltage based on the retention level, and The nonvolatile memory device is controlled to apply the read pass voltage to the memory cell block.

11. The storage device according to claim 10, wherein The memory controller is configured to perform an off-cell count operation on the memory cell block and check a retention level based on the off-cell count value.

12. The memory device of claim 11, wherein the memory controller is configured to determine the read pass voltage such that: The larger the off-cell count value, the lower the read pass voltage applied, and The higher the retention level, the lower the read pass voltage applied.

13. The storage device according to claim 10, wherein The memory controller is configured to check a retention level of the memory cell block after power is applied to the nonvolatile memory device.

14. The storage device according to claim 10, wherein The memory controller is configured to check a retention level of a memory cell block after performing a program operation on the memory cell block.

15. The storage device according to claim 14, wherein The memory controller is configured to count a time period from when a program operation is performed on the memory cell block, and to check a retention level of the memory cell block based on the time period.

16. The storage device according to claim 10, include: a temperature sensor configured to measure an internal temperature of the nonvolatile memory device, Wherein, the storage controller is configured as: determining a time period based on the temperature, and When the period of time has elapsed, the retention level of the memory cell block is checked.

17. A method for operating a storage device, include: checking a retention level of a memory cell block included in a nonvolatile memory device; determining a level of a read pass voltage applied to the memory cell block based on the retention level; as well as A command for controlling the level of the read pass voltage to the determined level is sent to the nonvolatile memory device.

18. The operating method according to claim 17, in, Checking the retention level of a block of memory cells includes: performing an off-cell count operation on the memory cell block; and A retention level of the memory cell block is checked based on the off-cell count value.

19. The operating method according to claim 18, wherein determining the level of a read pass voltage applied to the memory cell block comprises determining the level of the read pass voltage such that: The larger the shut-off unit count value is, the lower the read pass voltage is; and The higher the retention level, the lower the read pass voltage.

20. The operating method according to claim 17, include: measuring an internal temperature of the nonvolatile memory device; determining a time period based on the temperature; as well as A retention level of the block of memory cells is checked after the time period.

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