IGBT device based on trench gate and preparation method thereof

Abstract

According to the IGBT device based on the trench gate and the preparation method of the IGBT device based on the trench gate, through two times of trench etching, the first trench with the wide width is formed for the first time, downward etching continues on the basis of the first trench for the second time so that the second trench with the wide upper portion and the narrow lower portion can be formed, and the trench gate is formed in the second trench; meanwhile, a spacer region between two adjacent first grooves is used as a formation region of a subsequent conductive contact hole, so that the dielectric layer formed in the second groove can be self-aligned to form a contact hole of the conductive contact hole; the process that a contact hole mask and a trench gate mask need to be aligned when the contact hole is formed by adopting a photoetching process is avoided. Because the contact hole is formed by adopting a self-alignment mode, the consistency of the distance between the subsequently formed conductive contact hole and the trench gate is high, the discreteness of the saturation voltage drop Vcesat value in the IGBT wafer is greatly reduced and even can be avoided, and the saturation voltage drop Vcesat value is not increased at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to an IGBT device based on a trench gate and a preparation method thereof. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a device composed of MOSFET and bipolar transistor. Its input is MOSFET and its output is PNP transistor. Therefore, IGBT can be regarded as Darlington transistor with MOSFET input. IGBT has the advantages of high input impedance, low drive circuit power, simple drive, fast switching speed and low switching loss of MOSFET, and has the advantages of high current density, strong current handling capacity and low on-saturation voltage drop of bipolar power transistor. Therefore, it has been more and more widely used in modern power electronics technology. Since the early 1980s, it has been widely studied at home and abroad. At present, IGBT has broad application prospects and is widely used in many fields such as new energy vehicles, industrial frequency conversion, photovoltaics, smart grids and locomotives.

[0003] After nearly 40 years of development, IGBT has evolved from a planar type to a trench type, and the pitch (minimum repeating unit) of the cell has become smaller and smaller, and the distance from the active area contact hole to the trench gate has also become smaller and smaller, and the requirements for the alignment accuracy of the contact hole mask and the trench gate mask have become higher and higher. If the alignment accuracy of the contact hole mask and the trench gate mask is poor, it may lead to insufficient distance from the contact hole to the trench gate, which will cause the saturation voltage drop Vcesat value in the IGBT wafer to be highly discrete and the saturation voltage drop Vcesat value will also increase. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, an object of the present invention is to provide an IGBT device based on a trench gate and a method for preparing the same, so as to solve the problem in the prior art that the saturation voltage drop Vcesat value in the IGBT wafer is highly discrete and the saturation voltage drop Vcesat value is also increased due to insufficient distance from the contact hole to the trench gate.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing an IGBT device based on a trench gate, the method comprising:

[0006] Providing a substrate, the substrate comprising, from bottom to top, an N-type substrate layer, an N-type carrier storage layer, a P-type body region, and an N-type emitter region; wherein the doping concentration of the carrier storage layer is greater than the doping concentration of the substrate layer, and the doping concentration of the emitter region is greater than the doping concentration of the carrier storage layer;

[0007] Extending downward from the upper surface of the emitter region to form two or more first grooves of a preset depth; wherein the preset depth is less than the thickness of the emitter region;

[0008] forming a sidewall protection layer on the sidewall of the first trench;

[0009] Based on the first trench and the sidewall protection layer, the emitter region is continuously etched downwards until it reaches the substrate layer to form a second trench, and the sidewall protection layer is removed;

[0010] A gate insulating layer and a gate conductive layer are sequentially formed on the surface of the second trench; wherein the upper surface of the gate conductive layer is not lower than the upper surface of the P-type body region;

[0011] forming a dielectric layer in the second trench to cover the surface of the gate conductive layer and fill the second trench;

[0012] By self-aligned etching, the emitter region between two adjacent first trenches is etched until the body region is exposed to form a contact hole;

[0013] Filling the contact hole with a conductive material and then forming an emitter metal layer;

[0014] A buffer layer, a P-type collector region and a collector metal layer are formed on the lower surface of the substrate layer.

[0015] Optionally, the carrier storage layer, the body region and the emitter region are formed by sequentially performing ion implantation on the upper surface of the substrate.

[0016] Optionally, the method of forming the first groove includes:

[0017] Forming a hard mask layer on the surface of the emitter region and patterning the hard mask layer to form a patterned hard mask layer, wherein the patterned hard mask layer exposes the first trench region;

[0018] The emitter region is etched based on the patterned hard mask layer to form the first trench.

[0019] Furthermore, the method for forming the sidewall protection layer includes:

[0020] Depositing a sidewall protection material layer on the surface of the obtained structure;

[0021] The sidewall protection material layer other than the sidewall of the first trench is removed by etching back, so that the remaining sidewall protection material layer is formed into the sidewall protection layer.

[0022] Optionally, the substrate material is silicon material, and the gate insulating layer is formed by a thermal oxidation process.

[0023] Furthermore, the material of the dielectric layer includes BPSG.

[0024] Optionally, the angle between the contact hole and the horizontal plane is 70° to 90°.

[0025] Furthermore, before filling the contact hole with the conductive material, the method further includes: performing P-type ion implantation for ohmic contact on the surface of the body region exposed in the contact hole to form a P-type ohmic contact layer.

[0026] Furthermore, the angle between the contact hole and the horizontal plane is 70° to 85°, and the method for forming the ohmic contact layer includes:

[0027] forming a protective layer on the sidewall of the contact hole to prevent damage from ion implantation;

[0028] Performing ion implantation on the surface of the body region exposed by the contact hole based on the protective layer to form the ohmic contact layer;

[0029] The protective layer is removed.

[0030] The present invention also provides an IGBT device based on a trench gate, the IGBT device comprising, from bottom to top, a collector metal layer, a P-type collector region, a buffer layer, an N-type substrate layer, an N-type carrier storage layer, a P-type body region, an N-type emitter region and an emitter metal layer;

[0031] It also includes: more than two trench gates, conductive contact holes and a dielectric layer; wherein,

[0032] The trench gate comprises a second trench, a gate insulating layer and a gate conductive layer, the second trench extends from the surface of the emitter region to the substrate layer, and the second trench is divided into a first trench and a bottom trench from top to bottom, the depth of the first trench is less than the thickness of the emitter region, and the diameter of the first trench is greater than the diameter of the bottom trench, the gate insulating layer is formed on the surface of the second trench, the gate conductive layer is filled in the second trench on the gate insulating layer, and the upper surface of the gate conductive layer is not lower than the upper surface of the P-type body region;

[0033] The dielectric layer is formed in the second trench, covers the surface of the gate conductive layer and fills the second trench completely;

[0034] The conductive contact hole includes a contact hole and a conductive material filling the contact hole, and the conductive contact hole extends from the emitter region between two adjacent first trenches to expose the body region.

[0035] Optionally, the angle between the contact hole and the horizontal plane is 70° to 90°.

[0036] Optionally, a P-type ohmic contact layer is also formed at the bottom of the conductive contact hole.

[0037] As described above, the IGBT device based on the trench gate of the present invention and the preparation method thereof, through two trench etchings, the first time forms a first trench with a relatively wide width, the second time continues to etch downward on the basis of the first trench to form a second trench with a wide top and a narrow bottom, and forms a trench gate in the second trench, and at the same time uses the spacing area between the two adjacent first trenches as the formation area of ​​the subsequent conductive contact hole, so that the dielectric layer formed in the second trench can be self-aligned to form the contact hole of the conductive contact hole, avoiding the process of aligning the contact hole mask with the trench gate mask when forming the contact hole by the photolithography process, thereby avoiding the problem that the distance from the contact hole to the trench gate is insufficient due to the poor alignment accuracy of the contact hole mask and the trench gate mask, resulting in a large discreteness of the saturation voltage drop Vcesat value in the IGBT wafer and an increase in the saturation voltage drop Vcesat value. Since the contact hole is formed by the self-alignment method, the consistency of the distance between the subsequently formed conductive contact hole and the trench gate is high, so the discreteness of the saturation voltage drop Vcesat value in the IGBT wafer is greatly reduced or even avoided, and the saturation voltage drop Vcesat value will not increase. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figures 1 to 22 It shows a schematic cross-sectional structure diagram of each step in the method for preparing a trench gate-based IGBT device of the present invention.

[0039] Component number description

[0040] 10 Base

[0041] 100 substrate layer

[0042] 101 Carrier Storage Layer

[0043] 102 Body Area

[0044] 103 emitter region

[0045] 104 First Groove

[0046] 105 Hard mask layer

[0047] 106 Photoresist layer

[0048] 107 Patterned Hard Mask Layer

[0049] 108 first groove area

[0050] 109 side wall protection material layer

[0051] 110 Side wall protection layer

[0052] 111 Second Groove

[0053] 112 Bottom groove

[0054] 113 Trench Gate

[0055] 114 gate insulating layer

[0056] 115 gate conductive layer

[0057] 116 Dielectric layer

[0058] 117 Contact hole

[0059] 118 Conductive materials

[0060] 119 Conductive contact hole

[0061] 120 emitter metal layer

[0062] 121 Buffer layer

[0063] 122 Collector region

[0064] 123 Collector metal layer

[0065] 124 Ohm contact layer DETAILED DESCRIPTION

[0066] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0067] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0068] See also Figures 1 to 22 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0069] Embodiment 1

[0070] This embodiment provides a method for preparing an IGBT device based on a trench gate, and the method comprises the following steps:

[0071] S1. Providing a substrate, wherein the substrate comprises, from bottom to top, an N-type substrate layer, an N-type carrier storage layer, a P-type body region, and an N-type emitter region; wherein the doping concentration of the carrier storage layer is greater than the doping concentration of the substrate layer, and the doping concentration of the emitter region is greater than the doping concentration of the carrier storage layer;

[0072] S2, extending downward from the upper surface of the emitter region to form two or more first grooves of a preset depth and a preset width; wherein the preset depth is less than the thickness of the emitter region;

[0073] S3, forming a sidewall protection layer on the sidewall of the first trench;

[0074] S4, based on the first trench and the sidewall protection layer, continue to etch the emitter region downward until it reaches the substrate layer to form a second trench, and remove the sidewall protection layer;

[0075] S5, sequentially forming a gate insulating layer and a gate conductive layer on the surface of the second trench; wherein the upper surface of the gate conductive layer is not lower than the upper surface of the P-type body region;

[0076] S6, forming a dielectric layer in the second trench, covering the surface of the gate conductive layer and filling the second trench;

[0077] S7, etching the emitter region between two adjacent first trenches through self-aligned etching until the body region is exposed to form a contact hole;

[0078] S8, filling the contact hole with a conductive material, and then forming an emitter metal layer;

[0079] S9, forming a buffer layer, a P-type collector region and a collector metal layer on the lower surface of the substrate layer.

[0080] The preparation method of the IGBT device based on the trench gate of this embodiment is to form a first trench with a wider width by two trench etchings in the first time, and to continue to etch downward on the basis of the first trench in the second time to form a second trench with a width on the top and a narrowness on the bottom, and to form a trench gate in the second trench, and at the same time, the spacing area between the two adjacent first trenches is used as the formation area of ​​the subsequent conductive contact hole, so that the dielectric layer formed in the second trench can be self-aligned to form the contact hole of the conductive contact hole, avoiding the process of aligning the contact hole mask with the trench gate mask when forming the contact hole by the photolithography process, thereby avoiding the problem that the distance from the contact hole to the trench gate is insufficient due to the poor alignment accuracy of the contact hole mask and the trench gate mask, resulting in large discreteness of the saturation voltage drop Vcesat value in the IGBT wafer and the increase of the saturation voltage drop Vcesat value. Since the contact hole is formed by the self-alignment method, the consistency of the distance between the conductive contact hole and the trench gate formed subsequently is high, so the discreteness of the saturation voltage drop Vcesat value in the IGBT wafer is greatly reduced or even avoided, and the saturation voltage drop Vcesat value will not increase.

[0081] The method for preparing the trench gate-based IGBT device of this embodiment is described in detail below with reference to the specific drawings.

[0082] like Figure 1 As shown, firstly, step S1 is performed to provide a substrate 10, wherein the substrate 10 includes, from bottom to top, an N-type substrate layer 100, an N-type carrier storage layer 101, a P-type body region 102 and an N-type emitter region 103; wherein, the doping concentration of the carrier storage layer 101 is greater than the doping concentration of the substrate layer 100, and the doping concentration of the emitter region 103 is greater than the doping concentration of the carrier storage layer 101.

[0083] In the preparation method of the trench gate IGBT device of this embodiment, the N-type can be formed by doping the semiconductor material with VA group elements, such as phosphorus, and the P-type can be formed by doping the semiconductor material with IIIA group elements, such as boron. However, it is not limited to this, and other N-type ions and P-type ions can also achieve the formation of corresponding doping types, which are selected according to actual needs.

[0084] The material of the substrate 10 can be any semiconductor material suitable for preparing IGBT devices, such as silicon, germanium, silicon carbide, gallium arsenide or gallium nitride, etc. In this embodiment, the material of the substrate 10 is silicon material. In addition, the doping concentration of the substrate 10 depends on the withstand voltage requirement of the IGBT device and is specifically set according to actual needs.

[0085] As an example, the carrier storage layer 101, the body region 102 and the emitter region 103 are formed by sequentially implanting ions into the upper surface of the substrate 10. For example, in this embodiment, phosphorus ions are implanted into the surface of the substrate 10 at a dose of 1e12 cm -2 ~5e13cm -2 The implantation energy is 1MeV to 2MeV, the advancement temperature is 1050°C to 1250°C, and the advancement time is 30min to 300min to form the carrier storage layer 101; then, the surface of the substrate 10 is implanted with boron ions: the implantation dose is 2e13cm -2 ~5e14cm -2 The implantation energy is 60keV to 200keV, the advancement temperature is 1050℃ to 1250℃, and the advancement time is 1min to 120min to form the body region 102; then, arsenic ions are implanted into the surface of the substrate 10, and the implantation dose is 3e15 cm -2 ~2e16 cm -2 The implantation energy is 60keV to 600keV, the implantation temperature is 900°C to 1000°C, and the implantation time is 0.5min to 120min to form the emitter region 103 .

[0086] like Figure 5 As shown, step S2 is then performed to form two or more first grooves 104 of preset depths extending downward from the upper surface of the emitter region 103; wherein the preset depth is less than the thickness of the emitter region 103, that is, the first groove 104 is a blind groove relative to the emitter region 103.

[0087] As an example, a method of forming the first trench 104 includes: Figure 3 and Figure 4 As shown, a hard mask layer 105 is first formed on the surface of the emitter region 103, and is patterned to form a patterned hard mask layer 107. The patterned hard mask layer 107 exposes a first trench region 108. Specifically, as shown in FIG. Figure 2 In the embodiment, a hard mask layer 105 and a photoresist layer 106 may be formed on the surface of the emitter region 103 in sequence. Figure 3 Then the photoresist layer 106 is patterned, and the hard mask layer 105 is etched based on the patterned photoresist layer 106, so as to obtain the patterned hard mask layer 107, as shown in FIG. Figure 4 Finally, the photoresist layer 106 is removed. In this embodiment, when the substrate 10 is a silicon substrate, the hard mask layer 105 is preferably an ONO stacked structure formed by a silicon dioxide layer-silicon nitride layer-silicon dioxide layer, with a thickness of like Figure 5 As shown, the emitter region 103 is then etched based on the patterned hard mask layer 107 to form the first trench 104. In this embodiment, the depth of the first trench 104 is selected to be 0.4 μm to 1.0 μm.

[0088] When the first groove 104 is formed in this step, Fig.12 and Fig.13 As shown, since the formation of the subsequent contact hole 117 is based on the self-aligned etching of two adjacent dielectric layers 116, and since the dielectric layer 116 is formed in the first groove 104, the distance between the two adjacent first grooves 104 determines the aperture of the subsequent conductive contact hole. Therefore, in this step, the width of the first groove 104 and the distance between the two adjacent first grooves 104 need to be designed according to actual needs.

[0089] like Figure 7 As shown, step S3 is then performed to form a sidewall protection layer 110 on the sidewall of the first trench 104 .

[0090] As an example, the method of forming the sidewall protection layer 110 includes: Figure 6 As shown, firstly, a sidewall protection material layer 109 is deposited on the surface of the above-mentioned final structure, for example, a deposition process such as CVD can be used; Figure 7 As shown, the sidewall protection material layer 109 outside the sidewall of the first trench 104 is then removed by etching back, so that the remaining sidewall protection material layer 109 is formed into the sidewall protection layer 110, for example, a dry etching process can be used. In this embodiment, when forming the sidewall protection layer 110, the patterned hard mask layer 107 is not removed, so as Figure 7 The sidewall protection layer 110 is formed on the first groove 104 and also on the sidewall of the patterned hard mask layer 107, so that the patterned hard mask layer 107 and the sidewall protection layer 110 can be used as masks to continue etching the first groove 104 downward to form a subsequent second groove 111. In this embodiment, the material of the sidewall protection material layer 109 is preferably silicon nitride.

[0091] like Figure 8 and Fig. 9 As shown, step S4 is then performed to continue etching the emitter region 103 downwards to the substrate layer 100 based on the first trench 104 and the sidewall protection layer 110 to form a second trench 111 , and remove the sidewall protection layer 110 .

[0092] In this embodiment, since the second trench 111 is formed by etching while retaining the patterned hard mask layer 107 , the patterned hard mask layer 107 also needs to be removed in this step.

[0093] As an example, the method for removing the patterned hard mask layer 107 and the sidewall protection layer 110 can select a suitable removal process according to the specific materials, such as wet removal of silicon nitride material and dry etching removal of silicon oxide material.

[0094] like Fig.10 As shown, step S5 is then performed to sequentially form a gate insulating layer 114 and a gate conductive layer 115 on the surface of the second trench 111, thereby forming a trench gate 113 by the gate insulating layer 114 and the gate conductive layer 115; wherein the upper surface of the gate conductive layer 115 is not lower than the upper surface of the P-type body region 102, that is, the upper surface of the gate conductive layer 115 needs to be above the upper surface of the P-type body region 102.

[0095] In this embodiment, when the material of the substrate 10 is silicon, a thermal oxidation process (such as dry oxygen or wet oxygen) is selected to form the gate insulating layer 114 with a thickness of Then, a polysilicon material is deposited as a gate conductive layer material using a CVD process, and the deposited polysilicon material is etched back to obtain the gate conductive layer 115 of polysilicon material; in this embodiment, the distance between the upper surface of the gate conductive layer 115 and the upper surface of the second trench 111 is selected to be about 0.35μm to 0.45μm, so as to ensure that the thickness of the dielectric layer subsequently formed in the second trench 111 is sufficient to resist damage to the dielectric layer when etching to form a contact hole.

[0096] like Fig.11 As shown, step S6 is then performed to form a dielectric layer 116 in the second trench 111 to cover the surface of the gate conductive layer 115 and fill the second trench 111 .

[0097] In this embodiment, when the material of the substrate 10 is silicon, the material of the dielectric layer 116 preferably includes a silicate glass material (BPSG) doped with boron (B) and phosphorus (P). Other insulating materials having a high selective etching ratio with the emitter region 103 may also be selected, such as an IDL material, a BSG material, or a PSG material.

[0098] As a specific example, a dielectric layer material is first deposited by a CVD process until the second trench 111 is fully filled, and then the dielectric layer material is etched back to retain only the dielectric layer material filling the second trench 111 as the dielectric layer 116 .

[0099] like Fig.12 and Fig.13 As shown, step S7 is then performed to etch the emitter region 103 between two adjacent first trenches 104 through self-aligned etching until the body region 102 is exposed, thereby forming a contact hole 117 .

[0100] As an example, Fig.14 As shown, the angle θ between the contact hole 117 and the horizontal plane is 70° to 90°. When θ is 90°, that is, the contact hole 117 is a cylindrical hole, and the etching process of the contact hole 117 of this shape is easy to implement; when θ is in the range of 70° to 90°, excluding 90°, that is, the contact hole 117 is a prism hole, and the etching of the contact hole 117 of this shape requires inclined etching, which is more difficult, but can increase the area of ​​the emitter region 103 and increase the RBSOA (reverse bias voltage safe operating area) of the device. In practice, the angle θ between the contact hole 117 and the horizontal plane can be selected by combining these two considerations.

[0101] like Fig.15 and Fig.16 As shown, as an example, after forming the contact hole 117 and before subsequently filling the contact hole 117, the step of performing ohmic contact P-type ion implantation on the surface of the body region 102 exposed by the contact hole 117 to form a P-type ohmic contact layer 124 is also included. The ohmic contact layer 124 can achieve ohmic contact with the conductive material subsequently formed in the contact hole 117, thereby reducing contact resistance.

[0102] Depending on the angle θ between the contact hole 117 and the horizontal plane, the method of ion implantation to form the ohmic contact layer 124 is different. Specifically: the first method, when the angle θ between the contact hole 117 and the horizontal plane is close to vertical, for example, when θ is about 85° to 90°, the ion implantation will basically not affect the doping concentration of the emitter region 103, so the ion implantation can be directly performed to form the ohmic contact layer 124; the second method, when the angle θ between the contact hole 117 and the horizontal plane is small, for example, when θ is about 70° to 85°, since some doped ions will enter the emitter region 103 during ion implantation and affect the doping concentration of the emitter region 103, it is necessary to form a protective layer on the side wall of the contact hole 117 to avoid ion implantation damage before ion implantation, for example, a layer of about 1000 mm is formed by a deposition process. A thick silicon nitride protective material layer is formed, and the silicon nitride protective material layer outside the side wall of the contact hole 117 is removed by back etching, so that the silicon nitride protective material layer retained on the side wall of the contact hole 117 is formed as a silicon nitride protective layer. After the protective layer is formed, ions are implanted into the surface of the body region 102 exposed by the contact hole 117 based on the protective layer to form the ohmic contact layer 124, and finally the protective layer on the side wall of the contact hole 117 is removed.

[0103] like Figures 17 to 20 As shown, then proceed to step S8, as Fig.17 and Fig.18 As shown, the contact hole 117 is filled with a conductive material 118. Fig.19 and Fig. 20 As shown, an emitter metal layer 120 is then formed.

[0104] As an example, the conductive material 118 may be a single-layer conductive material layer or a laminated structure of multiple conductive material layers. For example, the conductive material 118 may be a laminated structure of a titanium layer-titanium nitride layer-tungsten layer from bottom to top, with the titanium layer serving as an adhesion layer, the titanium nitride layer serving as a barrier layer, and the tungsten layer serving as a conductive layer. The material of the emitter metal layer is preferably aluminum copper or aluminum silicon copper.

[0105] like Fig.21 and Fig. 22 As shown, step S9 is finally performed to form a buffer layer 121 , a P-type collector region 122 and a collector metal layer 123 on the lower surface of the substrate layer 100 .

[0106] As an example, before performing step S9, the lower surface of the substrate layer 100 may be thinned to a preset thickness according to actual needs, which specifically depends on the withstand voltage requirement of the IGBT device.

[0107] In this embodiment, the process of forming the buffer layer 121 and the collector region 122 includes: firstly, implanting P-type ions, such as boron ions, into the lower surface of the substrate layer 100, with an ion implantation energy of 20KeV to 60KeV and an ion implantation dose of 1e12 cm -2 ~1e14 cm -2 , and use laser annealing equipment to propel the injected P-type ions to form the collector region 122; then hydrogen ions are implanted into the lower surface of the substrate layer 100 and annealed to form the buffer layer 121.

[0108] As an example, the collector metal layer 123 may be a single conductive material layer or a stacked structure of multiple conductive material layers. For example, the collector metal layer 123 may be a stacked structure of aluminum layer-titanium layer-nickel layer-silver layer from top to bottom.

[0109] Embodiment 2

[0110] The present embodiment provides an IGBT device based on a trench gate. The IGBT device can be prepared by the preparation method described in the first embodiment, but is not limited thereto. Other feasible preparation methods are also acceptable. As long as the IGBT device can be obtained, it is included in the scope of the present embodiment.

[0111] like Fig.21 and Fig. 22As shown, the IGBT device includes, from bottom to top, a collector metal layer 123, a P-type collector region 122, a buffer layer 121, an N-type substrate layer 100, an N-type carrier storage layer 101, a P-type body region 102, an N-type emitter region 103 and an emitter metal layer 120;

[0112] It also includes: more than two trench gates 113, conductive contact holes and a dielectric layer 116; wherein,

[0113] The trench gate 113 includes a second trench 111 (such as Fig. 9 As shown), a gate insulating layer 114 and a gate conductive layer 115, the second trench 111 extends from the surface of the emitter region 103 to the substrate layer 100, and the second trench 111 is divided into a first trench 104 and a bottom trench 112 from top to bottom, the depth of the first trench 104 is less than the thickness of the emitter region 103, and the diameter of the first trench 104 is greater than the diameter of the bottom trench 112, the gate insulating layer 114 is formed on the surface of the second trench 111, the gate conductive layer 115 is filled in the second trench 111 on the gate insulating layer 114, and the upper surface of the gate conductive layer 115 is not lower than the upper surface of the P-type body region 102;

[0114] The dielectric layer 116 is formed in the second trench 111 to cover the surface of the gate conductive layer 115 and fill the second trench 111;

[0115] The conductive contact holes include contact holes 117 (such as Fig.15 and Fig.16 As shown) and the conductive material 118 filling the contact hole 117, and the conductive contact hole extends from the emitter region 103 between two adjacent first trenches 111 to expose the body region 102.

[0116] In the trench gate-based IGBT device of this embodiment, the area between the dielectric layer 116 on two adjacent trench gates 113 is entirely set as a conductive contact hole, which effectively ensures the consistency of the distance between the trench gate 113 and the conductive contact hole, thereby greatly reducing or even avoiding the discreteness of the saturation voltage drop Vcesat value between each repeating unit in the IGBT device, and at the same time, the saturation voltage drop Vcesat value will not increase.

[0117] like Fig.14 As shown, as an example, the angle between the contact hole 117 and the horizontal plane is 70° to 90°.

[0118] like Fig.21 and Fig. 22As shown, a P-type ohmic contact layer 124 is also formed at the bottom of the conductive contact hole. The ohmic contact layer 124 can achieve ohmic contact with the conductive contact hole to reduce contact resistance.

[0119] As an example, the semiconductor material used in the trench gate based IGBT device in this embodiment can be any semiconductor material suitable for preparing IGBT devices, such as silicon, germanium, silicon carbide, gallium arsenide or gallium nitride, etc. In this embodiment, silicon material is selected.

[0120] In summary, the present invention provides an IGBT device based on a trench gate and a preparation method thereof, wherein a first trench with a relatively wide width is formed by two trench etchings, and a second trench with a wide upper portion and a narrow lower portion is formed by further etching downward on the basis of the first trench, and a trench gate is formed in the second trench, and the spacing area between the two adjacent first trenches is used as the formation area of ​​the subsequent conductive contact hole, so that the dielectric layer formed in the second trench can be self-aligned to form the contact hole of the conductive contact hole, avoiding the process of aligning the contact hole mask with the trench gate mask when forming the contact hole by a photolithography process, thereby avoiding the problem that the distance from the contact hole to the trench gate is insufficient due to the poor alignment accuracy of the contact hole mask and the trench gate mask, resulting in a large discreteness of the saturation voltage drop Vcesat value in the IGBT wafer and an increase in the saturation voltage drop Vcesat value. Since the contact hole is formed by a self-alignment method, the consistency of the distance between the subsequently formed conductive contact hole and the trench gate is high, so the discreteness of the saturation voltage drop Vcesat value in the IGBT wafer is greatly reduced or even avoided, and the saturation voltage drop Vcesat value will not increase. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0121] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an IGBT device based on a trench gate, characterized in that: The preparation method comprises: Providing a substrate, the substrate comprising, from bottom to top, an N-type substrate layer, an N-type carrier storage layer, a P-type body region, and an N-type emitter region; wherein the doping concentration of the carrier storage layer is greater than the doping concentration of the substrate layer, and the doping concentration of the emitter region is greater than the doping concentration of the carrier storage layer; Extending downward from the upper surface of the emitter region to form two or more first grooves of a preset depth; wherein the preset depth is less than the thickness of the emitter region; forming a sidewall protection layer on the sidewall of the first trench; Based on the first trench and the sidewall protection layer, the emitter region is continuously etched downwards until it reaches the substrate layer to form a second trench, and the sidewall protection layer is removed; A gate insulating layer and a gate conductive layer are sequentially formed on the surface of the second trench; wherein the upper surface of the gate conductive layer is not lower than the upper surface of the P-type body region; forming a dielectric layer in the second trench to cover the surface of the gate conductive layer and fill the second trench; By self-aligned etching, the emitter region between two adjacent first trenches is etched until the body region is exposed to form a contact hole; Filling the contact hole with a conductive material and then forming an emitter metal layer; A buffer layer, a P-type collector region and a collector metal layer are formed on the lower surface of the substrate layer.

2. The method for preparing a trench gate-based IGBT device according to claim 1, characterized in that: The carrier storage layer, the body region and the emitter region are formed by sequentially performing ion implantation on the upper surface of the substrate.

3. The method for preparing a trench gate-based IGBT device according to claim 1, characterized in that: The method of forming the first trench includes: Forming a hard mask layer on the surface of the emitter region and patterning the hard mask layer to form a patterned hard mask layer, wherein the patterned hard mask layer exposes the first trench region; The emitter region is etched based on the patterned hard mask layer to form the first trench.

4. The method for preparing a trench gate-based IGBT device according to claim 3, characterized in that: The method for forming the sidewall protection layer includes: Depositing a sidewall protection material layer on the surface of the obtained structure; The sidewall protection material layer other than the sidewall of the first trench is removed by etching back, so that the remaining sidewall protection material layer is formed into the sidewall protection layer.

5. The method for preparing a trench gate-based IGBT device according to claim 1, characterized in that: The substrate material is silicon material, and the gate insulating layer is formed by a thermal oxidation process.

6. The method for preparing a trench gate-based IGBT device according to claim 5, characterized in that: The material of the dielectric layer includes BPSG.

7. The method for preparing a trench gate-based IGBT device according to claim 1, characterized in that: The angle between the contact hole and the horizontal plane is 70° to 90°.

8. The method for preparing a trench gate-based IGBT device according to any one of claims 1 to 7, characterized in that: Before filling the contact hole with the conductive material, the method further includes: performing ohmic contact P-type ion implantation on the surface of the body region exposed in the contact hole to form a P-type ohmic contact layer.

9. The method for preparing a trench gate-based IGBT device according to claim 8, characterized in that: The angle between the contact hole and the horizontal plane is 70° to 85°. The method for forming the ohmic contact layer includes: forming a protective layer on the sidewall of the contact hole to prevent damage from ion implantation; Performing ion implantation on the surface of the body region exposed by the contact hole based on the protective layer to form the ohmic contact layer; The protective layer is removed.

10. An IGBT device based on a trench gate, characterized in that: The IGBT device includes, from bottom to top, a collector metal layer, a P-type collector region, a buffer layer, an N-type substrate layer, an N-type carrier storage layer, a P-type body region, an N-type emitter region and an emitter metal layer; It also includes: more than two trench gates, conductive contact holes and a dielectric layer; wherein, The trench gate comprises a second trench, a gate insulating layer and a gate conductive layer, the second trench extends from the surface of the emitter region to the substrate layer, and the second trench is divided into a first trench and a bottom trench from top to bottom, the depth of the first trench is less than the thickness of the emitter region, and the diameter of the first trench is greater than the diameter of the bottom trench, the gate insulating layer is formed on the surface of the second trench, the gate conductive layer is filled in the second trench on the gate insulating layer, and the upper surface of the gate conductive layer is not lower than the upper surface of the P-type body region; The dielectric layer is formed in the second trench, covers the surface of the gate conductive layer and fills the second trench completely; The conductive contact hole includes a contact hole and a conductive material filling the contact hole, and the conductive contact hole extends from the emitter region between two adjacent first trenches to expose the body region.

11. The trench gate based IGBT device according to claim 10, characterized in that: The angle between the contact hole and the horizontal plane is 70° to 90°.

12. The trench gate based IGBT device according to claim 10, characterized in that: A P-type ohmic contact layer is also formed at the bottom of the conductive contact hole.

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