A method for realizing self-alignment of a gate of an extremely short channel nanowall field effect transistor (NWaFET) device

Abstract

The application discloses a kind of extremely short channel nanowall (NWaFET) device gate self-alignment implementation method, it is related to microelectronic technology and integrated circuit (IC) field.The application discloses a kind of extremely short channel nanowall (NWaFET) device gate self-alignment implementation method, the method is stacked in vertical direction to MOS device, the structure can improve IC integration, save chip area, the vertical structure simultaneously adopts the mode of gate self-alignment, the gate region of the structure of the application is only wrapped channel region or channel area and the lightly doped drift region adjacent thereto, can greatly reduce the parasitic capacitance between gate and heavily doped region, so that the frequency characteristic of device is improved.Silicon nitride and silicon oxide are used as mask, gate self-alignment is realized, the error caused by photoetching frequency and multiple overlay is reduced, the integration of integrated circuit is improved, and the difficulty and cost of manufacturing process are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronics and integrated circuits BACKGROUND

[0002] In recent years, integrated circuit technology has developed rapidly, following Moore's law [1] Since its inception, the development of integrated circuits has always followed the principle of scaling down [2] . As the device size is reduced, the principle of scaling down begins to face serious challenges, because the heat effect caused by the increase of transistor drain current at very small size greatly reduces the performance of the device, resulting in a significant decrease in the gate control ability of the chip. Therefore, many researchers have begun to consider improving integrated circuits from other angles, so as to continue Moore's law.

[0003] FinFET, i.e. Fin Field Effect Transistor, was first proposed by Professor Chenming Hu of the University of California, Berkeley in 2000 [3] . The main feature of FinFET is that the channel region is a fin-shaped semiconductor wrapped by a gate, and the length of the fin along the source-drain direction is the channel length. Compared with the traditional planar CMOS, the half-ring gate fin structure of FinFET increases the control area of the gate to the channel, greatly enhancing the gate control ability, so as to effectively suppress the short channel effect and reduce the sub-threshold leakage current. TSMC began to mass-produce 7nm process nodes in 2018, and recently developed 5nm and 3nm processes.

[0004] Although FinFET has many advantages in CMOS technology, it will face a series of challenges after the 5nm node: for example, the gate distance and metal intercept are further reduced, the increase of sub-threshold slope means the increase of sub-threshold swing and the large gate-drain current, and the increase of fin height will lead to the increase of parasitic capacitance. For this reason, many companies have proposed a Gate-All-Around transistor structure [4] . Its gate and source-drain no longer maintain the appearance of fin, but a column structure vertically through the gate, so the gate can wrap the channel from four sides, continuing the idea of FinFET three-dimensional structure, so as to maximize the control of the gate to the channel area, better control the short channel and drain-induced barrier lowering (DIBL) effect, and achieve greater power consumption and area advantage. According to the data given by IEEE International Roadmap for Devices and Systems (IRDS), the gate length of 5nm FINFET is actually 18nm, and under subsequent process nodes, the channel length Lch is also very difficult

[0005] The Lch will be scaled down proportionally until 2028, when it will shrink to 9.6nm. After that, the Lch will no longer be able to shrink further.

[0006] Novel nanowall NWaFET structure prior to this invention [5-7] The NWaFET structure employs a vertical design, significantly improving device integration and suppressing the DIBL effect through a combination of heavily doped channel and lightly doped drift regions. By using heavily doped channel, the NWaFET structure further reduces the channel length (Lch). It boasts a shorter channel length (Lch) and higher integration density compared to existing FINFET, GAA, and VGAA technologies.

[0007] This paper proposes a method for achieving gate self-alignment in ultra-short channel nanowall FET (NWaFET) devices. This method stacks MOS devices vertically, which improves IC integration density and saves chip area. Furthermore, by employing gate self-alignment, the gate region of this structure only surrounds the channel region or the channel region and its adjacent lightly doped drift region, which greatly reduces the parasitic capacitance between the gate and the heavily doped source / drain regions, thereby improving the device's frequency characteristics.

[0008] References

[0009] [1].Moore, Gordon E. "Cramming more components onto integrated

[0010] Circuits. Electronics. Retrieved 2016-07-01. Manual 1 / 7 pages 6CN 116705796A6

[0011] [2]. Thompson S, Packan P, Bohr M. MOS scaling: transistor challenges for the 21st century. Intel Technology Journal, 1998; pp 1-18.

[0012] [3].Chenming Hu,Lee WC,Kedzierski J,et al.FinFET-a self-aligneddouble-gate MOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices,2000,47(12):2320-2325.

[0013] [4]. J. P. Colinge, M. H. Gao, A. Romano, H. Maes, C. Claeys. Silicon-on- insulator "gate-all-around" MOS device [C]. 1990 IEEE SOS / SOI Technology Conference. Proceedings. Key West, FL, USA: IEEE, 1990: 137-138.

[0014] [5]. Liao Yongbo, Li Ping, Tang Ruifeng, et al. A new type of digital gate integrated circuit structure [P]. China, invention patent, application number: CN111048579.1.2020.

[0015] [6]. Li Ping, Tang Ruifeng, Liao Yongbo, et al. A new type of DRAM structure and implementation method [P]. China, invention patent, application number: CN202110252584.1.2021.

[0016] [7]. Liao Yongbo, Liu Jinming, Li Ping, et al. A high integration nanowall integrated circuit structure [P]. China, invention patent, application number: CN202210413345.4.2022. SUMMARY

[0017] The technical problem to be solved by the present application is to provide a very short channel nanowall (NWaFET) device gate self-alignment implementation method, which is manufactured by a special gate self-alignment process, and realizes the improvement of the frequency characteristics of the vertical channel MOS basic unit structure and the significant improvement of the integration density of large-scale integrated circuits.

[0018] The technical scheme 1 of the present application is a very short channel nanowall (NWaFET) device gate self-alignment implementation method, which comprises the following steps: Figure 1As shown, the lowermost of the structure is a P-well silicon single crystal semiconductor region 101, on the upper portion of which is formed a silicon single crystal N+ drain region 102 of an NMOS device; above the N+ drain region 102 is an N- silicon single crystal drain region 103; above the N- drain region 103 is a P-type channel semiconductor region 104; above the p-type channel semiconductor region 104 is an N+ silicon single crystal semiconductor source region 105; the N+ drain region 102 includes an upper portion and a lower portion, the lower portion being wider than the upper portion, the lower surface and side surface of the lower portion being surrounded by the P-well region 101, a trench is provided on the side surface of the N- drain region 103, the P-type channel semiconductor region 104, and the N+ source region 105 of the NMOS, the lower surface of the trench being lower than or flush with the interface of the N+ region 102 and the N- drain region 103 of the NMOS; the trench is filled with a gate electrode 108 and an insulating medium 110; the lower surface of the gate electrode 108 is lower than or flush with the interface of the P-type channel region 104 and the N- drain region 103 of the NMOS, the upper surface of the gate electrode 108 is higher than or flush with the interface of the P-type channel region 104 and the N+ source region 105 of the NMOS. The gate electrode 108 is composed of heavily doped polysilicon. The insulating gate medium 110 is used to isolate the gate electrode 108 and other semiconductor regions. The NMOS drain electrode 109 is provided on the side surface of the N- drain region 103, the P-type channel region 104, and the N+ source region 105 of the NMOS. The NMOS metal gate electrode 107 is provided above the polysilicon gate region 108, on the side surface of the P-type channel region 104 and the N+ source region 105 of the NMOS. The insulating material 106 isolates the NMOS drain electrode 109 from the N- drain region 103, the P-type channel semiconductor region 104, and the N+ source region 105 of the NMOS.

[0019] The technical solution 2 of the present application is a method for realizing self-alignment of a gate of an extremely short channel nanowall (NWaFET) device, as shown in Figure 2As shown, at the bottom of the structure is an N-well silicon single crystal semiconductor region 111, on top of which is formed a silicon single crystal N+ drain region 112 of a PMOS device; above the P+ drain region 112 is a P- silicon single crystal drain region 113; above the P- drain region 113 is an N-type channel semiconductor region 114; above the N-type channel semiconductor region 114 is a P+ silicon single crystal semiconductor source region 115; the P+ drain region 112 includes an upper portion and a lower portion, the lower portion being wider than the upper portion, the lower surface and side surface of the lower portion being surrounded by the N-well region 111, a trench is provided on the side surface of the P- drain region 113, the N-type channel semiconductor region 114, and the N+ source region 115 of the PMOS, the lower surface of the trench being lower than or level with the interface of the P+ region 112 and the P- drain region 113 of the PMOS; the trench is filled with a gate electrode 118 and an insulating medium 120; the lower surface of the gate electrode 118 is lower than or level with the interface of the N channel region 114 and the P- drain region 113 of the PMOS, and the upper surface of the gate electrode 118 is higher than or level with the interface of the N channel region 114 and the P+ source region 115 of the PMOS. The gate electrode 118 is composed of heavily doped polysilicon. The insulating gate medium 120 is used to isolate the gate electrode 118 from other semiconductor regions. The PMOS metal gate electrode 117 is provided above the polysilicon gate region 118 of the PMOS, on the side surface of the N channel region 114 and the P+ source region 115. The PMOS drain electrode 119 is provided on the side surface of the P- drain region 113, the N-type channel semiconductor region 114, and the P+ source region 115 of the PMOS. The insulating material 116 isolates the PMOS drain electrode 119 from the P- drain region 113, the N-type channel semiconductor region 114, and the N+ source region 115 of the PMOS.

[0020] Further, the thickness of the P-type channel (104) is less than 10 nm.

[0021] Further, the doping concentration of the P-type channel semiconductor region (104) is more than two orders of magnitude higher than that of the N-drain region (103).

[0022] Further, the thickness of the N-type channel (114) is less than 10 nm.

[0023] Further, the doping concentration of the N-type channel semiconductor region (114) is more than two orders of magnitude higher than that of the P-drain region (113).

[0024] Further, all layer thicknesses are in the range of 1 nm - 100 nm, and the doping concentration is in the range of 1e14 cm -3 - 1e20 cm -3 .

[0025] The application provides a gate self-alignment implementation method of an extremely short channel nanowall (NWaFET) device, which adopts a gate self-alignment mode, so that a gate region of a longitudinal MOS structure device only wraps a channel region or the channel region and a lightly doped drift region adjacent to the channel region, thereby greatly reducing parasitic capacitance between the gate and a heavily doped source-drain region and improving frequency characteristics of the device. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A perspective view of an NMOS structure (from top to bottom: source region, channel region, lightly doped drain region and drain region) unit of the application adopting a gate self-alignment implementation method of an extremely short channel nanowall (NWaFET) device.

[0027] Figure 2 A perspective view of a PMOS structure (from top to bottom: source region, channel region, lightly doped drain region and drain region) unit of the application adopting a gate self-alignment implementation method of an extremely short channel nanowall (NWaFET) device.

[0028] Figure 3 A top view of an NMOS structure unit of the application adopting a gate self-alignment implementation method of an extremely short channel nanowall (NWaFET) device.

[0029] Figure 4 A top view of a PMOS structure unit of the application adopting a gate self-alignment implementation method of an extremely short channel nanowall (NWaFET) device.

[0030] Figure 5 、 Figure 6 A process flow of the application, which realizes the structure described in technical solution 1 and technical solution 2. DETAILED DESCRIPTION

[0031] Embodiment 1: In order to clearly understand the application, the embodiment specifically introduces a process flow for realizing the structure described in technical solution 1.

[0032] The first step, as shown in (a), is to form a P-type substrate. Figure 5

[0033] The second step, as shown in (b), is to deposit a layer of silicon dioxide and a layer of silicon nitride with a relatively small thickness on the P-type substrate. Figure 5

[0034] The third step, as shown in (c), is to form a gate electrode on the silicon nitride layer. Figure 5 ​​(c) As shown, etching silicon nitride and silicon dioxide, and epitaxially growing a layer of N+ type semiconductor region and a layer of N- type semiconductor region, and performing chemical mechanical polishing (CMP) to make the upper surface of the silicon nitride level with the upper surface of the N- type semiconductor region;

[0035] Fourth step, as shown in Figure 5 (d) As shown, epitaxially growing a layer of P type semiconductor region, and the silicon nitride above the gate region will not grow P type semiconductor, forming an extremely short channel P type semiconductor region;

[0036] Fifth step, as shown in Figure 5 (e) As shown, chemically etching silicon nitride;

[0037] Sixth step, as shown in Figure 5 (f) As shown, growing a layer of thin silicon dioxide SiO2 by low temperature thermal oxidation to form a gate oxide layer;

[0038] Seventh step, as shown in Figure 5 (g) As shown, depositing polysilicon to make the upper surface of the polysilicon higher than the upper surface of the silicon dioxide above the P type semiconductor region, and then performing chemical mechanical polishing (CMP) to make the upper surface of the polysilicon level with the upper surface of the silicon dioxide above the P type semiconductor region;

[0039] Eighth step, as shown in Figure 5 (h) As shown, performing oxidation again, because of the blocking effect of the silicon dioxide, the growth rate of the silicon dioxide above the polysilicon is greater than that of the silicon dioxide above the P type semiconductor region, and the thickness of the silicon dioxide above the polysilicon is greater than that of the silicon dioxide above the P type semiconductor channel region;

[0040] Ninth step, as shown in Figure 5 (i) As shown, etching SiO2 by reactive ion etching while performing end point detection, and stopping the reactive ion etching when the SiO2 above the P type semiconductor region disappears while a certain thickness of silicon dioxide still exists above the polysilicon;

[0041] Tenth step, as shown in Figure 5 (j) As shown, epitaxially growing a layer of relatively thin N+ type semiconductor region source region, and the silicon dioxide above the polysilicon will not grow semiconductor silicon;

[0042] Eleventh step, as shown in Figure 5 (k) As shown, depositing silicon dioxide, and then performing chemical mechanical polishing (CMP) to make the upper surface of the silicon dioxide level with the upper surface of the P type semiconductor region;

[0043] Twelfth step, as shown in Figure 5 (l) As shown, etching a groove, filling insulating material, opening a hole in the insulating material, and filling a metal lead electrode.

[0044] Example 2: To clearly understand the gate self-alignment implementation method of the ultra-short channel nanowall (NWaFET) device of the present invention, this example specifically introduces the process flow for implementing the structure described in technical solution 2.

[0045] First step, such as Figure 6 (a) shows an N-shaped sinker;

[0046] The second step, as Figure 6 As shown in (b), a layer of silicon dioxide and a thin layer of silicon nitride are deposited on an N-type substrate;

[0047] The third step, as Figure 6 As shown in (c), silicon nitride and silicon dioxide are etched, and a P+ type semiconductor region and a P- type semiconductor region are epitaxially grown. The silicon nitride is planarized by chemical mechanical polishing (CMP) so that the upper surface of the silicon nitride is flush with the upper surface of the P- type semiconductor region.

[0048] Step four, as Figure 6 As shown in (d), an N-type semiconductor region is epitaxially grown, and no N-type semiconductor is grown over the silicon nitride in the gate region;

[0049] Step 5, as Figure 6 As shown in (e), silicon nitride is chemically etched;

[0050] Step 6, as follows Figure 6 As shown in (f), a thin layer of silicon oxide (SiO2) is grown by low-temperature thermal oxidation.

[0051] Step 7, as Figure 6 As shown in (g), polysilicon is deposited until the upper surface of the polysilicon is higher than the upper surface of the silicon oxide above the N-type semiconductor region, and then planarized by chemical mechanical polishing (CMP) until the upper surface of the polysilicon is flush with the upper surface of the silicon oxide above the N-type semiconductor region.

[0052] Step 8, as Figure 6 As shown in (h), oxidation is performed again. Because of the blocking effect of silicon oxide, the growth rate of silicon oxide above polysilicon is greater than that of silicon oxide above N-type semiconductor region, and the thickness of silicon oxide above polysilicon is greater than that of silicon oxide above N-type semiconductor channel region.

[0053] Step 9, as Figure 6 As shown in (i), SiO2 is etched by reactive ion etching while endpoint detection is performed. Reactive ion etching is stopped when SiO2 above the N-type semiconductor region disappears and there is still a certain thickness of silicon oxide above the polysilicon.

[0054] Step 10, as follows Figure 6 As shown in (j), a P+ type semiconductor region is epitaxially grown, and no growth occurs on top of the polysilicon.

[0055] Eleventh step, as shown in Figure 6 (k), depositing silicon oxide, and then planarizing by chemical mechanical polishing (CMP) ;

[0056] Twelfth step, as shown in ​ (l), etching grooves, filling insulator, opening holes in the insulator, and filling metal lead electrodes.

Claims

1. A method for gate self-alignment implementation of an extremely short channel nanowall (NWaFET) device, characterized by, At the bottom of the structure is a P-well silicon single crystal semiconductor region (101), on the upper part of which is formed a silicon single crystal N+ drain region (102) of an NMOS device; above the N+ drain region (102) is a silicon single crystal N- drain region (103); above the N- drain region (103) is a P-type channel semiconductor region (104); above the P-type channel semiconductor region (104) is a silicon single crystal semiconductor N+ source region (105); the N+ drain region (102) comprises an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by the P-well silicon single crystal semiconductor region (101), and a trench is arranged on the side surface of the N- drain region (103), the P-type channel semiconductor region (104), and the N+ source region (105) of the above-mentioned NMOS, the lower surface of the trench is lower than or level with the interface between the N+ drain region (102) and the N- drain region (103) of the NMOS; the trench is filled with a gate electrode (108) and an insulating medium (110); the lower surface of the gate electrode (108) is lower than or level with the interface between the P-type channel semiconductor region (104) and the N- drain region (103) of the NMOS, and the upper surface of the gate electrode (108) is higher than or level with the interface between the P-type channel semiconductor region (104) and the N+ source region (105) of the NMOS; the gate electrode (108) is composed of heavily doped polysilicon; the insulating medium (110) is used to isolate the gate electrode (108) and other semiconductor regions; an NMOS drain electrode (109) is arranged on the side surface of the N- drain region (103), the P-type channel semiconductor region (104), and the N+ source region (105) of the NMOS; an NMOS metal gate electrode (107) is arranged above the polysilicon gate electrode (108) of the NMOS, on the side surface of the P-type channel semiconductor region (104) and the N+ source region (105); an insulating material (106) is used to isolate the NMOS drain electrode (109) from the N- drain region (103), the P-type channel semiconductor region (104), and the N+ source region (105) of the NMOS.

2. A method for gate self-alignment of an extremely short channel nanowall (NWaFET) device, comprising: The structure is the lowest N-well silicon single crystal semiconductor region (111), the upper part of the N-well silicon single crystal semiconductor region (111) is the silicon single crystal P+ drain region (112) of the PMOS device; the upper part of the P+ drain region (112) is the silicon single crystal P- drain region (113); the upper part of the P- drain region (113) is the N-type channel semiconductor region (114); the upper part of the N-type channel semiconductor region (114) is the silicon single crystal semiconductor P+ source region (115); the P+ drain region (112) includes an upper part and a lower part, the lower part is wider than the upper part, the lower surface and the side surface of the lower part are surrounded by the N-well silicon single crystal semiconductor region (111), the side surface of the P- drain region (113), the N-type channel semiconductor region (114), and the P+ source region (115) of the PMOS is provided with a groove, the lower surface of the groove is lower than or level with the interface of the P+ drain region (112) and the P- drain region (113) of the PMOS; the groove is filled with a gate electrode (118) and an insulating medium (120); the lower surface of the gate electrode (118) is lower than or level with the interface of the N-type channel semiconductor region (114) and the P- drain region (113) of the PMOS, the upper surface of the gate electrode (118) is higher than or level with the interface of the N-type channel semiconductor region (114) and the P+ source region (115) of the PMOS; the gate electrode (118) is composed of heavily doped polysilicon; the insulating medium (120) is used to isolate the gate electrode (118) and other semiconductor regions; the PMOS metal gate electrode (117) is arranged above the polysilicon gate electrode (118) of the PMOS, the side surface of the N-type channel semiconductor region (114) and the P+ source region (115); the PMOS drain electrode (119) is arranged at the side surface of the P- drain region (113), the N-type channel semiconductor region (114), and the P+ source region (115) of the PMOS; the insulating material (116) isolates the PMOS drain electrode (119) from the P- drain region (113), the N-type channel semiconductor region (114), and the N+ source region (115) of the PMOS.

3. The method of any one of claims 1-2, wherein the method is performed by a nanowall field effect transistor (NWaFET) device. The thickness of the P-type channel semiconductor region (104) of the NMOS is less than 10 nm, and the thickness of the N-type channel semiconductor region (114) of the PMOS is less than 10 nm.

4. The method of any one of claims 1-3, wherein the gate electrode (108, 118) is polysilicon.

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