Semiconductor device

Abstract

To reduce parasitic capacitance in a semiconductor device including a transistor having an oxide semiconductor.SOLUTION: The transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide semiconductor film over the first gate insulating film, a source electrode electrically connected to the oxide semiconductor film, and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film has a higher atomic proportion of In than that of M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf), and the second oxide semiconductor film has a lower atomic proportion of In than the first oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Regarding the device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. Process, Machine, Manufacture, or Composition of Matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and their driving methods.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials, such as silicon, are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] To provide a highly reliable oxide semiconductor transistor with stable electrical characteristics. To obtain the device, oxide semiconductor films with different compositions are stacked, and the channel side is doped with more In. An oxide semiconductor film containing a large amount of stabilizers such as Ga is used on the back channel side. A semiconductor device using a compound semiconductor film has been disclosed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-175715 Summary of the Invention [Problem to be solved by the invention]

[0007] A transistor using an oxide semiconductor film as an active layer is A transistor with a structure in which the gate electrode and drain electrode partially overlap each other (referred to as "Lov" in this specification) On the other hand, the gate electrode and source electrode Or a transistor in which the gate electrode and the drain electrode do not overlap (referred to as "Loff" in this specification). In the case of a gate electrode and a source electrode of an oxide semiconductor film, It is difficult to reduce the electrical resistance in the area where the gate electrode and drain electrode do not overlap. This may result in a decrease in the field effect mobility of the transistor.

[0008] However, when Lov-type transistors are used as pixel transistors in LCD displays, , parasitic capacitances occur between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. The presence of parasitic capacitance increases the time constant during operation, which reduces the rise time of the pulse voltage. As a result, the time required for the display unit to be driven becomes longer. It is difficult to ensure that the voltage applied to the liquid crystal element and the capacitance element reaches the required value within the time limit. As the panel size of display devices such as LCDs and OLED displays increases, As the resolution of the display screen with pixels increases, the above problem becomes more pronounced. Therefore, in the case of Lov type transistors with large parasitic capacitance, the screen is high definition and large. This makes it difficult to create panels with large display screen sizes.

[0009] In addition, there are variations in transistor characteristics and deterioration of organic EL elements in the pixels of organic EL displays. It is effective to provide a circuit to correct the parasitic capacitance, but if the parasitic capacitance is large, it is difficult to design a correction circuit. The calculation becomes complicated.

[0010] In view of the above problem, one aspect of the present invention provides a semiconductor device with low parasitic capacitance. In one embodiment of the present invention, a display device with a large panel size and high resolution is provided. Another object of the present invention is to provide a display device. Another object of the present invention is to provide a display device with high image quality. Another object of the present invention is to provide a novel semiconductor device. In this regard, one of the objectives is to provide a novel display device.

[0011] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above can be solved by the specification. It is clear from the description of the specification, etc. that the problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor. a gate electrode, a first gate insulating film on the first gate electrode, and an oxide film on the first gate insulating film. a source electrode electrically connected to the oxide semiconductor film; and a drain electrode electrically connected to the gate electrode.

[0013] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atoms The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0014] The oxide semiconductor film has a first region overlapping with the first gate electrode, a second region overlapping with the source electrode, and a third region overlapping with the source electrode. The first region has a second region and a third region overlapping the drain electrode. The first region and the third region are not included.

[0015] Another embodiment of the present invention is a semiconductor device including a transistor. a first gate electrode, a first gate insulating film on the first gate electrode, and a second gate insulating film on the first gate electrode; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; and a second gate electrode on the second gate insulating film.

[0016] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the second gate electrode. a fourth region overlapping the source electrode, a second region overlapping the drain electrode, and a third region overlapping the drain electrode. The first region does not include the second region and the third region. does not include the second region and the third region.

[0017] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atoms The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0018] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the second gate electrode. a fourth region overlapping the source electrode, a second region overlapping the drain electrode, and a third region overlapping the drain electrode. In addition, the first region or the fourth region does not include the second region or the third region.

[0019] Another embodiment of the present invention is a semiconductor device including a transistor. a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the first gate insulating film on the oxide semiconductor film; and a first gate electrode on the gate insulating film.

[0020] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atoms The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0021] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the source electrode. The first region is a second region, and the third region overlaps with the drain electrode. and does not include the third region.

[0022] Another embodiment of the present invention is a semiconductor device including a transistor. a first gate electrode, a first gate insulating film on the first gate electrode, and a second gate insulating film on the first gate electrode; a source electrode electrically connected to the oxide semiconductor film; and a drain electrode electrically connected to the film.

[0023] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atoms The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0024] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the source electrode. The first region is a second region, and the third region overlaps with the drain electrode. Or does not include the third region.

[0025] Another embodiment of the present invention is a semiconductor device including a transistor. a first gate electrode, a first gate insulating film on the first gate electrode, and a second gate insulating film on the first gate electrode; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; and a second gate electrode on the second gate insulating film.

[0026] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atoms The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0027] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the second gate electrode. The gate electrode has a fourth region, a second region overlapping with the source electrode, and a third region overlapping with the drain electrode. Furthermore, the first region or the fourth region does not include the second region or the third region.

[0028] Another embodiment of the present invention is a semiconductor device including a transistor. a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the first gate insulating film on the oxide semiconductor film; and a first gate electrode on the gate insulating film.

[0029] The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor and a second oxide semiconductor film on the first oxide semiconductor film. M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) atoms The atomic ratio of In in the second oxide semiconductor film is larger than that in the first oxide semiconductor film. few.

[0030] The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region overlapping with the source electrode. The first region is a second region, and the third region overlaps with the drain electrode. Or does not include the third region.

[0031] In each of the above structures, the semiconductor device has a scanning line and a data line, and the first gate electrode is a scanning line. The source electrodes are electrically connected to the scan lines, and the source electrodes are electrically connected to the data lines. In the region where the gate insulating film is formed, an insulating film having a thickness larger than that of the first gate insulating film is formed between the scanning line and the data line. It is preferable to have a membrane.

[0032] In each of the above structures, the oxide semiconductor film contains In, M, and Zn. In each of the above structures, the oxide semiconductor film preferably has a crystal part. The crystal portion is a portion in which the c-axis of the crystal portion is parallel to the normal vector of the surface on which the oxide semiconductor film is formed. It is preferable that the

[0033] In each of the above structures, the first region has a higher proportion of crystal portions than the second region. In each of the above structures, the first region preferably has a thicker portion than the second region. It is preferable that the hydrogen concentration of the silicon dioxide particles is low.

[0034] Another embodiment of the present invention is a semiconductor device and a display element according to any one of the above structures. Another embodiment of the present invention is a display device including the display device and a touch sensor. Another embodiment of the present invention is a display module having any one of the above structures. a semiconductor device, the display device, or the display module according to one of the above; and an operation key or and a battery. [Effects of the Invention]

[0035] According to one embodiment of the present invention, a semiconductor device with low parasitic capacitance can be provided. According to one embodiment of the present invention, a display device with a large panel size and high resolution can be provided. According to one embodiment of the present invention, a display device with high display quality can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided.

[0036] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0037] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 3] 1A and 1B are a top view and a cross-sectional view illustrating an example of a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 5]1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 19] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 20] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 21] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 22] Electron diffraction pattern of CAAC-OS. [Figure 23] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 24] Schematic diagram illustrating the film formation model of CAAC-OS and nc-OS. [Figure 25]A diagram explaining InGaZnO4 crystals and pellets. [Figure 26] Schematic diagram illustrating a CAAC-OS film formation model. [Figure 27] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 28] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 29] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 30] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 31] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 32] 1A and 1B are a block diagram of a display unit, an equivalent circuit diagram of a pixel circuit provided in a pixel of the display unit, and a schematic diagram of the transmittance-voltage characteristics of polarized light transmitted through a liquid crystal element. [Figure 33] 3A and 3B are a timing chart and a schematic diagram illustrating the operation of a pixel circuit included in a pixel portion of a display device. [Figure 34] FIG. 2 is a diagram illustrating a display module. [Figure 35] 1A to 1C illustrate electronic devices. [Figure 36] 1A to 1C illustrate electronic devices. [Figure 37] 1A and 1B are top views illustrating a structure of a semiconductor device according to an embodiment. [Figure 38] FIG. 10 is a graph showing Id-Vg characteristics of a transistor according to an embodiment. [Figure 39] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 40] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 41] 10 shows an example of the configuration of an RF device tag according to an embodiment. [Figure 42] 1 shows an example of the configuration of a CPU according to an embodiment. [Figure 43] FIG. 2 is a circuit diagram of a memory element according to an embodiment. [Figure 44] FIG. 1 is a top view illustrating an apparatus according to one embodiment of the present invention. [Figure 45] FIG. 1 is a block diagram illustrating an apparatus according to one embodiment of the present invention. [Figure 46] 1 is a cross-sectional view of an apparatus according to one embodiment of the present invention. [Figure 47] 1 is a cross-sectional view of an apparatus according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0038] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the present invention in various ways without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0039] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0040] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The semiconductor device has a channel region therein, and a current flows through the drain, the channel region, and the source. In this specification and the like, the channel region is a region where a current mainly flows. The flow area.

[0041] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. Let's say.

[0042] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0043] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. A silicon nitride film is a film that contains more nitrogen than oxygen. This refers to a film with a high content of

[0044] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, the same The reference numerals are used commonly even among different drawings.

[0045] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0046] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably. For example, the "conductive layer" It may be possible to change the term to "conductive film". For example, it may be possible to change the term "insulating film" to the term "insulating layer." .

[0047] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention and a method for manufacturing the semiconductor device will be described. The method will be described with reference to Figures 1 to 7 and 10 to 18.

[0048] <Configuration Example 1 of Semiconductor Device> FIG. 1A shows a transistor which is a semiconductor device of one embodiment of the present invention. 1(B) is a top view of the rotor 100, and FIG. 1(B) is a diagram showing the rotor 100 between the dashed dotted line X1-X2 shown in FIG. 1(A). 1(C) corresponds to a cross-sectional view of the cutting surface between the dashed dotted line Y1-Y2 shown in FIG. 1(A). In FIG. 1(A), in order to avoid complication, Therefore, some of the components of the transistor 100 (such as an insulating film that functions as a gate insulating film) can be omitted. The dashed dotted line X1-X2 direction is the channel length direction, and the dashed dotted line Y1- The Y2 direction is sometimes called the channel width direction. In the subsequent drawings, as in FIG. 1(A), some of the components may be omitted. There is.

[0049] The transistor 100 includes a conductive film 104 over a substrate 102, which functions as a first gate electrode. an insulating film 106 on the substrate 102 and the conductive film 104; and an insulating film 107 on the insulating film 106. The oxide semiconductor film 108 on the insulating film 107 and the insulating film 108 electrically connected to the oxide semiconductor film 108 The conductive film 112a serving as a source electrode and the oxide semiconductor film 108 and a conductive film 112b which functions as a drain electrode connected to the gate electrode of the transistor 10. An insulating film is formed on the conductive films 112a and 112b and the oxide semiconductor film 108. 114, 116, and an insulating film 118 are provided. It functions as a protective insulating film for the transistor 100 .

[0050] A conductive film 104 functioning as a first gate electrode and a conductive film 112 functioning as a source electrode. a, a conductive film 104 functioning as a first gate electrode, and a conductive film 105 functioning as a drain electrode. The conductive films 112b are arranged so as not to overlap each other. A transistor in which the source electrode or gate electrode and drain electrode do not overlap each other is called a "Loff type" transistor. In this specification, when there are multiple gate electrodes, the source voltage If there is even one gate electrode that has an area that does not overlap with the electrode or drain electrode, A transistor having such a structure is referred to as a "Loff type transistor" or the like. means that all gate electrodes and source electrodes, and all gate electrodes and drain electrodes are mutually A structure having an overlapping region is referred to as a "Lov-type transistor" or the like.

[0051] The oxide semiconductor film 108 includes a first region overlapping with the conductive film 104 and a second region overlapping with the conductive film 112a. The first region includes a second region including the conductive film 112b, and a third region overlapping the conductive film 112b. In other words, the first region is arranged so as not to include the second region and the third region. The first region and the third region are disposed so as not to overlap.

[0052] The oxide semiconductor film 108 does not overlap with the conductive film 104, the conductive film 112a, and the conductive film 112b. The conductive film 104, the conductive film 112a, and the conductive film 112b do not overlap with each other. The area corresponds to area 122.

[0053] By forming a Loff type transistor, the first gate electrode, the source electrode, and the first The parasitic capacitance between the gate electrode and the drain electrode can be reduced. By using transistors in the display panel, the time constant can be reduced, It is possible to provide a display device with a large pixel size and high resolution. By using such transistors in LCD displays, feedthrough and other issues can be suppressed. Therefore, a display device with high display quality can be provided.

[0054] The oxide semiconductor film 108 is formed on the first gate electrode side of the conductive film 104. a first oxide semiconductor film 108a and a second oxide semiconductor film 108b on the first oxide semiconductor film 108a; The insulating film 106 and the insulating film 107 are formed in the transistor 100. It functions as the first gate insulating film.

[0055] The oxide semiconductor film 108 is an In-M (wherein M is Ti, Ga, Sn, Y, Zr, or La) , Ce, Nd, or Hf) oxide, In-M-Zn oxide can be used. In particular, it is preferable to use In-M-Zn oxide for the oxide semiconductor film 108.

[0056] The first oxide semiconductor film 108a has a first oxide semiconductor layer in which the atomic ratio of In is larger than the atomic ratio of M. The second oxide semiconductor film 108b has a region similar to that of the first oxide semiconductor film 108. The second region has a lower atomic ratio of In than the first region a. It has a thinner portion than

[0057] A first region in which the atomic ratio of In is larger than the atomic ratio of M is formed in the first oxide semiconductor film 108a. By having this, the field effect mobility (simply called mobility, or μFE) of the transistor 100 can be improved. (sometimes) can be increased.

[0058] The Loff type transistor has a first gate electrode and a source or a first gate electrode and a drain. The oxide semiconductor region where the gates do not overlap acts as a series resistor, so compared to Lov-type transistors, Therefore, the current (on-current) when the transistor is turned on tends to decrease. The atomic ratio of In in the first oxide semiconductor film 108a is made larger than the atomic ratio of M. an oxide semiconductor region where the first gate electrode and the source or the first gate electrode and the drain do not overlap; This reduces the resistance of the transistor, thereby suppressing the decrease in on-state current. Therefore, even Loff type transistors can be applied to various semiconductor devices and display devices. This makes it possible to:

[0059] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. driver (especially, the demux connected to the output terminal of the shift register of the gate driver) By using it in a semiconductor device or display device with a narrow frame width (also called a narrow frame), Locations can be provided.

[0060] On the other hand, a first oxide semiconductor having a first region in which the atomic ratio of In is greater than the atomic ratio of M is By using the solid film 108a, the electrical characteristics of the transistor 100 are less likely to change when irradiated with light. However, in the semiconductor device of one embodiment of the present invention, the first oxide semiconductor film 10 A second oxide semiconductor film 108b is formed on the second oxide semiconductor film 8a. The thickness of the first oxide semiconductor film 108b in the vicinity of the channel region is smaller than the thickness of the first oxide semiconductor film 108a. .

[0061] The second oxide semiconductor film 108b contains more In than the first oxide semiconductor film 108a. Since the second region having a smaller atomic ratio is included, Eg is smaller than that of the first oxide semiconductor film 108a. Therefore, the first oxide semiconductor film 108a and the second oxide semiconductor film 10 The oxide semiconductor film 108, which has a stacked structure with the oxide semiconductor film 8b, has a resistance to a negative bias stress test using light. becomes higher.

[0062] By using the oxide semiconductor film having the above structure, the oxide semiconductor film 108 can be effectively prevented from being damaged by light irradiation. Therefore, the amount of absorption of the transistor 100 when irradiated with light can be reduced. Fluctuations in electrical characteristics can be suppressed. Since the insulating film 114 or the insulating film 116 contains excess oxygen, the insulating film 114 or the insulating film 116 is not easily irradiated with light. This can further suppress fluctuations in the electrical characteristics of the transistor 100.

[0063] Here, the oxide semiconductor film 108 will be described in detail with reference to FIG.

[0064] FIG. 2 is an enlarged view of the oxide semiconductor film 108 and its vicinity in the transistor 100 shown in FIG. FIG.

[0065] In FIG. 2, the thickness of the first oxide semiconductor film 108a is t1, and the thickness of the second oxide semiconductor film 108b is t2. The thicknesses of the oxide film 108b are indicated as t2-1 and t2-2, respectively. Since the second oxide semiconductor film 108b is provided on the oxide semiconductor film 108a, When the films 112a and 112b are formed, the first oxide semiconductor film 108a is etched by the etching gas. Therefore, the first oxide semiconductor film 1 is not exposed to gas or etching solution. In the case of 08a, there is no or very little film loss. In the case of 108b, when the conductive films 112a and 112b are formed, the second oxide semiconductor The portions of the film 108b that do not overlap the conductive films 112a and 112b are etched to form recesses. That is, the second oxide semiconductor film 108b overlaps with the conductive films 112a and 112b. The thickness of the region is t2-1, and the conductive films 112a and 112b of the second oxide semiconductor film 108b are The thickness of the region that does not overlap with b is t2-2.

[0066] The relationship between the thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b is as follows: It is preferable that -1>t1>t2-2. By making such a film thickness relationship, high A transistor having high field-effect mobility and small fluctuation in threshold voltage when irradiated with light. It is possible to make it a digital camera.

[0067] Furthermore, when oxygen vacancies are formed in the oxide semiconductor film 108 of the transistor 100, This generates electrons as carriers, making it easy for the oxide semiconductor to have normally-on characteristics. By reducing oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a, This is also important for obtaining stable transistor characteristics. In the transistor configuration, an insulating film on the oxide semiconductor film 108, By introducing excess oxygen into the insulating film 114 and / or the insulating film 116 on the insulating film 108, Oxygen is transferred from the insulating film 114 and / or the insulating film 116 into the oxide semiconductor film 108, and the oxide To compensate for oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a. is characterized by.

[0068] In addition, as the insulating films 114 and 116, it is more preferable to have a region (oxygen-excess region) containing oxygen in excess of the stoichiometric composition. In other words, the insulating films 114 and 116 are insulating films capable of releasing oxygen. To provide an oxygen-excess region in the insulating films 114 and 116, for example, oxygen is introduced into the insulating films 114 and 116 after film formation to form an oxygen-excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used. region (oxygen-excess region). region, For example, oxygen is introduced into the insulating films 114 and 116 after film formation to form an oxygen-excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

[0069] In addition, in order to compensate for oxygen deficiencies in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2 - 2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, and more preferably 3 nm or more and 10 nm or less. In addition, in order to compensate for oxygen deficiencies in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2 - 2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, and more preferably 3 nm or more and 10 nm or less. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, and more preferably 3 nm or more and 10 nm or less.

[0070] Hereinafter, other components included in the semiconductor device of the present embodiment will be described in detail. Hereinafter, other components included in the semiconductor device of the present embodiment will be described in detail.

[0071] <Substrate> There are no major restrictions on the material of the substrate 102, etc., but it is necessary to have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can also be applied, and semiconductor elements are provided on these substrates. <Substrate> There are no major restrictions on the material of the substrate 102, etc., but it is necessary to have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can also be applied, and semiconductor elements are provided on these substrates. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can also be applied, and semiconductor elements are provided on these substrates. The substrate 102 may be a glass substrate. When used, 6th generation (1500mm x 1850mm), 7th generation (1870mm x 22 00mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 28 By using large area substrates such as 10th generation (2950mm x 3400mm) and 10th generation (2950mm x 3400mm), Therefore, a large display device can be manufactured.

[0072] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0073] <Conductive film functioning as first gate electrode, source electrode, and drain electrode> First gate The conductive film 104 functions as a ground electrode, the conductive film 112a functions as a source electrode, and The conductive film 112b functioning as the drain electrode may be made of chromium (Cr), copper (Cu), Aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), Tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), or the above-mentioned metal elements The alloys are formed using alloys containing the above-mentioned metal elements or alloys combining the above-mentioned metal elements. It is possible.

[0074] The conductive films 104, 112a, and 112b may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film on an aluminum film, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride film Two-layer structure with tungsten film laminated on top, tantalum nitride film or tungsten nitride film Two-layer structure with tungsten film stacked, titanium film, and aluminum film stacked on the titanium film. There are also three-layer structures, such as a titanium film on top of an aluminum film. Selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium Alternatively, an alloy film or a nitride film made by combining one or more of these may be used.

[0075] The conductive films 104, 112a, and 112b are made of indium tin oxide or tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, is used. It is also possible.

[0076] The conductive films 104, 112a, and 112b are made of a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied. This allows for processing using a wet etching process, which reduces manufacturing costs. It becomes possible.

[0077] <Insulating Film Functioning as First Gate Insulating Film> First gate insulating film of transistor 100 The insulating films 106 and 107 functioning as the insulating film are formed by plasma enhanced chemical vapor deposition (PECVD). Plasma Enhanced Chemical Vapor Depositio n)) method, sputtering method, etc., to form silicon oxide films, silicon oxynitride films, nitride oxide films, Silicon film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, an insulating layer containing one or more of a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film, It should be noted that the insulating films 106 and 107 may be formed of the above-mentioned materials without being stacked. A selected single layer insulating film or a three or more layer insulating film may be used.

[0078] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain excess acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0079] Note that the oxide semiconductor film 108, which functions as a channel region of the transistor 100, The insulating film 107 is preferably an oxide insulating film, and has an oxide content in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen-excess region). The insulating film 107 is an insulating film capable of releasing oxygen. To provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Oxygen may be introduced into the insulating film 107 later to form an oxygen-excess region. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Zuma processing or the like can be used.

[0080] Furthermore, when hafnium oxide is used as the insulating film 107, the following effects are achieved. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Since the thickness of the insulating film 107 can be made larger than when silicon oxide is used, the tunnel current In other words, a transistor with a small off-state current can be produced. Furthermore, hafnium oxide, which has a crystalline structure, can be used to form an amorphous structure. It has a higher dielectric constant than hafnium oxide, which has a low off-state current. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include a monoclinic system and a cubic system. are not limited to these.

[0081] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so The first gate insulating film of the transistor 100 includes a silicon nitride film, which makes the insulating film physically Therefore, the decrease in the dielectric strength of the transistor 100 can be suppressed, and In addition, the dielectric strength voltage can be improved, and electrostatic breakdown of the transistor 100 can be suppressed.

[0082] <Oxide Semiconductor Film> The oxide semiconductor film 108 can be formed using the materials shown above. When the oxide semiconductor film 108 is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose is In≧M, Zn≧M. It is preferable that the atomic ratio of the metal elements in such a sputtering target and In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1 are preferred. In addition, when the oxide semiconductor film 108 is an In-M-Zn oxide, the sputtering target It is preferable to use a target containing polycrystalline In-M-Zn oxide. By using a target containing crystalline In-M-Zn oxide, it is possible to obtain a crystalline oxide semiconductor. The conductor film 108 can be easily formed. The atomic ratio of the oxide semiconductor film 108 to be formed is The error is the atomic ratio of the metal elements contained in the sputtering target. Including a fluctuation of plus or minus 40%. For example, as a sputtering target, the number of atoms When the ratio of In:Ga:Zn=4:2:4.1 is used, the oxide semiconductor film 108 The atomic ratio of In:Ga:Zn may be approximately In:Ga:Zn=4:2:3.

[0083] For example, the first oxide semiconductor film 108a may be formed of the above-mentioned In:M:Zn=2:1:3 , In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, etc. The second oxide semiconductor film 108b may be formed using the above-described oxide semiconductor film. If the material is formed using In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, etc. Note that the metal element of the sputtering target used for the second oxide semiconductor film 108b is The atomic ratio of elements does not necessarily satisfy In≧M, Zn≧M, but In≧M, Zn <Mを A specific example is a composition where In:M:Zn=3:2:1.

[0084] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. eV or more, more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. In particular, the first oxide semiconductor film 108a preferably has an energy gap of 2 eV or more. The second oxide semiconductor film 108b is an oxide semiconductor film having a conductivity of 2 eV to 3.0 eV. When an oxide semiconductor film having an energy gap of 2.5 eV or more and 3.5 eV or less is used, In addition, the second oxide semiconductor film 108b is more preferable than the first oxide semiconductor film 108a. The larger the energy gap, the more preferable.

[0085] The thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are Each of these is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably Preferably, the thickness is 3 nm or more and 50 nm or less. .

[0086] The second oxide semiconductor film 108b is an oxide semiconductor film with low carrier density. For example, the second oxide semiconductor film 108b has a carrier density of 1×10 17 pcs / c m 3 Less than 1 × 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Less than 1×10, more preferably 11 pieces / cm 3 The following applies.

[0087] However, the semiconductor properties and electrical properties required (field effect mobility, etc.) are not limited to these. The appropriate atomic ratio can be used depending on the required transformer. In order to obtain semiconductor characteristics of a transistor, the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are The carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, and atomic It is preferable to set the distance between the elements, density, etc. appropriately.

[0088] Note that the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are formed of By using an oxide semiconductor film with a low impurity concentration and a low density of defect states, This is preferable because it allows the fabrication of a transistor with excellent electrical characteristics. The term "high purity intrinsic or substantially intrinsic" refers to a low concentration and a low defect level density (low oxygen vacancy). A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film is called a highly purified intrinsic oxide semiconductor film. Since there are fewer carrier sources, the carrier density can be reduced. The transistor in which the channel region is formed in the semiconductor film has an electrical characteristic in which the threshold voltage is negative. It is rare for the material to become normally on. A highly pure intrinsic oxide semiconductor film has a low density of defect states and therefore a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film may be formed by The off-state current is extremely small, and the channel width is 1×10 6 μm and channel length L is 10 μm Even if the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, In this range, the off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×1 0 -13 It can achieve a characteristic of A or below.

[0089] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small fluctuations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are lost. It takes a long time for the charge to dissipate, and it can behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has Impurities such as hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0090] The hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. The oxygen vacancies are formed in the lattice from which oxygen is desorbed (or in the portions from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can bond with oxygen, which bonds with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor film 108 obtained by SIMS analysis is degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than or equal to 5x1, more preferably 0 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 below Let's say.

[0091] The first oxide semiconductor film 108a has a higher hydrogen concentration than the second oxide semiconductor film 108b. It is preferable that the first oxide semiconductor film 108a has a portion where the degree of oxidation is low. By having a portion with a lower hydrogen concentration than the compound semiconductor film 108b, a highly reliable semiconductor It can be a body device.

[0092] In addition, the first oxide semiconductor film 108a contains silicon, which is one of the Group 14 elements, When carbon is contained, oxygen vacancies increase in the first oxide semiconductor film 108a, and the first oxide semiconductor film 108a becomes n-type. Therefore, the concentrations of silicon and carbon in the first oxide semiconductor film 108a and The concentrations of silicon and carbon near the interface with the first oxide semiconductor film 108a (as determined by SIMS analysis) The concentration obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0093] In addition, the alkali metal oxide film 108a obtained by SIMS analysis The concentration of metal or alkaline earth metal is 1×10 18 atoms / cm 3 The following is preferably is 2 x 10 16 atoms / cm 3 The alkali metals and alkaline earth metals are as follows: When bonded to an oxide semiconductor, carriers may be generated, increasing the off-state current of the transistor. Therefore, the alkali metal or It is preferable to reduce the concentration of alkaline earth metals.

[0094] When the first oxide semiconductor film 108a contains nitrogen, electrons serving as carriers This increases the carrier density and makes it easier to become n-type. A transistor using a conductor film tends to have normally-on characteristics. It is preferable that nitrogen is reduced as much as possible in the solid film. For example, SIMS analysis The nitrogen concentration obtained is 5×10 18 atoms / cm 3 It is preferable to do the following: .

[0095] The first oxide semiconductor film 108a and the second oxide semiconductor film 108b are The non-single crystal structure may be, for example, CAAC-OS (CAx is Aligned Crystalline Oxide Semiconductor or), polycrystalline structure, microcrystalline structure, or amorphous structure. The amorphous structure has the highest density of defect states, while the CAAC-OS has the lowest density of defect states.

[0096] <Insulating Film Functioning as a Protective Insulating Film for Transistor> The insulating films 114 and 116 are made of an oxide semiconductor. The insulating film 118 has a function of supplying oxygen to the conductive film 108. The insulating films 114 and 116 function as protective insulating films for the semiconductor device. The insulating film 114 is an insulating film that can transmit oxygen. is used to reduce damage to the oxide semiconductor film 108 when forming the insulating film 116 to be formed later. It also functions as a membrane.

[0097] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0098] Furthermore, it is preferable that the insulating film 114 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3 x 10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects is high, oxygen enters the defects, and the oxygen in the insulating film 114 The amount of transmission decreases.

[0099] In the insulating film 114, all the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, Oxygen may move in the film 114. When the oxide insulating film capable of forming the insulating film 114 is formed, the insulating film 116 and the insulating film 116 are formed on the insulating film 114. The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0100] The insulating film 114 is formed using an oxide insulating film with a low density of states due to nitrogen oxides. Note that the density of states due to the nitrogen oxide can be determined by the valence The energy at the top of the electron band (E v_os ) and the energy of the bottom of the conduction band of the oxide semiconductor film (E c_os) may be formed between the insulating film and the insulating layer. Silicon oxynitride film with low emission or aluminum oxynitride film with low nitrogen oxide emission For example, a silicon film or the like can be used.

[0101] In addition, a silicon oxynitride film that emits a small amount of nitrogen oxides can be analyzed by thermal desorption spectroscopy. This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of emission is 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher and 55°C or lower. The amount released by heating at 0°C or below.

[0102] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO or NO forms a level in the insulating film 114. The oxides of nitrogen are located within the energy gap of the insulating film 114 and the film 108. When the oxide semiconductor film 108 diffuses to the interface between the insulating film 114 and the oxide semiconductor film 108, the level As a result, the trapped electrons may be trapped in the insulating film 114 and the oxide semiconductor. Since it remains near the interface of the conductor film 108, the threshold voltage of the transistor is shifted in the positive direction. It makes them do it.

[0103] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with the ammonia contained in the insulating film 116 during the heat treatment. Therefore, the nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0104] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor can be reduced. It is possible to reduce the shift and the fluctuation of the electrical characteristics of the transistor. Cut.

[0105] Note that the heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less. The first signal has a g value of 2.037 or more and 2.039 or less, and the second signal has a g value of 2.001 or more. A second signal less than .003 and a third signal with a g value between 1.964 and 1.966. The split width of the first signal and the second signal, and the The split width of the second signal and the third signal is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 or more and 2.039 or less, and the g value is 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The total spin density of the third signal is 1×10 18 spins / cm 3 is less than A typical example is 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Less than be.

[0106] In addition, the g value is between 2.037 and 2.039 in the ESR spectrum below 100K. The first signal has a g value of 2.001 or more and 2.003 or less, and the second signal has a g value of 1 The third signal, between 0.964 and 1.966, is nitrogen oxide (NOx , x is greater than 0 These correspond to signals caused by nitrogen oxides (<2 or less, preferably 1 to 2). Examples include nitrogen monoxide and nitrogen dioxide. That is, the g value is between 2.037 and 2.039. a first signal having a g value of 2.001 or more and 2.003 or less, and a second signal having a g value of The smaller the total spin density of the third signal between 1.964 and 1.966, the more acid This means that the content of nitrogen oxides contained in the oxide insulating film is low.

[0107] The oxide insulating film has a nitrogen concentration of 6×10 as measured by SIMS. 20 atoms / cm 3 The following is the result.

[0108] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film using a VD method, a dense and hard film can be obtained. It can be formed.

[0109] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric value. The oxide insulating film had a desorption of 1.0 x 10 oxygen atoms in TDS analysis. 1 8 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 That's all The surface temperature of the film during the TDS analysis was 100°C or higher. The temperature range is preferably from 100°C to 500°C or from 100°C to 700°C.

[0110] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., of 400 nm or less can be used.

[0111] Furthermore, it is preferable that the insulating film 116 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating film 116 has a higher oxide semiconductor content than the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0112] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating films In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly identified. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a broken line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. However, the present invention is not limited to this, and the insulating film 114 may have a single-layer structure, for example.

[0113] The insulating film 118 contains nitrogen and silicon. The insulating film 118 also contains blockers such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. By providing the insulating film 118, the oxide semiconductor film 108 can be prevented from being oxidized. The diffusion of oxygen from the insulating films 114 and 116 to the outside. This can prevent hydrogen, water, and the like from entering the oxide semiconductor film 108. For example, a nitride insulating film can be used. Silicon nitride, silicon oxide nitride, aluminum nitride, aluminum oxide nitride, etc. Nitride insulating material with blocking effect against hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of the insulating film, an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc. may be provided. As an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc., aluminum oxide is preferable. aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, Examples include yttrium oxide nitride, hafnium oxide, and hafnium oxide nitride.

[0114] Note that the various films described above, such as the conductive film, insulating film, and oxide semiconductor film, are formed by sputtering. It can be formed by a coating method or a PECVD method, but other methods, such as thermal CVD ( It may be formed by thermal vapor deposition (CVD). As an example of the method, MOCVD (Metal Organic Chemical Vapor Deposition) Deposition (Atomic Layer Deposition) and ALD (Atomic Layer Deposition) n) method may also be used.

[0115] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0116] In the thermal CVD method, the source gas and oxidant are simultaneously fed into a chamber, and the chamber is heated to atmospheric pressure. Alternatively, a film can be formed by reacting the material near or on the substrate under reduced pressure and depositing the material on the substrate. You may go.

[0117] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating this gas introduction sequence. For example, by switching between two or more types of switching valves (also called high-speed valves), The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the fuel gas. In case of simultaneously introducing an inert gas, the inert gas is The second source gas may be introduced as a carrier gas, and an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation. The first source gas may be adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction order until a desired thickness is achieved. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. This is suitable for producing thin FETs.

[0118] Thermal CVD methods such as MOCVD and ALD can be used to form conductive films, insulating films, and oxides in the above-described embodiments. It can form various films such as semiconductor films and metal oxide films. For example, In-Ga-Zn When forming a -O film, trimethylindium, trimethylgallium, and dimethyl Zinc is used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The formula is Zn(CH3)2. In addition, it is not limited to these combinations, and trimethyl gas Triethylgallium (chemical formula Ga(C2H5)3) can also be used instead of gallium. Diethylzinc (chemical formula Zn(C2H5)2) can also be used instead of dimethylzinc. .

[0119] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is vaporized hafnium amide (such as TDMAH) and acid Two types of gases are used: tetrakisdimethylamide (TDMA) and ozone (O3) as a chlorine gas. The chemical formula for Hf is Hf[N(CH3)2]4. Other materials include tetrahydrofuran, Examples include rakis(ethylmethylamido) hafnium.

[0120] For example, when forming an aluminum oxide film using an ALD film forming device, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0121] For example, when forming a silicon oxide film using a film forming device that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, removing the chlorine contained in the adsorbed material, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0122] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by sequentially introducing BH gas and BH gas. The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. SiH4 gas may be used instead of gas.

[0123] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a Ga After that, Zn(CH3)2 gas and O3 gas were introduced repeatedly to form an O layer. The order of these layers is not limited to this example. Mixed compound layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O layers are formed. It is also possible to use H2 obtained by bubbling an inert gas such as Ar instead of O3 gas. Although O gas may be used, it is preferable to use O gas that does not contain H. Instead of Ga(CH3)3 gas, In(C2H5)3 gas may be used. Instead of the Zn(CH3)2 gas, Ga(C2H5)3 gas may be used. may also be used.

[0124] Another example of the transistor having the above structure is shown in FIG. 39. This structure is similar to the transistor shown in FIG. 39(A-1). It may also have a structure with a top view like that of the transistor 153. 9(A-1) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2-X3.

[0125] In addition, the transistor 100 shown in FIG. 1 has a structure in which the oxide semiconductor film 108b is thinned. However, there is no or very little film loss as in the transistor 154 shown in FIG. 39(B). Also, as shown in FIG. 39(C), a transistor 155 may be used. The structure may have a protective layer 125 .

[0126] <Configuration Example 2 of Semiconductor Device> Next, a semiconductor device different from the transistor 100 shown in FIGS. An example of such a configuration will be described with reference to Figs. 3(A), (B), and (C). If the function is the same as that of the other item, the hatch pattern shall be the same and no special code shall be attached. There is.

[0127] FIG. 3A is a top view of a transistor 170 which is a semiconductor device of one embodiment of the present invention. 3(B) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 3(A). 3(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 3(A). Correct.

[0128] The transistor 170 includes a conductive film 104 over a substrate 102, which functions as a first gate electrode. an insulating film 106 on the substrate 102 and the conductive film 104; and an insulating film 107 on the insulating film 106. the oxide semiconductor film 108 on the insulating film 107; and the insulating film 114 on the oxide semiconductor film 108. and an insulating film 116 on the insulating film 114 and a source electrically connected to the oxide semiconductor film 108. The conductive film 112a serving as a gate electrode and the gate electrode electrically connected to the oxide semiconductor film 108 are The conductive film 112b functions as a drain electrode, and the conductive film 112a, the conductive film 112b, and the acid The insulating film 114 on the compound semiconductor film 108, the insulating film 116 on the insulating film 114, and the insulating film 11 6, the insulating film 118, the conductive film 120a on the insulating film 118, and the conductive film 120b on the insulating film 118. The insulating films 114, 116, and 118 form the second gate of the transistor 170. The conductive film 120a functions as a gate insulating film. 18, the conductive film 112b is electrically connected to the conductive film 112b through an opening 142c provided in the conductive film 112b. In the transistor 170, the conductive film 120a is, for example, a pixel electrode used in a display device. In the transistor 170, the conductive film 120b functions as a second It functions as a gate electrode (also called a back gate electrode).

[0129] The conductive film 120b functions as a second gate electrode and the conductive film 11 functions as a source electrode. 2a, a conductive film 120b functioning as a second gate electrode, and a conductive film 120c functioning as a drain electrode. The conductive films 112b are arranged so as not to overlap each other.

[0130] In this configuration example, the oxide semiconductor film 108 includes a first region overlapping with the conductive film 104. a second region overlapping the conductive film 112a; a third region overlapping the conductive film 112b; The first region includes the second region and the third region. The fourth region is arranged so as not to include the second region and the third region. In other words, the first area is arranged so that the second area and the third area do not overlap. The fourth region is arranged so that the second region and the third region do not overlap. .

[0131] In FIG. 3B, the conductive film 104 and the conductive film 120b are depicted with the same width, but the width, shape, etc. may be different. The conductive film 120b and the conductive film 104 may have the same or different properties.

[0132] As shown in FIG. 3C, the conductive film 120b is formed by insulating films 106, 107, 114, and 1 In the openings 142a and 142b formed in the gate electrodes 16 and 118, Therefore, the conductive film 120b and the conductive film 104 are connected to the conductive film 104. A potential is applied.

[0133] In this embodiment, openings 142a and 142b are provided, and the conductive film 120b and Although the configuration in which the conductive film 104 is connected has been exemplified, the present invention is not limited to this. Only one of the openings 142a and 142b is formed. The conductive film 104 is connected, or the openings 142a and 142b are not provided, and the conductive film 104 is not connected. The conductive film 120b and the conductive film 104 may not be connected to each other. In the case where the conductive film 104 is not connected, the conductive film 120b and the conductive film 104 are respectively connected to different A potential can be applied.

[0134] As shown in FIG. 3B, the oxide semiconductor film 108 functions as a first gate electrode. and a conductive film 120b that functions as a second gate electrode. The second gate electrode is sandwiched between two conductive films that function as gate electrodes. The length of the conductive film 120b functioning as a gate electrode in the channel width direction is The length of the oxide semiconductor film 108 in the channel width direction is longer than the length of the insulating film 114. The gate electrode is covered with a conductive film 120b via the gate electrodes 116 and 118. The conductive film 120b that functions as the first gate electrode and the conductive film 104 that functions as the first gate electrode are formed by insulating film 1. In the openings 142a and 142b provided in the In order to be connected, the side surfaces of the oxide semiconductor film 108 in the channel width direction are covered with the insulating films 114 and 11 6 and 118, it faces the conductive film 120b which functions as the second gate electrode.

[0135] In other words, in the channel width direction of the transistor 170, The conductive film 104 functioning as the first gate electrode and the conductive film 120b functioning as the second gate electrode are The insulating films 106 and 107 function as gate insulating films, and the insulating film 108 function as a second gate insulating film. The insulating films 114, 116, and 118 are connected to each other through openings, and the first gate The insulating films 106 and 107 function as first gate insulating films, and the insulating film 108 functions as a second gate insulating film. The oxide semiconductor film 108 is surrounded by insulating films 114, 116, and 118.

[0136] With such a structure, the oxide semiconductor film 108 included in the transistor 170 The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. The transistor 170 can be electrically surrounded by the electric field of the conductive film 120b. The electric field of the first gate electrode and the second gate electrode causes the oxide film to form a channel region. The device structure of the transistor that electrically surrounds the oxide semiconductor film is called the surrounded ch This can be called an s-channel structure.

[0137] Since the transistor 170 has an s-channel structure, it has a first gate electrode The conductive film 104 functions as a gate electrode, and the electric field for inducing the channel is effectively applied to the oxide semiconductor. This allows the voltage to be applied to the body membrane 108, improving the current driving capability of the transistor 170. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, it is possible to miniaturize the transistor 170. The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. Since the transistor 170 has a structure surrounded by the conductive film 120b, the mechanical strength of the transistor 170 is increased. It can be done.

[0138] The other configurations of the transistor 170 are the same as those of the transistor 100 shown above. and has the same effect.

[0139] In addition, the transistor according to this embodiment can be freely combined with each of the above structures. For example, the transistor 100 shown in FIG. 1 can be used as a transistor for a pixel of a display device. 3 is used as a transistor for the gate driver of the display device. It can be used for

[0140] <Configuration Example 3 of Semiconductor Device> In Configuration Example 2, the first gate electrode and the source electrode and the first gate a first gate electrode and a second drain electrode, and a second gate electrode and a source electrode and a second gate electrode. The first gate electrode and the source electrode or the first drain electrode do not overlap. The gate electrode and the drain electrode may not overlap each other.

[0141] In addition, when a function similar to the function described above is provided, the hatch pattern is the same, and may not be signed.

[0142] FIG. 8A is a top view of a transistor 171 which is a semiconductor device of one embodiment of the present invention. FIG. 8(B) corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 8(A). 8(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line Y1-Y2 shown in FIG. 8(A). do.

[0143] FIG. 8B shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a functions as a first gate electrode, the conductive film 104 functions as a drain electrode, and the conductive film 112b functions as a first gate electrode. The conductive film 112b functioning as the second gate electrode does not overlap with the conductive film 112a. 120b, a conductive film 112a functioning as a source electrode, and a conductive film 112b functioning as a second gate electrode. The conductive film 120b functioning as the drain electrode and the conductive film 112b functioning as the drain electrode overlap each other. It is arranged to have

[0144] By adopting the above-mentioned configuration, the first gate electrode and the source electrode or the first gate electrode and the source electrode The parasitic capacitance between the drain electrodes can be reduced.

[0145] FIG. 9A is a top view of a transistor 172 which is a semiconductor device of one embodiment of the present invention. FIG. 9(B) corresponds to a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 9(A). 9(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line Y1-Y2 shown in FIG. 9(A). do.

[0146] FIG. 9B shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a functions as a first gate electrode, the conductive film 104 functions as a drain electrode, and the conductive film 112b functions as a first gate electrode. The conductive film 112b has an overlapping region and functions as a second gate electrode. the conductive film 120b serving as a source electrode, the conductive film 112a serving as a second gate electrode, and The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode overlap each other. are positioned so that

[0147] In this configuration example, the oxide semiconductor film 108 includes a first region overlapping with the conductive film 104. a second region overlapping the conductive film 112a; a third region overlapping the conductive film 112b; The first region or the fourth region is a region overlapping the second region and the fourth region. In other words, the first region or the fourth region is not included. is disposed so as not to overlap with the second region and the third region.

[0148] By adopting the above-mentioned configuration, the second gate electrode and the source electrode or the second gate electrode and the source electrode The parasitic capacitance between the drain electrodes can be reduced.

[0149] The other configurations of the transistors 171 and 172 are the same as those of the transistor 1 shown above. It is the same as 00 and has the same effect.

[0150] <Configuration Example 4 of Semiconductor Device> Note that in Configuration Example 1, the first gate electrode is located below the oxide semiconductor film. The present invention describes a bottom gate transistor located at the top of the first gate electrode. A top-gate transistor, which is located above the nitride semiconductor film, may also be used. The transistor 160 will be described with reference to FIGS. If the function is the same as the function described above, the hatch pattern will be the same and the symbol will be In some cases, the number may not be added.

[0151] FIG. 10A is a top view of a transistor 160 which is a semiconductor device of one embodiment of the present invention. 10(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 10(A). 10(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 10(A). This corresponds to a plan view.

[0152] The transistor 160 includes an oxide semiconductor film 108 over a substrate 102 and a gate insulating film 108 a conductive film 112a serving as a source electrode electrically connected to the oxide semiconductor film 10 A conductive film 112b serving as a drain electrode electrically connected to the gate electrode 8 and a conductive film 112a , the insulating film 107 over the conductive film 112b and the oxide semiconductor film 108, and the insulating film 107 and a conductive film 104 on the insulating film 106 that functions as a first gate electrode. In addition, on the transistor 160, more specifically, the insulating film 106, the conductive film 112a, and the 12b and insulating films 114, 116, and 118 are provided on the conductive film 104. The insulating films 114, 116, and 118 function as protective insulating films for the transistor 160. do.

[0153] A conductive film 104 functioning as a first gate electrode and a conductive film 112 functioning as a source electrode. a, a conductive film 104 functioning as a first gate electrode, and a conductive film 105 functioning as a drain electrode. The conductive films 112b are arranged so as not to overlap each other.

[0154] In this configuration example, the oxide semiconductor film 108 includes a first region overlapping with the conductive film 104. The second region overlaps with the conductive film 112a, and the third region overlaps with the conductive film 112b. The first region is arranged so as not to include the second region and the third region. The first region is disposed so as not to overlap with the second region and the third region.

[0155] By adopting the above-mentioned configuration, the first gate electrode and the source electrode and the first gate electrode The parasitic capacitance between the drain electrodes can be reduced.

[0156] The other configurations of the transistor 160 are the same as those of the transistor 100 shown above. and has the same effect.

[0157] <Configuration Example 5 of Semiconductor Device> In the first configuration example, the first gate electrode and the source electrode, and the first gate electrode and the drain electrode are Although the first gate electrode and the source electrode or the first gate electrode and the drain electrode are not overlapped, The inner electrodes may not overlap.

[0158] The above configuration example will be explained using FIG. 11. (A-1) and (B-1) of FIG. 11(A) and 11(B) are top views of transistors 151 and 152 which are semiconductor devices of one embodiment of the present invention. A-2) corresponds to the cross-sectional view of the cut surface between the dashed line X1-X2 shown in FIG. 11(A-1). 11(B-2) is a cross section taken along the dashed line X1-X2 in FIG. 11(B-1). The cross section of the cut surface between the dashed dotted line Y1-Y2 corresponds to the cross section of FIG. ) and therefore omitted. Also, if it has the same function as the function described above, In some cases, the hatch patterns are the same and no particular symbols are assigned.

[0159] FIG. 11(A-2) shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The functional conductive film 112a has an overlapping region and functions as a first gate electrode. The conductive film 104 and the conductive film 112b that functions as the drain electrode are arranged so as not to overlap each other. It has been done.

[0160] FIG. 11B-2 shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive films 112a that function do not overlap each other, and the conductive film 10 that functions as the first gate electrode The conductive film 112b functioning as the drain electrode and the conductive film 112b are arranged so as to have an overlapping region. It has been done.

[0161] In this configuration example, the oxide semiconductor film 108 includes a first region overlapping with the conductive film 104. The second region overlaps with the conductive film 112a, and the third region overlaps with the conductive film 112b. The first region is arranged so as not to include the second region or the third region. The first region is disposed so as not to overlap with the second region or the third region.

[0162] By adopting the above-mentioned configuration, the first gate electrode and the source electrode or the first gate electrode and the source electrode The parasitic capacitance between the drain electrodes can be reduced.

[0163] The other configurations of the transistors 151 and 152 are the same as those of the transistor 1 shown above. It is the same as 00 and has the same effect.

[0164] <Configuration Example 6 of Semiconductor Device> In Configuration Example 2, the first gate electrode and the source electrode and the first gate a first gate electrode and a drain electrode, and a second gate electrode and a source electrode and a second gate electrode The first gate electrode and the source electrode, and the first gate electrode and the drain electrode are not overlapped. a first gate electrode and a drain electrode, a second gate electrode and a source electrode, or a second gate electrode and a drain electrode. The rain electrodes may be configured not to overlap.

[0165] The above configuration example will be described with reference to Figs. 12 to 17. 1) and (B-1) are transistors 173 to 178 which are semiconductor devices according to one embodiment of the present invention. 12 to 17 are top views of the 84, and (A-2) and (B-2) of FIGS. Cross-sectional view of the cut surface between the dashed dotted lines X1-X2 shown in (A-1) and (B-1) of 17 The cross section taken along the dashed line Y1-Y2 corresponds to the same shape as in Figure 3(C). In addition, if the function is the same as that explained above, The patterns may be the same and may not be given specific symbols.

[0166] FIG. 12(A-2) shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a that functions as a first gate electrode and the conductive film 104 that functions as a drain electrode the conductive film 112b functioning as the second gate electrode, and the conductive film 120b functioning as the second gate electrode. The conductive film 112a functioning as the second gate electrode and the conductive film 112b functioning as the source electrode do not overlap each other. The conductive film 120b that functions as a drain electrode and the conductive film 112b that functions as a drain electrode overlap each other. The electrodes are arranged to have a region.

[0167] FIG. 12B-2 shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a that functions as a first gate electrode and the conductive film 104 that functions as a drain electrode the conductive film 112b functioning as the second gate electrode, and the conductive film 120b functioning as the second gate electrode. The conductive film 112b functioning as the second gate electrode and the conductive film 112b functioning as the drain electrode do not overlap each other. The conductive film 120b functioning as a source electrode and the conductive film 112a functioning as a source electrode overlap each other in the area. The electrodes are arranged to have a region.

[0168] FIG. 13(A-2) shows a conductive film 104 serving as a first gate electrode and a conductive film 105 serving as a drain electrode. a conductive film 112b functioning as a second gate electrode; a conductive film 120b functioning as a source electrode; a conductive film 112a functioning as a first electrode, and a conductive film 120 functioning as a second gate electrode. The conductive film 112b functioning as the first gate electrode and the conductive film 112b functioning as the drain electrode do not overlap each other. The conductive film 104 functioning as a source electrode and the conductive film 112a functioning as a source electrode overlap each other. The electrodes are arranged to have a region.

[0169] FIG. 13B-2 shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a functions as a second gate electrode, the conductive film 120b functions as a source electrode, and the the conductive film 112a functioning as a second gate electrode, and the conductive film 120b functioning as a second gate electrode. The conductive film 112b functioning as the first gate electrode and the conductive film 112b functioning as the drain electrode do not overlap each other. The conductive film 104 functioning as a drain electrode and the conductive film 112b functioning as a drain electrode overlap each other. The electrodes are arranged to have a region.

[0170] FIG. 14(A-2) shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive films 112a and 112b functioning as the first gate electrode do not overlap each other. 04, a conductive film 112b functioning as a drain electrode, and a conductive film 112c functioning as a second gate electrode. The conductive film 120b functions as a source electrode, the conductive film 112a functions as a second gate electrode, and the conductive film 112b functions as a second gate electrode. The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode are overlapped with each other. The electrodes are arranged to have a region where the electrodes are spaced apart.

[0171] FIG. 14B-2 shows a conductive film 104 serving as a first gate electrode and a conductive film 105 serving as a drain electrode. The conductive film 112b that functions as the first gate electrode does not overlap with the conductive film 112a. 104, a conductive film 112a functioning as a source electrode, and a conductive film 112b functioning as a second gate electrode. The conductive film 120b functions as a source electrode, the conductive film 112a functions as a second gate electrode, and the conductive film 112b functions as a second gate electrode. The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode are overlapped with each other. The electrodes are arranged to have a region where the electrodes are spaced apart.

[0172] FIG. 15(A-2) shows a conductive film 120b functioning as a second gate electrode and a drain electrode. The conductive film 112b that functions as the first gate electrode does not overlap with each other. The conductive film 112a functions as a first gate electrode, the conductive film 112b functions as a second gate electrode, and the conductive film 112c functions as a first gate electrode. The conductive film 104, the conductive film 112b functioning as a drain electrode, and the second gate electrode The conductive film 120b functioning as the source electrode and the conductive film 112a functioning as the source electrode overlap each other. The electrodes are arranged to have a region.

[0173] FIG. 15B-2 shows a conductive film 120b functioning as a second gate electrode and a conductive film 120c functioning as a source electrode. The conductive film 112a functioning as the first gate electrode does not overlap with the conductive film 112b. 104, a conductive film 112a functioning as a source electrode, and a conductive film 112b functioning as a first gate electrode. a conductive film 104, a conductive film 112b functioning as a drain electrode, and a second gate electrode The conductive film 120b functioning as a drain electrode and the conductive film 112b functioning as a drain electrode are overlapped with each other. The electrodes are arranged to have a region.

[0174] FIG. 16(A-2) shows a conductive film 104 serving as a first gate electrode and a conductive film 105 serving as a drain electrode. and a conductive film 120b that functions as a second gate electrode. The conductive film 112b, which functions as a drain electrode, does not overlap with each other and serves as a first gate electrode. The conductive film 104 functions as a source electrode, the conductive film 112a functions as a second gate electrode, and the conductive film 112b functions as a source electrode. The conductive film 120b functioning as an electrode and the conductive film 112a functioning as a source electrode are mutually are arranged to have an overlapping area.

[0175] FIG. 16B-2 shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a functions as a second gate electrode, and the conductive film 120b functions as a second gate electrode. The conductive film 112a, which functions as a first gate electrode, does not overlap with each other. The conductive film 104 functions as a drain electrode, the conductive film 112b functions as a second gate electrode, and the conductive film 112b functions as a second gate electrode. The conductive film 120b functioning as the electrode and the conductive film 112b functioning as the drain electrode are are arranged to have an overlapping area.

[0176] FIG. 17(A-2) shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a drain electrode. a conductive film 112b functioning as a second gate electrode, and a conductive film 120b functioning as a second gate electrode. The conductive film 112a, which functions as a source electrode, does not overlap with each other and serves as a first gate electrode. The conductive film 104 functions as a source electrode, the conductive film 112a functions as a second gate electrode, and the conductive film 112b functions as a source electrode. The conductive film 120b functions as a source electrode and the conductive film 112b functions as a drain electrode. They are arranged so as to have overlapping areas.

[0177] FIG. 17B-2 shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive film 112a functions as a gate electrode, and the conductive film 120b functions as a second gate electrode. The conductive film 112b, which functions as a drain electrode, does not overlap with each other and serves as a first gate electrode. The conductive film 104 functions as a drain electrode, the conductive film 112b functions as a drain electrode, and the second gate electrode. The conductive film 120b functions as a gate electrode and the conductive film 112a functions as a source electrode. They are arranged so as to have overlapping areas.

[0178] In this configuration example, the oxide semiconductor film 108 includes a first region overlapping with the conductive film 104. a second region overlapping the conductive film 112a; a third region overlapping the conductive film 112b; The first region or the fourth region overlaps the second region or the fourth region. In other words, the first region or the fourth region is not included. is disposed so as not to overlap with the second region or the third region.

[0179] By adopting the above-mentioned configuration, the first gate electrode and the source electrode, the first gate electrode and the drain electrode between the source electrode, the second gate electrode and the source electrode or the second gate electrode and the drain electrode The parasitic capacitance can be reduced.

[0180] The other configurations of the transistors 173 to 184 are the same as those of the transistor 10 shown above. It is the same as 0 and has the same effect.

[0181] <Configuration Example 7 of Semiconductor Device> In Configuration Example 4, the first gate The first gate electrode and the source electrode, and the first gate electrode and the drain electrode do not overlap. The first gate electrode and the source electrode or the first gate electrode and the drain electrode do not overlap each other. It may also be composed.

[0182] The above configuration example will be explained using FIG. 18. (A-1) and (B-1) of FIG. 18(A) and 18(B) are top views of transistors 161 and 162 which are semiconductor devices of one embodiment of the present invention. A-2) corresponds to the cross-sectional view of the cut surface between the dashed line X1-X2 shown in FIG. 18(A-1). 18(B-2) is a cross section taken along the dashed line X1-X2 in FIG. 18(B-1). The cross section of the cut surface between the dashed dotted line Y1-Y2 corresponds to the cross section of FIG. Since it has the same shape as C), it will be omitted. In such cases, the hatch pattern may be the same and no particular reference numeral may be assigned.

[0183] FIG. 18(A-1) shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The functional conductive film 112a has an overlapping region and functions as a first gate electrode. The conductive film 104 and the conductive film 112b that functions as the drain electrode are arranged so as not to overlap each other. It has been done.

[0184] FIG. 18B-2 shows a conductive film 104 functioning as a first gate electrode and a conductive film 105 functioning as a source electrode. The conductive films 112a that function do not overlap each other, and the conductive film 10 that functions as the first gate electrode The conductive film 112b functioning as the drain electrode and the conductive film 112b are arranged so as to have an overlapping region. It has been done.

[0185] In this configuration example, the oxide semiconductor film 108 includes a first region overlapping with the conductive film 104. The second region overlaps with the conductive film 112a, and the third region overlaps with the conductive film 112b. The first region is arranged so as not to include the second region or the third region. The first region is disposed so as not to overlap with the second region or the third region.

[0186] By adopting the above-mentioned configuration, the first gate electrode and the source electrode or the first gate electrode and the source electrode The parasitic capacitance between the drain electrodes can be reduced.

[0187] The other configurations of the transistors 161 and 162 are the same as those of the transistor 1 shown above. It is the same as 00 and has the same effect.

[0188] <Method 1 for manufacturing semiconductor device> Next, a transistor 10 which is a semiconductor device of one embodiment of the present invention will be described. The method for manufacturing the semiconductor device 10 will be described in detail below with reference to FIGS. 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device.

[0189] Note that the films (insulating film, oxide semiconductor film, conductive film, etc.) constituting the transistor 100 are Sputtering, Chemical Vapor Deposition (CVD), Vacuum Evaporation, Pulsed Laser Deposition (PLD) Alternatively, the layer can be formed by a coating method or a printing method. Typical film formation methods are sputtering and plasma enhanced chemical vapor deposition (PECVD). However, thermal CVD may also be used. An example of a thermal CVD method is MOCVD (metal organic chemical vapor deposition). ) method or ALD (atomic layer deposition) method may also be used.

[0190] In the thermal CVD method, the pressure in the chamber is atmospheric or reduced, and the source gas and oxidant are simultaneously mixed. The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0191] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating this gas introduction sequence. By switching each switching valve (also called high-speed valve), two or more types of raw materials can be The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Simultaneously with or after the second gas, an inert gas (argon, nitrogen, etc.) is introduced. Introduce the source gas. If an inert gas is introduced at the same time, the inert gas is used as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first monoatomic layer. The second monoatomic layer is formed by reacting with the second source gas introduced later. Layer upon layer is laminated to form a thin film.

[0192] This gas introduction sequence is repeated multiple times while controlling it until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. Therefore, precise film thickness control is possible, and fine transistors can be fabricated. It is suitable for manufacturing.

[0193] First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, a conductive film 104 is formed, which functions as a first gate electrode. On the conductive film 104, insulating films 106 and 107 are formed to function as a first gate insulating film (see FIG. 4(A)).

[0194] The conductive film 104 functioning as the first gate electrode is formed by a method such as sputtering, chemical vapor deposition ( It can be formed using the CVD method, vacuum evaporation method, pulsed laser deposition (PLD) method, etc. Alternatively, it can be formed by a coating method or a printing method. The most common methods are the plasma-enhanced chemical vapor deposition (PECVD) method, but the organic metal Thermal CVD methods such as MOCVD or atomic layer deposition (ALD) can also be used. good.

[0195] In this embodiment, a glass substrate is used as the substrate 102, and a gate electrode is formed on the substrate 102. A tungsten film having a thickness of 100 nm is formed as the conductive film 104 by sputtering. .

[0196] The insulating films 106 and 107, which function as the first gate insulating film, are formed by sputtering, PE It can be formed by using a CVD method, a thermal CVD method, a vacuum deposition method, a PLD method, etc. In this embodiment, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 106 by the PECVD method. Then, a silicon oxynitride film having a thickness of 50 nm is formed as the insulating film 107.

[0197] The insulating film 106 may have a stacked structure of silicon nitride films. The insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminated structure with a silicon film can be formed. An example of the three-layer laminated structure is as follows: It can be formed as follows.

[0198] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PECVD was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gases. The pressure in the reaction chamber was controlled to 100 Pa, and a high frequency of 27.12 MHz was generated. A power of 2000 W is supplied using a microwave power supply, and the thickness is formed to be 50 nm. stomach.

[0199] For the second silicon nitride film, silane at a flow rate of 200 sccm and 2000 sccm The PECVD equipment was operated using nitrogen at a flow rate of 2000 sccm and ammonia gas at a flow rate of 2000 sccm as raw material gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency power supply A power of 2000 W may be supplied using a heater to form the film to a thickness of 300 nm.

[0200] The third silicon nitride film was formed using silane at a flow rate of 200 sccm and silane at a flow rate of 5000 sccm. The pressure in the reaction chamber was adjusted to 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power supply. It is sufficient to form it so that the thickness is 50 nm.

[0201] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during the formation can be set to 350°C.

[0202] By forming the insulating film 106 as a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper (Cu) is used for 4, the following effects are achieved.

[0203] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 104. The second silicon nitride film has a function of releasing hydrogen and can be used as the first gate insulating film. The third silicon nitride film can improve the breakdown voltage of the insulating film that functions as a third nitride film. The hydrogen released from the second silicon nitride film is small, and the hydrogen released from the second silicon nitride film is small. The diffusion of can be suppressed.

[0204] The insulating film 107 is formed by the oxide semiconductor film 108 (more specifically, the first In order to improve the interface characteristics with the oxide semiconductor film 108a), It would be preferable if this could be done.

[0205] Next, a first oxide semiconductor film 108a is formed over the insulating film 107. A second oxide semiconductor film 108b is formed over the oxide semiconductor film 108a (see FIG. 4B). see).

[0206] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: A first oxide semiconductor film was formed by sputtering using a SiO 2 / SiO 2 (atomic ratio: 2:4.1). Then, in vacuum, the In-Ga-Zn metal oxide target (In:Ga: Zn=1:1:1.2 (atomic ratio)) by sputtering. A conductive film is formed to form a stacked oxide semiconductor film. A mask is formed on the oxide semiconductor film by a lithography process, and the oxide semiconductor film of the stack is formed in a desired region. By processing the oxide semiconductor film 108 into an island shape, the oxide semiconductor film 108 is formed.

[0207] When the oxide semiconductor film 108 is formed by a sputtering method, a sputtering gas In this case, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is appropriately used. In the case of a mixed gas, it is preferable to increase the ratio of oxygen to rare gas. It is also necessary to increase the purity of the sputtering gas. For example, the oxygen used as the sputtering gas The dew point of the gas or argon gas is -40°C or less, preferably -80°C or less, more preferably By using gas that has been highly purified to temperatures below -100°C, and more preferably below -120°C, This can prevent moisture and the like from being taken into the oxide semiconductor film 108 as much as possible.

[0208] In addition, when the oxide semiconductor film 108 is formed by a sputtering method, a sputtering apparatus The chamber is designed to remove water and other impurities that may be present in the oxide semiconductor film 108 as much as possible. To remove the gas, a high vacuum pump (5×10) was used, such as a cryopump. -7 Pa to 1 x 10 -4 It is preferable to use a turbomolecular pump. A combination of a pump and a cold trap is used to extract gases, especially carbon or water, from the exhaust system into the chamber. It is preferable to prevent backflow of gas containing oxygen.

[0209] Next, a source electrode and a drain electrode are formed on the insulating film 107 and the second oxide semiconductor film 108b. A conductive film 112 that functions as an electrode is formed (see FIG. 4C).

[0210] In this embodiment, the conductive film 112 is a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 40 A laminated film with a 0 nm aluminum film is formed by sputtering. In the embodiment, the conductive film 112 has a stacked structure of two layers, but is not limited to this. The conductive film 112 is a tungsten film having a thickness of 50 nm and an aluminum film having a thickness of 400 nm. Alternatively, the film may have a three-layer structure consisting of a 100 nm thick titanium film and a 100 nm thick titanium film.

[0211] Next, masks 140a and 140b are formed in desired regions on the conductive film 112 (FIG. 4(D) )reference).

[0212] In this embodiment, the masks 140a and 140b are formed by applying a photosensitive resin film. The photosensitive resin film is then patterned by a lithography process to form the film.

[0213] Next, etching gas 138 is used to remove the conductive film 112 and the masks 140a and 140b. Then, the conductive film 112 and the second oxide semiconductor film 108b are processed (see FIG. 5A).

[0214] In this embodiment, the conductive film 112 and the second acid are removed by using a dry etching apparatus. However, the method for forming the conductive film 112 is not limited to this. For example, by using a chemical solution as the etching gas 138, a wet etching apparatus can be used. The conductive film 112 and the second oxide semiconductor film 108b may be processed by using a device. Then, the conductive film 112 and the second oxide semiconductor film 108 were removed using a wet etching apparatus. Rather than processing the conductive film 112 and the second oxide semiconductor layer 113 using a dry etching apparatus, Processing the conductive film 108b is preferable because it allows for the formation of finer patterns. is.

[0215] Next, the masks 140a and 140b are removed, so that the second oxide semiconductor film 108b is left unremoved. The conductive film 112a serving as a source electrode of the second oxide semiconductor film 108b and the drain electrode of the second oxide semiconductor film 108b are A conductive film 112b serving as an in-electrode is formed. The first oxide semiconductor film 108a and the second oxide semiconductor film 108b having a recess are (See FIG. 5(B)).

[0216] In addition, a chemical solution was sprayed onto the second oxide semiconductor film 108b and the conductive films 112a and 112b. The surface (on the back channel side) of the second oxide semiconductor film 108b may be cleaned by applying the solution. The cleaning method may be, for example, cleaning using a chemical solution such as phosphoric acid. By performing cleaning using a chemical solution, impurities attached to the surface of the second oxide semiconductor film 108b are removed. (For example, elements contained in the conductive films 112a and 112b) can be removed. However, the washing is not necessarily required, and in some cases washing may not be performed.

[0217] In addition, when forming the conductive films 112a and 112b and / or in the cleaning process, The oxide semiconductor film 108b has a second region thinner than the first oxide semiconductor film 108a. A region is formed.

[0218] Next, insulating films 114 and 112 are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. 6 is formed (see FIG. 5(C)).

[0219] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposure to the air. After the insulating film 114 is formed, it is preferable to control the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the atmosphere. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. At the same time, oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. As a result, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0220] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. It is preferable to use the following gases. Typical examples of deposition gases containing silicon include silane, disilane, and the like. Examples of oxidizing gases include nitrous oxide, nitrous dioxide, etc. In addition, the flow rate of the oxidizing gas is set to be 20 times or more greater than the flow rate of the deposition gas. The pressure in the processing chamber is set to less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is set to less than 100 Pa. By using the PECVD method at a pressure of 50 Pa or less, preferably 50 Pa or less, the insulating film 114 is The insulating film contains the above and has a small amount of defects.

[0221] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220°C. Silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm were used as source gases. The pressure in the processing chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6 x 10 -2 W / cm 2 ) PECVD method A silicon oxynitride film is formed using the silicon oxynitride film.

[0222] The insulating film 116 is formed by depositing a substrate placed in a vacuum-evacuated processing chamber of a PECVD device. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the processing chamber. is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less. , 0.17 W / cm to the electrode installed in the processing chamber 2 More than 0.5W / cm 2 Below are some more good ones: Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0223] The conditions for forming the insulating film 116 are as follows: a high frequency voltage of the above power density in a reaction chamber of the above pressure; By supplying power, the decomposition efficiency of the source gas in the plasma increases, and oxygen radicals increase. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes higher than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is As a result, the stoichiometric amount of oxygen in the film is reduced by the heat treatment in the subsequent process. Oxides that contain more oxygen than the stoichiometric composition and lose some of the oxygen when heated An insulating film can be formed.

[0224] The process of forming the insulating film 116 is carried out in a PECVD apparatus at a temperature of 180° C. to 350° C. The insulating film 116 is formed during the manufacturing process of the transistor 100. For example, the temperature for forming the insulating film 116 is set to 350° C. By implementing the method, it is possible to form the transistor 100 directly on a flexible substrate or the like. .

[0225] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0226] In the film formation conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the number of defects in the insulating film 116. In the ESR measurement, the g value of 2.001, which is due to the dangling bond of silicon, The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5 × 10 17 spins / cm 3 The following is a missing An oxide insulating layer with fewer defects can be formed, resulting in improved reliability of the transistor. It can be done.

[0227] After the insulating films 114 and 116 are formed, heat treatment may be performed. This can reduce the amount of nitrogen oxide contained in the insulating films 114 and 116. By the heat treatment, part of oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. By this, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0228] The temperature for the heat treatment of the insulating films 114 and 116 is typically 150° C. or higher and 350° C. or lower. Heat treatment is carried out in nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably air at 1 ppm or less, preferably 10 ppb or less), or rare gases (argon, helium The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas may be added to the atmosphere of water. It is preferable that the material does not contain oxygen, water, etc. The heat treatment is carried out using an electric furnace, an RTA device, etc. It is possible.

[0229] In this embodiment mode, heat treatment is performed in a nitrogen atmosphere at 350° C. for 1 hour. In the step of forming the transistor 100, the temperature at which the insulating film 116 is formed should be the highest. Alternatively, heat treatment at a temperature equivalent to the temperature at which the insulating film 116 is formed may be performed in a different step.

[0230] Next, an oxide conductive film 131 is formed over the insulating film 116 (see FIG. 5D).

[0231] The oxide conductive film 131 is made of oxygen and a metal (indium, zinc, titanium, aluminum, tantalum, etc.). at least one selected from the group consisting of tungsten, tantalum, and molybdenum; do.

[0232] Examples of the oxide conductive film 131 include a tantalum oxynitride film, a titanium oxide film, and an indium oxide film. Tin oxide (hereinafter also referred to as ITO) film, aluminum oxide film, oxide semiconductor film (e.g., I A GZO film (In:Ga:Zn=1:4:5 (atomic ratio)) can be used. The oxide conductive film 131 can be formed by a sputtering method. The thickness of the oxide conductive film 131 is 1 nm or more and 20 nm or less, or 2 nm or more and 10 nm or less. In this embodiment, the oxide conductive film 131 has a thickness of 50 nm or less. Indium tin oxide doped with silicon oxide (hereinafter referred to as ITSO) is used.

[0233] Next, the insulating films 114 and 116 and the oxide semiconductor film 108 are Oxygen 139 is added. In the figure, the insulating film 114 and the insulating film 116 are doped with oxygen. The oxygen atom is represented schematically as oxygen 139 (see FIG. 6(A)).

[0234] The insulating films 114 and 116 and the oxide semiconductor film 108 are filled with oxygen through the oxide conductive film 131. The methods for adding 39 include ion doping, ion implantation, and plasma treatment. In addition, when adding oxygen 139, applying a bias to the substrate side can effectively increase the amount of oxygen. The element 139 can be added to the insulating films 114 and 116 and the oxide semiconductor film 108. The bias may be, for example, a power density of 1 W / cm 2 More than 5W / cm 2 If we do the following, By providing the oxide conductive film 131 over the insulating film 116 and adding oxygen, the oxide conductive film The insulating film 131 functions as a protective film that prevents oxygen from being released from the insulating film 116. Therefore, more oxygen can be added to the insulating films 114 and 116 and the oxide semiconductor film 108. can.

[0235] Next, the oxide conductive film 131 is removed by an etchant 142 (see FIG. 6B). .

[0236] The oxide conductive film 131 can be removed by dry etching or wet etching. or a method in which dry etching and wet etching are combined. In the case of dry etching, the etchant 142 is an etching gas. In the case of wet etching, the etchant 142 is a chemical liquid. In the second step, the oxide conductive film 131 is removed by wet etching.

[0237] Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 6C).

[0238] Note that heat treatment is performed before or after the insulating film 118 is formed to form an insulating film. Excess oxygen contained in the films 114 and 116 is diffused into the oxide semiconductor film 108, and the oxide semiconductor Alternatively, the insulating film 118 can be formed by heating and filling the oxygen vacancies in the insulating film 108. By this, excess oxygen contained in the insulating films 114 and 116 is diffused into the oxide semiconductor film 108. As a result, oxygen vacancies in the oxide semiconductor film 108 can be filled.

[0239] When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to 180° C. or more and 350° C. or less. This is preferable because it allows the formation of a dense film.

[0240] For example, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, the silicon It is preferable to use a deposition gas containing carbon, nitrogen, and ammonia as the source gas. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma and becomes active. The activated species react with silicon and hydrogen contained in the silicon-containing deposition gas. This breaks the silicon-nitrogen triple bond, promoting the bonding of silicon and nitrogen. To form a dense silicon nitride film with few bonds between silicon and hydrogen and few defects. On the other hand, if the amount of ammonia relative to nitrogen is large, the deposition gas containing silicon and Nitrogen decomposition does not progress, silicon and hydrogen bonds remain, defects increase, and roughness occurs. For these reasons, the source gas should be ammonia-free. The flow rate ratio of nitrogen to oxygen is preferably 5 or more and 50 or less, and more preferably 10 or more and 50 or less.

[0241] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, and the like using a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed using nitrogen and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 1000 sccm for ammonia. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and the flow rate was 27.12 Mpa. A high-frequency power supply of 1000 W was used to supply high-frequency power to the parallel plate electrodes. The device has an electrode area of ​​6000 cm 2 It is a parallel plate type PECVD device, and the supplied voltage The force can be converted to power per unit area (power density) as 1.7 x 10 -1 W / cm 2 is .

[0242] Through the above steps, the transistor 100 shown in FIG. 1 can be formed.

[0243] The Loff type transistor and the Lov type transistor have a first gate electrode, an oxide semiconductor, It can be made differently by changing the pattern of the conductor film, source electrode, or drain electrode. Therefore, they can be formed on the same substrate at the same time by the same manufacturing method.

[0244] In addition, in this manufacturing method, the first gate electrode and the source electrode and the first gate electrode and the drain electrode are Although the above description is given taking the example of a configuration in which the first gate electrode and the source electrode do not overlap, The same manufacturing method can be applied to a configuration in which the first gate electrode and the drain electrode do not overlap.

[0245] <Method for Manufacturing Semiconductor Device 2> Next, a method for manufacturing the transistor 170 of one embodiment of the present invention will be described. This will be described in detail below with reference to FIG. 7. Note that FIG. 7 illustrates a method for manufacturing a semiconductor device. 7(A), (C), (E), and (G) are cross-sectional views illustrating the fabrication of the transistor 170. 7(B), (D), (F), and (H) are cross-sectional views in the channel length direction during fabrication. 10 is a cross-sectional view of the capacitor 170 in the channel width direction during fabrication. FIG.

[0246] First, the same steps as in the manufacturing method of the transistor 100 described above (the steps shown in FIGS. 4 to 6) were performed. ) is performed, and the conductive film 104, the insulating films 106 and 107, and the oxide semiconductor film 108 are formed on the substrate 102. , conductive films 112a and 112b and insulating films 114, 116, and 118 are formed (FIG. 7(A) )(see B)).

[0247] Next, a mask is formed on the insulating film 118 by a lithography process, and the insulating films 114 and 11 An opening 142c is formed in a desired region of the insulating film 118. A mask is formed by a film process, and the desired insulating films 106, 107, 114, 116, and 118 are formed. The openings 142a and 142b are formed in the conductive film 112. The openings 142a and 142b are formed so as to reach the conductive film 10 4 (see Figures 7(C) and (D)).

[0248] The openings 142a, 142b and the opening 142c may be formed in the same process or in different processes. The openings 142a, 142b and the opening 142c may be formed in the same process. When forming the mask, for example, a gray-tone mask or a half-tone mask may be used. The openings 142a and 142b may be formed in multiple steps. , the insulating films 106 and 107 are processed, and then the insulating films 114, 116 and 118 are processed.

[0249] Next, a conductive film 12 is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. 0 (see Figures 7(E) and (F)).

[0250] The conductive film 120 may be made of, for example, indium (In), zinc (Zn), or tin (Sn). In particular, the conductive film 120 may be made of a material containing one selected from the group consisting of: Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide (ITO), indium zinc oxide, indium stannate with silicon oxide A conductive material having light-transmitting properties, such as an ITSO (Insulator-Titanium Dioxide), can be used. The layer 120 can be formed by using, for example, a sputtering method. In this embodiment, an ITSO film having a thickness of 110 nm is formed by sputtering.

[0251] Next, a mask is formed on the conductive film 120 by a lithography process, and the conductive film 112 is By processing the conductive film 120a into the shape shown in FIG. 7(G) and FIG. 7(H), the conductive film 120a and the conductive film 120b are formed. ).

[0252] The conductive films 120a and 120b can be formed by dry etching or wet etching. Examples include a dry etching method, or a combination of dry etching and wet etching. In this embodiment, the conductive film 120 is formed by wet etching. The conductive films 120a and 120b are then processed.

[0253] Through the above steps, the transistor 170 shown in FIGS.

[0254] The Loff type transistor and the Lov type transistor have a first gate electrode and a second gate electrode. By changing the patterns of the gate electrode, the oxide semiconductor film, the source electrode, or the drain electrode, Since it is possible to separately manufacture them, they can be formed simultaneously on the same substrate using the same manufacturing method. It is possible.

[0255] In addition, in this manufacturing method, the first gate electrode and the source electrode, the first gate electrode and the drain electrode the first gate electrode and the source electrode, and the second gate electrode and the drain electrode are connected to each other. Although the explanation has been given using an example of a non-overlapping configuration, the first gate electrode and the source electrode and the first A gate electrode and a drain electrode, or a second gate electrode and a source electrode and a second gate The same manufacturing method can be applied to a configuration in which the first electrode and the drain electrode do not overlap each other. a first gate electrode and a source electrode, a first gate electrode and a drain electrode, a second gate electrode and a source electrode, The same method can also be used to fabricate a structure in which the source electrode or the second gate electrode and the drain electrode do not overlap each other. The method can be applied.

[0256] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0257] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor included in a semiconductor device of one embodiment of the present invention will be described. A detailed explanation will be given below.

[0258] <Structure of oxide semiconductor> Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxides. As a non-single-crystal oxide semiconductor, CAAC-OS (C Ax is Aligned Crystalline Oxide Semiconductor or), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide e Semiconductor), pseudo-amorphous oxide semiconductor (a-like OS:a morphous-like oxide semiconductor), amorphous oxide semiconductors, etc.

[0259] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0260] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. This can also be described as a structure that has a high degree of order but no long-range order.

[0261] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor (isotropic amorphous). The oxide semiconductor is then oxidized to form a completely amorphous structure. However, a-like OS is a semiconductor that can be used in a microscopic area. Although it has a periodic structure, it has voids and is an unstable structure. It can be said that the physical properties are similar to those of an amorphous oxide semiconductor.

[0262] <caac-os>First, let me explain about CAAC-OS.

[0263] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0264] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, high-resolution TEM images reveal the boundaries between pellets, i.e., grain boundaries. Therefore, the CAAC-OS is not clearly characterized by the grain boundaries. It can be said that the resulting decrease in electron mobility is unlikely to occur.

[0265] Below, we will explain the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration correction function was used to obtain high-resolution TEM images. , specifically referred to as a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images can be obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0266] An enlarged Cs-corrected high-resolution TEM image of area (1) in Figure 19(A) is shown in Figure 19(B). From Figure 19(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0267] As shown in Figure 19(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the sintered body and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS is also used for CANC (C-Axis Aligned Nanoclip). The semiconductor may also be referred to as an oxide semiconductor having metals.

[0268] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 19(D)). Between the pellets observed in FIG. 19(C), The portion where the tilt occurs corresponds to the region 5161 shown in FIG. 19(D).

[0269] FIG. 20(A) shows the C of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. The s-corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 20(A). ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 20(B), Fig. 20(C), and Fig. 20(D), respectively. As shown in Figure 20(D), Figure 20(B), Figure 20(C) and Figure 20(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0270] Next, C analyzed by X-ray diffraction (XRD) For example, CAAC-O with InGaZnO4 crystals When S is subjected to structural analysis using the out-of-plane method, the results are as shown in Figure 21(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal is c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0271] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31 In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS crystals do not have a c-axis orientation. The more preferable CAAC-OS is a structure produced by the out-of-plane method. The analysis shows a peak at 2θ around 31°, but no peak at 2θ around 36°.

[0272] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction almost perpendicular to the c-axis. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I It is attributed to the (110) plane of the nGaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 5 The sample is fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears, as shown in Figure 21(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane as shown in Figure 21(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and b-axis is irregular.

[0273] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the probe diameter is 300 nm parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the presence of InGaZnO4 Therefore, electron diffraction also reveals spots due to the (009) plane of the crystal. The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied to the same sample perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 22(B). 2(B) shows a ring-shaped diffraction pattern. It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. The first ring in FIG. 22(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface.

[0274] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the incorporation of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0275] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0276] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0277] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Such an oxide semiconductor is a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. It can be said that the oxide semiconductor has the following structure.

[0278] <nc-os>Next, we will explain nc-OS.

[0279] In the high-resolution TEM image, nc-OS has two distinct regions: one where crystals can be confirmed and the other where clear crystals can be confirmed. The crystalline part contained in nc-OS is The size is often between 1 nm and 10 nm, or more than 1 nm. The oxide semiconductor having a size of more than 10 nm and not more than 100 nm is called a microcrystalline oxide semiconductor. For example, in high-resolution TEM images, the grain boundaries of nc-OS are clearly visible. It should be noted that the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS may be called a pellet. be.

[0280] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, in contrast to nc-OS, there are cases where it is difficult to distinguish the particles from the pellets. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, a probe diameter larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction is performed on nc-OS, high brightness regions are observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. This may be the case.

[0281] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) The semiconductor may also be referred to as an oxide semiconductor having a structure (s).

[0282] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0283] <a-like OS> The a-like OS is a composite of nc-OS and amorphous oxide semiconductor. The oxide semiconductor has the following structure.

[0284] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystalline parts can be clearly seen, and areas where crystalline parts can be seen. and areas where it is not possible to

[0285] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0286] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as Sample B) and CAAC-OS (hereinafter referred to as Sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0287] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all the materials have crystalline parts.

[0288] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing is 0.28 nm or more and 0.30 nm or less are considered to be InGaZnO4 crystal parts. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0289] Figure 23 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of ke OS grows in size according to the cumulative amount of electron irradiation. Specifically, as shown by (1) in Figure 23, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2 × 10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron irradiation dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystal part within the range of As shown in (2) and (3) in Figure 23, regardless of the cumulative electron dose, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that...

[0290] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC- It is clear that it has an unstable structure compared to the OS.

[0291] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the normal crystal. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0292] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It will be less than For example, in an oxide semiconductor satisfying the atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0293] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions may be used in any proportion. By combining single crystals with the desired composition, the density equivalent to that of a single crystal can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0294] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0295] <Film formation model> Below, we will introduce an example of a film formation model for CAAC-OS and nc-OS. explain.

[0296] FIG. 24(A) shows a process of forming a CAAC-OS film by sputtering. Schematic diagram of the inside of the membrane chamber.

[0297] The target 5130 is glued to a backing plate. A plurality of magnets are arranged at positions facing the target 5130 through the magnets. The magnetic field is generated by a number of magnets. The arrangement and configuration of the magnets are as described above. Please refer to the description of the film deposition chamber mentioned above. The ring method is called a magnetron sputtering method.

[0298] The target 5130 has a polycrystalline structure, and each grain contains a cleavage plane.

[0299] As an example, the cleavage surface of target 5130 having In-Ga-Zn oxide is described. FIG. 25(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In addition, in FIG. 25(A), the c-axis is directed upward, and InGaZn This is the structure of an O4 crystal.

[0300] As shown in Figure 25(A), in two adjacent Ga-Zn-O layers, It can be seen that the oxygen atoms are arranged close to each other. By doing so, two adjacent Ga-Zn-O layers repel each other. The aZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0301] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (also called the TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is 0.02m or more and 0.5m or less. oxygen, argon, or a gas mixture containing 5% or more by volume of oxygen) and The pressure is controlled to 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a voltage above a certain level to the target 5130, a discharge begins and plasma is generated. It is confirmed that a high density plasma region is generated near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 The ions 5101 are, for example, positive ions of oxygen (O + ) and argon cations ( Ar + ) etc.

[0302] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are separated and knocked out. The pellet 5100a and the pellet 5100b are formed by the impact of the collision of the ion 5101. distortion may occur.

[0303] The pellet 5100a is a flat plate or pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles in the form of plates or pellets. Sputter particles in the form of flat or pellets, such as pellets 5100b, are collectively called pellets. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon, for example. For example, there are cases where the shape is made up of multiple triangles. In some cases, two squares (or polygons) may join together to form a quadrilateral (for example, a rhombus).

[0304] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be explained later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes. The thickness of the PET 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. The pellet 5100 has a width of 1 nm or more. 100 corresponds to the initial nucleus explained in (1) in FIG. 23. For example, In-Ga- When ions 5101 are bombarded onto a target 5130 having Zn oxide, the ) has three layers: Ga-Zn-O layer, In-O layer, and Ga-Zn-O layer. The pellet 5100 pops out. Note that FIG. 25(C) shows the pellet 5100 aligned along the c-axis. This is the structure when viewed from a parallel direction. Therefore, the pellet 5100 has two G A nano-sized sandwich structure with a-Zn-O layer (bread) and In-O layer (stuffing) It can also be called construction.

[0305] The pellet 5100 receives a charge as it passes through the plasma, causing the sides to become negative or The pellet 5100 has oxygen atoms on the side, and the oxygen atoms In this way, the sides can be charged with the same polarity, The loads repel each other, allowing the flat shape to be maintained. When S is an In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. Or, the compound bonded to an indium atom, a gallium atom, or a zinc atom may The oxygen atoms may become negatively charged. Also, as the pellet 5100 passes through the plasma, When this happens, the atoms bond with indium, gallium, zinc, and oxygen, etc., and grow. This corresponds to the difference in size between (2) and (1) in FIG. 23 above. Here, when the substrate 5120 is at room temperature, the pellet 5100 does not grow any further. As a result, it becomes nc-OS (see Figure 24(B)). Since the temperature at which film formation is possible is around room temperature, Therefore, even if the substrate 5120 has a large area, the nc-OS film can be formed. In order to grow 5100 in plasma, the film formation power in the sputtering method must be increased. It is effective to increase the film formation power to stabilize the structure of the pellet 5100. It is possible.

[0306] As shown in FIG. 24(A) and FIG. 24(B), for example, the pellet 5100 is a plasma It flies like a kite through the air and flutters up to the top of the board 5120. Since the pellet 100 is electrically charged, it will be attracted to an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. A horizontal magnetic field (also called a horizontal magnetic field) is generated between the substrate 5120 and the target 5120. Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is on the upper surface of the substrate 5120. , and is subjected to a force (Lorentz force) due to the action of a magnetic field and an electric current. This can be understood using Gu's left-hand rule.

[0307] The pellet 5100 has a larger mass than an atom. In order to move the surface, it is important to apply some kind of force from the outside. One of these forces is It may be a force generated by the action of a magnetic field and an electric current. In order to increase the force, the upper surface of the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably Alternatively, it is preferable to provide an area where the resistance is 50 G or more. A magnetic field oriented parallel to the top surface of the plate 5120 is 1. 5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is advisable to set up an area where

[0308] At this time, the magnet unit and / or the substrate 5120 move relatively. By rotating the substrate 5120, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. Therefore, on the upper surface of the substrate 5120, the pellet 5100 is subjected to forces in various directions. can be received and moved in various directions.

[0309] Also, when the substrate 5120 is heated as shown in FIG. 24(A), the pellet 510 0 and the substrate 5120, the resistance due to friction etc. is small. The pellet 5100 glides over the top surface of the substrate 5120. The transfer occurs with the flat surface facing the substrate 5120. When the particles reach the side of the pellet 5100, the sides are joined together. The oxygen atom on the side of 00 is released. The released oxygen atom causes the Since oxygen vacancies may be filled, a CAAC-OS with a low density of defect states is obtained. The temperature of the upper surface of the plate 5120 is, for example, 100°C or higher and lower than 500°C, or 150°C or higher and 450°C. The temperature may be less than 170°C and less than 400°C, or 170°C and more and 350°C and less. Therefore, it is possible to form a CAAC-OS film even when the substrate 5120 has a large area.

[0310] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relaxed. Pellet 5100 becomes almost single crystal. Even if the 5100 is heated after bonding, the pellet 5100 itself hardly expands or contracts. Therefore, the gaps between the pellets 5100 widen, and the grain boundaries and other No defects or crevasses will form.

[0311] In addition, the CAAC-OS is not made of a single-crystal oxide semiconductor. The aggregates of pellets 5100 (nanocrystals) resemble bricks or blocks stacked on top of each other. In addition, there are no grain boundaries between them. Even if deformation such as shrinkage occurs in CAAC-OS due to subsequent heating or bending, local stress It is therefore possible to provide a flexible semi-conductor. The structure is suitable for semiconductor devices. nc-OS is a collection of pellets 5100 (nanocrystals). The resulting arrangement is like a chaotic pile of combined particles.

[0312] When the target is sputtered with ions, not only pellets but also zinc oxide etc. fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And it reaches 0.1nm to 10nm, 0.2nm to 5nm, or 0. A zinc oxide layer 5102 having a thickness of 5 nm or more and 2 nm or less is formed. A cross-sectional schematic diagram is shown in FIG.

[0313] As shown in FIG. 26(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are deposited. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the pellet 510 slides on pellet 5105b. In another aspect of FIG. 05a, a plurality of particles 51 ejected from the target along with zinc oxide. The substrate 5120 is heated and crystallized to form a region 5105a1. The particles 5103 may include oxygen, zinc, indium, gallium, and the like.

[0314] As shown in FIG. 26(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c has a side surface that is the same as that of the pellet 5105a. It is arranged so as to be in contact with another side surface of 105b.

[0315] Next, as shown in FIG. 26(C), a pellet 5105d is further added to the pellet 5105a2. After being deposited on pellet 5105a2 and pellet 5105b, It slides on the other side of the pellet 5105c. The pellet 5105e slides on the zinc oxide layer 5102.

[0316] As shown in FIG. 26(D), the pellet 5105d has a side surface similar to that of the pellet 51. The pellet 5105e is placed so that its side faces the pellet 5105a2. Also, the other side of the pellet 5105d is placed in contact with the other side of the pellet 5105c. At the surface, a plurality of particles 5103 that have been ejected from the target together with zinc oxide are deposited on the substrate 51. The film is crystallized by heating at 20 to form a region 5105d1.

[0317] As described above, the piled pellets are arranged so that they come into contact with each other, and the side surfaces of the pellets are Crystal growth occurs, forming a CAAC-OS on the substrate 5120. CAAC-OS has larger pellets than nc-OS. This corresponds to the difference in size between (3) and (2) in Figure 23.

[0318] In addition, the gaps between the 5100 pellets are extremely small, making it appear as if they were one large pellet. Large pellets may form. Large pellets have a single crystal structure. The pellet size, as viewed from the top, is 10 nm to 200 nm, 15 nm to 100 nm m or less, or 20 nm to 50 nm. If the channel formation area of ​​the pellet is smaller than that of the large pellet, the single crystal is used as the channel formation area. In addition, the pellets can be enlarged to allow for the formation of a region with a crystalline structure. The transistor has a channel forming region, a source region, and a drain region each having a single crystal structure. In some cases, a region can be used.

[0319] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0320] Based on the above model, it is assumed that the pellet 5100 is deposited on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is to be formed does not have a crystalline structure, It can be seen that CAAC-OS film formation is possible even in the case of a substrate 5120. Even if the structure of the top surface (surface to be formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a film of AC-OS.

[0321] In addition, even if the upper surface of the substrate 5120 on which the formation is performed is uneven, the CAAC-OS It can be seen that the pellets 5100 are arranged along the shape of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed on a flat surface that is parallel to the ab plane. Since the layers are aligned toward each other, a layer with uniform thickness, flatness, and high crystallinity is formed. By stacking these layers n times (n is a natural number), CAAC-OS can be obtained. Cut.

[0322] On the other hand, even if the upper surface of the substrate 5120 has irregularities, the CAAC-OS can be easily formed by the pellet 51 The structure is made up of n layers (n is a natural number) of 00 arranged side by side along the convex surface. Because the surface of the CAAC-OS is uneven, gaps tend to form between the pellets. However, intermolecular forces act between the pellets 5100, so even if there are irregularities, the pellets Therefore, even if there are irregularities, high crystallinity can be achieved. The CAAC-OS may have the following characteristics:

[0323] Therefore, CAAC-OS does not require laser crystallization and can be grown on large-area glass substrates. Even if the thickness is small, a uniform film can be formed.

[0324] Since the CAAC-OS film is formed using this model, the sputtered particles are distributed evenly across the film thickness. It is preferable that the sputtered particles are in the form of thick dices. In this case, the surface facing the substrate 5120 is not uniform, and the thickness and crystal orientation cannot be made uniform. There is.

[0325] The film formation model shown above allows for highly crystalline films to be formed even on a surface with an amorphous structure. Therefore, a CAAC-OS having the desired properties can be obtained.

[0326] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0327] (Embodiment 3) In this embodiment, a display device including the transistor described in the previous embodiment will be described. An example will be described below with reference to FIGS.

[0328] 27 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver 703 is provided on the second substrate 701. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, a sealant 712 disposed to surround the path portion 704 and the gate driver circuit portion 706; and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 27, a display element is provided between the first substrate 701 and the second substrate 705. It can be done.

[0329] The display device 700 is surrounded by a sealant 712 on the first substrate 701. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are arranged in a region different from the region. and an FPC terminal portion 708 (FPC: Flexible Printed Circuit) that is electrically connected to the flexible printed circuit portion 706. In addition, the FPC terminal portion 708 is provided with The FPC 716 is connected to the pixel section 702 and the source driver circuit Various signals are supplied to the pixel section 704 and the gate driver circuit section 706. 02, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal section 7 08 are connected to signal lines 710. Various signals are supplied by the FPC 716. 7. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, and the like are connected to each other via a signal line 710. The power supply is provided to a driver circuit portion 706 and an FPC terminal portion 708 .

[0330] Furthermore, the display device 700 may be provided with a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit etc. is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead of COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0331] The display device 700 also includes a pixel section 702, a source driver circuit section 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0332] The display device 700 can also include various elements, such as liquid crystal Elements, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) transistors (transistors that emit light according to the current), electron emitters, electron insulators Electrophoretic element, Grating light valve (GLV), Plasma display (P Display elements using DP, MEMS (microelectromechanical systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter) ), MIRASOL (registered trademark), IMOD (Interference Modulation ) element, shutter type MEMS display element, optical interference type MEMS display element, elect Low-wetting element, piezoelectric ceramic display, display using carbon nanotubes In addition to these, the contrast, brightness, reflection The display device may have a display medium whose refractive index, transmittance, etc. change. Examples include EL displays. is a field emission display (FED) or SED type flat panel display (SED:Surface-conduction Electron-emitter An example of a display device using a liquid crystal element is a liquid crystal display. Play (transmissive LCD, semi-transmissive LCD, reflective LCD) , direct view LCD, projection LCD). An example of a display device using electrophoretic elements is electronic paper. When realizing a liquid crystal display or a reflective liquid crystal display, a part of the pixel electrode or , all of which may function as a reflective electrode. Alternatively, the entire material may be aluminum, silver, or the like. It is also possible to provide a memory circuit such as an SRAM under the reflective electrode. Furthermore, power consumption can be reduced.

[0333] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors include R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a B pixel, and a W (white) pixel. Like the column, two colors of RGB make up one color element, and two different colors are created by the color element. Alternatively, you can select one or more colors such as yellow, cyan, magenta, etc. for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. The present invention can also be applied to display devices such as those shown in the accompanying drawings.

[0334] In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) uses white light ( In order to display full color on the display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B) Yellow (Y) and other colors can be used in combination as appropriate. The color reproducibility can be improved compared to when no color layer is used. By arranging a region having a colored layer and a region not having a colored layer, the region not having a colored layer can be The white light in the region may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the light emission by about 30%. When using a device to display full color, R, G, B, Y, and white (W) are It is also possible to emit light from an element having a luminescent color. In some cases, power consumption can be reduced even further than when the

[0335] In this embodiment, a liquid crystal element and an EL element are used as display elements. 28 and 29. Note that FIG. 28 shows the area indicated by the dashed line QR in FIG. 27. 29 is a cross-sectional view of the display device, which uses a liquid crystal element as the display element. 27 is a cross-sectional view taken along the dashed line QR, and shows a configuration in which an EL element is used as a display element. is.

[0336] First, the common parts shown in Figures 28 and 29 will be explained, and then the different parts will be explained. This will be explained below.

[0337] <Explanation of Common Parts of the Display Device> The display device 700 shown in FIGS. The wiring section 711, the pixel section 702, the source driver circuit section 704, and the FPC terminal section 70 8. The wiring portion 711 has a signal line 710. 702 includes a transistor 750 and a capacitor 790. The unit 704 includes a transistor 752 .

[0338] The transistors 750 and 752 may be the transistors shown above. can.

[0339] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The transistor has a low current value in an off state (off-state current value). Therefore, the retention time of the electric signals such as the image signals can be extended, and the power supply When it is on, the write interval can be set longer. Therefore, the frequency of refresh operations can be reduced. This has the effect of reducing power consumption.

[0340] In addition, the transistor described in Embodiment 1 can be used as a transistor in a pixel portion. On the other hand, the transistors used in the drive circuit section are Lo It is preferable to use a V-type transistor in the driver circuit section. For example, a transistor having a Lov type structure may be used. The transistor includes a first gate electrode, a second gate electrode, an oxide semiconductor film, a source electrode, and a By changing the pattern of the drain electrode, it is possible to create different types of pixel. The switching transistor in the drive circuit and the driver transistor in the drive circuit are made of the same material. In addition, the transistor in the pixel portion can be formed on a substrate. By using a transistor, it is possible to reduce the parasitic capacitance, This allows the time constant during switching operation to be reduced. It is possible to manufacture a large, high-definition display device. Since there is no need to use semiconductor devices formed from silicon wafers, etc., The number of points can be reduced.

[0341] The capacitor 790 has a structure in which a dielectric is provided between a pair of electrodes. One electrode of the transistor 790 functions as the first gate electrode of the transistor 750. The other electrode of the capacitor 790 is formed using a conductive film formed in the same process as the conductive film. A conductive film is used to function as a source electrode and a drain electrode of the transistor 750. The dielectric sandwiched between the pair of electrodes functions as a gate insulating film of the transistor 750. A functional insulating film is used.

[0342] 28 and 29, the transistor 750, the transistor 752, and the capacitor The insulating films 764, 766, and 768, the oxide semiconductor film 767, and the planarization film 768 are formed over the capacitor 790. An insulating film 770 is provided.

[0343] The insulating films 764, 766, and 768 are the same as the insulating film 114 shown in the previous embodiment. , 116, 118 can be formed using the same materials and manufacturing methods. The oxide semiconductor film 767 may be formed using the same material as the oxide semiconductor film 117 described in the above embodiment. The planarization insulating film 770 can be formed by the same method as above. resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin Heat-resistant organic materials such as grease and epoxy resin can be used. The planarization insulating film 770 may be formed by stacking a plurality of insulating films formed from the same material. The planarization insulating film 770 may not be provided.

[0344] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 75. 0, 752 source electrode and drain electrode, for example, a conductive film formed in a different process The signal line 710 may be formed of, for example, a copper element. When materials containing ZnO are used, signal delays caused by wiring resistance are minimal, making it possible to display on a large screen. It becomes Noh.

[0345] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the drain electrode. The terminal of the PC 716 is electrically connected via an anisotropic conductive film 780 .

[0346] The first substrate 701 and the second substrate 705 may be made of, for example, glass. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0347] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled. It should be noted that a spherical spacer may be used as the structure 778. In this embodiment, the structure 778 is provided on the first substrate 701 side. For example, a structure 778 may be provided on the second substrate 705 side, or Alternatively, the structure 778 may be provided on both the first substrate 701 and the second substrate 705. .

[0348] On the second substrate 705 side, there is a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, a light-shielding film 738, and a film that contacts the colored film 736 An insulating film 734 is provided.

[0349] <Configuration example of a display device using a liquid crystal element as a display element> A display device 700 shown in FIG. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. The display device 700 shown in FIG. The orientation of the liquid crystal layer 776 is changed by the voltage, thereby controlling the light transmission or non-transmission. The image can be displayed.

[0350] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. 28 uses external light and emits light through a conductive film 772. and displays the light through the colored film 736, which is a so-called reflective color liquid crystal display device.

[0351] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a light-transmitting property in visible light can be used. For example, a material containing one of the elements selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed using a material containing silver or silver. A conductive film that is reflective in visible light is used.

[0352] In addition, when a conductive film that is reflective to visible light is used as the conductive film 772, the conductive film The film may have a laminated structure. For example, an aluminum film having a thickness of 100 nm is formed as a lower layer, A 30 nm thick silver alloy film (e.g., an alloy film containing silver, palladium, and copper) is formed on the upper layer. The above-described structure provides the following excellent effects.

[0353] (1) The adhesiveness between the base film and the conductive film 772 can be improved. (2) The chemical solution This allows the aluminum film and the silver alloy film to be etched at the same time. The cross-sectional shape of the conductive film 772 can be made into a good shape (for example, a tapered shape). The reason for this is that the etching rate of aluminum films with chemicals is slower than that of silver alloy films. Or, after etching the upper silver alloy film, when the lower aluminum film is exposed, the silver alloy The electrons are taken from aluminum, which is a metal less noble than gold, in other words, a metal with a high tendency to ionize. The etching of the silver alloy film is suppressed by pulling out the film, and the etching of the underlying aluminum film is suppressed. This is because the progression is faster.

[0354] In the display device 700 shown in FIG. 28, the planarization insulating film 770 of the pixel section 702 The unevenness is formed in a part of the insulating film 770 by, for example, forming the planarization insulating film 770 with an organic resin film or the like. The reflection current can be formed by forming a film on the surface of the organic resin film and providing irregularities on the surface of the organic resin film. The conductive film 772 that functions as an electrode is formed along the above-mentioned unevenness. When light is incident on the conductive film 772, it is possible for the light to be diffused and reflected on the surface of the conductive film 772. This makes it possible to improve visibility.

[0355] The display device 700 shown in FIG. 28 is a reflective color liquid crystal display device. However, the conductive film 772 is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. A transmissive color liquid crystal display device may be formed by using the above. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0356] Although not shown in FIG. 28, the conductive films 772 and 774 are in contact with the liquid crystal layer 776. Although not shown in FIG. Optical members (optical substrates) such as optical members, phase difference members, and anti-reflection members may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Critters, sidelights, etc. may also be used.

[0357] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0358] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in a liquid crystal layer. It has a short response time, is optically isotropic so alignment treatment is not required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. Therefore, it is possible to prevent electrostatic breakdown caused by the electrostatic discharge, and to prevent defects in the liquid crystal display device during the manufacturing process. Damage can be reduced.

[0359] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr It can be used in dielectric liquid crystal mode. .

[0360] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode Mode, ASV mode, etc. can be used.

[0361] In display devices using liquid crystal elements, image data is usually rewritten at a rate of 60 Hz or so. However, since the off-state current of a transistor using an oxide semiconductor is extremely low, For example, it is possible to reduce the write frequency to 15Hz or even 1H By reducing the write frequency, for example, the power consumption This has the effect of reducing

[0362] <Display Device Using Light-Emitting Devices as Display Elements> A display device 700 shown in FIG. 29 uses light-emitting devices The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 shown in FIG. 29 includes an EL layer 786 that emits light. By doing so, an image can be displayed.

[0363] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one electrode of the display element. In this case, a conductive film that is light-transmitting or a conductive film that is reflective to visible light can be used. Examples of conductive films that are transparent to visible light include indium (In) and zinc (Zn). It is recommended to use a material containing one of the following elements: (Zn) and tin (Sn). As the reflective conductive film, for example, a material containing aluminum or silver is preferably used. stomach.

[0364] 29, an insulating film is formed on the planarization insulating film 770 and the conductive film 784. An insulating film 730 is provided. The insulating film 730 covers part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to, for example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0365] A colored film 736 is provided at a position overlapping the light-emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided in the position where the light-shielding film 738 is to be drawn, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is exemplified. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0366] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0367] (Fourth embodiment) <Examples of problems that can be solved by one embodiment of the present invention> The problem will be explained with reference to FIGS. 32 and 33. Specifically, When the liquid crystal element is driven with an AC voltage to prevent deterioration of the liquid crystal, This will explain the problem of eye fatigue caused by blacking, which causes eye strain to the user of the display device.

[0368] <<Configuration of display unit and pixel>> Block diagram of the display unit provided in the display device, The figure shows an equivalent circuit diagram of the pixel circuit and a schematic diagram of the transmittance-voltage characteristics of polarized light passing through the liquid crystal element. Shown in Figure 32.

[0369] FIG. 33 is a timing chart and a diagram illustrating the operation of a pixel circuit included in a pixel portion of a display device. FIG.

[0370] <<Regarding the Display Device>> The display unit 930 is a part of the display device. The display unit 930 includes a pixel unit 9 31 (see FIG. 32(A)).

[0371] The pixel section 931 includes a plurality of pixels 931p, and a first driving signal (also referred to as an S signal) is applied to each column of the pixels 931p. A plurality of signal lines S (S1 to Sx) that can supply a second signal to each row of the pixels 931p. It has a plurality of scanning lines G (G1 to Gy) that can supply drive signals (also called G signals).

[0372] Each pixel 931p is connected to at least one of the scanning lines G and at least one of the signal lines S. It is being done.

[0373] Note that a signal for selecting the pixel 931p for each row may be used as the G signal, and the pixel 931p may be selected according to the G signal. An S signal including image gradation information may be supplied to the pixel 931p.

[0374] The G driving circuit 932 can control the input of the G signal to the scanning line G. The S driving circuit 933 can control the input of the G signal to the scanning line G. You can control the input of S signals to S.

[0375] The pixel 931p illustrated here includes a liquid crystal element 935LC and the liquid crystal element 935LC. It has a pixel circuit 934 (see FIG. 32(B)).

[0376] The pixel circuit 934 is a transistor that can control the supply of an S signal to the liquid crystal element 935LC. It has a dial 934t.

[0377] The gate of the transistor 934t is electrically connected to one of the scan lines G. The first electrode (either the source or the drain) of the transistor 934t is connected to one of the signal lines S. The second electrode (the other of the source and drain) of the transistor 934t is electrically connected to ) is electrically connected to the first electrode of the liquid crystal element 935LC. The electrode 2 is electrically connected to a common line C.

[0378] The transistor 934t has a parasitic capacitance 934tc. The capacitance between the gate electrode and the source or drain and the capacitance between the gate electrode and the channel Includes the capacity to

[0379] In addition, the pixel circuit 934 maintains a voltage between the first electrode and the second electrode of the liquid crystal element 935LC. The capacitor 934c may include a capacitor element 934c.

[0380] The transistor 934t receives a G signal at its gate electrode and a S signal at its liquid crystal element 935LC The input to the inverter can be controlled as a single switching element.

[0381] The liquid crystal element 935LC has a first electrode, a second electrode, and a gap between the first electrode and the second electrode. The liquid crystal layer includes a liquid crystal material to which a voltage of .gtoreq..gtoreq.1 ... is applied.

[0382] The transmittance of polarized light passing through the liquid crystal element 935LC depends on the alignment state of the liquid crystal molecules contained in the liquid crystal layer. The alignment state of the liquid crystal layer depends on the voltage applied between the first electrode and the second electrode of the liquid crystal element 935LC. Therefore, the voltage corresponding to the S signal containing the gradation information of the image is applied to the liquid crystal. When applied between the first electrode and the second electrode of the liquid crystal element 935LC, The transmittance of polarized light can be set according to the grayscale information.

[0383] <Characteristics of Liquid Crystal Elements> The transmittance of polarized light passing through a normally white liquid crystal element and The relationship between the voltage applied to the liquid crystal element and the polarized light is shown in FIG. The horizontal axis corresponds to the ratio of the voltage applied to the first electrode relative to the voltage applied to the second electrode.

[0384] The transmittance of polarized light passing through a normally white liquid crystal element is determined by the ratio of the first electrode to the second electrode. When the voltage between them is 0, the transmittance is high, and when the voltage is increased, the transmittance decreases. When this element is used in a transmissive liquid crystal display device, white is displayed when the voltage of the S signal is close to 0, and when it is large, Can display black.

[0385] It is known that applying a DC voltage to the liquid crystal layer of a liquid crystal element for a long period of time will cause the liquid crystal element to deteriorate. To avoid this, the liquid crystal element must be driven using an AC voltage.

[0386] To maintain the transmittance of polarized light passing through the liquid crystal element at transmittance Ta, the first electrode The polarity of the electrode can be switched between positive (potential +Va) and negative (potential -Va). In other words, the liquid crystal element may be driven using an AC voltage whose amplitude is kept constant.

[0387] <<About the driving method of the liquid crystal element>> The liquid crystal element 935LC of the pixel circuit 934 is driven by an AC voltage. This section explains how to drive the device.

[0388] The potential Vg of the G signal input to the gate electrode of the transistor 934t of the pixel circuit 934 and 33A shows a timing chart of the potential Vsa of the S signal input to the first electrode. Also, a timing chart of the potential Vs output from the second electrode is shown in FIG. The potential Vs is also a potential input to the first electrode of the liquid crystal element 935LC.

[0389] The S drive circuit 933 receives the secondary image signal and outputs the S signal. The secondary image signal may have the same amplitude as the primary image signal. The difference between the potential of the image signal and the reference potential Vsc can be set as the amplitude of the secondary image signal. The secondary image signal is a signal whose polarity is inverted for each successive frame.

[0390] The period from when one scanning line G provided in the pixel portion 931 is selected until when it is selected again is defined as 1 Therefore, the G signal is input to the gate electrode of the transistor 934t every frame. When the G signal is high, the potential Vg is VgH. When the signal is low, the potential Vg is VgL.

[0391] <<Feedthrough Occurrence>> The potential Vs of the second electrode of the transistor 934t is As a result, the voltage Vg input to the first electrode of the transistor 934t is This potential is different from the potential Vsa of the S signal (same as the potential of the secondary image signal). Two periods in which the potential is higher than the sub-potential Vsc by Vsa1 and lower by Vsa2. The secondary image signal is input to the S drive circuit, which generates an S signal with the same potential as the secondary image signal. This will be explained using an example where

[0392] In the first frame F1, the difference between the potential Vg of the gate electrode and the potential Vsa of the S signal is When the threshold voltage Vth of the transistor 934t is exceeded, the transistor 934t is turned on. The potential Vs rises to the potential Vsa.

[0393] After that, when the difference between the potential Vg of the gate electrode and the potential Vsa of the S signal becomes less than the threshold voltage Vth, , the transistor 934t is turned off, and the potential V The potential of the second electrode of the transistor 934t is lower than the potential Vsa of the S signal by ΔV1. The amount by which the potential Vs drops from the potential Vsa of the S signal is defined as a first feedthrough ΔV1. .

[0394] In the second frame F2, the polarity-inverted secondary image signal is input to the S driver circuit 933. The difference between the potential Vg and the potential Vsa of the S signal is the threshold voltage Vth of the transistor 934t. When the voltage exceeds the threshold voltage, the transistor 934t is turned on, and the second electrode of the transistor 934t The potential Vs of the S signal drops to the potential Vsa of the S signal.

[0395] After that, when the difference between the potential Vg of the gate electrode and the potential Vsa of the S signal becomes less than the threshold voltage Vth, , the transistor 934t is turned off, and the potential V The potential Vs of the second electrode of the transistor 934t drops by ΔV2 from the potential Vsa. The amount of drop from the potential Vsa is defined as a second feedthrough ΔV2.

[0396] <About the size of the feedthrough> The feedthrough is the parasitic capacitance of the transistor 934t. This occurs due to capacitive coupling by the quantity 934tc (see Figure 32(B)). The magnitude ΔV of the voltage Vg can be predicted using the following formula (3). LH is the gate voltage The amplitude of the potential of the electrodes (the difference between VgH and VgL), CL is the capacitance of the liquid crystal element 935LC, and Cs is the capacitance The capacitance of element 934c, Cdg, is the parasitic capacitance 934tc of transistor 934t.

[0397]

number

[0398] <<Asymmetry of the feedthrough size>> The gate electrode of transistor 934t The input G signal is not a perfect square wave. For example, if the G signal has a shorter upper base than the lower base, When the potential Vs of the input S signal is low, the trigger The time that the transistor 934t is in the on state is increased. This increases the value of Cdg. Since the second feedthrough ΔV2 varies depending on the influence of the filter capacitance, the first feedthrough Δ V1, and the magnitude of the first feedthrough ΔV1 and the second feedthrough ΔV2 The size becomes asymmetric.

[0399] By keeping the waveform of the G signal constant, the first feedthrough ΔV1 and the second feedthrough Even if the magnitude of the feedthrough ΔV2 becomes asymmetric, the feedthrough value is input. This can be predicted for each potential of the S signal.

[0400] <<Effect of feedthrough on the transmittance of polarized light passing through a liquid crystal element>> Amplitude is constant When a liquid crystal element is driven using an AC voltage maintained at is kept constant.

[0401] However, if feedthrough occurs in the pixel circuit, the transmission of polarized light passing through the liquid crystal element The rate does not remain constant.

[0402] The first feedthrough ΔV1 is a differential voltage between the potential Vs of the second electrode of the transistor 934t and the reference potential Vs. The second feedthrough acts to reduce the difference |Vs-Vsc| between the voltages Vsc and Vs. ΔV2 is the difference between the potential Vs of the second electrode of the transistor 934t and the reference potential Vsc |Vs- Vsc| increases (see FIG. 33(C)).

[0403] As a result, when the liquid crystal element 935LC is a normally white type, The transmittance of polarized light transmitted through C is higher than the transmittance Ta in the first frame F1 by ΔT1. In the second frame F2, the transmittance is lower than Ta by ΔT2 (see FIG. 3). 3(D)). The common potential Vcom is input to the second electrode of the liquid crystal element 935LC. This is the conducting potential and is equal to the reference potential Vsc.

[0404] As a result, the transmittance of polarized light passing through the liquid crystal element 935LC of the display unit of the display device changes (specifically, In practical terms, this is a change equivalent to the sum of ΔT1 and ΔT2, and flicker is observed.

[0405] Normally, this effect is made invisible by adjusting the common potential. If there is a problem, flicker may be observed. However, this would affect the aperture ratio, so we If the impact of the feed-through itself is kept small, the impact itself is less likely to be apparent.

[0406] [About eye fatigue] There is nervous system eye fatigue.

[0407] Nervous system fatigue can be caused by looking at the light emitted by the display or a flashing screen for a long time, and the brightness of the screen can be It stimulates the retina, nerves, and brain, causing fatigue. The phenomenon in which the display blinks rapidly is called flicker, and this type of flicker is caused by nervous system fatigue. causes labor.

[0408] As described above, when an AC voltage is applied to the liquid crystal element to prevent deterioration of the liquid crystal element, This causes flicker due to the light, which can cause eye fatigue for users of the display device. .

[0409] The transistor described in the first embodiment has a small parasitic capacitance and a high field-effect mobility. By using this high-performance transistor with low parasitic capacitance, As described in the embodiments, various defects caused by feedthroughs can be reduced. This can be done.

[0410] (Embodiment 5) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0411] The display device shown in FIG. 30(A) has a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504), and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. That's fine.

[0412] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or all of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Bearing). It can be implemented by

[0413] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter referred to as a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a), for supplying signals (data signals) for driving the display elements of the pixels. The source driver 504b includes a driving circuit such as the circuit (hereinafter referred to as a source driver 504b).

[0414] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is inputted through the terminal section 507, and a signal for outputting the shift register is outputted. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a receives a scanning signal and outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the plurality of gate drivers 504a drive the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it into the initialization signal However, the gate driver 50 has a function of supplying 4a may also provide other signals.

[0415] The source driver 504b includes a shift register and the like. Through the terminal section 507, signals for driving the shift register as well as the source of the data signal are transmitted. The source driver 504b receives a signal (image signal) that is to be output from the pixel circuit The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0416] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches, The image signal can be time-divided and output as a data signal. The source driver 504b may be configured using the same.

[0417] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is input via the data line DL, and a data signal is given via one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or less than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via the input terminal 504a (n is a natural number equal to or less than Y).

[0418] The protection circuit 506 shown in FIG. 30(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal section 507. Alternatively, the protection circuit 506 may be formed by wiring between the source driver 504b and the terminal section 507. The terminal section 507 can be connected to a power supply and a line from an external circuit to the display device. This refers to the part where terminals for inputting control signals and image signals are provided.

[0419] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 This is a circuit that brings one wire into electrical continuity with another wire.

[0420] As shown in FIG. 30A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 50. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrents caused by electrostatic discharges and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a configuration in which the protection circuit 506 is connected to the source driver 504b Alternatively, a configuration in which a protection circuit 506 is connected to the terminal portion 507 may be used. It can also be done as follows.

[0421] In FIG. 30(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a separately prepared source driver circuit is formed. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is implemented. It may also be configured to be equipped with

[0422] Furthermore, the plurality of pixel circuits 501 shown in FIG. 30(A) may be, for example, a configuration shown in FIG. 30(B). It can be said that:

[0423] The pixel circuit 501 shown in FIG. 30B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiments. can be applied.

[0424] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0425] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mode) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li Quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electric Carrier Board) or the like. Ally Controlled Birefringence mode, PDLC (P Polymer Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of materials can be used.

[0426] In the pixel circuit 501 in the mth row and the nth column, the source electrode or the drain electrode of the transistor 550 One of the electrodes is electrically connected to the data line DL_n, and the other is connected to a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the electrodes of the scan line G. L_m. The transistor 550 can be turned on or off. This provides a function of controlling the writing of data signals.

[0427] One of the pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0428] For example, in a display device having the pixel circuit 501 of FIG. 30(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 550 is turned on and data of the data signal is written.

[0429] The pixel circuit 501 in which data has been written is turned off by turning off the transistor 550. By repeating this process for each row, an image can be displayed.

[0430] Furthermore, the plurality of pixel circuits 501 shown in FIG. 30(A) may be, for example, a configuration shown in FIG. 30(C). It can be said that:

[0431] The pixel circuit 501 shown in FIG. 30C includes transistors 552 and 554 and a capacitor. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either one or both of the above. .

[0432] One of the source and drain electrodes of the transistor 552 is supplied with a data signal. The transistor 5 is electrically connected to a wiring (hereinafter referred to as a data line DL_n). The gate electrode 52 is connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is applied. electrically connected.

[0433] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0434] One of the pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0435] The capacitor 562 functions as a storage capacitor for holding written data.

[0436] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0437] One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b. The other is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0438] The light emitting element 572 may be, for example, an organic electroluminescence element (also known as an organic EL element). However, the light emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0439] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0440] In a display device having the pixel circuit 501 of FIG. 30(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0441] The pixel circuit 501 to which the data has been written is turned off by turning off the transistor 552. Furthermore, the transistor 554 is held in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted at a brightness that corresponds to the flow rate. By repeating this process row by row, an image can be displayed.

[0442] In the region 580 where the GL_m line and the DL_n line overlap shown in FIGS. 30(B) and 30(C), the parasitic Capacity C GD Similar to the parasitic capacitance of a transistor, the parasitic capacitance C GD If it is large, Since the rising time is slow, it becomes difficult to increase the panel size of the display device. Therefore, it is preferable to reduce the capacitance between the GL_m line and the DL_n line.

[0443] Usually, an insulating layer is formed between the GL_m line and the DL_n line in the same process as the first gate insulating layer. The film 106 and the insulating film 107 are present. Therefore, the insulating film 107 is formed between the GL_m line and the DL_n line. 106 and insulating film 107, and inserting an insulating film to make the total insulating film thicker. is preferable because it can reduce the parasitic capacitance of the transistor.

[0444] FIG. 31(A) shows a top view of the vicinity of region 580 in FIGS. 30(B) and 30(C). A cross-sectional view of Z1-Z2 of A) is shown in Figure 31(B). For example, as shown in Figures 31(A) and (B), As shown in FIG. 1, the insulating film 106, the insulating film 107, and the insulating film 121 are formed between the GL_m line and the DL_n line. In this laminated structure, the insulating film 106 and the insulating film 107 are between the GL_m line and the DL_n line. The thickness of the insulating film between the GL_m line and the DL_n line is thicker than in the case of only one line. Parasitic capacitance C between DL_n lines GD Also, the parasitic capacitance C GD To reduce Therefore, it is preferable to use a material with a low dielectric constant for the insulating film 121.

[0445] The insulating film 121 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or an aluminum oxide film. aluminum film, aluminum oxide nitride film, aluminum nitride oxide film, aluminum nitride film, etc. You can use:

[0446] The insulating film 121 is formed by a sputtering method, a CVD method (thermal CVD method, MOCVD method, PECVD method, etc. The layer can be formed by using a method such as MBE, ALD, or PLD. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, the coating property is improved. In addition, to reduce damage caused by plasma, The CVD method, the MOCVD method or the ALD method is preferred.

[0447] Furthermore, a silicon carbonitride film (SiCN film) can be used as the insulating film 121. USG (Undoped Silicate Glass), BPSG (Boron Phosphorus Silicate Glass), BSG (Borosili USG, BPSG, etc. can be used by the atmospheric pressure CVD method. Alternatively, for example, HSQ (hydrogen silsesquioxane) or the like may be used by coating. It may be formed using

[0448] The insulating film 121 may be a laminate of two or more layers. Alternatively, a USG may be laminated on the insulating film.

[0449] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0450] (Sixth embodiment) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be explained with reference to FIGS. 34, 35 and 36.

[0451] The display module 8000 shown in FIG. 34 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003 and Display panel 8006, backlight 8007, frame 8009, printed circuit board 801 0, has battery 8011.

[0452] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0453] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 8006.

[0454] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of 006 to make it an optical touch panel.

[0455] The backlight 8007 has a light source 8008. In FIG. Although the configuration in which the light source 8008 is disposed on the base 8007 has been illustrated, the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 8007 may not be provided.

[0456] The frame 8009 has a function of protecting the display panel 8006 and also a function of preventing the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the The frame 8009 may also function as a heat sink.

[0457] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. This can be omitted if a commercial power source is used.

[0458] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0459] 35(A) to 35(G) are diagrams showing electronic devices. These electronic devices are A body 9000, a display unit 9001, a speaker 9003, operation keys 9005 (power switch, includes an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, speed, Acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electricity Measures field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared It may have a microphone 9008, etc.

[0460] The electronic devices shown in FIGS. 35A to 35G can have various functions. For example, functions to display various information (still images, videos, text images, etc.) on the display, Touch panel function, calendar, date or time display function, various software ( It has the function of controlling processing by using a program, wireless communication function, and various functions using wireless communication function. Functions for connecting to computer networks, transmitting various data using wireless communication functions, or receiving the program or data recorded on the recording medium, and It is possible to have a function to display the information on the display unit. The functions that the electronic device shown in the figure can have are not limited to these, and it may have various functions. Although not shown in FIGS. 35(A) to 35(G), the electronic device may include: The electronic device may have a plurality of display units. The function to take pictures, take videos, and save the images to a recording medium (external or built-in to the camera) ) and a function to display the captured image on the display unit.

[0461] The electronic devices shown in FIGS. 35(A) to 35(G) will be described in detail below.

[0462] FIG. 35(A) is a perspective view showing a mobile information terminal 9100. The display portion 9001 is flexible. The display unit 9001 can be incorporated along the screen. It is equipped with a touch panel, and can be operated by touching the screen with a finger or a stylus. By touching the icon displayed on the display 9001, the application can be started. can.

[0463] 35(B) is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 is For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, it can be used as a smartphone. The speaker 9003, the connection terminal 9006, the sensor 9007, etc. are omitted in the illustration. It can be installed in the same position as the mobile information terminal 9100 shown in FIG. The information terminal 9101 can display text and image information on multiple surfaces. For example, Three operation buttons 9050 (also called operation icons or simply icons) are displayed on the display unit 900. 9051 shown in a dashed rectangle can be displayed on one side of the display unit 90. 01. An example of the information 9051 is an e-mail A display that notifies you of incoming calls, SNS (social networking services), etc. , subject of email or SNS, sender name of email or SNS, date and time, time, The remaining battery level, antenna reception strength, etc. Or, information 9051 is displayed. In place of the information 9051, an operation button 9050 or the like may be displayed.

[0464] 35(C) is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 is , and has the function of displaying information on three or more surfaces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 stores the portable information terminal 9102 in the breast pocket of his / her clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed in a position that can be observed from above the mobile information terminal 9102. The user can view the display without taking the mobile information terminal 9102 out of his pocket. You can check the call and decide whether to accept it or not.

[0465] 35(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is suitable for mobile phone calls, e-mail, document browsing and writing, music playback, and internet communications. It is possible to run various applications such as computer games. The display surface of the display unit 9001 is curved, and the display is performed along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, handset The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. It may also be possible to supply power wirelessly without going through 6.

[0466] 35(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 35(E) is a perspective view of the portable information terminal 9201 in an unfolded state, and FIG. (F) shows the mobile information terminal 9201 being changed from one of the unfolded state and the folded state to the other. 35(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded, and is easily portable when unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 01 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. This allows the portable information terminal 9201 to be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0467] 36(A) to 36(G) are diagrams showing electronic devices. These electronic devices are Body 5000, display unit 5001, speaker 5003, LED lamp 5004, operation key 50 05 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 ( Force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances , sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, 5008, a microphone 5009, etc. can.

[0468] FIG. 36(A) shows a mobile computer, which includes, in addition to the above, a switch 5009 , an infrared port 5010, etc. FIG. 36(B) shows a portable terminal equipped with a recording medium. A portable image reproducing device (for example, a DVD reproducing device) is also included. It can have a display unit 5002, a recording medium reading unit 5011, etc. It is a group-type display, and in addition to the above, it has a second display unit 5002, a support unit 5012 , earphones 5013, etc. FIG. 36(D) shows a portable gaming machine. In addition to the above, it may have a recording medium reading unit 5011, etc. It is a digital camera with a TV receiving function, and in addition to the above, it also has an antenna 5014, The mobile phone may have a shutter button 5015, an image receiving unit 5016, etc. It is a belt-type gaming machine, and in addition to the above, it has a second display unit 5002, a recording medium reading unit 5011, , etc. FIG. 36(G) shows a portable television receiver, which can be used with the above-mentioned In addition, it may have a charger 5017 capable of transmitting and receiving signals, etc.

[0469] The electronic devices shown in FIGS. 36A to 36G can have various functions. For example, functions to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software ( It has a function to control processing by a program, a wireless communication function, and various controls using the wireless communication function. Functions for connecting to computer networks, transmitting various data using wireless communication functions, The function of receiving, reading out the program or data recorded on the recording medium and displaying it on the display Furthermore, in an electronic device having multiple display units, In this case, one display section is used mainly to display image information, and another display section is used mainly to display text information. or a function to display images that take parallax into account on multiple displays to create a three-dimensional effect. Furthermore, in electronic devices having an image receiving unit, The camera has the functions to take still images, record videos, and automatically or manually correct captured images. function to correct the image, to save the captured image to a recording medium (external or built-in to the camera), 36(A) to 36(B) can have a function of displaying the image on the display unit. The functions that the electronic device shown in 6(G) can have are not limited to these, and various functions can be It can have.

[0470] The electronic device described in this embodiment has a display unit for displaying some information. The display device described in Embodiment 5 can be applied to the display portion. do.

[0471] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. It can also be applied to vessels.

[0472] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0473] (Embodiment 7) <Memory Device> A memory device in which a transistor according to one embodiment of the present invention is used and power is supplied A semiconductor device that can retain its memory contents even when the device is not connected to a power source, and has no limit on the number of times it can be written to. An example of the device (memory device) is shown in Figure 40. Note that Figure 40(B) shows Figure 40(A) in circuit diagram form. This is what was done.

[0474] The semiconductor device shown in FIGS. 40(A) and 40(B) includes a transistor 3 using a first semiconductor material. 200 and a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that the transistor described in Embodiment 1 is used as the transistor 3300. It can be used.

[0475] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 3300 has a small off-state current, so that This means that the memory contents can be retained for a longer period of time without requiring a refresh operation. Alternatively, the semiconductor memory device may be one in which the frequency of refresh operations is extremely low. This makes it possible to sufficiently reduce power consumption.

[0476] In FIG. 40B, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode and the drain electrode of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is connected to the capacitor 3400. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0477] In the semiconductor device shown in FIG. 40A, the potential of the gate electrode of the transistor 3200 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0478] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is A predetermined charge is applied (write). Here, the charge that gives two different potential levels is (hereinafter referred to as Low level charge and High level charge) After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, the gate of the transistor 3200 The charge applied to the port electrode is retained (retention).

[0479] Since the off-state current of the transistor 3300 is extremely small, the gate voltage of the transistor 3200 The charge on the pole is maintained for a long period of time.

[0480] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of transistor 3200, the second wiring 3002 assumes different potentials . Generally, if transistor 3200 is an n-channel type, the apparent threshold value Vth_H when a high-level charge is applied to the gate electrode of transistor 3200 is lower than the apparent threshold value Vth_L when a low-level charge is applied to the gate electrode of transistor 3200. Here, the apparent threshold voltage is defined as the potential of the fifth wiring 3005 required to turn transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3005 to a potential V0 between Vth_H and Vth_L , the charge applied to the gate electrode of transistor 3200 can be discriminated . For example, in writing, if a high-level charge was applied, when the potential of the fifth wiring 3005 becomes V0 (> Vth_H), transistor 3200 enters the "on state" . If a low-level charge was applied, even when the potential of the fifth wiring 3005 becomes V0 (< Vth_L), transistor 3200 remains in the "off state" . Therefore, by discriminating the potential of the second wiring 3002, the stored information can be read out . When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. For example, in a memory cell from which information is not read, a potential such that transistor 3200 enters the "off state" regardless of the gate state, that is, a potential smaller than Vth_H is applied to the fifth wiring 3005, so that only the information of the desired memory cell can be read . Or, in a memory cell from which information is not read, the gate

[0481] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. For example, in a memory cell from which information is not read, a potential such that transistor 3200 enters the "off state" regardless of the gate state, that is, a potential smaller than Vth_H is applied to the fifth wiring 3005, so that only the information of the desired memory cell can be read . Or, in a memory cell from which information is not read, the gate state, a potential lower than Vth_H is applied to the fifth wiring 3005 so that only the information of the desired memory cell can be read. Alternatively, in a memory cell from which information is not read, the gate ​​ The potential at which transistor 3200 is in the "on" state regardless of the state of the port, i.e. By applying a potential higher than Vth_L to the fifth wiring 3005, the information of the desired memory cell is It is sufficient to have a configuration in which only the information can be read out.

[0482] The semiconductor device shown in FIG. 40(C) is different from the semiconductor device shown in FIG. 40(A) in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and store information. It is possible.

[0483] Next, reading of information from the semiconductor device shown in FIG. When the capacitor 3300 is turned on, the third wiring 3003 and the capacitor 3400, which are in a floating state, becomes conductive, and charge is redistributed between the third wiring 3003 and the capacitor 3400. The potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the capacitance element. The potential of one of the electrodes of the capacitor 3400 (or the charge stored in the capacitor 3400) It takes different values.

[0484] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the third The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell 250 is If the potential of one of the electrodes of the element 3400 takes two states, V1 and V0 (V1>V0), then: The potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0485] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0486] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be stacked on the driver circuit.

[0487] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0488] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high speed operation can be easily achieved.

[0489] The storage device shown in this embodiment is, for example, a CPU (Central Processing Unit). g Unit), DSP (Digital Signal Processor), LSI, PLD (Programmable Logic Device) etc. I, RF-ID (Radio Frequency Identification) can also be applied.

[0490] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0491] (Embodiment 8) In this embodiment, an RF including the transistor or memory device exemplified in the above embodiment is The device tag will be explained with reference to FIG.

[0492] The RF device tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. The information is stored in the storage device and transmitted to and from the outside using a non-contact means, such as wireless communication. Due to these characteristics, RF device tags can identify objects by reading their individual information. It can be used for individual authentication systems that identify products. Extremely high reliability is required for use.

[0493] The structure of the RF device tag will be described with reference to Fig. 41. Fig. 41 shows the structure of the RF device tag. FIG. 1 is a block diagram showing a configuration example of the

[0494] As shown in FIG. 41, the RF device tag 800 includes a communicator 801 (interrogator, reader / writer) 803 is transmitted from an antenna 802 connected to the The RF device tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, demodulation circuit 807, modulation circuit 808, logic circuit 809, memory circuit 810, ROM8 11. The demodulation circuit 807 includes a transistor having a rectifying function. A material capable of sufficiently suppressing the directional current, for example, an oxide semiconductor, is used. This can suppress the degradation of the rectification action caused by the reverse current, and the output of the demodulation circuit can be In other words, the output of the demodulation circuit is linearly proportional to the input of the demodulation circuit. The data transmission format is a pair of coils arranged facing each other and mutually inductively coupled. The electromagnetic coupling method uses induction to communicate, the electromagnetic induction method uses an induced electromagnetic field to communicate, and the radio wave The RF device tag 8 shown in this embodiment is 00 can be used in either method.

[0495] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 rectifies an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side of the rectifier circuit 805. A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent power above a certain level from being input to the subsequent circuit. This is a circuit for controlling the

[0496] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the rising edge of the stable power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0497] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the

[0498] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. It is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for

[0499] The above-mentioned circuits can be selected or removed as needed.

[0500] Here, the memory cell described in the previous embodiment can be used for the memory circuit 810. Memory cells using oxide semiconductors can retain information even when the power supply is cut off. Therefore, it can be suitably used for RF device tags. The power (voltage) required to write data to a memory cell is significantly higher than that of conventional non-volatile memory. It is so small that there is no difference in the maximum communication distance when reading and writing data. Furthermore, there is a risk of insufficient power when writing data, causing malfunction or erroneous writing. This can prevent this from happening.

[0501] In addition, a memory cell using an oxide semiconductor can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer A separate command is provided to write data to the memory, preventing users from freely rewriting it. It is preferable to have the manufacturer write a unique number on the product before shipping it. By doing so, instead of assigning a unique number to each RF device tag that is produced, This allows the allocation of unique numbers only to non-defective products, eliminating the need for unique numbers after shipment. This prevents continuity and facilitates customer management of products after shipment.

[0502] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0503] (Embodiment 9) In this embodiment, at least the transistors described in the embodiment can be used. A CPU including the storage device described in the previous embodiment will now be described.

[0504] FIG. 42 shows a CPU using the transistors described in the previous embodiments at least in part. FIG. 10 is a block diagram showing the configuration of an example.

[0505] The CPU shown in FIG. 42 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, or the like. A glass substrate or the like is used. The ROM 1199 and the ROM interface 1189 are separately Of course, the CPU shown in FIG. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, The configuration including the CPU or arithmetic circuit shown in FIG. 42 is regarded as one core, and includes multiple such cores, The CPU may be configured so that each core operates in parallel. The number of bits that can be handled by the data bus is, for example, 8 bits, 16 bits, 32 bits, and 64 bits. It can be something like this.

[0506] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0507] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0508] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by an internal clock generator. Supply to the seed circuit.

[0509] In the CPU shown in FIG. 42, a memory cell is provided in the register 1196. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0510] In the CPU shown in FIG. 42, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0511] FIG. 43 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, a transistor 1210, The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a capacitor.

[0512] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the gate of the transistor 1209 is connected via a load such as a resistor. The configuration will be as follows.

[0513] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., traction) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0514] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connecting portion is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply potential. The other is electrically connected to a wiring (for example, a GND line) that can supply a voltage to the switch 1. 203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) The first terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) ) is electrically connected to the second terminal of the switch 1204 (the source of the transistor 1214). The other of the source and drain is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214). The input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor 1207 are Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. For example, A potential (GND, etc.) or a high power supply potential (VDD, etc.) can be input. The other of the pair of electrodes of the capacitor 1207 is connected to a wiring that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to the other of the pair of electrodes (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input to the Alternatively, a high power supply potential (such as VDD) can be input. The other of the pair of electrodes is a wiring that can supply a low power supply potential (for example, a GND line ) is electrically connected to

[0515] The capacitors 1207 and 1208 are formed by accumulating parasitic capacitances of transistors and wirings. It is possible to omit it by using it sparingly.

[0516] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are controlled by a control signal RD that is different from the control signal WE. Therefore, a conductive state or a non-conductive state between the first terminal and the second terminal is selected, and one of the switches When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no conduction between the terminals.

[0517] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 43, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0518] In FIG. 43, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is passed through logic element 1206 and circuit 1220 to the circuit 1201 is shown as an example, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the input If there is a node that holds a signal whose logical value is the inverted value of the signal input from the input terminal, , the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0519] In addition, in FIG. 43, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed by a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor with a channel formed in a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed of oxide semiconductor films. Alternatively, the memory element 1200 may be implemented by any other element than the transistor 1209. The other transistors may include a transistor in which a channel is formed using an oxide semiconductor film. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may also be a transistor that is connected to the gate of the transistor.

[0520] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0521] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0522] Further, a transistor in which a channel is formed in an oxide semiconductor film has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor film is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, Even when the power supply voltage is not supplied to 200, the signal held in the capacitor element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0523] In addition, by providing the switches 1203 and 1204, the precharge operation Since this is a memory element characterized by performing the above, after the supply of power supply voltage is resumed, the circuit 1201 is restored to its original state. This can shorten the time it takes to re-store the data.

[0524] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal can be accurately read out.

[0525] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0526] In this embodiment, the storage element 1200 is used as a CPU. 200 is equipped with a DSP (Digital Signal Processor), custom L LSIs such as SI and PLD (Programmable Logic Devices), R Also applicable to F-ID (Radio Frequency Identification) It is possible.

[0527] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0528] (Embodiment 10) <Imaging Device> Hereinafter, an imaging device according to one aspect of the present invention will be described.

[0529] 44A is a plan view showing an example of an imaging device 2000 according to one aspect of the present invention. The device 2000 includes a pixel section 2010 and a peripheral circuit 2060 for driving the pixel section 2010. 20, a peripheral circuit 2070, a peripheral circuit 2080, and a peripheral circuit 2090. 010 is a matrix of multiple pixels arranged in p rows and q columns (p and q are integers greater than or equal to 2). The peripheral circuit 2060, the peripheral circuit 2070, the peripheral circuit 2080, and the peripheral The side circuits 2090 are connected to the plurality of pixels 2011, respectively, and drive the plurality of pixels 2011. In this specification, the peripheral circuit 2060, The peripheral circuits 2070, 2080, and 2090 are all referred to as "peripherals." For example, the peripheral circuit 2060 is one of the peripheral circuits. It can be said to be a club.

[0530] The imaging device 2000 preferably includes a light source 2091. It is possible to emit an outgoing light P1.

[0531] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuit may be formed on the substrate on which the pixel section 2010 is formed. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. The peripheral circuits include a peripheral circuit 2060, a peripheral circuit 2070, a peripheral circuit 2080, and a peripheral circuit One or more of the paths 2090 may be omitted.

[0532] Furthermore, as shown in FIG. 44(B), in the pixel section 2010 of the imaging device 2000, The pixel 2011 may be arranged at an angle. This allows the pixel interval (pitch) in the vertical and column directions to be shortened. This can further improve the quality of the image captured at 000.

[0533] <Example of pixel configuration> One pixel 2011 included in the imaging device 2000 is divided into a plurality of sub-pixels 2012 Each sub-pixel 2012 is provided with a filter (color) that transmits light of a specific wavelength band. By combining these filters, it is possible to obtain information needed to display a color image. can be done.

[0534] FIG. 45(A) is a plan view showing an example of a pixel 2011 for acquiring a color image. The pixel 2011 shown in FIG. 45(A) has a color filter that transmits light in the red (R) wavelength band. a subpixel 2012 (hereinafter also referred to as "subpixel 2012R") provided with a green (G) wavelength A subpixel 2012 (hereinafter referred to as "subpixel 201") is provided with a color filter that transmits light in the It has a color filter that transmits light in the blue (B) and blue (C) wavelength bands. The subpixel 2012 (hereinafter also referred to as "subpixel 2012B") is It can function as a photosensor.

[0535] The subpixels 2012 (subpixels 2012R, 2012G, and 2012B) are Electrically connected to wire 2031, wire 2047, wire 2048, wire 2049, and wire 2050 The subpixels 2012R, 2012G, and 2012B are connected to each other. Each of them is connected to an independent wiring 2053. The wiring 2048 and the wiring 2049 connected to the eye pixel 2011 are respectively connected to the wiring 204 8[n] and wiring 2049[n]. The connected wiring 2053 is referred to as wiring 2053[m]. , the wiring 2053 connected to the sub-pixel 2012R of the pixel 2011 in the m-th column is connected to the wiring 205 3[m]R, the wiring 2053 connected to the subpixel 2012G is called wiring 2053[m]G, and The wiring 2053 connected to the subpixel 2012B is indicated as wiring 2053[m]B. The element 2012 is electrically connected to the peripheral circuitry via the wiring.

[0536] In addition, the imaging device 2000 has color filters 2011 that transmit light in the same wavelength band. The sub-pixels 2012 provided with filters are electrically connected to each other via switches. In FIG. 45(B), there is a matrix with n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). The pixel 2011 has a sub-pixel 2012 arranged in the pixel 2011 (number of pixels) and the sub-pixels 2012 adjacent to the pixel 2011 (number of pixels) An example of connection of the sub-pixel 2012 of the pixel 2011 arranged in the +1st row and the mth column is shown in FIG. In B), the sub-pixel 2012R arranged in the nth row and the mth column and the sub-pixel 2012R arranged in the n+1th row and the mth column are The pixel 2012R is connected via a switch 2001. The sub-pixel 2012G arranged in the n+1th row and the mth column is connected to the switch 2002. The sub-pixels 2012B arranged in the nth row and the mth column are connected via the The sub-pixels 2012B arranged in a column are connected via switches 2003.

[0537] The color filters used for the subpixel 2012 are limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A single pixel 2011 may have a sub-pixel for detecting light of three different wavelength bands. By providing the pixels 2012, a full color image can be obtained.

[0538] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are installed. In addition to the sub-pixel 2012, a color filter that transmits yellow (Y) light is provided. A pixel 2011 with a sub-pixel 2012 may be used. Alternatively, cyan (C), Subpixel 201 provided with a color filter that transmits yellow (Y) and magenta (M) light In addition to the pixel 2, the pixel 2012 has a color filter that transmits blue (B) light. A pixel 2011 that detects light of four different wavelength bands may be used. By providing a sub-pixel 2012 that outputs a color, it is possible to further improve the color reproducibility of the acquired image. can.

[0539] Also, for example, in FIG. 45(A), a sub-pixel 2012 for detecting the red wavelength band and a sub-pixel 2013 for detecting the green wavelength band are A sub-pixel 2012 for detecting the long wavelength band and a sub-pixel 2012 for detecting the blue wavelength band The ratio of the number of pixels (or the ratio of the light receiving area) does not have to be 1:1:1. The area ratio may be a Bayer array with red:green:blue=1:2:1. The ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0540] The pixel 2011 may have one sub-pixel 2012, but preferably has two or more. For example, by providing two or more sub-pixels 2012 that detect the same wavelength band, redundancy can be increased. The reliability of the imaging device 2000 can be improved.

[0541] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 2000 that detects infrared light.

[0542] In addition, an ND (Neutral Density) filter (neutral density filter) is used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows for a wider dynamic range of the device.

[0543] In addition to the above-mentioned filter, a lens may be provided in the pixel 2011. An example of the arrangement of the pixel 2011, the filter 2054, and the lens 2055 will be described using a cross-sectional view of the pixel 2011. By providing the lens 2055, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 46(A), the lens 2055 formed in the pixel 2011 , Filter 2054 (Filter 2054R, Filter 2054G and Filter 2054 B), and light 2056 is incident on the photoelectric conversion element 2020 through the pixel circuit 2030, etc. The structure can be such that:

[0544] However, as shown in the area surrounded by the dashed line, a part of the light 2056 indicated by the arrow is incident on the wiring 205 Therefore, as shown in Figure 46(B), A lens 2055 and a filter 2054 are arranged on the photoelectric conversion element 2020 side. The element 2020 preferably has a structure that allows it to efficiently receive light 2056. By making light 2056 incident on the photoelectric conversion element 2020 from the side, an imaging device with high detection sensitivity can be obtained. 2000 can be provided.

[0545] As the photoelectric conversion element 2020 shown in FIG. 46, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0546] The photoelectric conversion element 2020 is made of a material that absorbs radiation and generates electric charges. The material having the function of absorbing radiation and generating charges may be: Selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy There is money etc.

[0547] For example, if selenium is used in the photoelectric conversion element 2020, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element with optical absorption coefficient over a wide wavelength range, including X-rays and gamma rays We can make 2020 a reality.

[0548] Here, one pixel 2011 included in the imaging device 2000 is a sub-pixel 2012 shown in FIG. In addition, the pixel 2012 may have a first filter.

[0549] <Structural example of an imaging device> Figure 47 is a cross-sectional view of an element that constitutes an imaging device. The imaging device is composed of a layer 621, a layer 620 provided on the layer 621, and a The layer 621 includes the transistor 491 provided on the substrate 400, and the layer 622 includes the transistor 491 provided on the substrate 400. and a photodiode 2360 disposed on the substrate 400. Layer 622 is a transistor. The transistor 490 and the transistor 490b are The transistor described in Embodiment 1 can be used as the transistor 490b.

[0550] The photodiode 2360 of the imaging device has two electrodes 2361 and 2362. The electrode 2362 has a semiconductor layer sandwiched between the conductive layer 312 of the layer 621. The conductive layer 313b is connected to the conductive layer 343b of the layer 620 via the conductive layer 313b. The conductive layer 313b is in contact with at least a part of the top and side surfaces of the protrusions of the conductive layer 313b. The conductive layer 416b of the transistor 490 is connected through the conductive layer 344b of the transistor 622. In addition, part of the conductive layer 313b is preferably in contact with the top surface of the insulating film 371. .

[0551] The electrode 2361 includes a conductive layer 341c provided on the upper side of the low resistance layer 2363, and a layer The conductive layer 343e of the layer 620 is connected via other wiring layers such as the conductive layer 312c of the layer 621. The conductive layer 313e is connected to at least the top and side surfaces of the protrusions of the conductive layer 343e. The conductive layer 313e is in contact with a part of the layer 622 through the conductive layer 344c and the like. The conductive layer 313e is connected to other wiring layers of the insulating film 322. It is preferable that it contacts the upper surface of 71.

[0552] The conductive layers 313b and 313e are the conductive layer 313, and the conductive layers 343b and 343e are the conductive layers 343b and 343e. For details, the description of the conductive layer 343 can be referred to.

[0553] In the example of the cross-sectional view shown in FIG. 47, a transistor 491 is formed on a substrate 400. The light receiving surface of the photodiode 2360 is located on the opposite side of the surface where the light is received. This allows the optical path to be secured without being affected by various transistors and wiring. Therefore, it is possible to form a pixel with a high aperture ratio. The light-receiving surface of the transistor 491 may be the same as the surface on which the transistor 491 is formed.

[0554] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Example]

[0555] In this embodiment, the transistor 100 shown in FIG. 1 and the transistor 101 shown in FIG. A transistor equivalent to 71 was fabricated and its Id-Vg characteristics were evaluated. Ta.

[0556] In this example, the following samples A1 and A2 were prepared and evaluated. Samples A1 and A2 are samples according to one embodiment of the present invention. Sample A1 is The sample A1 is a transistor having one gate electrode, and the sample A2 is a transistor having two gate electrodes. It is a pedestrian.

[0557] The structure of the transistor shown in this embodiment will be described with reference to FIG. 37. 37A shows a top view of the transistor 100, and FIG. 37B shows a top view of the transistor 171. The length 123 of the gate electrodes A1 and A2 was set to 6 μm. The distance 122a ( In this specification, this may be referred to as the "offset length of the source" and the drain electrode. The distance 12 between the conductive film 112b functioning as the first gate electrode and the conductive film 104 functioning as the second gate electrode is 2b (sometimes referred to as "drain offset length" in this specification) is set to 1.5 μm. The width 124 of the oxide semiconductor film 108 was set to 10 μm.

[0558] The samples A1 and A2 prepared in this example will be described below. 1 and the transistor 171 shown in FIG. The following description will be given using the same reference numerals. Note that the fabrication process was not carried out for Sample A1, but for Sample A2. There is a process that is only performed on the

[0559] <Method of manufacturing samples A1 and A2> First, a conductive film 104 was formed on a substrate 102. A glass substrate was used as 102. The size of the glass substrate was 600 mm. The conductive film 104 was made of a 100 nm thick film. The tungsten film was formed using a sputtering device.

[0560] Next, insulating films 106 and 107 were formed on the substrate 102 and the conductive film 104. As the layer 6, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. The insulating film 107 is a silicon oxynitride film having a thickness of 50 nm, which is grown using a PECVD apparatus. It was formed by

[0561] The conditions for forming the insulating film 106 were a substrate temperature of 350° C. and a flow rate of 200 sccm. Run gas, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm The pressure was set to 100 Pa, and the parallel flat plate installed in the PECVD device was A 2000 W RF power was supplied between the electrodes of the plate to form a silicon nitride film with a thickness of 50 nm. Next, the flow rate of ammonia gas was changed to 2000 sccm, and a nitride silicon layer with a thickness of 300 nm was formed. Then, the flow rate of ammonia gas was changed to 100 sccm to form a silicon film with a thickness of 50 A silicon nitride film with a thickness of nm was deposited.

[0562] The conditions for forming the insulating film 107 are a substrate temperature of 350° C. and a flow rate of 20 sccm. Silane gas at a flow rate of 3000 sccm and nitrous oxide gas at a flow rate of 3000 sccm were introduced into the chamber. The pressure was set to 40 Pa, and a 100 W RF voltage was applied between the parallel plate electrodes installed in the PECVD device. A force was applied to form the film.

[0563] Next, the oxide semiconductor film 108 was formed over the insulating film 107. a first oxide semiconductor film 108a on the conductive film 104 side which functions as a first gate electrode; The second oxide semiconductor film 108b was formed by stacking the first oxide semiconductor film 108a and the second oxide semiconductor film 108b. In addition, an IGZO film having a thickness of 10 nm was formed as the first oxide semiconductor film 108a. As the second oxide semiconductor film 108b, an IGZO film having a thickness of 15 nm was formed.

[0564] The first oxide semiconductor film 108a was formed under the following conditions: a substrate temperature of 170° C. Argon gas at a flow rate of 140 sccm and oxygen gas at a flow rate of 60 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In:G The film was formed by applying 2500 W of AC power to a mixture of aluminum and zinc (Al:Zn=4:2:4.1 [atomic ratio]).

[0565] The second oxide semiconductor film 108b was formed under the following conditions: a substrate temperature of 170° C. Argon gas at a flow rate of 100 sccm and oxygen gas at a flow rate of 100 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn=1:1:1.2 (atomic ratio). .

[0566] Next, a first heat treatment was carried out at 450° C. in a nitrogen gas atmosphere. The heating was carried out at 450°C for 1 hour in a nitrogen gas and oxygen gas atmosphere.

[0567] Next, conductive films 112a and 112b are formed over the insulating film 107 and the oxide semiconductor film 108. The conductive films 112a and 112b were made of a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 400 nm. nm thick aluminum film and 100 nm thick titanium film were deposited using a sputtering device. A tungsten film, an aluminum film, and a titanium film were successively formed in this order in a vacuum.

[0568] Next, an insulating film was formed over the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. The insulating film 114 and the insulating film 116 were formed. The insulating film 114 was a 50 nm thick oxynitride film. The silicon film was formed using a PECVD apparatus. A silicon oxynitride film having a thickness of 1000 nm was formed using a PECVD apparatus. The insulating film 4 and the insulating film 116 were formed successively in a vacuum using a PECVD apparatus.

[0569] The conditions for forming the insulating film 114 were a substrate temperature of 220° C. and a silica flow rate of 50 sccm. Nitrogen gas and nitrous oxide gas at a flow rate of 2000 sccm were introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0 Pa, and 100 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. The insulating film 116 was formed under the conditions of a substrate temperature of 220° C. and a flow rate of 1000 kJ / cm. Silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the gas was introduced into the chamber between the parallel plate electrodes installed in the PECVD device. The film was formed by supplying RF power of 1500 W to the substrate.

[0570] Next, a second heat treatment was carried out at 350° C. in a nitrogen gas atmosphere. It was set to one hour.

[0571] An ITSO film having a thickness of 5 nm was formed on the insulating film 116 using a sputtering device. The conditions for forming the ITSO film were: the substrate temperature was room temperature, and the flow rate of argon was 72 sccm. Gas and oxygen gas at a flow rate of 5 sccm were introduced into the chamber, and the pressure was set to 0.15 Pa. A metal oxide target (In2O3:SnO2:Si) was placed in the sputtering system. The film was formed by supplying 1000 W of DC power to a mixture of 1000 W and 1000 W of O2 (85:10:5 [wt %]).

[0572] Next, an oxygen addition process was performed on the insulating film 116 through the ITSO film. The ashing device was used, the substrate temperature was set to 40°C, and oxygen gas was used at a flow rate of 250 sccm. was introduced into the chamber, the pressure was set to 15 Pa, and a bias was applied to the substrate side. RF power of 4500 W was applied between parallel plate electrodes installed in the ashing device for 120 seconds. I supplied it.

[0573] Next, the ITSO film was removed to expose the insulating film 116. A wet etching device was used, and a 5% oxalic acid solution was used for etching. After etching for 15 seconds, 0.5% hydrofluoric acid was used. I performed the patching.

[0574] Next, an insulating film 118 was formed on the insulating film 116. The insulating film 118 had a thickness of 100 The insulating film 118 was formed by using a PECVD apparatus. The conditions were a substrate temperature of 350°C, silane gas at a flow rate of 50 sccm, and Nitrogen gas at a flow rate of 0 sccm and ammonia gas at a flow rate of 100 sccm were introduced into the chamber. The pressure was set to 100 Pa, and a 1000 W power was applied between the parallel plate electrodes installed in the PECVD device. The film was formed by supplying RF power of 1000 .mu.m.

[0575] Next, only for the sample A2, the opening 142c reaching the conductive film 112b and the opening 142b reaching the conductive film 104 were formed. The openings 142a, 142b, and 142c are formed. was formed using a dry etching device.

[0576] Next, only the sample A2 is coated with the insulating film 118 so as to cover the openings 142a, 142b, and 142c. A conductive film was formed thereon and processed to form conductive films 120a and 120b. The conductive films 120a and 120b are ITSO films with a thickness of 100 nm, which are deposited by sputtering. The target composition used for the ITSO film was the same as that of the ITSO film shown above. The composition was the same as that of the film.

[0577] Next, for sample A1, a layer was formed on the insulating film 118, and for sample A2, a layer was formed on the insulating film 118 and the conductive film. A photosensitive acrylic film having a thickness of 1.5 μm was spin-coated on the film 120a and the conductive film 120b. After forming the film by a coating method, exposure was carried out.

[0578] Next, a third heat treatment was carried out at 250° C. in a nitrogen gas atmosphere. It was set to one hour.

[0579] Next, a fourth heat treatment was carried out at 250° C. in a nitrogen gas atmosphere. It was set to one hour.

[0580] Samples A1 and A2 of this example were fabricated through the above steps.

[0581] <Transistor Id-Vg Characteristics> Next, the Id-Vg characteristics of the samples A1 and A2 prepared above were measured. The Id-Vg characteristics of the samples A1 and A2 are shown in FIG. In Fig. 38(A) and (B), the first vertical axis represents Id(A) and the second vertical axis represents μFE(cm 2 / Vs), and the horizontal axis represents Vg (V).

[0582] In addition, the sample A1 functions as the first gate electrode in the Id-Vg measurement of the transistor. The voltage applied to the conductive film 104 (hereinafter also referred to as gate voltage (Vg)) is: Voltages were applied from -15 V to +15 V in 0.25 V steps. In the Id-Vg measurement of the photodiode, the voltage applied to the conductive film 104 functioning as the first gate electrode was and a voltage (Vg) applied to the conductive film 120b that functions as the second gate electrode. (Vbg) was applied in steps of 0.25V from -15V to +15V. In the samples A1 and A2, the voltage applied to the conductive film 112a functioning as the source electrode was The voltage applied to the drain electrode (hereinafter referred to as the source voltage (Vs)) is set to 0V (comm). The voltage applied to the conductive film 112b that functions as a drain voltage (hereinafter also referred to as drain voltage (Vd)) is ) was set to 0.1 V or 10 V. For the field effect mobility (μFE), Vd = The results for 10V are shown.

[0583] The field effect mobility is calculated by multiplying the length 123 of the gate electrode in FIGS. 37(A) and 37(B) by the channel length L (L=6 μm), the width 124 of the oxide semiconductor film 108 is the channel width W (W=10 μm). The field-effect mobility in the saturated region was calculated using the formula for the saturated mobility. The maximum value of the saturated mobility obtained by calculation is the saturation region (gate voltage The current driving force when the drain voltage (Vg) is less than the drain voltage (Vd) + threshold voltage (Vth) This is a target value and is different from the approximate value of the mobility as a physical property value of the oxide semiconductor film. In the case of sample A2, the insulating film 106 and the insulating film 107 functioning as the first gate insulating film are Calculations were performed using the capacity of 07.

[0584] From the results shown in FIG. 38(A), it can be seen that in the transistor of sample A1, the source and drain When the offset length of the gate is 1.5 μm, the maximum field-effect mobility is 2 cm. 2 / Vs or later In addition, from the results shown in FIG. 38(B), it was confirmed that the trace of sample A2 In a transistor, the field effect Maximum mobility is 5cm 2 It was confirmed that the voltage was above / Vs.

[0585] As described above, in the semiconductor device according to one embodiment of the present invention, the first gate electrode, the source electrode, and the In addition, even in a transistor in which the first gate electrode and the drain electrode do not overlap, oxidation By using a layered structure of semiconductor films, it has excellent electrical properties with high field-effect mobility. It was shown that...

[0586] As described above, the configuration shown in this embodiment can be used in appropriate combination with other embodiments. . [Explanation of symbols]

[0587] 100 transistors 102 Circuit Board 104 Conductive film 106 insulating film 107 Insulating film 108 Oxide semiconductor film 108a Oxide semiconductor film 108b Oxide semiconductor film 112 Conductive film 112a Conductive film 112b Conductive film 114 insulating film 116 Insulating film 117 Oxide semiconductor film 118 insulating film 120 Conductive film 120a Conductive film 120b Conductive film 121 insulating film 122 areas 122a distance 122b distance 125 Channel Protection Layer 131 Oxide Conductive Film 138 Etching gas 139 Oxygen 140a Mask 140b mask 142 Etchant 142a opening 142b opening 142c opening 151 transistors 152 transistors 153 Transistor 154 transistors 155 transistors 160 transistors 161 transistors 162 transistors 170 transistors 171 transistors 172 transistors 173 transistors 184 transistors 312b Conductive layer 312c conductive layer 313 Conductive Layer 313b Conductive layer 313e conductive layer 341c conductive layer 343 Conductive Layer 343b Conductive layer 343e conductive layer 344b Conductive layer 344c conductive layer 371 Insulating Film 400 boards 416b Conductive layer 490 transistors 490b transistor 491 Transistors 501 pixel circuit 502 pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistor 554 Transistor 560 Capacitor 562 Capacitor 570 Liquid Crystal Devices 572 Ligh...

Claims

1. A transistor is included. A semiconductor device capable of causing an electric current flowing through the transistor to flow through an EL element, thereby causing the EL element to emit light, a first conductive layer; and a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer; a second conductive layer having a region located above the oxide semiconductor layer; a third conductive layer having a region located above the oxide semiconductor layer; a second insulating layer having a region located above the oxide semiconductor layer; a fourth conductive layer having a region located above the second insulating layer; the first conductive layer functions as a first gate electrode of the transistor; the oxide semiconductor layer has a channel formation region of the transistor, the second conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the third conductive layer is electrically connected to a pixel electrode of the EL element; the fourth conductive layer functions as a second gate electrode of the transistor, the oxide semiconductor layer has a first region, a second region, a third region, a fourth region, and a fifth region; the oxide semiconductor layer contains indium, the first region does not overlap with the first conductive layer, contacts with the second conductive layer, does not contact with the third conductive layer, and does not overlap with the fourth conductive layer; the second region does not overlap with the first conductive layer, does not contact with the second conductive layer, does not contact with the third conductive layer, and does not overlap with the fourth conductive layer; the third region overlaps the first conductive layer, does not contact the second conductive layer, does not contact the third conductive layer, and overlaps the fourth conductive layer; the fourth region overlaps the first conductive layer, does not contact the second conductive layer, does not contact the third conductive layer, and does not overlap the fourth conductive layer; the fifth region overlaps the first conductive layer, does not contact the second conductive layer, contacts the third conductive layer, and does not overlap the fourth conductive layer; the first conductive layer overlaps with an entire region of the fourth conductive layer that overlaps with the oxide semiconductor layer in a plan view; the first conductive layer overlaps with the entire third region in a plan view; the first conductive layer overlaps with the entire fourth region in a plan view; the first conductive layer overlaps with the entire fifth region in a plan view; a region of the oxide semiconductor layer that overlaps with the fourth conductive layer does not overlap with the second conductive layer in a plan view;

2. A transistor is included. A semiconductor device capable of causing an electric current flowing through the transistor to flow through an EL element, thereby causing the EL element to emit light, a first conductive layer; and a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer; a second conductive layer having a region located above the oxide semiconductor layer; a third conductive layer having a region located above the oxide semiconductor layer; a second insulating layer having a region located above the oxide semiconductor layer; a fourth conductive layer having a region located above the second insulating layer; the first conductive layer functions as a first gate electrode of the transistor; the oxide semiconductor layer has a channel formation region of the transistor, the second conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the third conductive layer is electrically connected to a pixel electrode of the EL element; the fourth conductive layer functions as a second gate electrode of the transistor, the oxide semiconductor layer has a first region, a second region, a third region, a fourth region, and a fifth region; the oxide semiconductor layer contains indium, the first region does not overlap with the first conductive layer, contacts with the second conductive layer, does not contact with the third conductive layer, and does not overlap with the fourth conductive layer; the second region does not overlap with the first conductive layer, does not contact with the second conductive layer, does not contact with the third conductive layer, and does not overlap with the fourth conductive layer; the third region overlaps the first conductive layer, does not contact the second conductive layer, does not contact the third conductive layer, and overlaps the fourth conductive layer; the fourth region overlaps the first conductive layer, does not contact the second conductive layer, does not contact the third conductive layer, and does not overlap the fourth conductive layer; the fifth region overlaps the first conductive layer, does not contact the second conductive layer, contacts the third conductive layer, and does not overlap the fourth conductive layer; the first conductive layer overlaps with an entire region of the fourth conductive layer that overlaps with the oxide semiconductor layer in a plan view; the first conductive layer overlaps with the entire third region in a plan view; the first conductive layer overlaps with the entire fourth region in a plan view; the first conductive layer overlaps with the entire fifth region in a plan view; a region of the oxide semiconductor layer that overlaps with the fourth conductive layer does not overlap with the second conductive layer in a plan view; The semiconductor device may be configured such that different potentials can be applied to the first conductive layer and the fourth conductive layer.

3. A transistor is included. A semiconductor device capable of causing an electric current flowing through the transistor to flow through an EL element, thereby causing the EL element to emit light, a first conductive layer; and a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer; a second conductive layer having a region located above the oxide semiconductor layer; a third conductive layer having a region located above the oxide semiconductor layer; a second insulating layer having a region located above the oxide semiconductor layer; a fourth conductive layer having a region located above the second insulating layer; the first conductive layer functions as a first gate electrode of the transistor; the oxide semiconductor layer has a channel formation region of the transistor, the second conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the third conductive layer is electrically connected to a pixel electrode of the EL element; the fourth conductive layer functions as a second gate electrode of the transistor, the oxide semiconductor layer has a first region, a second region, a third region, a fourth region, and a fifth region; the oxide semiconductor layer contains indium, the first region does not overlap the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the second region does not overlap with the first conductive layer, does not overlap with the second conductive layer, does not overlap with the third conductive layer, and does not overlap with the fourth conductive layer; the third region overlaps the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and overlaps the fourth conductive layer; the fourth region overlaps the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the fifth region overlaps the first conductive layer, does not overlap the second conductive layer, overlaps the third conductive layer, and does not overlap the fourth conductive layer; the first conductive layer overlaps with an entire region of the fourth conductive layer that overlaps with the oxide semiconductor layer in a plan view; the first conductive layer overlaps with the entire third region in a plan view; the first conductive layer overlaps with the entire fourth region in a plan view; the first conductive layer overlaps with the entire fifth region in a plan view; a region of the oxide semiconductor layer that overlaps with the fourth conductive layer does not overlap with the second conductive layer in a plan view;

4. A transistor is included. A semiconductor device capable of causing an electric current flowing through the transistor to flow through an EL element, thereby causing the EL element to emit light, a first conductive layer; and a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer; a second conductive layer having a region located above the oxide semiconductor layer; a third conductive layer having a region located above the oxide semiconductor layer; a second insulating layer having a region located above the oxide semiconductor layer; a fourth conductive layer having a region located above the second insulating layer; the first conductive layer functions as a first gate electrode of the transistor; the oxide semiconductor layer has a channel formation region of the transistor, the second conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the third conductive layer is electrically connected to a pixel electrode of the EL element; the fourth conductive layer functions as a second gate electrode of the transistor, the oxide semiconductor layer has a first region, a second region, a third region, a fourth region, and a fifth region; the oxide semiconductor layer contains indium, the first region does not overlap the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the second region does not overlap with the first conductive layer, does not overlap with the second conductive layer, does not overlap with the third conductive layer, and does not overlap with the fourth conductive layer; the third region overlaps the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and overlaps the fourth conductive layer; the fourth region overlaps the first conductive layer, does not overlap the second conductive layer, does not overlap the third conductive layer, and does not overlap the fourth conductive layer; the fifth region overlaps the first conductive layer, does not overlap the second conductive layer, overlaps the third conductive layer, and does not overlap the fourth conductive layer; the first conductive layer overlaps with an entire region of the fourth conductive layer that overlaps with the oxide semiconductor layer in a plan view; the first conductive layer overlaps with the entire third region in a plan view; the first conductive layer overlaps with the entire fourth region in a plan view; the first conductive layer overlaps with the entire fifth region in a plan view; a region of the oxide semiconductor layer that overlaps with the fourth conductive layer does not overlap with the second conductive layer in a plan view; The semiconductor device may be configured such that different potentials can be applied to the first conductive layer and the fourth conductive layer.

5. In any one of claims 1 to 4, the second region has a region having a thickness smaller than that of the first region, The fourth region has a thickness smaller than that of the fifth region.

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