A packaging method suitable for a hybrid device package structure of a micro LED

Abstract

The application relates to the fields of microelectronic packaging and novel display technology, and discloses a packaging method suitable for a hybrid device packaging structure of a MicroLED, which comprises the following steps: preparing a wide-bandgap semiconductor driving chip, a logic control chip and a light-emitting pixel chip; transferring and fixing the wide-bandgap semiconductor driving chip, the logic control chip and the light-emitting pixel chip on the surface of a carrier plate in a coplanar mode; depositing a dielectric layer on the surface of the carrier plate to expose electrode contacts; manufacturing metal wires to build an internal electrical interconnection structure and lead out a peripheral interface; coating a packaging material on the surface of the carrier plate to insulate and coat the internal electrical interconnection structure; curing and cutting to separate an independent pixel packaging body; and assembling the pixel packaging body to a display panel substrate and connecting the peripheral interface to a global power supply network. The application suppresses the hot carrier effect under high-temperature working conditions, solves the problem of thermal failure, reduces the parasitic capacitance of high-frequency driving interconnection, removes potential failure products before macroscopic mounting, and improves the assembly yield of a display panel array.

Description

Technical Field

[0001] This invention relates to the field of microelectronic packaging and novel display technology, specifically to a packaging method for a hybrid device package structure suitable for MicroLEDs. Background Technology

[0002] Miniature LED display technology, characterized by high brightness and low power consumption, is widely used in various display terminals. Current miniature LED display panels typically use silicon-based integrated circuits as the driving module. Under outdoor high-brightness display conditions, the panel requires a continuous large current input, leading to heat accumulation. Due to the narrow bandgap of traditional silicon-based semiconductor materials, the kinetic energy of internal charge carriers increases at high temperatures, easily triggering the hot carrier effect. High-energy charge carriers penetrate the potential barrier and inject into the gate oxide layer, causing irreversible drift in the transistor threshold voltage. This deviation in physical characteristics directly alters the output current amplitude of the analog driving circuit, resulting in brightness decay and color unevenness failure of the display panel after long-term operation.

[0003] Conventional micro-LED panel manufacturing processes primarily rely on mass transfer technology, directly mounting a massive number of luminescent pixel chips and driving control chips onto a macroscopic display substrate. This architecture forcibly binds the micro-chip interconnection process to the macro-panel assembly. Before macro-mounting is complete, system-level optoelectronic performance and leakage current closed-loop testing cannot be performed. Early latent failures of micro-devices or structural damage during the transfer process directly translate into physical defects in the final display panel. The process of reworking dead pixels in ultra-large matrix displays is complex, resulting in low overall manufacturing yield and high manufacturing costs.

[0004] When transmitting high-frequency video pulse-width modulation signals across chips on a macroscopic substrate, traditional wiring methods result in significant parasitic capacitance between the signal and the underlying substrate. The transmission of high-frequency signals over long physical traces is limited by the charging and discharging time constant of the capacitors, easily inducing signal transmission delays. Simultaneously, electromagnetic crosstalk can easily occur between adjacent pixel circuits within a dense wiring network. The combination of these factors makes it difficult for the display system to meet the signal integrity requirements of high refresh rate displays, affecting the final quality of dynamic image presentation. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a packaging method for a hybrid device package structure suitable for MicroLEDs. This method solves the problems of thermal failure of traditional silicon-based integrated circuits in high-temperature environments leading to luminous brightness decay, and the inability to perform closed-loop testing before macroscopic assembly, resulting in low array mounting yield and high rework costs.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a packaging method for a hybrid device package structure suitable for MicroLEDs, the method comprising the following steps:

[0007] S100: Fabricate a wide bandgap semiconductor driver chip, a logic control chip, and a light-emitting pixel chip, and transfer and fix the wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chip coplanarly onto the surface of a carrier board;

[0008] S200, deposit a dielectric layer on the surface of the carrier board and expose the electrode contacts of each chip, fabricate metal interconnects to connect the electrode contacts to construct an internal electrical interconnect structure, and bring out the peripheral interface;

[0009] S300, an encapsulation material is coated on the surface of the carrier board to insulate and cover the internal electrical interconnection structure and expose the peripheral interface. After curing, the individual pixel encapsulation is cut and separated.

[0010] S400, the pixel package is assembled onto the display panel substrate, and the peripheral interface is connected to the scan lines, data lines and global power supply network arranged on the display panel substrate.

[0011] Preferably, in step S100, before fabricating the wide bandgap semiconductor driver chip, the semiconductor device structure constant, hot carrier stress duration, time degradation index factor, injection activation energy, and actual junction temperature parameters are obtained.

[0012] Based on the laws of solid-state physics, the above parameters are substituted into the physical model to calculate the value of the transistor threshold voltage drift.

[0013] When the threshold voltage drift of the transistor is determined to be greater than one-zero of the rated drive voltage, a material replacement command is output.

[0014] According to the material replacement instructions, the wide bandgap semiconductor driver chip is manufactured on a native substrate using gallium nitride material.

[0015] Preferably, in step S100, the coplanar transfer and fixation of the wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chip onto the carrier surface specifically includes:

[0016] A benzocyclobutene resin is coated onto the selected glass substrate or silicon substrate bearing surface, and a flat bonding layer is formed by thermosetting to constitute the carrier plate.

[0017] The wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chip are separated from their respective native substrates using laser lift-off technology.

[0018] Extract the spatial coordinate system alignment index based on the preset pixel circuit topology layout;

[0019] According to the alignment index, the microelectromechanical system (MEMS) controls the separated chips to bond and fix them on the surface of the bonding layer.

[0020] Preferably, in step S200, depositing a dielectric layer on the surface of the carrier plate specifically includes:

[0021] Obtain the effective facing area of ​​the subsequent metal interconnects and the underlying conductive substrate, the relative permittivity of the photosensitive polyimide material, and the edge parasitic capacitance compensation constant;

[0022] A safe transmission threshold for the parasitic capacitance of the metal interconnect node is set. Combining the vacuum dielectric constant with the safe transmission threshold, the target coating thickness lower limit is calculated and derived by substituting it into the electromagnetic field capacitance model.

[0023] Photosensitive polyimide material is selected as the dielectric material, and the dielectric material is spin-coated onto the carrier board and the top surface of each chip in strict accordance with the target coating thickness limit to form the dielectric layer.

[0024] Preferably, in step S200, fabricating the metal interconnects connecting the electrode contacts to construct the internal electrical interconnect structure specifically includes:

[0025] A titanium-copper composite film is attached as a seed layer on the surface of the dielectric layer and in the exposed holes using a magnetron sputtering process, and the metal interconnect is formed by filling the preset line trench with electroplated copper material.

[0026] Obtain the peak output current parameters of the display panel under high current long-term operation conditions;

[0027] Based on the electromigration failure threshold of copper material and the peak output current parameter, the cross-sectional area of ​​the metal interconnect is calculated and set, and the actual maximum current density through the metal interconnect is strictly controlled to be less than the electromigration failure threshold.

[0028] Preferably, in step S300, coating the surface of the carrier plate with the encapsulation material specifically includes:

[0029] The peak thermosetting temperature of the pre-selected resin molding compound, the coefficient of thermal expansion of the carrier material, the maximum diagonal physical length of the carrier, and the structural thickness parameters of the carrier are obtained.

[0030] Based on the preset physical coating thickness of the encapsulation layer and the planar geometric constant, the above parameters are input into the thermal deformation theoretical model of the double-layer thin plate to calculate the predicted value of the center warpage of the encapsulation carrier.

[0031] When the predicted value of the center warpage is less than 0.002 times the maximum diagonal physical length of the carrier board, the pre-selected resin molding compound is identified as the target encapsulation material and applied to the surface of the carrier board.

[0032] Preferably, in step S300, cutting and separating the individual pixel packages specifically includes:

[0033] Using ultraviolet laser ablation technology, the epoxy resin material covering each light-emitting pixel chip is removed directly above it to form a vertical light extraction channel that penetrates the protective layer, and the light extraction channel is filled with high-transmittance organosilicon gel.

[0034] A continuous pixel array is generated by globally smoothing the top surface of the protective layer and the filling gel using a chemical mechanical polishing process.

[0035] Along the inactive dicing path set between adjacent pixel units in the continuous pixel array, picosecond-level pulse parameters are input to guide an ultrashort pulse cold laser to perform ablation cutting, thereby dividing the carrier plate through and dividing it into the independent pixel packages.

[0036] Preferably, in step S400, before connecting the peripheral interface to the global power supply network arranged on the display panel substrate, a global power supply network configuration step is included, specifically including:

[0037] Extract the resistivity of the metal traces on the display panel substrate, the physical length of the distributed wiring network segments, the wiring width, and the copper foil thickness parameters.

[0038] By combining the transient current consumption under peak brightness conditions of a single node pixel unit with the concurrent sparsity coefficient of dynamic image display load, the voltage drop value of the bus from the edge power input terminal to the central target pixel node is calculated.

[0039] When the bus voltage drop value is determined to exceed 0.05 times the rated operating voltage of the driver chip, a multi-layer thickened copper-clad plane and a distributed parallel decoupling capacitor array are arranged on the back side of the display panel substrate to update the physical architecture of the global power supply network.

[0040] Preferably, in step S400, assembling the pixel package onto the display panel substrate specifically includes:

[0041] Individual pixel screening tests are performed by inputting a rated pulse width modulation signal and a standard drive current into the individual pixel package using a high-frequency microneedle test station.

[0042] Extract evaluation data for indicators where the measured luminous intensity is within ±0.05 times the target standard value and the static current fluctuation amplitude during continuous operation is strictly less than 0.03 times the target standard value.

[0043] A set of good product indexes is established based on the evaluation data of the aforementioned indicators;

[0044] Based on the set of good product indexes, the surface mount equipment is invoked to transfer the corresponding qualified pixel package to the surface of the corresponding pad on the display panel substrate to complete the intermetallic compound bonding.

[0045] Preferably, in step S400, after connecting the peripheral interface to the global power supply network, a display performance closed-loop correction step is performed, specifically including:

[0046] The main control chip sends a global synchronization clock signal to synchronously trigger the camera shutter and the row scanning circuit of the display panel substrate, and collects the column vector of actual luminous brightness corresponding to the preset grayscale command.

[0047] By comparing the actual luminous brightness column vector with the preset ideal brightness target vector, a regularization correction constant is inserted into the main diagonal of the compensation coefficient matrix to prevent numerical divergence, and the target compensation coefficient matrix is ​​calculated.

[0048] The target compensation coefficient matrix is ​​loaded into the digital processing module of the display system to perform spatial luminous uniformity correction calculation.

[0049] This invention provides a packaging method for a hybrid device package structure suitable for MicroLEDs. It offers the following advantages:

[0050] 1. This invention integrates a wide bandgap semiconductor driver chip containing gallium nitride high electron mobility transistors, a logic control chip, and a light-emitting pixel chip onto a carrier board for heterogeneous integration. By utilizing the physical property of gallium nitride material's large bandgap, the surge in intrinsic carrier concentration of the display panel is limited under high temperature and high current operating conditions, suppressing threshold voltage drift of the driver transistor. This feature directly eliminates the physical path of output current decay, solves the thermal failure problem of traditional pure silicon-based driver circuits, and achieves a high-temperature resistant and stable driving effect.

[0051] 2. This invention constructs an internal electrical interconnect structure by depositing a photosensitive polyimide dielectric layer on the surface of a carrier board and fabricating metal interconnects. By deriving and limiting the lower limit of the coating thickness of the dielectric layer through a physical model, the physical spacing between line nodes is increased, thereby controlling the parasitic capacitance of the interconnect network within a safe transmission threshold. This reduces the delay and distortion of high-frequency video pulse width modulation signals during cross-chip transmission, reduces electromagnetic crosstalk between adjacent pixels, and ensures the data integrity of the display system signal scheduling.

[0052] 3. This invention transforms heterogeneous chip arrays into independent pixel packages by performing overall insulating encapsulation and through-cutting on the carrier board after rewiring. This method enables pixel units to undergo closed-loop screening tests for photoelectric indicators and steady-state leakage current before being mounted onto the macro display panel substrate. This pre-testing mechanism physically isolates potential failed chips from entering the final assembly stage, improves the initial yield of panel-level array mounting, and reduces the rework cost of the entire manufacturing process. Attached Figure Description

[0053] Figure 1This is a schematic diagram of the manufacturing process of the MicroLED light-emitting module of the present invention;

[0054] Figure 2 This is a flowchart of the heterogeneous hybrid drive packaging process of the present invention;

[0055] Figure 3 This is a diagram of the pixel package connection structure of the present invention;

[0056] Figure 4 This is a flowchart illustrating the cutting and separation process of the package body of the present invention;

[0057] Figure 5 This is a schematic diagram of the panel-level array assembly and power supply network architecture of the present invention. Detailed Implementation

[0058] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] See attached document Figure 1 , Figure 1 This is a schematic flowchart of a MicroLED light-emitting module manufacturing method according to an embodiment of the present invention. The present invention provides a packaging method for a hybrid device package structure suitable for MicroLEDs, the method comprising:

[0060] S100: Fabricate micro-semiconductor devices and transfer them to a carrier substrate. Fabricate wide-bandgap semiconductor driver chips, logic control chips, and light-emitting pixel chips on the native substrate. The wide-bandgap semiconductor driver chips include gallium nitride high electron mobility transistors, and the light-emitting pixel chips include red, green, and blue MicroLED chips. Provide a carrier substrate with a bonding layer on its surface. Using a mass transfer process, peel off the fabricated wide-bandgap semiconductor driver chips, logic control chips, and light-emitting pixel chips from their respective native substrates and transfer them to the bonding layer of the carrier substrate. The bonding layer makes the wide-bandgap semiconductor driver chips, logic control chips, and light-emitting pixel chips coplanarly fixed on the surface of the carrier substrate, resulting in a carrier substrate with chips to be interconnected.

[0061] In step S200, a rewiring process is performed on a carrier board with chips to be interconnected, forming internal electrical interconnection structures and peripheral interfaces. A dielectric layer is deposited on the surface of the carrier board with the chips to be interconnected, and the dielectric layer is patterned to expose the electrode contacts of the wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chip fixed on the carrier board. Metal interconnects are fabricated on the surface of the dielectric layer, and the output contacts of the wide bandgap semiconductor driver chip are connected to the input contacts of the corresponding red, green, and blue MicroLED chips through the metal interconnects to form internal electrical interconnection structures. Based on the metal interconnects, peripheral interfaces corresponding to each internal electrical interconnection structure are led out on the carrier board. The peripheral interfaces include a gate control terminal, a data input terminal, a positive power supply terminal, and a negative power supply terminal, resulting in a carrier board with completed rewiring.

[0062] S300 performs overall encapsulation and cutting on the carrier board after rewiring, separating independent pixel packages. Encapsulation material is applied to the surface of the carrier board after rewiring, and the encapsulation material is used to insulate and cover each chip and internal electrical interconnection structure on the carrier board, exposing the peripheral interfaces. The encapsulation material is then cured to form a protective layer covering the carrier board. The carrier board with the protective layer is cut along the preset cutting area on the carrier board, and the independent pixel packages are separated by cutting. Each pixel package contains a complete internal electrical interconnection structure and a peripheral interface exposed to the outside.

[0063] S400 assembles individual pixel packages onto a display panel substrate and connects them to a global power supply network. A display panel substrate is provided, and scan lines and data lines are fabricated on the substrate to form a matrix addressing architecture. Individual pixel packages are mounted at the intersections of the scan lines and data lines. The exposed gate control terminals of the pixel packages are connected to the scan lines, and the data input terminals are connected to the data lines. A global power supply network is fabricated on the display panel substrate. All positive power supply traces and all negative power supply traces within the display panel are physically shorted. The positive and negative power supply terminals on each mounted pixel package are connected to the physically shorted positive and negative power supply traces in the global power supply network, respectively.

[0064] See attached document Figure 2 , Figure 2 This is a flowchart of the heterogeneous hybrid drive packaging process according to an embodiment of the present invention. In this embodiment, before performing electrical interconnection, the micro-semiconductor device fabrication and transfer method fabricates drive and logic devices with different bandgap characteristics on the native substrate, and uses a carrier board to construct a coplanar integrated physical platform. This changes the physical failure path of traditional single silicon-based materials under high temperature and high current drive, and creates the boundary conditions for heterogeneous integration in advance for the subsequent construction of high-stability display pixels.

[0065] S110, the micro LED display panel requires high current drive under outdoor high-brightness conditions, resulting in heat accumulation inside the panel. Due to the narrow bandgap of silicon-based semiconductor materials, the kinetic energy of internal carriers increases under high temperatures, generating a hot carrier effect. High-energy carriers penetrate the potential barrier and inject into the gate oxide layer, leading to an increase in interface state density and oxide layer charge accumulation, causing a shift in the transistor's threshold voltage. For analog current-driven circuits, this threshold voltage shift directly changes the output current amplitude, macroscopically manifesting as brightness decay and color unevenness in the display panel. Based on this failure mechanism, to accurately predict and avoid performance degradation throughout the device's lifespan, a physical model of semiconductor device reliability needs to be introduced. To quantify the impact of hot carrier injection on device performance degradation under high-temperature conditions, this embodiment characterizes and verifies the threshold voltage drift process based on solid-state physics and thermodynamics. This verification process not only serves as a theoretical evaluation but also provides data support for the subsequent selection of wide-bandgap semiconductor materials. The specific physical calculation process is shown in the formula:

[0066] ;

[0067] In the formula, This represents the drift of the transistor threshold voltage, typically ranging from millivolts to hundreds of millivolts, and is used to visually characterize the degree of deviation in device characteristics. In the engineering settings of this embodiment, when the above-calculated value... When the driving voltage exceeds 10 percent of the rated driving voltage, the system determines that the material system has an irreversible risk of luminescence uniformity failure, and uses this physical critical point as a quantitative basis for migration to wide bandgap semiconductor materials. This represents a constant related to the physical structure and manufacturing process of semiconductor devices. This constant is a proportionality coefficient obtained by fitting historical data from accelerated aging experiments on a specific process line, and its value is always greater than zero. This indicates the duration of the hot carrier stress, expressed in seconds. The time degradation index factor is a positive real number constrained by the quality of the device oxide layer, and its value is usually in the range of 0.3 to 0.7. It represents an exponential function with the natural constant as its base, used to characterize the nonlinear probability distribution of hot carriers crossing the potential barrier; It represents the activation energy required for hot carriers to be injected into the gate oxide layer, measured in electron volts, and reflects the ease with which carriers can cross the interface barrier. Represents the Boltzmann constant; The actual junction temperature of a semiconductor device during operation is expressed in Kelvin. Due to objective limitations of the physical environment, the actual junction temperature is always greater than absolute zero. This automatically avoids overflow anomalies caused by the denominator approaching zero in division operations in the algorithm logic. Through the characterization of the above formula, the upper limit of the tolerance of a single silicon-based device to high-temperature stress can be established in the early design stage, thereby deriving the necessity of replacing the underlying material.

[0068] To address the light emission failure caused by threshold voltage drift, a wide bandgap semiconductor material is used to fabricate the driving circuit on the native substrate. In this embodiment, gallium nitride (GaN) is used as the wide bandgap semiconductor material, with an actual bandgap wider than that of silicon. The larger bandgap results in extremely high energy required for interband transitions, physically limiting the surge in intrinsic carrier concentration at high temperatures. A high electron mobility transistor (HMT) is built inside the wide bandgap semiconductor driving chip. This HMT utilizes a two-dimensional electron gas generated by polarization at the heterojunction interface for conduction. The two-dimensional electron gas possesses extremely high electron mobility and surface charge density. When driving a micro-LED, the HMT provides low on-resistance and high current carrying capacity, and maintains a stable threshold voltage at high temperatures, cutting off the physical path of output current decay. For the etching and metallization processes of epitaxially growing a GaN thin film on the substrate and fabricating the HMT, those skilled in the art can use conventional compound semiconductor manufacturing processes. The wafer-level processing methods are well-known in the field and will not be elaborated upon here.

[0069] After clarifying the material system of the driving module, S120 further focuses on the fabrication of the main control module of the display system. A logic control chip is manufactured on a silicon-based native substrate using complementary metal-oxide-semiconductor (CMOS) technology. This logic control chip, within the heterogeneous integrated architecture, undertakes signal processing and controlled instruction issuance functions. Since the tolerance for threshold voltage drift in digital logic circuits is much higher than that of analog driving circuits, a mature silicon-based process is used to manufacture the logic control chip to meet the integration requirements of large-scale signal processing. As a specific feature implementation, the logic control chip integrates a pulse width modulation circuit and a static random access memory. The logic control chip receives externally input digital video signals, converts them into time-modulated signals, and outputs them to the gate control terminal of the wide-bandgap semiconductor driving chip to adjust the display grayscale of the light-emitting pixel chips. Simultaneously, light-emitting pixel chips are fabricated on a sapphire native substrate. These chip chips include red, green, and blue micro-light-emitting diode (LED) chips. Each LED chip has independent anode and cathode contacts on its top surface to receive subsequent metal interconnect signals.

[0070] S130 In order to physically integrate the heterogeneous devices that are independently formed on different native substrates, a carrier board with an insulating surface is required as a physical support base. The carrier board material is selected from glass substrate or silicon substrate. A polymer material is coated on the bearing surface of the carrier board, and after thermosetting, a permanent bonding layer with a flat surface is formed. As a preferred method, the polymer material is benzocyclobutene resin. The permanent bonding layer provides physical adhesion to fix the external chip during the subsequent transfer process, while isolating the bottom stress and providing a flat coplanar substrate for subsequent high-precision rewiring processes.

[0071] S140: After the permanent bonding layer of the carrier board is prepared, the wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chips of various colors are separated from their respective native substrates using laser lift-off technology or chemical etching technology. Microelectromechanical systems (MEMS) gripping or electrostatic adsorption equipment is used to pick up the separated microchips and transfer them above the permanent bonding layer of the carrier board. Based on the preset pixel circuit topology, the picking equipment is controlled to align the positions in a two-dimensional coordinate system. After alignment, each chip is placed on the surface of the permanent bonding layer for bonding and fixation. The transferred and fixed wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chips are distributed on the same horizontal plane on the carrier board surface. The back side of each chip is in direct contact with and anchored to the permanent bonding layer, and the active side of each chip with electrode contacts is exposed upwards, creating physical conditions for subsequent interconnection circuitry on the same plane. For the specific wavelength laser lift-off and electrostatic array picking control methods involved in the transfer process, those skilled in the art can perform routine adjustments according to the equipment parameters. The specific substrate lift-off and picking techniques are well-known in the field and will not be described in detail here.

[0072] See attached document Figure 3 , Figure 3 This is a diagram of the pixel package connection structure according to an embodiment of the present invention. In this embodiment, the substrate-level rewiring process is performed after the coplanar transfer and fixation of the heterogeneous micro-semiconductor devices is completed. By depositing an insulating dielectric on the substrate surface and fabricating micron-level metal traces, electrical paths are established between physically independent driving units, logic control units, and light-emitting pixels, thereby constructing a highly integrated electrical interconnection topology network within a single substrate plane. This rewiring and interconnection process is divided into the following sub-steps:

[0073] S210, based on the physical principle of coplanar fixation of heterogeneous chips, in order to isolate the electrical contact between the subsequently fabricated metal interconnects and the underlying non-target areas, a dielectric layer with insulating properties is integrally covered on the top surface of the carrier board and the wide-bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chip it carries. As a preferred method, this dielectric layer uses photosensitive polyimide material. In the field of microelectronic packaging, high-frequency drive signals are prone to signal delay and crosstalk during cross-chip transmission due to parasitic capacitance between the wiring layer and the substrate. To quantify the impact of the dielectric layer on the integrity of high-frequency signal transmission, this embodiment characterizes the parasitic capacitance of the wiring nodes based on electromagnetic field theory before performing thin film deposition, thereby determining the optimal coating thickness of the dielectric layer. The specific parasitic capacitance evaluation model is shown in the formula:

[0074] ;

[0075] In the formula, This represents the parasitic capacitance value at the metal interconnect wiring node. Its magnitude directly determines the transmission delay of high-frequency video signals. In practical applications, the safety threshold for this value is usually set below the picofarad level to meet the driving requirements of high refresh rates of display panels. This represents the vacuum permittivity, a universally accepted constant in physics, typically valued at 8.854. Farads per meter; The relative permittivity of the photosensitive polyimide dielectric layer is a dimensionless positive real number determined by the polarization characteristics of the material itself. In the high-frequency transmission scenario of this embodiment, its value is usually constant between 2.9 and 3.5. This represents the effective face-to-face area where the metal trace overlaps with the underlying conductive substrate, in square meters. This area is uniquely determined by the preset circuit layout. The physical coating thickness of the dielectric layer is expressed in meters. It is subject to the actual coating process and the spatial distribution of the polymer molecular chains. Due to the physical limitations of the manufacturing process itself, the thickness value is always greater than zero and is usually taken in the range of 2 to 10 micrometers. This naturally avoids the abnormal situation of calculation overflow caused by the denominator approaching zero in the division operation in the algorithm logic. This represents the edge parasitic capacitance compensation constant caused by spatial field strength distortion. This constant is an empirical correction value extracted from previous multiphysics coupling calculations using electromagnetic simulation software, used to improve the fit between theoretical calculations and actual measurements.

[0076] Based on the above formula, the lower limit of the dielectric layer coating thickness that keeps the parasitic capacitance within the safe transmission threshold can be derived under the premise of meeting the insulation penetration resistance strength. After the dielectric layer coating is completed, the dielectric layer is patterned by photolithography and development process to accurately expose the electrode contacts on the surface of the wide bandgap semiconductor driver chip, logic control chip and micro light-emitting diode chips of each color. For the spin coating pre-baking and photolithography and development operations of the dielectric layer, those skilled in the art can configure conventional process parameters according to the photoresist specifications. The specific microelectronic thin film patterning processing method is a well-known technology in the field and will not be described in detail here.

[0077] S220, after exposing the electrode contacts, the physical construction of the conductive path is further performed. A metal seed layer is deposited on the patterned dielectric layer surface and within the exposed electrode contact holes. In this embodiment, a titanium-copper composite film is typically attached as the seed layer using magnetron sputtering. Based on a preset redistribution mask, a photoresist resist layer with circuit trenches is prepared above the seed layer. A highly conductive metal material is then filled into the circuit trenches using an electroplating process. After removing the residual photoresist resist layer from the surface, the main conductive structure remaining on the dielectric layer surface is micron-sized. As a preferred approach, the metal interconnect with a width of 100 mm is made of electroplated copper. When designing this electroplated copper structure, considering the harsh operating conditions of outdoor display panels running at high current for extended periods, the cross-sectional area of ​​the metal interconnect needs to be designed with safety redundancy in the cross-sectional dimensions, taking into account the estimated peak output current and the physical limit of electromigration. This means that the maximum current density passing through the metal interconnect must be strictly less than the electromigration failure threshold of the copper material, typically set to less than 10⁵ to 10⁵ amperes per square centimeter, thereby ensuring that the metal trace does not undergo electromigration melting and circuit breakage under electrothermal coupling stress.

[0078] S230, based on the physical wiring, it is necessary to clarify the signal flow relationship between the heterogeneous devices. Using the metal interconnects fabricated above, the current output contacts of the wide bandgap semiconductor driver chip are precisely connected one by one to the input contacts of the corresponding red, green, and blue micro LED chips. In order to achieve accurate timing control of the display grayscale, the control signal output contacts of the logic control chip are connected to the gate input contacts of the wide bandgap semiconductor driver chip through specific metal interconnect branches. The above connection relationship completely opens up the system-level electrical link from the logic main control module to the analog current drive module and then to the light-emitting pixel module in a single pixel area, forming an internal electrical interconnection structure with closed-loop operation at the micro level.

[0079] S240, in order for the independently enclosed packaged module to receive global power supply and data scheduling signals transmitted from the macro display panel, it is necessary to pre-plan the physical channels for external interaction. In a specific area at the edge of the carrier board, based on the physical extension of metal interconnects, peripheral interfaces corresponding to each internal electrical interconnect structure are led out. These peripheral interfaces serve as the connection base for subsequent panel-level surface mount processes. Specifically, they include a gate control terminal for receiving global scan timing, a data input terminal for receiving grayscale video signals, a power supply positive terminal for connecting to the system high level, and a power supply negative terminal for connecting to the system reference level. To ensure the reliability of subsequent cross-scale mounting and soldering and to prevent oxidation of exposed metal layers, the ends of the peripheral interfaces are further covered with an anti-oxidation and wear-resistant metal protective layer through a chemical plating process. As a preferred method, this metal protective layer is usually a nickel-gold alloy layer. After completing all the above processes, a carrier board with a fine circuit connection network on the surface and peripheral interface leads is obtained.

[0080] See attached document Figure 4 , Figure 4 This is a flowchart illustrating the packaging cutting and separation process according to an embodiment of the present invention. In this embodiment, the overall insulating packaging and individual unit cutting and separation are the final steps performed after the carrier-level redistribution process. By covering the entire surface of the carrier board with packaging material and performing physical cutting, the coplanar integrated micro-semiconductor device array is transformed into independently mountable heterogeneous hybrid driving pixel units, providing standardized components for the final display panel-level assembly. This insulating packaging and separation process is divided into the following sub-steps:

[0081] S310, based on the already constructed carrier-level electrical interconnect topology, to isolate external moisture and provide mechanical support, a polymer encapsulation material with high impedance characteristics is coated entirely on top of the carrier. As a preferred method, this encapsulation material uses an epoxy resin molding compound doped with black light-absorbing particles to simultaneously absorb ambient stray light during the operation of the display panel. Due to the high-temperature thermal cycling involved in the subsequent curing process, the mismatch in thermal expansion coefficients between the encapsulation material and the underlying carrier can easily generate thermomechanical stress, leading to warping deformation of the substrate during the cooling stage. With the continuous increase in the size of the encapsulation, this warping can easily cause the breakage of internal micro-interconnects. To quantitatively evaluate the degree of physical deformation of the encapsulation material and the carrier under thermal stress and to guide the selection of encapsulation material parameters, this embodiment introduces a double-layer thin plate thermal deformation theoretical model for preliminary calculation and prediction. The specific warping deformation evaluation process is shown in the formula:

[0082] ;

[0083] In the formula, The value represents the center warpage of the packaging substrate, expressed in millimeters. This parameter is used to visually characterize the degree of physical deformation caused by thermomechanical stress. In this embodiment, its safety control threshold is usually set to be strictly less than two-thousandths of the diagonal length of the substrate to ensure that the focus alignment accuracy of the subsequent cutting process does not drift. This represents a dimensionless geometric constant related to the planar geometry of the package. Based on the standard rectangular package boundary conditions and boundary constraint states, its empirical value is constant between 0.08 and 0.12. The coefficient of thermal expansion of epoxy resin encapsulation material is expressed in Kelvin. This parameter is an inherent thermodynamic property of the material itself. This represents the coefficient of thermal expansion of the bottom carrier material, expressed in Kelvin. It represents the peak temperature during the thermosetting process of the encapsulation material, and is measured in Kelvin. It is usually determined by the cross-linking reaction temperature of the resin material. The ambient temperature after curing and sufficient cooling is indicated by Kelvin. This indicates the maximum physical length of the carrier plate's diagonal, in millimeters. Indicates the structural thickness of the carrier plate, in millimeters; This indicates the physical coating thickness of the insulating encapsulation layer, measured in millimeters. Since both the carrier board and the encapsulation layer exist as physical structural entities, they are subject to material processing specifications and three-dimensional spatial properties. and The value is always a positive real number, which physically ensures that the overall thickness of the substrate is greater than zero, thus effectively avoiding the overflow anomaly caused by the denominator approaching zero in the division operation in the algorithm logic.

[0084] By solving the above model, material combinations with excessively large differences in thermal expansion coefficients can be eliminated before the process is implemented, thus suppressing warping from a physical cause-and-effect perspective. For the vacuum molding and stepped temperature-controlled curing process of molding compound, those skilled in the art can set conventional parameters according to the specifications of the hot pressing equipment. The specific resin molding and curing methods are well-known technologies in the field and will not be elaborated here.

[0085] After the overall encapsulation layer is cured, the S320 needs to open up the outward transmission path of the light signal based on the physical requirement of top light emission from the micro LED chip. Using ultraviolet laser ablation or deep reactive ion etching processes, the epoxy resin material covering each light-emitting pixel chip is precisely removed directly above it, forming a light extraction channel that vertically penetrates the encapsulation layer. In order to reduce the physical loss of total internal reflection at the interface between the inner wall of the light extraction channel and the air, a high-transmittance silicone gel with a relative refractive index between that of the light-emitting chip crystal and air is filled inside the channel. Furthermore, a chemical mechanical polishing process is used to perform global planarization treatment on the top surface of the encapsulation layer and the filling gel to meet the stringent physical requirements of the final surface mount process for the coplanarity of the device pins.

[0086] S330, after the planarization process described above, a continuous array of multiple heterogeneous pixel units is formed on the carrier. According to the pre-designed device boundary layout, inactive dicing channels are set between adjacent pixel units. The carrier and the insulating encapsulation layer above it are fully divided by laser cutting equipment. In order to avoid the extension of microcracks caused by traditional mechanical dicing and the structural damage to the internal micron-level metal interconnects caused by thermal stress, this embodiment uses an ultra-short pulse cold laser for step-by-step ablation cutting. The pulse width of the cold laser is physically limited to the picosecond level, so that the material undergoes phase transition ablation before the heat is conducted to the surrounding lattice over a large area.

[0087] During the cutting process, the cutting path strictly avoids the distribution area of ​​the internal electrical interconnection network. Through comprehensive physical cutting, the original coplanar continuous array is completely blocked, achieving physical isolation and separating it into a large number of independent heterogeneous hybrid driving pixel packages.

[0088] After completing the physical division of individual units, the S340 transfers the cut and separated pixel packages sequentially onto the test carrier to eliminate potential defective products in the process. The high-frequency micro-needle test stage contacts the exposed power and data interaction interface at the bottom of the pixel package and inputs a test vector containing specific grayscale instructions and a standard drive current. In this state, the test system not only monitors the absolute brightness output of the light-emitting pixels, but also collects the steady-state leakage current and on-state voltage drop of the drive module in real time under the applied current state.

[0089] The output results are judged to be qualified based on multi-dimensional evaluation logic: the system requires that the measured luminous brightness should fall within the range of ±5% of the target standard value under the rated pulse width modulation signal, and the static current fluctuation amplitude under continuous working state should be strictly less than 3%.

[0090] This joint judgment logic abandons the one-sided screening that relies solely on a single brightness extreme value. It comprehensively investigates hidden failure modules caused by early hot carrier effects or microstructure defects, and finally encodes pixel packaging units that meet all threshold conditions into the reel carrier tape for use in the matrix mounting process of downstream display panels.

[0091] See attached document Figure 5 , Figure 5 This is a schematic diagram of the panel-level array assembly and power supply network architecture according to an embodiment of the present invention. In this embodiment, the panel-level array assembly process is based on a heterogeneous hybrid driving pixel package that has completed individual component separation and various optoelectronic index tests at the front end. To achieve macroscopic video image display, it is necessary to integrate independent micro-components to construct a panel-level substrate with global signal scheduling and high-power energy transmission capabilities. The assembly and network architecture configuration process is divided into the following sub-steps:

[0092] The S410 provides a large-size printed circuit board or glass substrate as a support base for the macro display system. Based on the resolution requirements of the target display panel, a matrix of mounting pads is designed and laid on the substrate surface. Using high-speed surface mount equipment or mass transfer microelectromechanical systems, the verified individual pixel packages in the reel carrier are precisely transferred to the corresponding pads on the panel-level substrate. Through reflow soldering or anisotropic conductive adhesive thermo-pressing technology, the peripheral interface at the bottom of the pixel package forms a strong intermetallic compound with the substrate pads, thereby establishing a dual connection of physical fixation and system-level electrical interaction in one go.

[0093] In S420, in ultra-large-size micro-LED display panels, the voltage drop caused by the parasitic resistance of the power supply bus is particularly significant due to the large current consumption of the pixel units in the large-scale array when lit. This voltage drop causes the actual driving power supply level in the center area of ​​the panel to be lower than that in the edge feeding area, thus causing spatial inconsistency in macroscopic display brightness. In order to accurately characterize the ohmic loss of large current in the transmission path at the physical level, this embodiment evaluates the voltage attenuation of the worst node in the center of the panel based on Kirchhoff's current law and the physical model of the distributed resistor network. The specific physical model for calculating the voltage drop is shown in the formula:

[0094] ;

[0095] In the formula, This is the bus voltage drop value between the edge power input terminal and the central target pixel node in the global power supply network, in volts. This parameter is used to intuitively characterize the DC transmission loss of the power supply network. Its upper limit allowed in actual engineering must be strictly controlled within five percent of the rated operating voltage of the driver chip to prevent triggering the chip's undervoltage protection. The volume resistivity of the substrate trace metal material is expressed in ohms-meters and is usually taken as the basic physical property value of rolled copper foil or electroplated copper layer. For the first in a distributed cabling network line, number The actual physical length of the grid line segments, in meters; The width of the corresponding line segment is in meters; The thickness of the copper foil corresponding to the line segment is in meters. Due to the physical benchmark set by the manufacturing process and the physical properties of the material itself, the product of the wiring width and thickness is always greater than zero. This objectively ensures the effective existence of the conductive cross-sectional area of ​​the substrate, thereby automatically avoiding the calculation overflow anomaly caused by the denominator term approaching 0 in the division operation in the algorithm logic. and These represent the total number of horizontal and vertical topological nodes in the panel array, respectively, both of which are positive integers; It is the transient current consumed by a pixel unit at a single node under peak brightness conditions, measured in amperes, and its value is determined by the physical luminous efficiency of the light-emitting device. The load concurrency sparsity coefficient is used to correct the statistical probability that the full-screen light-emitting devices do not reach their peak brightness simultaneously when displaying dynamic images. Its engineering value is usually between 0.1 and 1.0. As a preferred approach, for conventional dynamic video sources, the empirical value of this sparsity coefficient is between 0.3 and 0.5.

[0096] Based on the quantitative evaluation results of the above formula, as a preferred approach, the system effectively reduces the equivalent distributed impedance of the power supply network by adding a multi-layer thickened large-area copper-clad plane and a distributed parallel decoupling capacitor array on the back side of the substrate, ensuring that the power supply voltage of any node in the world is stably maintained above the rated operating voltage threshold of the wide bandgap semiconductor driver chip.

[0097] After the S430 completes physical assembly and global power supply network construction, it is necessary to perform closed-loop correction on the overall display performance. High-resolution optical industrial cabinet cameras are used to capture the actual luminous brightness and chromaticity coordinates of the panel under different grayscale instructions. During this process, the system strictly aligns the collected optical multi-source data with the ideal video timing signal sent down. The specific technical implementation is as follows: the main control chip sends a global synchronization clock signal to synchronously trigger the camera shutter exposure and the horizontal scanning circuit of the substrate.

[0098] Eliminate sampling misalignment errors caused by inter-frame delay. Optical multi-source data was constructed as a dimension of The brightness column vector, where This represents the total number of pixel nodes processed in a single operation. By comparing this number with a preset ideal brightness target vector, the result is calculated to be the same. The compensation coefficient matrix of the dimension;

[0099] Considering the problem that singular matrices can easily occur in compensation matrix operations due to local dead lights or open loops, the system pre-implants a regularization correction term with a small constant on the main diagonal before executing the pseudo-inverse matrix solution algorithm. This ensures the absolute numerical convergence of the digital compensation algorithm from a mathematical perspective, preventing the inverse matrix solution from being unsolvable or the results from diverging.

[0100] The final panel factory qualification judgment is based on multi-dimensional weighted logic: the system not only requires that the full-screen brightness uniformity after loading the digital compensation matrix be greater than 97%, but also requires that the maximum voltage fluctuation of the global power supply network in the full-load high-temperature aging test be strictly limited to the tolerance range of ±100 millivolts. This multi-dimensional joint judgment logic avoids the one-sided screening that relies solely on a single brightness extreme value, and ensures the long-term reliable operation of the heterogeneous hybrid driven micro light-emitting diode display system from the dual levels of grating uniformity and electrical robustness.

[0101] Specific application examples are described.

[0102] This embodiment provides a manufacturing process for a heterogeneous hybrid driving pixel package and its display panel used in outdoor commercial displays. The pixel center-to-center spacing of the target display is set to 1.5 mm, the rated peak brightness is set to 5000 nits, and the upper limit of the continuous working environment temperature is set to 85 degrees Celsius.

[0103] In the fabrication and transfer stage of micro semiconductor devices, the light-emitting pixel chip uses red, green and blue micro light-emitting diodes with light emission wavelengths of 622 nm, 527 nm and 453 nm, respectively. The wide bandgap semiconductor driver chip uses gallium nitride high electron mobility transistors with a process node of 0.15 micrometers. The logic control chip uses silicon-based integrated circuits manufactured by 65-nanometer complementary metal-oxide-semiconductor process. The substrate is an alkali-free glass substrate with a thickness of 0.5 mm, and its surface is spin-coated with benzocyclobutene resin with a thickness of 4.2 micrometers as a permanent bonding layer.

[0104] In the redistribution process, the dielectric layer uses photosensitive polyimide material, and its actual coating thickness is controlled at 4.8 micrometers. The metal interconnects are prepared by magnetron sputtering of a titanium-copper composite seed layer combined with electroplating copper. The cross-sectional width of the interconnects is set to 4.5 micrometers and the thickness is set to 2.5 micrometers.

[0105] During the packaging and cutting stages, the packaging material uses a coefficient of thermal expansion of 1.5. A black epoxy resin molding compound per Kelvin was used, with a thermosetting peak temperature set at 145 degrees Celsius. After curing and smoothing the light extraction channel, an ultrashort pulse cold laser with a pulse width of 15 picoseconds was used to perform through-cutting along the dicing path, separating planar sections with a size of 1.2 mm. 1.2 mm individual pixel package.

[0106] In the panel-level array assembly stage, a 6-layer printed circuit board is selected as the display panel substrate. The inner layer reserves a full-plate copper-clad power plane with a thickness of 35 micrometers. The pixel package that has passed the individual unit test is soldered onto the substrate pads through surface mount technology. Its peripheral interface is connected to the global power supply network and data bus of the substrate.

[0107] To verify the technical parameters of this embodiment, a solution using traditional pure silicon-based drive without single-unit packaging and direct transfer was used as a comparison. Parallel experiments were conducted under the same physical test conditions, and the measured data are recorded in the table below.

[0108] Table 1: Comparison of photoelectric performance and reliability test data between heterogeneous hybrid drive solutions and traditional silicon-based solutions

[0109] Test Project Traditional pure silicon-based solutions This invention provides a solution (heterogeneous hybrid driver package). Initial average brightness (nits) 5012.4 5021.7 Center brightness (nits) after 500 hours of continuous operation in an 85°C environment. 4215.8 4956.2 Brightness decay rate (%) after continuous aging 15.89 1.30 Threshold voltage drift of the driving transistor (mV) 142.3 4.1 Parasitic capacitance (pF) of the metal interconnects between signal transmission nodes within a pixel. 1.85 0.43 Panel-level single array assembly yield (%) 99.894 99.991 Maximum voltage drop (mV) under full load in the global power supply network 215.6 46.8 Temperature (°C) of the center area of ​​the display panel after 1 hour of full-load white field operation. 92.4 81.3

[0110] According to the data in Table 1, the heterogeneous hybrid driving scheme proposed in this invention is superior to traditional schemes in terms of photoelectric stability under high temperature environment, high frequency signal transmission integrity, and panel-level manufacturing yield.

[0111] Regarding luminous stability, after 500 hours of continuous operation at 85 degrees Celsius, the threshold voltage drift of the traditional solution reached 142.3 mV, resulting in a decrease in pixel output current and a decrease in luminous brightness from the initial 5012.4 nits to 4215.8 nits, with a decay rate of 15.89%. In contrast, the threshold voltage drift of the gallium nitride driving transistor in this invention is only 4.1 mV, with a corresponding brightness decay rate controlled at 1.30%, and the output brightness maintained at 4956.2 nits. Test data show that by using a wide bandgap semiconductor material to replace silicon-based analog driving devices in the microstructure, the luminous failure problem caused by the high-temperature hot carrier effect is suppressed from a physical mechanism, and the driving current is kept constant.

[0112] In terms of signal transmission and circuit interconnection, the parasitic capacitance of conventional solutions is 1.85 picofarads. This invention reduces the node parasitic capacitance of the internal electrical interconnection structure to 0.43 picofarads by depositing a photosensitive polyimide dielectric layer of a specific thickness on the substrate and redistributing the wiring. The reduction in parasitic capacitance reduces the delay and distortion of high-frequency control signals during transmission across devices.

[0113] In terms of manufacturing process parameters, traditional mass transfer technology assembles chips directly on the display panel, with a single-batch panel-level assembly yield of 99.894%, which includes a certain number of failure nodes. This invention transforms heterogeneous micro-devices into independent pixel packages through overall packaging and cutting processes, and performs individual component screening before mounting, thereby increasing the single-batch panel-level assembly yield to 99.991% and reducing the defect rate and repair time in the macro panel manufacturing process.

[0114] Regarding the panel-level architecture operation, the maximum voltage drop of the global power supply network under full load in the traditional solution reaches 215.6 millivolts, and the temperature in the central area under full load rises to 92.4 degrees Celsius. The test data of this invention shows that its maximum voltage drop is limited to 46.8 millivolts, and the temperature in the central area drops to 81.3 degrees Celsius. The above data proves that the power supply network architecture based on independent pixel package assembly reduces the distributed impedance and heat dissipation on the energy transmission path, and improves the electrical and thermal stability of the large-size display system during operation.

[0115] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A packaging method for a hybrid device package structure suitable for MicroLEDs, characterized in that, The method includes the following steps: S100: Fabricate a wide bandgap semiconductor driver chip, a logic control chip, and a light-emitting pixel chip, and transfer and fix the wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chip coplanarly onto the surface of a carrier board; S200, deposit a dielectric layer on the surface of the carrier board and expose the electrode contacts of each chip, fabricate metal interconnects to connect the electrode contacts to construct an internal electrical interconnect structure, and bring out the peripheral interface; S300, an encapsulation material is coated on the surface of the carrier board to insulate and cover the internal electrical interconnection structure and expose the peripheral interface. After curing, the individual pixel encapsulation is cut and separated. S400, the pixel package is assembled onto the display panel substrate, and the peripheral interface is connected to the scan lines, data lines and global power supply network arranged on the display panel substrate.

2. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 1, characterized in that, In step S100, before fabricating the wide bandgap semiconductor driver chip, the semiconductor device structure constants, hot carrier stress duration, time degradation index factor, injection activation energy, and actual junction temperature parameters are obtained. Based on the laws of solid-state physics, the above parameters are substituted into the physical model to calculate the value of the transistor threshold voltage drift. When the threshold voltage drift of the transistor is determined to be greater than one-zero of the rated drive voltage, a material replacement command is output. According to the material replacement instructions, the wide bandgap semiconductor driver chip is manufactured on a native substrate using gallium nitride material.

3. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 1, characterized in that, In step S100, the coplanar transfer and fixation of the wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chip onto the carrier surface specifically includes: A benzocyclobutene resin is coated onto the selected glass substrate or silicon substrate bearing surface, and a flat bonding layer is formed by thermosetting to constitute the carrier plate. The wide bandgap semiconductor driver chip, logic control chip, and light-emitting pixel chip are separated from their respective native substrates using laser lift-off technology. Extract the spatial coordinate system alignment index based on the preset pixel circuit topology layout; According to the alignment index, the microelectromechanical system (MEMS) controls the separated chips to bond and fix them on the surface of the bonding layer.

4. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 1, characterized in that, In step S200, depositing a dielectric layer on the surface of the carrier plate specifically includes: Obtain the effective facing area of ​​the subsequent metal interconnects and the underlying conductive substrate, the relative permittivity of the photosensitive polyimide material, and the edge parasitic capacitance compensation constant; A safe transmission threshold for the parasitic capacitance of the metal interconnect node is set. Combining the vacuum dielectric constant with the safe transmission threshold, the target coating thickness lower limit is calculated and derived by substituting it into the electromagnetic field capacitance model. Photosensitive polyimide material is selected as the dielectric material, and the dielectric material is spin-coated onto the carrier board and the top surface of each chip in strict accordance with the target coating thickness limit to form the dielectric layer.

5. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 4, characterized in that, In step S200, fabricating metal wires to connect the electrode contacts and construct the internal electrical interconnection structure specifically includes: A titanium-copper composite film is attached as a seed layer on the surface of the dielectric layer and in the exposed holes using a magnetron sputtering process, and the metal interconnect is formed by filling the preset line trench with electroplated copper material. Obtain the peak output current parameters of the display panel under high current long-term operation conditions; Based on the electromigration failure threshold of copper material and the peak output current parameter, the cross-sectional area of ​​the metal interconnect is calculated and set, and the actual maximum current density through the metal interconnect is strictly controlled to be less than the electromigration failure threshold.

6. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 1, characterized in that, In step S300, coating the surface of the carrier board with encapsulation material specifically includes: The peak thermosetting temperature of the pre-selected resin molding compound, the coefficient of thermal expansion of the carrier material, the maximum diagonal physical length of the carrier, and the structural thickness parameters of the carrier are obtained. Based on the preset physical coating thickness of the encapsulation layer and the planar geometric constant, the above parameters are input into the thermal deformation theoretical model of the double-layer thin plate to calculate the predicted value of the center warpage of the encapsulation carrier. When the predicted value of the center warpage is less than 0.002 times the maximum diagonal physical length of the carrier board, the pre-selected resin molding compound is identified as the target encapsulation material and applied to the surface of the carrier board.

7. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 1, characterized in that, In step S300, cutting and separating the individual pixel packages specifically includes: Using ultraviolet laser ablation technology, the epoxy resin material covering each light-emitting pixel chip is removed directly above it to form a vertical light extraction channel that penetrates the protective layer, and the light extraction channel is filled with high-transmittance organosilicon gel. A continuous pixel array is generated by globally smoothing the top surface of the protective layer and the filling gel using a chemical mechanical polishing process. Along the inactive dicing path set between adjacent pixel units in the continuous pixel array, picosecond-level pulse parameters are input to guide an ultrashort pulse cold laser to perform ablation cutting, thereby dividing the carrier plate through and dividing it into the independent pixel packages.

8. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 1, characterized in that, In step S400, before connecting the peripheral interface to the global power supply network arranged on the display panel substrate, a global power supply network configuration step is included, specifically including: Extract the resistivity of the metal traces on the display panel substrate, the physical path length of the distributed wiring network segments, the wiring width, and the copper foil thickness parameters. By combining the transient current consumption under peak brightness conditions of a single node pixel unit with the concurrent sparsity coefficient of dynamic image display load, the voltage drop value of the bus from the edge power input terminal to the central target pixel node is calculated. When the bus voltage drop value is determined to exceed 0.05 times the rated operating voltage of the driver chip, a multi-layer thickened copper-clad plane and a distributed parallel decoupling capacitor array are arranged on the back side of the display panel substrate to update the physical architecture of the global power supply network.

9. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 1, characterized in that, In step S400, assembling the pixel package onto the display panel substrate specifically includes: Individual pixel screening tests are performed by inputting a rated pulse width modulation signal and a standard drive current into the individual pixel package using a high-frequency microneedle test station. Extract evaluation data for indicators where the measured luminous intensity is within ±0.05 times the target standard value and the static current fluctuation amplitude during continuous operation is strictly less than 0.03 times the target standard value. A set of good product indexes is established based on the evaluation data of the aforementioned indicators; Based on the set of good product indexes, the surface mount equipment is called to transfer the corresponding qualified pixel package to the surface of the corresponding pad on the display panel substrate to complete the intermetallic compound bonding.

10. The packaging method for a hybrid device package structure suitable for MicroLEDs according to claim 9, characterized in that, In step S400, after connecting the peripheral interface to the global power supply network, a display performance closed-loop correction step is performed, specifically including: The main control chip sends a global synchronization clock signal to synchronously trigger the camera shutter and the row scanning circuit of the display panel substrate, and collects the column vector of actual luminous brightness corresponding to the preset grayscale command. By comparing the actual luminous brightness column vector with the preset ideal brightness target vector, a regularization correction constant is inserted into the main diagonal of the compensation coefficient matrix to prevent numerical divergence, and the target compensation coefficient matrix is ​​calculated. The target compensation coefficient matrix is ​​loaded into the digital processing module of the display system to perform spatial luminous uniformity correction calculation.

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