Panel-level substrate packaging method and device and warping reducing method

Abstract

The invention relates to a panel-level packaging substrate method and device and a warping reducing method. The warping reduction method is applied to a panel-level packaging substrate, and comprises the following steps: providing a mother substrate; cutting the mother substrate to obtain a son substrate; providing a pressing plate, wherein the pressing plate is provided with an opening; the pressing plate is arranged in the processing cavity and is positioned on the substrate table; the sub-substrate enters the processing cavity and is placed on the substrate table; the pressing plate presses the edge of the sub-substrate, and the sub-substrate is exposed through the opening. The substrate table is applied to the panel-level packaging substrate, the warping problem of the panel-level packaging substrate is solved through the design that the pressing plate is matched with the substrate table, and the substrate table is particularly suitable for the panel-level packaging requirement that a panel is larger and larger; compared with wafer-level packaging, productivity can be increased, and the area utilization rate can be further improved; compared with a traditional panel-level package, the larger the size of the panel is, the larger the warping reduction amplitude of each embodiment of the invention is, so that the size of the panel-level package is larger.

Description

Technical Field

[0001] The present application relates to the field of panel-level packaging, and in particular to a panel-level packaging substrate method, device, and warpage reduction method. Background Art

[0002] Packaging is usually a later step in integrated circuit manufacturing. Chiplet-level packaging is a core particle or small chip packaging. The packaging can protect one or more bare chips inside the chiplet-level package and has pins connected to the outside world.

[0003] The system on chip (SoC) is decomposed into multiple small chips or modules with specific functions. These modules are called chiplets. Chiplet can be designed and manufactured independently, and then reassembled through packaging technology to form a complete system. Semiconductor packaging technology has been continuously developing, gradually developing from 2D packaging to 2.5D packaging, and now entering 3D packaging.

[0004] Simply put, 2.5D packaging is to install multiple chips on the same silicon interposer, then install the silicon interposer on the PCB substrate, and then package them together as a whole to form a complete integrated chip. 3D packaging is based on 2.5D packaging, and further removes the silicon interposer, directly stacking each chip together to shorten the transmission path and reduce the volume.

[0005] The materials of the carrier of chiplet-level packaging mainly include organic substrates, silicon substrates, and glass substrates. If classified by the form of carrier, chiplet-level packaging includes wafer-level packaging (WLP) and panel-level packaging (PLP). The advantage of panel-level packaging lies mainly in cost. As an example, comparing 300mm wafer-level packaging with 515×510mm panel-level packaging, the area ratio of panel-level packaging chips, that is, the area utilization rate, is about 93%, while the area ratio of wafer-level packaging chips is about 64%. This directly leads to huge differences in production costs and production rate UPH during the production process.

[0006] The area utilization rate of traditional fan-out wafer level packaging (FOWLP) technology is less than 85%, while the area utilization rate of fan-out panel level packaging (FOPLP) is over 93%, which allows more chips to be placed, thus helping to reduce production costs. As an example, it is estimated that the transition from 200mm wafer level packaging to 300mm can save about 25% of the cost, while the transition from 300mm wafer level packaging to panel level packaging can save 66% of the cost, that is, the cost of panel level packaging is reduced by 66% compared with the cost of wafer level packaging. Therefore, it is inevitable that panel level packaging will replace wafer level packaging.

[0007] Fan-out is relative to fan-in. The wire redistribution layer (RDL) lines and pins of fan-in package are all within the projected area of ​​the packaged chip, while the RDL lines and pins of fan-out package are not only within the projected area of ​​the chip, but also distributed outside the projected area. That is, fan-in package is completed directly on the original silicon wafer, and the required I / O is arranged within the original chip size, and the package size is basically equal to the chip size; in contrast, the fan-out package process is basically the same as the fan-in type, but the difference is that it is not done on the original silicon wafer, but the chip is cut off and then the wafer is reassembled. The purpose of this is to create space for the fan-out area, so fan-out package can achieve more I / O.

[0008] However, FOPLP is still in its early stages of development. Since it is panel-level packaging, as the panels become larger, warping and chip shifting problems are inevitable. Summary of the invention

[0009] Based on this, it is necessary to provide a panel-level packaging substrate method, device and method for reducing warpage.

[0010] In one embodiment, a method for reducing warpage is applied to a panel-level packaging substrate; the method for reducing warpage comprises the steps of:

[0011] S10, providing a mother substrate;

[0012] S20, cutting the mother substrate to obtain a sub-substrate;

[0013] S30, providing a pressing plate, wherein the pressing plate is provided with an opening;

[0014] S40, the pressing plate is disposed in the process chamber and is located on the substrate table;

[0015] S50, the sub-substrate enters the process chamber and is placed on the substrate table;

[0016] S60, the pressing plate presses the edge of the sub-base and exposes the sub-base through the opening.

[0017] The above-mentioned warpage reduction method is applied to panel-level packaging substrates. Through the design of a pressure plate combined with a substrate table, the warpage problem existing in panel-level packaging substrates is overcome. The method is particularly suitable for panel-level packaging requirements with increasingly larger panels. Compared with wafer-level packaging, it is beneficial to increase production capacity and further improve area utilization. Compared with traditional panel-level packaging, the larger the size of the panel, the greater the degree of warpage reduction in the embodiments of the present application, thereby enabling panel-level packaging to move towards larger sizes.

[0018] In one embodiment, in step S20, the mother substrate is cut according to the packaging specification of the sub-substrate; or,

[0019] In step S30, the opening is set according to the specification of the sub-substrate.

[0020] In one embodiment, in step S30, a carrier is further provided, wherein the carrier is provided with a carrying area for carrying the sub-substrate; and

[0021] Step S50 includes:

[0022] S51, placing the sub-substrate on the carrier, with the sub-substrate at least partially located in the carrying area;

[0023] S52, the carrier carrying the sub-substrate enters the process chamber and is placed on the substrate table.

[0024] In one embodiment, in step S20, the mother substrate is cut in a preset cutting manner to obtain the sub-substrates with the same specifications;

[0025] In step S30, the carrier plate is provided with the carrying areas distributed in a matrix, each of the carrying areas carries one of the sub-substrates; and the pressing plate is provided with the openings distributed in a matrix, each of the openings exposing one of the sub-substrates.

[0026] In one embodiment, in step S30, the pressing plate and the carrier plate are provided as a set; or,

[0027] In step S60 , the pressing plate and the carrier plate jointly clamp and fix each of the sub-substrates.

[0028] In one embodiment, in step S60, the substrate stage is raised or the pressing plate is lowered so that the pressing plate presses against the edge of the sub-substrate.

[0029] In one embodiment, a panel-level packaging substrate method includes the warpage reduction method described in any embodiment.

[0030] In one of the embodiments, the panel-level packaging substrate method further includes a fan-out packaging step.

[0031] In one embodiment, a panel-level packaging substrate device includes a process chamber and a pressing plate, a carrier plate, and a substrate stage disposed in the process chamber;

[0032] The carrier plate is provided with a carrying area for carrying the sub-substrate;

[0033] The carrier plate is arranged on the substrate table;

[0034] The pressing plate is located on the substrate table and is provided with an opening;

[0035] The pressing plate and the substrate stage are movably arranged so that the pressing plate presses the sub-substrate on the carrier and exposes the sub-substrate through the opening.

[0036] In one of the embodiments, the carrier plate is provided with the carrying areas distributed in a matrix, the pressure plate is provided with the openings distributed in a matrix, and each of the openings is arranged in a one-to-one correspondence with each of the carrying areas; or, the pressure plate and the carrier plate jointly clamp and fix each of the sub-substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] FIG. 1 is a schematic diagram of cutting a mother substrate according to a first embodiment of the panel-level packaging substrate method described in the present application.

[0039] FIG. 2 is a schematic diagram of obtaining a sub-substrate after cutting the mother substrate according to the embodiment shown in FIG. 1 .

[0040] FIG. 3 is a schematic structural diagram of a pressing plate corresponding to the sub-base plate of the embodiment shown in FIG. 2 .

[0041] FIG. 4 is a schematic diagram of the embodiment shown in FIG. 3 in another direction.

[0042] FIG. 5 is a schematic diagram of the pressing plate of the embodiment shown in FIG. 3 pressing the edge of the sub-substrate.

[0043] FIG. 6 is a schematic diagram of a process of pressing an edge of a sub-substrate on a substrate stage using a pressing plate in the embodiment shown in FIG. 1 .

[0044] FIG. 7 is a schematic structural diagram of a pressing plate according to a second embodiment of the panel-level packaging substrate method described in the present application.

[0045] FIG. 8 is a schematic diagram of the pressing plate of the embodiment shown in FIG. 7 pressing the edge of the sub-substrate.

[0046] FIG. 9 is a schematic structural diagram of a carrier board according to a second embodiment of the panel-level packaging substrate method described in the present application.

[0047] FIG. 10 is a schematic diagram of the embodiment shown in FIG. 9 in another direction.

[0048] FIG. 11 is a schematic structural diagram of the carrier board carrying the sub-substrate in the embodiment shown in FIG. 9 .

[0049] FIG. 12 is a schematic structural diagram of the carrier board carrying the sub-substrate in the embodiment shown in FIG. 10 .

[0050] FIG. 13 is a schematic diagram of the structure of the embodiment shown in FIG. 12 after being crimped by a pressing plate.

[0051] FIG. 14 is a schematic diagram of a process of pressing an edge of a sub-substrate on a substrate stage using a pressing plate in the embodiment shown in FIG. 13 .

[0052] FIG. 15 is a schematic structural diagram of a pressing plate according to a third embodiment of the panel-level packaging substrate method described in the present application.

[0053] FIG. 16 is a schematic diagram of the embodiment shown in FIG. 15 in another direction.

[0054] FIG. 17 is a schematic structural diagram of a pressing plate according to a fourth embodiment of the panel-level packaging substrate method described in the present application.

[0055] FIG. 18 is a schematic diagram of the edge of the sub-substrate being pressed by the pressing plate of the embodiment shown in FIG. 15 .

[0056] FIG. 19 is a schematic structural diagram of a carrier board according to a third embodiment of the panel-level packaging substrate method described in the present application.

[0057] FIG. 20 is a schematic diagram of the embodiment shown in FIG. 19 in another direction.

[0058] FIG. 21 is a schematic structural diagram of a carrier board according to a fourth embodiment of the panel-level packaging substrate method described in the present application.

[0059] FIG. 22 is a schematic diagram of the structure of the embodiment shown in FIG. 19 after crimping with a pressing plate.

[0060] FIG. 23 is a schematic diagram of the structure of the embodiment shown in FIG. 21 after being crimped using the pressing plate shown in FIG. 16 .

[0061] FIG. 24 is a schematic diagram of the structure of the embodiment shown in FIG. 21 after being crimped using the pressing plate shown in FIG. 17 .

[0062] Figure numerals: mother substrate 100 , sub-substrate 110 , pressing plate 200 , opening 210 , first limiting groove 211 , carrier plate 300 , bearing area 310 , second limiting groove 311 , substrate stage 400 , process chamber 500 . DETAILED DESCRIPTION

[0063] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0064] It should be noted that when a component is referred to as being "fixed to" or "disposed on" another component, it may be directly on the other component or there may also be a central component. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may be a central component at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in the specification of this application are for illustrative purposes only and do not represent the only implementation method.

[0065] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0066] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first feature is directly in contact with the second feature, or the first feature and the second feature are in contact indirectly through an intermediate medium. Moreover, a first feature being “above”, “above”, or “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, or “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0067] Unless otherwise defined, all technical and scientific terms used in the specification of this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in the specification of this application includes any and all combinations of one or more related listed items.

[0068] The present application discloses a panel-level packaging substrate method, a panel-level packaging substrate device, and a method for reducing warpage, which include some or all of the technical features of the following embodiments; that is, the panel-level packaging substrate method, device, and method for reducing warpage include some or all of the following structures. In one embodiment of the present application, a method for reducing warpage is applied to a panel-level packaging substrate; the method for reducing warpage includes the steps: S10, providing a mother substrate; S20, cutting the mother substrate to obtain a sub-substrate; S30, providing a pressing plate, the pressing plate having an opening; S40, the pressing plate is disposed in a process chamber and is located on a substrate stage; S50, the sub-substrate enters the process chamber and is placed on the substrate stage; S60, the pressing plate presses the edge of the sub-substrate, and the sub-substrate is exposed through the opening. The above-mentioned warpage reduction method is applied to the panel-level packaging substrate. Through the design of the pressure plate and the substrate stage, the warpage problem of the panel-level packaging substrate is overcome, which is particularly suitable for the panel-level packaging demand with increasing panel size; compared with wafer-level packaging, it is conducive to increasing production capacity and further improving area utilization; and compared with traditional panel-level packaging, the larger the size of the panel, the greater the reduction in warpage in each embodiment of the present application, thereby making the panel-level packaging move towards a larger size. The panel-level packaging substrate method, panel-level packaging substrate device and warpage reduction method are described in detail below in conjunction with Figures 1 to 24.

[0069] In one embodiment, a panel-level packaging substrate method includes the warpage reduction method described in any embodiment. Since the panel-level packaging substrate method adopts the warpage reduction method described in each embodiment, it also has the beneficial technical effects corresponding to the warpage reduction method described in each embodiment, which will not be described in detail here.

[0070] Those skilled in the art can understand that the panel-level packaging substrate method may also include other processes or steps of the panel-level packaging substrate; in one embodiment, the panel-level packaging substrate method also includes a fan-out packaging step. In other embodiments, the panel-level packaging substrate method also includes wire bonding, packaging substrate and other steps, which are not described here.

[0071] In one of the embodiments, a warpage reduction method is applied to a panel-level packaging substrate to reduce warpage during the manufacturing process. Therefore, the warpage reduction method can also be referred to as a method for reducing warpage during the manufacturing process, which includes the following steps, which are described in detail as follows.

[0072] As an example, in step S10, a mother substrate is provided; the mother substrate is a substrate for panel-level packaging, which has a relatively large area and can be called a large substrate; relative to the substrate after cutting involved in each embodiment of this article, the substrate before cutting is called a mother substrate, and the substrate after cutting is called a sub-substrate. For example, with the development of technology, the mother substrate tends to be larger and larger, but the temperature inside the process chamber for chip preparation is usually high, which leads to the inevitable edge warping problem of the mother substrate. The larger the area of ​​the mother substrate, the more serious the edge warping problem.

[0073] As an example, in step S20, the mother substrate is cut to obtain a sub-substrate; in one embodiment, as shown in FIG. 1 and FIG. 2, in step S20, the mother substrate 100 is cut in a preset cutting manner to obtain the sub-substrates 110 with the same specifications. In one embodiment, in step S20, the mother substrate is cut according to the packaging specifications of the sub-substrate. As an example, in step S20, the mother substrate is cut in a preset cutting manner according to the packaging specifications of the sub-substrate; the rest of the embodiments are analogous and will not be repeated. Exemplarily, the mother substrate is cut to obtain the sub-substrates with the same or different specifications. As an example, the multiple sub-substrates have the same size or different sizes. As an example, as shown in FIG. 1 and FIG. 8, the specifications of each sub-substrate 110 are the same, that is, the shapes of each sub-substrate 110 are the same and substantially the same; in other embodiments, each sub-substrate may have the same shape but different sizes, or may have similar shapes; or may have different shapes and different sizes, which can be set according to actual needs, and the embodiments of the present application do not impose additional restrictions on this.

[0074] Exemplarily, the preset cutting method is to use mutually parallel and mutually perpendicular cutting methods in combination, and the step distance is equal, that is, the mother substrate is cut in a preset cutting method to obtain the square sub-substrate. In each embodiment, the sub-substrates with the same specifications, that is, the sub-substrates have the same shape and size. In other embodiments, the mother substrate can also be flexibly cut according to actual needs to obtain sub-substrates of different sizes. It should be noted that the chiplet-level packaging has developed from 2D to 2.5D and even 3D, and the technical trend is panel-level packaging. However, due to the size of the wafer-level packaging chip itself, there is no technical requirement for cutting before packaging in traditional wafer-level packaging. However, this application proposes a technical improvement of cutting before packaging for the currently developing panel-level packaging technology, especially in conjunction with the pressure plate and carrier plate to be described below. While improving efficiency and increasing production capacity, it greatly improves the improvement of the warping problem of large-size panels, so that panel-level packaging can be suitable for larger panels.

[0075] It should be noted that, in the panel-level packaging substrate, there are some process invalid areas, that is, unusable areas, at the edge positions of the large substrates; and in the double-sided process, since the double-sided process requires turning over, but for the large substrate, due to the large area and resulting mass, it is not enough to rely solely on the process invalid areas at the edge positions for support or adsorption force, which can easily cause the substrate to slide due to gravity deformation during the flipping process. Therefore, the large substrate also needs to provide a force-bearing area in the middle position. These force-bearing areas will cause indentations or other damages due to the force, so they are also process invalid areas, which can be called process invalid areas in the middle position; exemplarily, in step S20, based on the double-sided process, the flipping mechanism clamping device cuts the mother substrate at the invalid area corresponding to the mother substrate, so that the process invalid area in the middle area caused by cutting the mother substrate overlaps or contains the invalid area caused by the flipping mechanism clamping device; in this way, cutting the mother substrate in the double-sided process will not cause new invalid areas due to cutting the substrate into a field-shaped area of ​​multiple small substrates. That is to say, in the conventional process that needs to be turned over for double-sided processing, the position clamped by the turning mechanism is the invalid area of ​​the substrate, that is, the mother substrate. Exemplarily, the warpage reduction method is applied to the panel-level packaging substrate that needs to be turned over for double-sided processing, and in step S20, the process invalid area in the middle area caused by cutting the mother substrate overlaps or contains the invalid area caused by the clamping device of the turning mechanism. With such a design, the warpage reduction method is applicable to the panel-level packaging substrate that needs to be turned over for double-sided processing, and its related equipment and process flow; cutting the mother substrate to obtain a sub-substrate will produce a process invalid area, but for the double-sided process, that is, the panel-level packaging substrate that needs to be turned over for double-sided processing and its related equipment and process flow, the process invalid area in the middle area caused by cutting the mother substrate overlaps or contains the invalid area caused by the clamping device of the turning mechanism, so that the warpage problem existing in the panel-level packaging substrate is overcome without affecting the product performance and without wasting the area.

[0076] As an example, in step S30, a pressing plate is provided, and the pressing plate is provided with an opening; in one embodiment, in step S30, the opening is provided according to the specifications of the sub-substrate. In one embodiment, as shown in FIG. 3 and FIG. 4, in step S30, a pressing plate 200 is provided, and the pressing plate 200 is provided with an opening 210. Exemplarily, the specifications of the opening match the specifications of the sub-substrate, and in one embodiment, the shape of the opening is similar to the shape of the sub-substrate, so that the sub-substrate is exposed to the greatest extent when the pressing plate is pressed against the edge of the sub-substrate.

[0077] As an example, in step S40, the pressing plate is disposed in the process chamber and is located on the substrate stage; in step S50, the sub-substrate enters the process chamber and is placed on the substrate stage; in step S60, the pressing plate presses the edge of the sub-substrate and exposes the sub-substrate through the opening. In one embodiment, as shown in FIG. 5 and FIG. 6, the pressing plate 200 is disposed in the process chamber 500 and is located on the substrate stage 400; the sub-substrate 110 enters the process chamber 500 and is placed on the substrate stage 400; the pressing plate 200 presses the edge of the sub-substrate 110 and exposes the sub-substrate 110 through the opening 210. Exemplarily, in the illustrated embodiment, the shape of the opening is similar to that of the sub-substrate, and the pressing plate 200 continuously presses all edges of the sub-substrate 110; in other embodiments, the pressing plate may also intermittently press part of the edge of the sub-substrate, as long as the sub-substrate is prevented from warping during the process. It is understandable that due to the thermal processing environment and the physical properties of the substrate itself, the warping problem of the panel-level packaging substrate is inevitable; the present application, through the design concept of cutting first and then processing, essentially greatly reduces the warping degree of the panel-level packaging substrate, and on the one hand, by adopting the design of pressing the edge of the sub-substrate with a pressure plate, the sub-substrate is prevented from warping; on the other hand, by cutting the mother substrate, the mother substrate with a relatively large area is decomposed into sub-substrates with a relatively small area, thereby greatly reducing the warping problem of the panel-level packaging substrate; on the other hand, the opening design is conducive to cooperating with other processes to realize the panel-level packaging substrate. Therefore, such a design is very suitable for the increasing panel-level packaging needs; compared with wafer-level packaging, it is conducive to increasing production capacity and further improving area utilization; and compared with traditional panel-level packaging, the larger the size of the panel, the greater the reduction in warping in each embodiment of the present application, thereby making the panel-level packaging move towards a larger size.

[0078] In one embodiment, in step S60, the substrate stage is raised or the pressure plate is lowered so that the pressure plate presses against the edge of the sub-substrate. As an example, as shown in FIG6 , by raising the substrate stage 400, the pressure plate 200 presses against the edge of the sub-substrate 110 on the substrate stage 400 to avoid the sub-substrate 110 from warping in subsequent processes.

[0079] In order to improve the packaging efficiency of a large number of sub-substrates after cutting, in one embodiment, in step S30, a carrier is also provided, and the carrier is provided with a carrying area for carrying the sub-substrate; and step S50 includes: S51, placing the sub-substrate on the carrier, and the sub-substrate is at least partially located in the carrying area; S52, the carrier carrying the sub-substrate enters the process chamber and is placed on the substrate table. In one embodiment, in step S30, the pressing plate and the carrier are set as a set, that is, the pressing plate matches the shape of the carrier, and the opening of the pressing plate also matches the carrying area of ​​the carrier. Exemplarily, the pressing plate and the carrier jointly clamp the sub-substrate or limit the position of the sub-substrate in an accommodating manner. In such a design, the carrier is used as a supporting plate. When the number of sub-substrates is large, the carrier can be used to carry multiple sub-substrates into the process chamber at one time to improve production efficiency. In contrast, in the conventional process that requires flipping over for double-sided processing, the flipping mechanism directly clamps the substrate, namely the mother substrate, and the related clamping mechanism of the flipping mechanism clamps the invalid area of ​​the substrate, while the present embodiment and related embodiments use a pressure plate in conjunction with a carrier plate to support at least one small substrate, namely the sub-substrate. In this way, when it is necessary to flip over for double-sided processing, the design of the clamping mechanism used by the flipping mechanism only needs to clamp the pressure plate and the carrier plate, and there is no need to position and clamp the invalid process area in the middle area of ​​the large-size substrate. Therefore, compared with the clamping mechanism used by the conventional flipping mechanism of large-size substrates, it is simpler, more efficient and safer, thereby reducing process defects and facilitating subsequent processes.

[0080] In one embodiment, in step S20, the mother substrate is cut in a preset cutting method to obtain the sub-substrates with the same specifications; and in step S30, the carrier is provided with the carrying areas distributed in a matrix, and each of the carrying areas carries a sub-substrate; and the pressing plate is provided with the openings distributed in a matrix, and each of the openings exposes a sub-substrate. As an example, as shown in FIG7, the pressing plate 200 is provided with four openings 210 distributed in a matrix, and in combination with FIG8, the pressing plate 200 presses the edges of four sub-substrates 110 at a time, and exposes each of the sub-substrates 110 through each of the openings 210 one by one. In combination with FIG9 and FIG10, the carrier 300, which is set as a set with the pressing plate 200, is provided with four carrying areas 310 distributed in a matrix, and in combination with FIG11 and FIG12, each of the carrying areas 310 carries a sub-substrate 110 one by one, and then the pressing plate 200 is pressed as shown in FIG13 and FIG14. Such a design reduces warping by dividing a large substrate into multiple small substrates of the same or different sizes, and has the advantages of being simple and convenient.

[0081] As an example, as shown in FIG. 15 and FIG. 16 , the pressing plate 200 is provided with sixteen openings 210 distributed in a matrix, arranged in four rows and four columns. In conjunction with FIG. 18 , the pressing plate 200 presses the edges of the sixteen sub-substrates 110 at a time, and exposes each sub-substrate 110 through each opening 210 in a one-to-one correspondence. In conjunction with FIG. 19 and FIG. 20 , the carrier 300, which is set as a set with the pressing plate 200, is provided with sixteen supporting areas 310 distributed in a matrix. In conjunction with FIG. 22 , each supporting area 310 carries a sub-substrate 110 in a one-to-one correspondence, and then the pressing plate 200 is pressed. As an example, a method for reducing warpage is provided by dividing a large substrate into a plurality of small substrates of the same size, and using a field-shaped carrier and a field-shaped edge pressing device in combination. In this embodiment, the panel-level packaging substrate is configured to be a plurality of rectangular substrates combined into a large T-shaped structure substrate as shown in the figure, so that the area utilization rate can be improved compared with the wafer-level packaging, and the problem of warping can be solved at the same time; if the panel-level packaging size is further increased from 510mm×515mm or 600mm×600mm to 800mm×800mm or even larger, the warping problem will be more serious. In this embodiment, that is, the area of ​​the mother substrate is increased, and only the number of rectangles needs to be increased, and the warping problem will not become more serious, but the production capacity can be increased, and the area utilization rate can be further improved. It can be deduced that the larger the panel size, the greater the reduction in warping by the technology of the present application, thereby enabling the panel-level packaging to move towards a larger size; and while reducing the warping, the production quantity per unit time is guaranteed, which is beneficial to improving production efficiency and reducing production costs.

[0082] Exemplarily, as shown in FIG21, the carrying area 310 is a through hole, and the carrier 300 is provided with a second limiting groove 311 in the carrying area 310, and the second limiting groove 311 is used to limit the position of the sub-substrate 110 in the carrying area 310, so as to prevent the sub-substrate 110 from passing through the carrying area 310 and detaching from the carrier 300; in conjunction with FIG23, each of the carrying areas 310 carries a sub-substrate 110 in a one-to-one correspondence, and then the pressing plate 200 is pressed. Such a design can be used with a substrate stage with holes or a floating carrier to process the sub-substrate from two positions, namely, the opening and the carrying area, thereby improving the adaptability of the panel-level packaging substrate method or the warpage reduction method to the panel-level packaging substrate.

[0083] In one of the embodiments, in step S60, the pressing plate and the carrier plate jointly clamp and fix each of the sub-substrates. Exemplarily, as shown in FIG17 , the pressing plate 200 is provided with a first limiting groove 211 in the opening 210, and the first limiting groove 211 is used to provide a space for the sub-substrate 110 to be accommodated in the opening 210; as an example, in combination with FIG24 , the pressing plate 200 and the carrier plate 300 cooperate with the first limiting groove 211 and the second limiting groove 311 to jointly clamp and fix each of the sub-substrates 110. With such a design, the pressing plate and the carrier plate can be floatingly arranged on the substrate stage by adopting a corresponding fixing method or connection method, thereby providing more implementation methods for the panel-level packaging substrate, thereby further improving the adaptability of the panel-level packaging substrate method or its warpage reduction method to the panel-level packaging substrate.

[0084] Based on the design concept of the panel-level packaging substrate method or the method for reducing warpage thereof, in one of the embodiments, a panel-level packaging substrate device includes a process chamber and a pressure plate, a carrier plate, and a substrate stage arranged in the process chamber; the carrier plate is provided with a carrying area for carrying a sub-substrate; the carrier plate is arranged on the substrate stage; the pressure plate is located on the substrate stage and is provided with an opening; wherein the pressure plate and the substrate stage are movably arranged so that the pressure plate presses the sub-substrate on the carrier plate and exposes the sub-substrate through the opening. In one of the embodiments, the panel-level packaging substrate device is implemented by the panel-level packaging substrate method or the method for reducing warpage thereof described in any embodiment. With such a design, the panel-level packaging substrate device also has the beneficial technical effects of the panel-level packaging substrate method or the method for reducing warpage thereof, which will not be elaborated here.

[0085] In one embodiment, the carrier plate is provided with the carrying areas distributed in a matrix, the pressure plate is provided with the openings distributed in a matrix, and each opening is arranged in a one-to-one correspondence with each carrying area; or, the pressure plate and the carrier plate jointly clamp and fix each sub-substrate. The structure of the panel-level packaging substrate device is specifically shown in Figures 1 to 24, and will not be described in detail here.

[0086] As an example, as shown in FIG1 , the specifications of the mother substrate 100 are 510 mm×515 mm×1.1 mm; or 600 mm×600 mm×1.1 mm; in conjunction with FIG6 and FIG14 , the carrier 300 carrying the sub-substrate 110 is placed in the process chamber 500, and then the substrate stage 400 rises to the process position, at which time the pressing plate 200 acts as a pressing device to press the sub-substrate 110. In conjunction with FIG8 and FIG18 , the pressing plate 200 presses multiple sub-substrates 110 at the same time.

[0087] As an example, the specification of the substrate is 245mm×245mm×1.1mm; the thickness of the PVD coating is Ti 150nm and Cu1000nm. If the embodiments of the present application are not adopted, the maximum warpage of the substrate produced in the coating process is measured by a plug gauge and reaches 12.0mm. As shown in Figure 8, the specification of the pressing plate 200 is 600mm×600mm×1.1mm, and four substrates are processed at a time as sub-substrates 110. The maximum warpage of the sub-substrate 110 produced in the coating process is measured by a plug gauge and is only 2.2mm. By comparison, it can be seen that the panel-level packaging substrate device, the panel-level packaging substrate method or the warpage reduction method thereof do greatly overcome the warpage problem existing in the panel-level packaging substrate.

[0088] It should be noted that other embodiments of the present application also include panel-level packaging substrate methods, devices and warpage reduction methods that can be implemented by combining the technical features in the above embodiments.

[0089] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of patent protection of the present application shall be subject to the attached claims.

Claims

1. A method for reducing warpage, characterized in that: Applied to panel-level packaging substrate; the method for reducing warpage comprises the steps of: S10, providing a mother substrate; S20, cutting the mother substrate to obtain a sub-substrate; S30, providing a pressing plate, wherein the pressing plate is provided with an opening; S40, the pressing plate is disposed in the process chamber and is located on the substrate table; S50, the sub-substrate enters the process chamber and is placed on the substrate table; S60, the pressing plate presses the edge of the sub-base and exposes the sub-base through the opening.

2. The method for reducing warpage according to claim 1, characterized in that: In step S20, the mother substrate is cut according to the packaging specifications of the sub-substrates; or, In step S30, the opening is set according to the specification of the sub-substrate.

3. The method for reducing warpage according to claim 1, characterized in that: In step S30, a carrier is further provided, wherein the carrier is provided with a carrying area for carrying the sub-substrate; and Step S50 includes: S51, placing the sub-substrate on the carrier, with the sub-substrate at least partially located in the carrying area; S52, the carrier carrying the sub-substrate enters the process chamber and is placed on the substrate table.

4. The method for reducing warpage according to claim 3, characterized in that: In step S20, the mother substrate is cut in a preset cutting method to obtain the sub-substrates with the same specifications; In step S30, the carrier plate is provided with the carrying areas distributed in a matrix, each of the carrying areas carries one of the sub-substrates; and the pressing plate is provided with the openings distributed in a matrix, each of the openings exposing one of the sub-substrates.

5. The method for reducing warpage according to claim 4, characterized in that: In step S30, the pressing plate and the carrier plate are provided as a set; or, In step S60 , the pressing plate and the carrier plate jointly clamp and fix each of the sub-substrates.

6. The method for reducing warpage according to any one of claims 1 to 5, characterized in that: In step S60, the substrate stage is raised or the pressing plate is lowered so that the pressing plate presses against the edge of the sub-substrate.

7. A panel-level packaging substrate method, characterized in that: The method for reducing warpage comprises the method according to any one of claims 1 to 6.

8. The panel-level packaging substrate method according to claim 7, characterized in that: A fan-out packaging step is also included.

9. A panel-level packaging substrate device, characterized in that: It includes a process chamber and a pressing plate, a carrier plate and a substrate table arranged in the process chamber; The carrier plate is provided with a carrying area for carrying the sub-substrate; The carrier plate is arranged on the substrate table; The pressing plate is located on the substrate table and is provided with an opening; The pressing plate and the substrate stage are movably arranged so that the pressing plate presses the sub-substrate on the carrier and exposes the sub-substrate through the opening.

10. The panel-level packaging substrate device according to claim 9, characterized in that: The carrier plate is provided with the carrying areas distributed in a matrix, the pressing plate is provided with the openings distributed in a matrix, and each opening is arranged in a one-to-one correspondence with each carrying area; or, the pressing plate and the carrier plate jointly clamp and fix each sub-substrate.

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